arch/x86_64/kernel/pci-dma.c

   1 /*
   2  * Dynamic DMA mapping support.
   3  */
   4
   5 #include <linux/types.h>
   6 #include <linux/mm.h>
   7 #include <linux/string.h>
   8 #include <linux/pci.h>
   9 #include <linux/module.h>
  10 #include <asm/io.h>
  11 #include <asm/proto.h>
  12 #include <asm/calgary.h>
  13
  14 int iommu_merge __read_mostly = 0;
  15 EXPORT_SYMBOL(iommu_merge);
  16
  17 dma_addr_t bad_dma_address __read_mostly;
  18 EXPORT_SYMBOL(bad_dma_address);
  19
  20 /* This tells the BIO block layer to assume merging. Default to off
  21    because we cannot guarantee merging later. */
  22 int iommu_bio_merge __read_mostly = 0;
  23 EXPORT_SYMBOL(iommu_bio_merge);
  24
  25 int iommu_sac_force __read_mostly = 0;
  26 EXPORT_SYMBOL(iommu_sac_force);
  27
  28 int no_iommu __read_mostly;
  29 #ifdef CONFIG_IOMMU_DEBUG
  30 int panic_on_overflow __read_mostly = 1;
  31 int force_iommu __read_mostly = 1;
  32 #else
  33 int panic_on_overflow __read_mostly = 0;
  34 int force_iommu __read_mostly= 0;
  35 #endif
  36
  37 /* Set this to 1 if there is a HW IOMMU in the system */
  38 int iommu_detected __read_mostly = 0;
  39
  40 /* Dummy device used for NULL arguments (normally ISA). Better would
  41    be probably a smaller DMA mask, but this is bug-to-bug compatible
  42    to i386. */
  43 struct device fallback_dev = {
  44         .bus_id = "fallback device",
  45         .coherent_dma_mask = DMA_32BIT_MASK,
  46         .dma_mask = &fallback_dev.coherent_dma_mask,
  47 };
  48
  49 /* Allocate DMA memory on node near device */
  50 noinline static void *
  51 dma_alloc_pages(struct device *dev, gfp_t gfp, unsigned order)
  52 {
  53         struct page *page;
  54         int node;
  55 #ifdef CONFIG_PCI
  56         if (dev->bus == &pci_bus_type)
  57                 node = pcibus_to_node(to_pci_dev(dev)->bus);
  58         else
  59 #endif
  60                 node = numa_node_id();
  61
  62         if (node < first_node(node_online_map))
  63                 node = first_node(node_online_map);
  64
  65         page = alloc_pages_node(node, gfp, order);
  66         return page ? page_address(page) : NULL;
  67 }
  68
  69 /*
  70  * Allocate memory for a coherent mapping.
  71  */
  72 void *
  73 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
  74                    gfp_t gfp)
  75 {
  76         void *memory;
  77         unsigned long dma_mask = 0;
  78         u64 bus;
  79
  80         if (!dev)
  81                 dev = &fallback_dev;
  82         dma_mask = dev->coherent_dma_mask;
  83         if (dma_mask == 0)
  84                 dma_mask = DMA_32BIT_MASK;
  85
  86         /* Don't invoke OOM killer */
  87         gfp |= __GFP_NORETRY;
  88
  89         /* Kludge to make it bug-to-bug compatible with i386. i386
  90            uses the normal dma_mask for alloc_coherent. */
  91         dma_mask &= *dev->dma_mask;
  92
  93         /* Why <=? Even when the mask is smaller than 4GB it is often
  94            larger than 16MB and in this case we have a chance of
  95            finding fitting memory in the next higher zone first. If
  96            not retry with true GFP_DMA. -AK */
  97         if (dma_mask <= DMA_32BIT_MASK)
  98                 gfp |= GFP_DMA32;
  99
 100  again:
 101         memory = dma_alloc_pages(dev, gfp, get_order(size));
 102         if (memory == NULL)
 103                 return NULL;
 104
 105         {
 106                 int high, mmu;
 107                 bus = virt_to_bus(memory);
 108                 high = (bus + size) >= dma_mask;
 109                 mmu = high;
 110                 if (force_iommu && !(gfp & GFP_DMA))
 111                         mmu = 1;
 112                 else if (high) {
 113                         free_pages((unsigned long)memory,
 114                                    get_order(size));
 115
 116                         /* Don't use the 16MB ZONE_DMA unless absolutely
 117                            needed. It's better to use remapping first. */
 118                         if (dma_mask < DMA_32BIT_MASK && !(gfp & GFP_DMA)) {
 119                                 gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
 120                                 goto again;
 121                         }
 122
 123                         /* Let low level make its own zone decisions */
 124                         gfp &= ~(GFP_DMA32|GFP_DMA);
 125
 126                         if (dma_ops->alloc_coherent)
 127                                 return dma_ops->alloc_coherent(dev, size,
 128                                                            dma_handle, gfp);
 129                         return NULL;
 130                 }
 131
 132                 memset(memory, 0, size);
 133                 if (!mmu) {
 134                         *dma_handle = virt_to_bus(memory);
 135                         return memory;
 136                 }
 137         }
 138
 139         if (dma_ops->alloc_coherent) {
 140                 free_pages((unsigned long)memory, get_order(size));
 141                 gfp &= ~(GFP_DMA|GFP_DMA32);
 142                 return dma_ops->alloc_coherent(dev, size, dma_handle, gfp);
 143         }
 144
 145         if (dma_ops->map_simple) {
 146                 *dma_handle = dma_ops->map_simple(dev, memory,
 147                                               size,
 148                                               PCI_DMA_BIDIRECTIONAL);
 149                 if (*dma_handle != bad_dma_address)
 150                         return memory;
 151         }
 152
 153         if (panic_on_overflow)
 154                 panic("dma_alloc_coherent: IOMMU overflow by %lu bytes\n",size);
 155         free_pages((unsigned long)memory, get_order(size));
 156         return NULL;
 157 }
 158 EXPORT_SYMBOL(dma_alloc_coherent);
 159
 160 /*
 161  * Unmap coherent memory.
 162  * The caller must ensure that the device has finished accessing the mapping.
 163  */
 164 void dma_free_coherent(struct device *dev, size_t size,
 165                          void *vaddr, dma_addr_t bus)
 166 {
 167         if (dma_ops->unmap_single)
 168                 dma_ops->unmap_single(dev, bus, size, 0);
 169         free_pages((unsigned long)vaddr, get_order(size));
 170 }
 171 EXPORT_SYMBOL(dma_free_coherent);
 172
 173 static int forbid_dac __read_mostly;
 174
 175 int dma_supported(struct device *dev, u64 mask)
 176 {
 177 #ifdef CONFIG_PCI
 178         if (mask > 0xffffffff && forbid_dac > 0) {
 179
 180
 181
 182                 printk(KERN_INFO "PCI: Disallowing DAC for device %s\n", dev->bus_id);
 183                 return 0;
 184         }
 185 #endif
 186
 187         if (dma_ops->dma_supported)
 188                 return dma_ops->dma_supported(dev, mask);
 189
 190         /* Copied from i386. Doesn't make much sense, because it will
 191            only work for pci_alloc_coherent.
 192            The caller just has to use GFP_DMA in this case. */
 193         if (mask < DMA_24BIT_MASK)
 194                 return 0;
 195
 196         /* Tell the device to use SAC when IOMMU force is on.  This
 197            allows the driver to use cheaper accesses in some cases.
 198
 199            Problem with this is that if we overflow the IOMMU area and
 200            return DAC as fallback address the device may not handle it
 201            correctly.
 202
 203            As a special case some controllers have a 39bit address
 204            mode that is as efficient as 32bit (aic79xx). Don't force
 205            SAC for these.  Assume all masks <= 40 bits are of this
 206            type. Normally this doesn't make any difference, but gives
 207            more gentle handling of IOMMU overflow. */
 208         if (iommu_sac_force && (mask >= DMA_40BIT_MASK)) {
 209                 printk(KERN_INFO "%s: Force SAC with mask %Lx\n", dev->bus_id,mask);
 210                 return 0;
 211         }
 212
 213         return 1;
 214 }
 215 EXPORT_SYMBOL(dma_supported);
 216
 217 int dma_set_mask(struct device *dev, u64 mask)
 218 {
 219         if (!dev->dma_mask || !dma_supported(dev, mask))
 220                 return -EIO;
 221         *dev->dma_mask = mask;
 222         return 0;
 223 }
 224 EXPORT_SYMBOL(dma_set_mask);
 225
 226 /* iommu=[size][,noagp][,off][,force][,noforce][,leak][,memaper[=order]][,merge]
 227          [,forcesac][,fullflush][,nomerge][,biomerge]
 228    size  set size of iommu (in bytes)
 229    noagp don't initialize the AGP driver and use full aperture.
 230    off   don't use the IOMMU
 231    leak  turn on simple iommu leak tracing (only when CONFIG_IOMMU_LEAK is on)
 232    memaper[=order] allocate an own aperture over RAM with size 32MB^order.
 233    noforce don't force IOMMU usage. Default.
 234    force  Force IOMMU.
 235    merge  Do lazy merging. This may improve performance on some block devices.
 236           Implies force (experimental)
 237    biomerge Do merging at the BIO layer. This is more efficient than merge,
 238             but should be only done with very big IOMMUs. Implies merge,force.
 239    nomerge Don't do SG merging.
 240    forcesac For SAC mode for masks <40bits  (experimental)
 241    fullflush Flush IOMMU on each allocation (default)
 242    nofullflush Don't use IOMMU fullflush
 243    allowed  overwrite iommu off workarounds for specific chipsets.
 244    soft  Use software bounce buffering (default for Intel machines)
 245    noaperture Don't touch the aperture for AGP.
 246    allowdac Allow DMA >4GB
 247    nodac    Forbid DMA >4GB
 248    panic    Force panic when IOMMU overflows
 249 */
 250 __init int iommu_setup(char *p)
 251 {
 252         iommu_merge = 1;
 253
 254         if (!p)
 255                 return -EINVAL;
 256
 257         while (*p) {
 258                 if (!strncmp(p,"off",3))
 259                         no_iommu = 1;
 260                 /* gart_parse_options has more force support */
 261                 if (!strncmp(p,"force",5))
 262                         force_iommu = 1;
 263                 if (!strncmp(p,"noforce",7)) {
 264                         iommu_merge = 0;
 265                         force_iommu = 0;
 266                 }
 267
 268                 if (!strncmp(p, "biomerge",8)) {
 269                         iommu_bio_merge = 4096;
 270                         iommu_merge = 1;
 271                         force_iommu = 1;
 272                 }
 273                 if (!strncmp(p, "panic",5))
 274                         panic_on_overflow = 1;
 275                 if (!strncmp(p, "nopanic",7))
 276                         panic_on_overflow = 0;
 277                 if (!strncmp(p, "merge",5)) {
 278                         iommu_merge = 1;
 279                         force_iommu = 1;
 280                 }
 281                 if (!strncmp(p, "nomerge",7))
 282                         iommu_merge = 0;
 283                 if (!strncmp(p, "forcesac",8))
 284                         iommu_sac_force = 1;
 285                 if (!strncmp(p, "allowdac", 8))
 286                         forbid_dac = 0;
 287                 if (!strncmp(p, "nodac", 5))
 288                         forbid_dac = -1;
 289
 290 #ifdef CONFIG_SWIOTLB
 291                 if (!strncmp(p, "soft",4))
 292                         swiotlb = 1;
 293 #endif
 294
 295 #ifdef CONFIG_IOMMU
 296                 gart_parse_options(p);
 297 #endif
 298
 299                 p += strcspn(p, ",");
 300                 if (*p == ',')
 301                         ++p;
 302         }
 303         return 0;
 304 }
 305 early_param("iommu", iommu_setup);
 306
 307 void __init pci_iommu_alloc(void)
 308 {
 309         /*
 310          * The order of these functions is important for
 311          * fall-back/fail-over reasons
 312          */
 313 #ifdef CONFIG_IOMMU
 314         iommu_hole_init();
 315 #endif
 316
 317 #ifdef CONFIG_CALGARY_IOMMU
 318         detect_calgary();
 319 #endif
 320
 321 #ifdef CONFIG_SWIOTLB
 322         pci_swiotlb_init();
 323 #endif
 324 }
 325
 326 static int __init pci_iommu_init(void)
 327 {
 328 #ifdef CONFIG_CALGARY_IOMMU
 329         calgary_iommu_init();
 330 #endif
 331
 332 #ifdef CONFIG_IOMMU
 333         gart_iommu_init();
 334 #endif
 335
 336         no_iommu_init();
 337         return 0;
 338 }
 339
 340 /* Must execute after PCI subsystem */
 341 fs_initcall(pci_iommu_init);