2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
72 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
75 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
78 unsigned long segment_offset
;
80 if (!seg
|| !trb
|| trb
< seg
->trbs
)
83 segment_offset
= trb
- seg
->trbs
;
84 if (segment_offset
> TRBS_PER_SEGMENT
)
86 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
89 /* Does this link TRB point to the first segment in a ring,
90 * or was the previous TRB the last TRB on the last segment in the ERST?
92 static inline bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
93 struct xhci_segment
*seg
, union xhci_trb
*trb
)
95 if (ring
== xhci
->event_ring
)
96 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
97 (seg
->next
== xhci
->event_ring
->first_seg
);
99 return trb
->link
.control
& LINK_TOGGLE
;
102 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
103 * segment? I.e. would the updated event TRB pointer step off the end of the
106 static inline int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
107 struct xhci_segment
*seg
, union xhci_trb
*trb
)
109 if (ring
== xhci
->event_ring
)
110 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
112 return (trb
->link
.control
& TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
);
115 static inline int enqueue_is_link_trb(struct xhci_ring
*ring
)
117 struct xhci_link_trb
*link
= &ring
->enqueue
->link
;
118 return ((link
->control
& TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
));
121 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
122 * TRB is in a new segment. This does not skip over link TRBs, and it does not
123 * effect the ring dequeue or enqueue pointers.
125 static void next_trb(struct xhci_hcd
*xhci
,
126 struct xhci_ring
*ring
,
127 struct xhci_segment
**seg
,
128 union xhci_trb
**trb
)
130 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
132 *trb
= ((*seg
)->trbs
);
139 * See Cycle bit rules. SW is the consumer for the event ring only.
140 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
142 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
144 union xhci_trb
*next
= ++(ring
->dequeue
);
145 unsigned long long addr
;
148 /* Update the dequeue pointer further if that was a link TRB or we're at
149 * the end of an event ring segment (which doesn't have link TRBS)
151 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
152 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
153 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
155 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
157 (unsigned int) ring
->cycle_state
);
159 ring
->deq_seg
= ring
->deq_seg
->next
;
160 ring
->dequeue
= ring
->deq_seg
->trbs
;
161 next
= ring
->dequeue
;
163 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
164 if (ring
== xhci
->event_ring
)
165 xhci_dbg(xhci
, "Event ring deq = 0x%llx (DMA)\n", addr
);
166 else if (ring
== xhci
->cmd_ring
)
167 xhci_dbg(xhci
, "Command ring deq = 0x%llx (DMA)\n", addr
);
169 xhci_dbg(xhci
, "Ring deq = 0x%llx (DMA)\n", addr
);
173 * See Cycle bit rules. SW is the consumer for the event ring only.
174 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
176 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
177 * chain bit is set), then set the chain bit in all the following link TRBs.
178 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
179 * have their chain bit cleared (so that each Link TRB is a separate TD).
181 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
182 * set, but other sections talk about dealing with the chain bit set. This was
183 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
184 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
186 * @more_trbs_coming: Will you enqueue more TRBs before calling
187 * prepare_transfer()?
189 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
190 bool consumer
, bool more_trbs_coming
)
193 union xhci_trb
*next
;
194 unsigned long long addr
;
196 chain
= ring
->enqueue
->generic
.field
[3] & TRB_CHAIN
;
197 next
= ++(ring
->enqueue
);
200 /* Update the dequeue pointer further if that was a link TRB or we're at
201 * the end of an event ring segment (which doesn't have link TRBS)
203 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
205 if (ring
!= xhci
->event_ring
) {
207 * If the caller doesn't plan on enqueueing more
208 * TDs before ringing the doorbell, then we
209 * don't want to give the link TRB to the
210 * hardware just yet. We'll give the link TRB
211 * back in prepare_ring() just before we enqueue
212 * the TD at the top of the ring.
214 if (!chain
&& !more_trbs_coming
)
217 /* If we're not dealing with 0.95 hardware,
218 * carry over the chain bit of the previous TRB
219 * (which may mean the chain bit is cleared).
221 if (!xhci_link_trb_quirk(xhci
)) {
222 next
->link
.control
&= ~TRB_CHAIN
;
223 next
->link
.control
|= chain
;
225 /* Give this link TRB to the hardware */
227 next
->link
.control
^= TRB_CYCLE
;
229 /* Toggle the cycle bit after the last ring segment. */
230 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
231 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
233 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
235 (unsigned int) ring
->cycle_state
);
238 ring
->enq_seg
= ring
->enq_seg
->next
;
239 ring
->enqueue
= ring
->enq_seg
->trbs
;
240 next
= ring
->enqueue
;
242 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
243 if (ring
== xhci
->event_ring
)
244 xhci_dbg(xhci
, "Event ring enq = 0x%llx (DMA)\n", addr
);
245 else if (ring
== xhci
->cmd_ring
)
246 xhci_dbg(xhci
, "Command ring enq = 0x%llx (DMA)\n", addr
);
248 xhci_dbg(xhci
, "Ring enq = 0x%llx (DMA)\n", addr
);
252 * Check to see if there's room to enqueue num_trbs on the ring. See rules
254 * FIXME: this would be simpler and faster if we just kept track of the number
255 * of free TRBs in a ring.
257 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
258 unsigned int num_trbs
)
261 union xhci_trb
*enq
= ring
->enqueue
;
262 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
263 struct xhci_segment
*cur_seg
;
264 unsigned int left_on_ring
;
266 /* If we are currently pointing to a link TRB, advance the
267 * enqueue pointer before checking for space */
268 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
269 enq_seg
= enq_seg
->next
;
273 /* Check if ring is empty */
274 if (enq
== ring
->dequeue
) {
275 /* Can't use link trbs */
276 left_on_ring
= TRBS_PER_SEGMENT
- 1;
277 for (cur_seg
= enq_seg
->next
; cur_seg
!= enq_seg
;
278 cur_seg
= cur_seg
->next
)
279 left_on_ring
+= TRBS_PER_SEGMENT
- 1;
281 /* Always need one TRB free in the ring. */
283 if (num_trbs
> left_on_ring
) {
284 xhci_warn(xhci
, "Not enough room on ring; "
285 "need %u TRBs, %u TRBs left\n",
286 num_trbs
, left_on_ring
);
291 /* Make sure there's an extra empty TRB available */
292 for (i
= 0; i
<= num_trbs
; ++i
) {
293 if (enq
== ring
->dequeue
)
296 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
297 enq_seg
= enq_seg
->next
;
304 void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
309 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
310 xhci
->event_ring
->dequeue
);
311 if (deq
== 0 && !in_interrupt())
312 xhci_warn(xhci
, "WARN something wrong with SW event ring "
314 /* Update HC event ring dequeue pointer */
315 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
316 temp
&= ERST_PTR_MASK
;
317 /* Don't clear the EHB bit (which is RW1C) because
318 * there might be more events to service.
321 xhci_dbg(xhci
, "// Write event ring dequeue pointer, preserving EHB bit\n");
322 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
323 &xhci
->ir_set
->erst_dequeue
);
326 /* Ring the host controller doorbell after placing a command on the ring */
327 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
331 xhci_dbg(xhci
, "// Ding dong!\n");
332 temp
= xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]) & DB_MASK
;
333 xhci_writel(xhci
, temp
| DB_TARGET_HOST
, &xhci
->dba
->doorbell
[0]);
334 /* Flush PCI posted writes */
335 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
338 static void ring_ep_doorbell(struct xhci_hcd
*xhci
,
339 unsigned int slot_id
,
340 unsigned int ep_index
,
341 unsigned int stream_id
)
343 struct xhci_virt_ep
*ep
;
344 unsigned int ep_state
;
346 __u32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
348 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
349 ep_state
= ep
->ep_state
;
350 /* Don't ring the doorbell for this endpoint if there are pending
351 * cancellations because the we don't want to interrupt processing.
352 * We don't want to restart any stream rings if there's a set dequeue
353 * pointer command pending because the device can choose to start any
354 * stream once the endpoint is on the HW schedule.
355 * FIXME - check all the stream rings for pending cancellations.
357 if (!(ep_state
& EP_HALT_PENDING
) && !(ep_state
& SET_DEQ_PENDING
)
358 && !(ep_state
& EP_HALTED
)) {
359 field
= xhci_readl(xhci
, db_addr
) & DB_MASK
;
360 field
|= EPI_TO_DB(ep_index
) | STREAM_ID_TO_DB(stream_id
);
361 xhci_writel(xhci
, field
, db_addr
);
362 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
363 * isn't time-critical and we shouldn't make the CPU wait for
366 xhci_readl(xhci
, db_addr
);
370 /* Ring the doorbell for any rings with pending URBs */
371 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
372 unsigned int slot_id
,
373 unsigned int ep_index
)
375 unsigned int stream_id
;
376 struct xhci_virt_ep
*ep
;
378 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
380 /* A ring has pending URBs if its TD list is not empty */
381 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
382 if (!(list_empty(&ep
->ring
->td_list
)))
383 ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
387 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
389 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
390 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
391 ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
396 * Find the segment that trb is in. Start searching in start_seg.
397 * If we must move past a segment that has a link TRB with a toggle cycle state
398 * bit set, then we will toggle the value pointed at by cycle_state.
400 static struct xhci_segment
*find_trb_seg(
401 struct xhci_segment
*start_seg
,
402 union xhci_trb
*trb
, int *cycle_state
)
404 struct xhci_segment
*cur_seg
= start_seg
;
405 struct xhci_generic_trb
*generic_trb
;
407 while (cur_seg
->trbs
> trb
||
408 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
409 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
410 if ((generic_trb
->field
[3] & TRB_TYPE_BITMASK
) ==
411 TRB_TYPE(TRB_LINK
) &&
412 (generic_trb
->field
[3] & LINK_TOGGLE
))
413 *cycle_state
= ~(*cycle_state
) & 0x1;
414 cur_seg
= cur_seg
->next
;
415 if (cur_seg
== start_seg
)
416 /* Looped over the entire list. Oops! */
423 static struct xhci_ring
*xhci_triad_to_transfer_ring(struct xhci_hcd
*xhci
,
424 unsigned int slot_id
, unsigned int ep_index
,
425 unsigned int stream_id
)
427 struct xhci_virt_ep
*ep
;
429 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
430 /* Common case: no streams */
431 if (!(ep
->ep_state
& EP_HAS_STREAMS
))
434 if (stream_id
== 0) {
436 "WARN: Slot ID %u, ep index %u has streams, "
437 "but URB has no stream ID.\n",
442 if (stream_id
< ep
->stream_info
->num_streams
)
443 return ep
->stream_info
->stream_rings
[stream_id
];
446 "WARN: Slot ID %u, ep index %u has "
447 "stream IDs 1 to %u allocated, "
448 "but stream ID %u is requested.\n",
450 ep
->stream_info
->num_streams
- 1,
455 /* Get the right ring for the given URB.
456 * If the endpoint supports streams, boundary check the URB's stream ID.
457 * If the endpoint doesn't support streams, return the singular endpoint ring.
459 static struct xhci_ring
*xhci_urb_to_transfer_ring(struct xhci_hcd
*xhci
,
462 return xhci_triad_to_transfer_ring(xhci
, urb
->dev
->slot_id
,
463 xhci_get_endpoint_index(&urb
->ep
->desc
), urb
->stream_id
);
467 * Move the xHC's endpoint ring dequeue pointer past cur_td.
468 * Record the new state of the xHC's endpoint ring dequeue segment,
469 * dequeue pointer, and new consumer cycle state in state.
470 * Update our internal representation of the ring's dequeue pointer.
472 * We do this in three jumps:
473 * - First we update our new ring state to be the same as when the xHC stopped.
474 * - Then we traverse the ring to find the segment that contains
475 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
476 * any link TRBs with the toggle cycle bit set.
477 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
478 * if we've moved it past a link TRB with the toggle cycle bit set.
480 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
481 unsigned int slot_id
, unsigned int ep_index
,
482 unsigned int stream_id
, struct xhci_td
*cur_td
,
483 struct xhci_dequeue_state
*state
)
485 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
486 struct xhci_ring
*ep_ring
;
487 struct xhci_generic_trb
*trb
;
488 struct xhci_ep_ctx
*ep_ctx
;
491 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
492 ep_index
, stream_id
);
494 xhci_warn(xhci
, "WARN can't find new dequeue state "
495 "for invalid stream ID %u.\n",
499 state
->new_cycle_state
= 0;
500 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
501 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
502 dev
->eps
[ep_index
].stopped_trb
,
503 &state
->new_cycle_state
);
504 if (!state
->new_deq_seg
)
506 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
507 xhci_dbg(xhci
, "Finding endpoint context\n");
508 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
509 state
->new_cycle_state
= 0x1 & ep_ctx
->deq
;
511 state
->new_deq_ptr
= cur_td
->last_trb
;
512 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
513 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
515 &state
->new_cycle_state
);
516 if (!state
->new_deq_seg
)
519 trb
= &state
->new_deq_ptr
->generic
;
520 if ((trb
->field
[3] & TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
) &&
521 (trb
->field
[3] & LINK_TOGGLE
))
522 state
->new_cycle_state
= ~(state
->new_cycle_state
) & 0x1;
523 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
525 /* Don't update the ring cycle state for the producer (us). */
526 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
528 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
529 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
530 (unsigned long long) addr
);
531 xhci_dbg(xhci
, "Setting dequeue pointer in internal ring state.\n");
532 ep_ring
->dequeue
= state
->new_deq_ptr
;
533 ep_ring
->deq_seg
= state
->new_deq_seg
;
536 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
537 struct xhci_td
*cur_td
)
539 struct xhci_segment
*cur_seg
;
540 union xhci_trb
*cur_trb
;
542 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
544 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
545 if ((cur_trb
->generic
.field
[3] & TRB_TYPE_BITMASK
) ==
546 TRB_TYPE(TRB_LINK
)) {
547 /* Unchain any chained Link TRBs, but
548 * leave the pointers intact.
550 cur_trb
->generic
.field
[3] &= ~TRB_CHAIN
;
551 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
552 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
553 "in seg %p (0x%llx dma)\n",
555 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
557 (unsigned long long)cur_seg
->dma
);
559 cur_trb
->generic
.field
[0] = 0;
560 cur_trb
->generic
.field
[1] = 0;
561 cur_trb
->generic
.field
[2] = 0;
562 /* Preserve only the cycle bit of this TRB */
563 cur_trb
->generic
.field
[3] &= TRB_CYCLE
;
564 cur_trb
->generic
.field
[3] |= TRB_TYPE(TRB_TR_NOOP
);
565 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
566 "in seg %p (0x%llx dma)\n",
568 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
570 (unsigned long long)cur_seg
->dma
);
572 if (cur_trb
== cur_td
->last_trb
)
577 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
578 unsigned int ep_index
, unsigned int stream_id
,
579 struct xhci_segment
*deq_seg
,
580 union xhci_trb
*deq_ptr
, u32 cycle_state
);
582 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
583 unsigned int slot_id
, unsigned int ep_index
,
584 unsigned int stream_id
,
585 struct xhci_dequeue_state
*deq_state
)
587 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
589 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
590 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
591 deq_state
->new_deq_seg
,
592 (unsigned long long)deq_state
->new_deq_seg
->dma
,
593 deq_state
->new_deq_ptr
,
594 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
595 deq_state
->new_cycle_state
);
596 queue_set_tr_deq(xhci
, slot_id
, ep_index
, stream_id
,
597 deq_state
->new_deq_seg
,
598 deq_state
->new_deq_ptr
,
599 (u32
) deq_state
->new_cycle_state
);
600 /* Stop the TD queueing code from ringing the doorbell until
601 * this command completes. The HC won't set the dequeue pointer
602 * if the ring is running, and ringing the doorbell starts the
605 ep
->ep_state
|= SET_DEQ_PENDING
;
608 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
609 struct xhci_virt_ep
*ep
)
611 ep
->ep_state
&= ~EP_HALT_PENDING
;
612 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
613 * timer is running on another CPU, we don't decrement stop_cmds_pending
614 * (since we didn't successfully stop the watchdog timer).
616 if (del_timer(&ep
->stop_cmd_timer
))
617 ep
->stop_cmds_pending
--;
620 /* Must be called with xhci->lock held in interrupt context */
621 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
622 struct xhci_td
*cur_td
, int status
, char *adjective
)
624 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
626 struct urb_priv
*urb_priv
;
629 urb_priv
= urb
->hcpriv
;
632 /* Only giveback urb when this is the last td in urb */
633 if (urb_priv
->td_cnt
== urb_priv
->length
) {
634 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
635 xhci_dbg(xhci
, "Giveback %s URB %p\n", adjective
, urb
);
637 spin_unlock(&xhci
->lock
);
638 usb_hcd_giveback_urb(hcd
, urb
, status
);
639 xhci_urb_free_priv(xhci
, urb_priv
);
640 spin_lock(&xhci
->lock
);
641 xhci_dbg(xhci
, "%s URB given back\n", adjective
);
646 * When we get a command completion for a Stop Endpoint Command, we need to
647 * unlink any cancelled TDs from the ring. There are two ways to do that:
649 * 1. If the HW was in the middle of processing the TD that needs to be
650 * cancelled, then we must move the ring's dequeue pointer past the last TRB
651 * in the TD with a Set Dequeue Pointer Command.
652 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
653 * bit cleared) so that the HW will skip over them.
655 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
658 unsigned int slot_id
;
659 unsigned int ep_index
;
660 struct xhci_ring
*ep_ring
;
661 struct xhci_virt_ep
*ep
;
662 struct list_head
*entry
;
663 struct xhci_td
*cur_td
= NULL
;
664 struct xhci_td
*last_unlinked_td
;
666 struct xhci_dequeue_state deq_state
;
668 memset(&deq_state
, 0, sizeof(deq_state
));
669 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
670 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
671 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
673 if (list_empty(&ep
->cancelled_td_list
)) {
674 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
675 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
679 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
680 * We have the xHCI lock, so nothing can modify this list until we drop
681 * it. We're also in the event handler, so we can't get re-interrupted
682 * if another Stop Endpoint command completes
684 list_for_each(entry
, &ep
->cancelled_td_list
) {
685 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
686 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
688 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
689 ep_ring
= xhci_urb_to_transfer_ring(xhci
, cur_td
->urb
);
691 /* This shouldn't happen unless a driver is mucking
692 * with the stream ID after submission. This will
693 * leave the TD on the hardware ring, and the hardware
694 * will try to execute it, and may access a buffer
695 * that has already been freed. In the best case, the
696 * hardware will execute it, and the event handler will
697 * ignore the completion event for that TD, since it was
698 * removed from the td_list for that endpoint. In
699 * short, don't muck with the stream ID after
702 xhci_warn(xhci
, "WARN Cancelled URB %p "
703 "has invalid stream ID %u.\n",
705 cur_td
->urb
->stream_id
);
706 goto remove_finished_td
;
709 * If we stopped on the TD we need to cancel, then we have to
710 * move the xHC endpoint ring dequeue pointer past this TD.
712 if (cur_td
== ep
->stopped_td
)
713 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
,
714 cur_td
->urb
->stream_id
,
717 td_to_noop(xhci
, ep_ring
, cur_td
);
720 * The event handler won't see a completion for this TD anymore,
721 * so remove it from the endpoint ring's TD list. Keep it in
722 * the cancelled TD list for URB completion later.
724 list_del(&cur_td
->td_list
);
726 last_unlinked_td
= cur_td
;
727 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
729 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
730 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
731 xhci_queue_new_dequeue_state(xhci
,
733 ep
->stopped_td
->urb
->stream_id
,
735 xhci_ring_cmd_db(xhci
);
737 /* Otherwise ring the doorbell(s) to restart queued transfers */
738 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
740 ep
->stopped_td
= NULL
;
741 ep
->stopped_trb
= NULL
;
744 * Drop the lock and complete the URBs in the cancelled TD list.
745 * New TDs to be cancelled might be added to the end of the list before
746 * we can complete all the URBs for the TDs we already unlinked.
747 * So stop when we've completed the URB for the last TD we unlinked.
750 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
751 struct xhci_td
, cancelled_td_list
);
752 list_del(&cur_td
->cancelled_td_list
);
754 /* Clean up the cancelled URB */
755 /* Doesn't matter what we pass for status, since the core will
756 * just overwrite it (because the URB has been unlinked).
758 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0, "cancelled");
760 /* Stop processing the cancelled list if the watchdog timer is
763 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
765 } while (cur_td
!= last_unlinked_td
);
767 /* Return to the event handler with xhci->lock re-acquired */
770 /* Watchdog timer function for when a stop endpoint command fails to complete.
771 * In this case, we assume the host controller is broken or dying or dead. The
772 * host may still be completing some other events, so we have to be careful to
773 * let the event ring handler and the URB dequeueing/enqueueing functions know
774 * through xhci->state.
776 * The timer may also fire if the host takes a very long time to respond to the
777 * command, and the stop endpoint command completion handler cannot delete the
778 * timer before the timer function is called. Another endpoint cancellation may
779 * sneak in before the timer function can grab the lock, and that may queue
780 * another stop endpoint command and add the timer back. So we cannot use a
781 * simple flag to say whether there is a pending stop endpoint command for a
782 * particular endpoint.
784 * Instead we use a combination of that flag and a counter for the number of
785 * pending stop endpoint commands. If the timer is the tail end of the last
786 * stop endpoint command, and the endpoint's command is still pending, we assume
789 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
791 struct xhci_hcd
*xhci
;
792 struct xhci_virt_ep
*ep
;
793 struct xhci_virt_ep
*temp_ep
;
794 struct xhci_ring
*ring
;
795 struct xhci_td
*cur_td
;
798 ep
= (struct xhci_virt_ep
*) arg
;
801 spin_lock(&xhci
->lock
);
803 ep
->stop_cmds_pending
--;
804 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
805 xhci_dbg(xhci
, "Stop EP timer ran, but another timer marked "
806 "xHCI as DYING, exiting.\n");
807 spin_unlock(&xhci
->lock
);
810 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
811 xhci_dbg(xhci
, "Stop EP timer ran, but no command pending, "
813 spin_unlock(&xhci
->lock
);
817 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
818 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
819 /* Oops, HC is dead or dying or at least not responding to the stop
822 xhci
->xhc_state
|= XHCI_STATE_DYING
;
823 /* Disable interrupts from the host controller and start halting it */
825 spin_unlock(&xhci
->lock
);
827 ret
= xhci_halt(xhci
);
829 spin_lock(&xhci
->lock
);
831 /* This is bad; the host is not responding to commands and it's
832 * not allowing itself to be halted. At least interrupts are
833 * disabled, so we can set HC_STATE_HALT and notify the
834 * USB core. But if we call usb_hc_died(), it will attempt to
835 * disconnect all device drivers under this host. Those
836 * disconnect() methods will wait for all URBs to be unlinked,
837 * so we must complete them.
839 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
840 xhci_warn(xhci
, "Completing active URBs anyway.\n");
841 /* We could turn all TDs on the rings to no-ops. This won't
842 * help if the host has cached part of the ring, and is slow if
843 * we want to preserve the cycle bit. Skip it and hope the host
844 * doesn't touch the memory.
847 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
850 for (j
= 0; j
< 31; j
++) {
851 temp_ep
= &xhci
->devs
[i
]->eps
[j
];
852 ring
= temp_ep
->ring
;
855 xhci_dbg(xhci
, "Killing URBs for slot ID %u, "
856 "ep index %u\n", i
, j
);
857 while (!list_empty(&ring
->td_list
)) {
858 cur_td
= list_first_entry(&ring
->td_list
,
861 list_del(&cur_td
->td_list
);
862 if (!list_empty(&cur_td
->cancelled_td_list
))
863 list_del(&cur_td
->cancelled_td_list
);
864 xhci_giveback_urb_in_irq(xhci
, cur_td
,
865 -ESHUTDOWN
, "killed");
867 while (!list_empty(&temp_ep
->cancelled_td_list
)) {
868 cur_td
= list_first_entry(
869 &temp_ep
->cancelled_td_list
,
872 list_del(&cur_td
->cancelled_td_list
);
873 xhci_giveback_urb_in_irq(xhci
, cur_td
,
874 -ESHUTDOWN
, "killed");
878 spin_unlock(&xhci
->lock
);
879 xhci_to_hcd(xhci
)->state
= HC_STATE_HALT
;
880 xhci_dbg(xhci
, "Calling usb_hc_died()\n");
881 usb_hc_died(xhci_to_hcd(xhci
));
882 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
886 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
887 * we need to clear the set deq pending flag in the endpoint ring state, so that
888 * the TD queueing code can ring the doorbell again. We also need to ring the
889 * endpoint doorbell to restart the ring, but only if there aren't more
890 * cancellations pending.
892 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
893 struct xhci_event_cmd
*event
,
896 unsigned int slot_id
;
897 unsigned int ep_index
;
898 unsigned int stream_id
;
899 struct xhci_ring
*ep_ring
;
900 struct xhci_virt_device
*dev
;
901 struct xhci_ep_ctx
*ep_ctx
;
902 struct xhci_slot_ctx
*slot_ctx
;
904 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
905 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
906 stream_id
= TRB_TO_STREAM_ID(trb
->generic
.field
[2]);
907 dev
= xhci
->devs
[slot_id
];
909 ep_ring
= xhci_stream_id_to_ring(dev
, ep_index
, stream_id
);
911 xhci_warn(xhci
, "WARN Set TR deq ptr command for "
912 "freed stream ID %u\n",
914 /* XXX: Harmless??? */
915 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
919 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
920 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
922 if (GET_COMP_CODE(event
->status
) != COMP_SUCCESS
) {
923 unsigned int ep_state
;
924 unsigned int slot_state
;
926 switch (GET_COMP_CODE(event
->status
)) {
928 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
929 "of stream ID configuration\n");
932 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
933 "to incorrect slot or ep state.\n");
934 ep_state
= ep_ctx
->ep_info
;
935 ep_state
&= EP_STATE_MASK
;
936 slot_state
= slot_ctx
->dev_state
;
937 slot_state
= GET_SLOT_STATE(slot_state
);
938 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
939 slot_state
, ep_state
);
942 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
943 "slot %u was not enabled.\n", slot_id
);
946 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
947 "completion code of %u.\n",
948 GET_COMP_CODE(event
->status
));
951 /* OK what do we do now? The endpoint state is hosed, and we
952 * should never get to this point if the synchronization between
953 * queueing, and endpoint state are correct. This might happen
954 * if the device gets disconnected after we've finished
955 * cancelling URBs, which might not be an error...
958 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
962 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
963 /* Restart any rings with pending URBs */
964 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
967 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
968 struct xhci_event_cmd
*event
,
972 unsigned int ep_index
;
974 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
975 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
976 /* This command will only fail if the endpoint wasn't halted,
979 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
980 (unsigned int) GET_COMP_CODE(event
->status
));
982 /* HW with the reset endpoint quirk needs to have a configure endpoint
983 * command complete before the endpoint can be used. Queue that here
984 * because the HW can't handle two commands being queued in a row.
986 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
987 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
988 xhci_queue_configure_endpoint(xhci
,
989 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
991 xhci_ring_cmd_db(xhci
);
993 /* Clear our internal halted state and restart the ring(s) */
994 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
995 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
999 /* Check to see if a command in the device's command queue matches this one.
1000 * Signal the completion or free the command, and return 1. Return 0 if the
1001 * completed command isn't at the head of the command list.
1003 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
1004 struct xhci_virt_device
*virt_dev
,
1005 struct xhci_event_cmd
*event
)
1007 struct xhci_command
*command
;
1009 if (list_empty(&virt_dev
->cmd_list
))
1012 command
= list_entry(virt_dev
->cmd_list
.next
,
1013 struct xhci_command
, cmd_list
);
1014 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
1018 GET_COMP_CODE(event
->status
);
1019 list_del(&command
->cmd_list
);
1020 if (command
->completion
)
1021 complete(command
->completion
);
1023 xhci_free_command(xhci
, command
);
1027 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
1028 struct xhci_event_cmd
*event
)
1030 int slot_id
= TRB_TO_SLOT_ID(event
->flags
);
1032 dma_addr_t cmd_dequeue_dma
;
1033 struct xhci_input_control_ctx
*ctrl_ctx
;
1034 struct xhci_virt_device
*virt_dev
;
1035 unsigned int ep_index
;
1036 struct xhci_ring
*ep_ring
;
1037 unsigned int ep_state
;
1039 cmd_dma
= event
->cmd_trb
;
1040 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1041 xhci
->cmd_ring
->dequeue
);
1042 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1043 if (cmd_dequeue_dma
== 0) {
1044 xhci
->error_bitmask
|= 1 << 4;
1047 /* Does the DMA address match our internal dequeue pointer address? */
1048 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
1049 xhci
->error_bitmask
|= 1 << 5;
1052 switch (xhci
->cmd_ring
->dequeue
->generic
.field
[3] & TRB_TYPE_BITMASK
) {
1053 case TRB_TYPE(TRB_ENABLE_SLOT
):
1054 if (GET_COMP_CODE(event
->status
) == COMP_SUCCESS
)
1055 xhci
->slot_id
= slot_id
;
1058 complete(&xhci
->addr_dev
);
1060 case TRB_TYPE(TRB_DISABLE_SLOT
):
1061 if (xhci
->devs
[slot_id
])
1062 xhci_free_virt_device(xhci
, slot_id
);
1064 case TRB_TYPE(TRB_CONFIG_EP
):
1065 virt_dev
= xhci
->devs
[slot_id
];
1066 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1069 * Configure endpoint commands can come from the USB core
1070 * configuration or alt setting changes, or because the HW
1071 * needed an extra configure endpoint command after a reset
1072 * endpoint command or streams were being configured.
1073 * If the command was for a halted endpoint, the xHCI driver
1074 * is not waiting on the configure endpoint command.
1076 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
1078 /* Input ctx add_flags are the endpoint index plus one */
1079 ep_index
= xhci_last_valid_endpoint(ctrl_ctx
->add_flags
) - 1;
1080 /* A usb_set_interface() call directly after clearing a halted
1081 * condition may race on this quirky hardware. Not worth
1082 * worrying about, since this is prototype hardware. Not sure
1083 * if this will work for streams, but streams support was
1084 * untested on this prototype.
1086 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
1087 ep_index
!= (unsigned int) -1 &&
1088 ctrl_ctx
->add_flags
- SLOT_FLAG
==
1089 ctrl_ctx
->drop_flags
) {
1090 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1091 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1092 if (!(ep_state
& EP_HALTED
))
1093 goto bandwidth_change
;
1094 xhci_dbg(xhci
, "Completed config ep cmd - "
1095 "last ep index = %d, state = %d\n",
1096 ep_index
, ep_state
);
1097 /* Clear internal halted state and restart ring(s) */
1098 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
1100 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1104 xhci_dbg(xhci
, "Completed config ep cmd\n");
1105 xhci
->devs
[slot_id
]->cmd_status
=
1106 GET_COMP_CODE(event
->status
);
1107 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1109 case TRB_TYPE(TRB_EVAL_CONTEXT
):
1110 virt_dev
= xhci
->devs
[slot_id
];
1111 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1113 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
1114 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1116 case TRB_TYPE(TRB_ADDR_DEV
):
1117 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
1118 complete(&xhci
->addr_dev
);
1120 case TRB_TYPE(TRB_STOP_RING
):
1121 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
);
1123 case TRB_TYPE(TRB_SET_DEQ
):
1124 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1126 case TRB_TYPE(TRB_CMD_NOOP
):
1127 ++xhci
->noops_handled
;
1129 case TRB_TYPE(TRB_RESET_EP
):
1130 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1132 case TRB_TYPE(TRB_RESET_DEV
):
1133 xhci_dbg(xhci
, "Completed reset device command.\n");
1134 slot_id
= TRB_TO_SLOT_ID(
1135 xhci
->cmd_ring
->dequeue
->generic
.field
[3]);
1136 virt_dev
= xhci
->devs
[slot_id
];
1138 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
);
1140 xhci_warn(xhci
, "Reset device command completion "
1141 "for disabled slot %u\n", slot_id
);
1143 case TRB_TYPE(TRB_NEC_GET_FW
):
1144 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1145 xhci
->error_bitmask
|= 1 << 6;
1148 xhci_dbg(xhci
, "NEC firmware version %2x.%02x\n",
1149 NEC_FW_MAJOR(event
->status
),
1150 NEC_FW_MINOR(event
->status
));
1153 /* Skip over unknown commands on the event ring */
1154 xhci
->error_bitmask
|= 1 << 6;
1157 inc_deq(xhci
, xhci
->cmd_ring
, false);
1160 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1161 union xhci_trb
*event
)
1165 trb_type
= TRB_FIELD_TO_TYPE(event
->generic
.field
[3]);
1166 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1167 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1168 handle_cmd_completion(xhci
, &event
->event_cmd
);
1171 static void handle_port_status(struct xhci_hcd
*xhci
,
1172 union xhci_trb
*event
)
1176 /* Port status change events always have a successful completion code */
1177 if (GET_COMP_CODE(event
->generic
.field
[2]) != COMP_SUCCESS
) {
1178 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
1179 xhci
->error_bitmask
|= 1 << 8;
1181 /* FIXME: core doesn't care about all port link state changes yet */
1182 port_id
= GET_PORT_ID(event
->generic
.field
[0]);
1183 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
1185 /* Update event ring dequeue pointer before dropping the lock */
1186 inc_deq(xhci
, xhci
->event_ring
, true);
1187 xhci_set_hc_event_deq(xhci
);
1189 spin_unlock(&xhci
->lock
);
1190 /* Pass this up to the core */
1191 usb_hcd_poll_rh_status(xhci_to_hcd(xhci
));
1192 spin_lock(&xhci
->lock
);
1196 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1197 * at end_trb, which may be in another segment. If the suspect DMA address is a
1198 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1201 struct xhci_segment
*trb_in_td(struct xhci_segment
*start_seg
,
1202 union xhci_trb
*start_trb
,
1203 union xhci_trb
*end_trb
,
1204 dma_addr_t suspect_dma
)
1206 dma_addr_t start_dma
;
1207 dma_addr_t end_seg_dma
;
1208 dma_addr_t end_trb_dma
;
1209 struct xhci_segment
*cur_seg
;
1211 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1212 cur_seg
= start_seg
;
1217 /* We may get an event for a Link TRB in the middle of a TD */
1218 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1219 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1220 /* If the end TRB isn't in this segment, this is set to 0 */
1221 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1223 if (end_trb_dma
> 0) {
1224 /* The end TRB is in this segment, so suspect should be here */
1225 if (start_dma
<= end_trb_dma
) {
1226 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1229 /* Case for one segment with
1230 * a TD wrapped around to the top
1232 if ((suspect_dma
>= start_dma
&&
1233 suspect_dma
<= end_seg_dma
) ||
1234 (suspect_dma
>= cur_seg
->dma
&&
1235 suspect_dma
<= end_trb_dma
))
1240 /* Might still be somewhere in this segment */
1241 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1244 cur_seg
= cur_seg
->next
;
1245 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1246 } while (cur_seg
!= start_seg
);
1251 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1252 unsigned int slot_id
, unsigned int ep_index
,
1253 unsigned int stream_id
,
1254 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1256 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1257 ep
->ep_state
|= EP_HALTED
;
1258 ep
->stopped_td
= td
;
1259 ep
->stopped_trb
= event_trb
;
1260 ep
->stopped_stream
= stream_id
;
1262 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1263 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1265 ep
->stopped_td
= NULL
;
1266 ep
->stopped_trb
= NULL
;
1267 ep
->stopped_stream
= 0;
1269 xhci_ring_cmd_db(xhci
);
1272 /* Check if an error has halted the endpoint ring. The class driver will
1273 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1274 * However, a babble and other errors also halt the endpoint ring, and the class
1275 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1276 * Ring Dequeue Pointer command manually.
1278 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1279 struct xhci_ep_ctx
*ep_ctx
,
1280 unsigned int trb_comp_code
)
1282 /* TRB completion codes that may require a manual halt cleanup */
1283 if (trb_comp_code
== COMP_TX_ERR
||
1284 trb_comp_code
== COMP_BABBLE
||
1285 trb_comp_code
== COMP_SPLIT_ERR
)
1286 /* The 0.96 spec says a babbling control endpoint
1287 * is not halted. The 0.96 spec says it is. Some HW
1288 * claims to be 0.95 compliant, but it halts the control
1289 * endpoint anyway. Check if a babble halted the
1292 if ((ep_ctx
->ep_info
& EP_STATE_MASK
) == EP_STATE_HALTED
)
1298 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
1300 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1301 /* Vendor defined "informational" completion code,
1302 * treat as not-an-error.
1304 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1306 xhci_dbg(xhci
, "Treating code as success.\n");
1313 * Finish the td processing, remove the td from td list;
1314 * Return 1 if the urb can be given back.
1316 static int finish_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1317 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1318 struct xhci_virt_ep
*ep
, int *status
, bool skip
)
1320 struct xhci_virt_device
*xdev
;
1321 struct xhci_ring
*ep_ring
;
1322 unsigned int slot_id
;
1324 struct urb
*urb
= NULL
;
1325 struct xhci_ep_ctx
*ep_ctx
;
1327 struct urb_priv
*urb_priv
;
1330 slot_id
= TRB_TO_SLOT_ID(event
->flags
);
1331 xdev
= xhci
->devs
[slot_id
];
1332 ep_index
= TRB_TO_EP_ID(event
->flags
) - 1;
1333 ep_ring
= xhci_dma_to_transfer_ring(ep
, event
->buffer
);
1334 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1335 trb_comp_code
= GET_COMP_CODE(event
->transfer_len
);
1340 if (trb_comp_code
== COMP_STOP_INVAL
||
1341 trb_comp_code
== COMP_STOP
) {
1342 /* The Endpoint Stop Command completion will take care of any
1343 * stopped TDs. A stopped TD may be restarted, so don't update
1344 * the ring dequeue pointer or take this TD off any lists yet.
1346 ep
->stopped_td
= td
;
1347 ep
->stopped_trb
= event_trb
;
1350 if (trb_comp_code
== COMP_STALL
) {
1351 /* The transfer is completed from the driver's
1352 * perspective, but we need to issue a set dequeue
1353 * command for this stalled endpoint to move the dequeue
1354 * pointer past the TD. We can't do that here because
1355 * the halt condition must be cleared first. Let the
1356 * USB class driver clear the stall later.
1358 ep
->stopped_td
= td
;
1359 ep
->stopped_trb
= event_trb
;
1360 ep
->stopped_stream
= ep_ring
->stream_id
;
1361 } else if (xhci_requires_manual_halt_cleanup(xhci
,
1362 ep_ctx
, trb_comp_code
)) {
1363 /* Other types of errors halt the endpoint, but the
1364 * class driver doesn't call usb_reset_endpoint() unless
1365 * the error is -EPIPE. Clear the halted status in the
1366 * xHCI hardware manually.
1368 xhci_cleanup_halted_endpoint(xhci
,
1369 slot_id
, ep_index
, ep_ring
->stream_id
,
1372 /* Update ring dequeue pointer */
1373 while (ep_ring
->dequeue
!= td
->last_trb
)
1374 inc_deq(xhci
, ep_ring
, false);
1375 inc_deq(xhci
, ep_ring
, false);
1379 /* Clean up the endpoint's TD list */
1381 urb_priv
= urb
->hcpriv
;
1383 /* Do one last check of the actual transfer length.
1384 * If the host controller said we transferred more data than
1385 * the buffer length, urb->actual_length will be a very big
1386 * number (since it's unsigned). Play it safe and say we didn't
1387 * transfer anything.
1389 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1390 xhci_warn(xhci
, "URB transfer length is wrong, "
1391 "xHC issue? req. len = %u, "
1393 urb
->transfer_buffer_length
,
1394 urb
->actual_length
);
1395 urb
->actual_length
= 0;
1396 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1397 *status
= -EREMOTEIO
;
1401 list_del(&td
->td_list
);
1402 /* Was this TD slated to be cancelled but completed anyway? */
1403 if (!list_empty(&td
->cancelled_td_list
))
1404 list_del(&td
->cancelled_td_list
);
1407 /* Giveback the urb when all the tds are completed */
1408 if (urb_priv
->td_cnt
== urb_priv
->length
)
1416 * Process control tds, update urb status and actual_length.
1418 static int process_ctrl_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1419 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1420 struct xhci_virt_ep
*ep
, int *status
)
1422 struct xhci_virt_device
*xdev
;
1423 struct xhci_ring
*ep_ring
;
1424 unsigned int slot_id
;
1426 struct xhci_ep_ctx
*ep_ctx
;
1429 slot_id
= TRB_TO_SLOT_ID(event
->flags
);
1430 xdev
= xhci
->devs
[slot_id
];
1431 ep_index
= TRB_TO_EP_ID(event
->flags
) - 1;
1432 ep_ring
= xhci_dma_to_transfer_ring(ep
, event
->buffer
);
1433 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1434 trb_comp_code
= GET_COMP_CODE(event
->transfer_len
);
1436 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
1437 switch (trb_comp_code
) {
1439 if (event_trb
== ep_ring
->dequeue
) {
1440 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB "
1441 "without IOC set??\n");
1442 *status
= -ESHUTDOWN
;
1443 } else if (event_trb
!= td
->last_trb
) {
1444 xhci_warn(xhci
, "WARN: Success on ctrl data TRB "
1445 "without IOC set??\n");
1446 *status
= -ESHUTDOWN
;
1448 xhci_dbg(xhci
, "Successful control transfer!\n");
1453 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
1454 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1455 *status
= -EREMOTEIO
;
1460 if (!xhci_requires_manual_halt_cleanup(xhci
,
1461 ep_ctx
, trb_comp_code
))
1463 xhci_dbg(xhci
, "TRB error code %u, "
1464 "halted endpoint index = %u\n",
1465 trb_comp_code
, ep_index
);
1466 /* else fall through */
1468 /* Did we transfer part of the data (middle) phase? */
1469 if (event_trb
!= ep_ring
->dequeue
&&
1470 event_trb
!= td
->last_trb
)
1471 td
->urb
->actual_length
=
1472 td
->urb
->transfer_buffer_length
1473 - TRB_LEN(event
->transfer_len
);
1475 td
->urb
->actual_length
= 0;
1477 xhci_cleanup_halted_endpoint(xhci
,
1478 slot_id
, ep_index
, 0, td
, event_trb
);
1479 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, true);
1482 * Did we transfer any data, despite the errors that might have
1483 * happened? I.e. did we get past the setup stage?
1485 if (event_trb
!= ep_ring
->dequeue
) {
1486 /* The event was for the status stage */
1487 if (event_trb
== td
->last_trb
) {
1488 if (td
->urb
->actual_length
!= 0) {
1489 /* Don't overwrite a previously set error code
1491 if ((*status
== -EINPROGRESS
|| *status
== 0) &&
1492 (td
->urb
->transfer_flags
1493 & URB_SHORT_NOT_OK
))
1494 /* Did we already see a short data
1496 *status
= -EREMOTEIO
;
1498 td
->urb
->actual_length
=
1499 td
->urb
->transfer_buffer_length
;
1502 /* Maybe the event was for the data stage? */
1503 if (trb_comp_code
!= COMP_STOP_INVAL
) {
1504 /* We didn't stop on a link TRB in the middle */
1505 td
->urb
->actual_length
=
1506 td
->urb
->transfer_buffer_length
-
1507 TRB_LEN(event
->transfer_len
);
1508 xhci_dbg(xhci
, "Waiting for status "
1515 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1519 * Process isochronous tds, update urb packet status and actual_length.
1521 static int process_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1522 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1523 struct xhci_virt_ep
*ep
, int *status
)
1525 struct xhci_ring
*ep_ring
;
1526 struct urb_priv
*urb_priv
;
1530 union xhci_trb
*cur_trb
;
1531 struct xhci_segment
*cur_seg
;
1534 ep_ring
= xhci_dma_to_transfer_ring(ep
, event
->buffer
);
1535 trb_comp_code
= GET_COMP_CODE(event
->transfer_len
);
1536 urb_priv
= td
->urb
->hcpriv
;
1537 idx
= urb_priv
->td_cnt
;
1540 /* The transfer is partly done */
1542 td
->urb
->iso_frame_desc
[idx
].status
= -EXDEV
;
1544 /* handle completion code */
1545 switch (trb_comp_code
) {
1547 td
->urb
->iso_frame_desc
[idx
].status
= 0;
1548 xhci_dbg(xhci
, "Successful isoc transfer!\n");
1551 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1552 td
->urb
->iso_frame_desc
[idx
].status
=
1555 td
->urb
->iso_frame_desc
[idx
].status
= 0;
1558 td
->urb
->iso_frame_desc
[idx
].status
= -ECOMM
;
1561 case COMP_BUFF_OVER
:
1563 td
->urb
->iso_frame_desc
[idx
].status
= -EOVERFLOW
;
1567 td
->urb
->iso_frame_desc
[idx
].status
= -EPROTO
;
1571 case COMP_STOP_INVAL
:
1574 td
->urb
->iso_frame_desc
[idx
].status
= -1;
1579 /* calc actual length */
1581 td
->urb
->iso_frame_desc
[idx
].actual_length
= 0;
1582 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, true);
1585 if (trb_comp_code
== COMP_SUCCESS
|| skip_td
== 1) {
1586 td
->urb
->iso_frame_desc
[idx
].actual_length
=
1587 td
->urb
->iso_frame_desc
[idx
].length
;
1588 td
->urb
->actual_length
+=
1589 td
->urb
->iso_frame_desc
[idx
].length
;
1591 for (cur_trb
= ep_ring
->dequeue
,
1592 cur_seg
= ep_ring
->deq_seg
; cur_trb
!= event_trb
;
1593 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1594 if ((cur_trb
->generic
.field
[3] &
1595 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_TR_NOOP
) &&
1596 (cur_trb
->generic
.field
[3] &
1597 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_LINK
))
1599 TRB_LEN(cur_trb
->generic
.field
[2]);
1601 len
+= TRB_LEN(cur_trb
->generic
.field
[2]) -
1602 TRB_LEN(event
->transfer_len
);
1604 if (trb_comp_code
!= COMP_STOP_INVAL
) {
1605 td
->urb
->iso_frame_desc
[idx
].actual_length
= len
;
1606 td
->urb
->actual_length
+= len
;
1610 if ((idx
== urb_priv
->length
- 1) && *status
== -EINPROGRESS
)
1613 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1617 * Process bulk and interrupt tds, update urb status and actual_length.
1619 static int process_bulk_intr_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1620 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1621 struct xhci_virt_ep
*ep
, int *status
)
1623 struct xhci_ring
*ep_ring
;
1624 union xhci_trb
*cur_trb
;
1625 struct xhci_segment
*cur_seg
;
1628 ep_ring
= xhci_dma_to_transfer_ring(ep
, event
->buffer
);
1629 trb_comp_code
= GET_COMP_CODE(event
->transfer_len
);
1631 switch (trb_comp_code
) {
1633 /* Double check that the HW transferred everything. */
1634 if (event_trb
!= td
->last_trb
) {
1635 xhci_warn(xhci
, "WARN Successful completion "
1637 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1638 *status
= -EREMOTEIO
;
1642 if (usb_endpoint_xfer_bulk(&td
->urb
->ep
->desc
))
1643 xhci_dbg(xhci
, "Successful bulk "
1646 xhci_dbg(xhci
, "Successful interrupt "
1652 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1653 *status
= -EREMOTEIO
;
1658 /* Others already handled above */
1661 dev_dbg(&td
->urb
->dev
->dev
,
1662 "ep %#x - asked for %d bytes, "
1663 "%d bytes untransferred\n",
1664 td
->urb
->ep
->desc
.bEndpointAddress
,
1665 td
->urb
->transfer_buffer_length
,
1666 TRB_LEN(event
->transfer_len
));
1667 /* Fast path - was this the last TRB in the TD for this URB? */
1668 if (event_trb
== td
->last_trb
) {
1669 if (TRB_LEN(event
->transfer_len
) != 0) {
1670 td
->urb
->actual_length
=
1671 td
->urb
->transfer_buffer_length
-
1672 TRB_LEN(event
->transfer_len
);
1673 if (td
->urb
->transfer_buffer_length
<
1674 td
->urb
->actual_length
) {
1675 xhci_warn(xhci
, "HC gave bad length "
1676 "of %d bytes left\n",
1677 TRB_LEN(event
->transfer_len
));
1678 td
->urb
->actual_length
= 0;
1679 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1680 *status
= -EREMOTEIO
;
1684 /* Don't overwrite a previously set error code */
1685 if (*status
== -EINPROGRESS
) {
1686 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1687 *status
= -EREMOTEIO
;
1692 td
->urb
->actual_length
=
1693 td
->urb
->transfer_buffer_length
;
1694 /* Ignore a short packet completion if the
1695 * untransferred length was zero.
1697 if (*status
== -EREMOTEIO
)
1701 /* Slow path - walk the list, starting from the dequeue
1702 * pointer, to get the actual length transferred.
1704 td
->urb
->actual_length
= 0;
1705 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1706 cur_trb
!= event_trb
;
1707 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1708 if ((cur_trb
->generic
.field
[3] &
1709 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_TR_NOOP
) &&
1710 (cur_trb
->generic
.field
[3] &
1711 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_LINK
))
1712 td
->urb
->actual_length
+=
1713 TRB_LEN(cur_trb
->generic
.field
[2]);
1715 /* If the ring didn't stop on a Link or No-op TRB, add
1716 * in the actual bytes transferred from the Normal TRB
1718 if (trb_comp_code
!= COMP_STOP_INVAL
)
1719 td
->urb
->actual_length
+=
1720 TRB_LEN(cur_trb
->generic
.field
[2]) -
1721 TRB_LEN(event
->transfer_len
);
1724 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1728 * If this function returns an error condition, it means it got a Transfer
1729 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1730 * At this point, the host controller is probably hosed and should be reset.
1732 static int handle_tx_event(struct xhci_hcd
*xhci
,
1733 struct xhci_transfer_event
*event
)
1735 struct xhci_virt_device
*xdev
;
1736 struct xhci_virt_ep
*ep
;
1737 struct xhci_ring
*ep_ring
;
1738 unsigned int slot_id
;
1740 struct xhci_td
*td
= NULL
;
1741 dma_addr_t event_dma
;
1742 struct xhci_segment
*event_seg
;
1743 union xhci_trb
*event_trb
;
1744 struct urb
*urb
= NULL
;
1745 int status
= -EINPROGRESS
;
1746 struct urb_priv
*urb_priv
;
1747 struct xhci_ep_ctx
*ep_ctx
;
1751 slot_id
= TRB_TO_SLOT_ID(event
->flags
);
1752 xdev
= xhci
->devs
[slot_id
];
1754 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
1758 /* Endpoint ID is 1 based, our index is zero based */
1759 ep_index
= TRB_TO_EP_ID(event
->flags
) - 1;
1760 xhci_dbg(xhci
, "%s - ep index = %d\n", __func__
, ep_index
);
1761 ep
= &xdev
->eps
[ep_index
];
1762 ep_ring
= xhci_dma_to_transfer_ring(ep
, event
->buffer
);
1763 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1765 (ep_ctx
->ep_info
& EP_STATE_MASK
) == EP_STATE_DISABLED
) {
1766 xhci_err(xhci
, "ERROR Transfer event for disabled endpoint "
1767 "or incorrect stream ring\n");
1771 event_dma
= event
->buffer
;
1772 trb_comp_code
= GET_COMP_CODE(event
->transfer_len
);
1773 /* Look for common error cases */
1774 switch (trb_comp_code
) {
1775 /* Skip codes that require special handling depending on
1782 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
1784 case COMP_STOP_INVAL
:
1785 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
1788 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
1789 ep
->ep_state
|= EP_HALTED
;
1793 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
1796 case COMP_SPLIT_ERR
:
1798 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
1802 xhci_warn(xhci
, "WARN: babble error on endpoint\n");
1803 status
= -EOVERFLOW
;
1806 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
1810 xhci_warn(xhci
, "WARN: bandwidth overrun event on endpoint\n");
1812 case COMP_BUFF_OVER
:
1813 xhci_warn(xhci
, "WARN: buffer overrun event on endpoint\n");
1817 * When the Isoch ring is empty, the xHC will generate
1818 * a Ring Overrun Event for IN Isoch endpoint or Ring
1819 * Underrun Event for OUT Isoch endpoint.
1821 xhci_dbg(xhci
, "underrun event on endpoint\n");
1822 if (!list_empty(&ep_ring
->td_list
))
1823 xhci_dbg(xhci
, "Underrun Event for slot %d ep %d "
1824 "still with TDs queued?\n",
1825 TRB_TO_SLOT_ID(event
->flags
), ep_index
);
1828 xhci_dbg(xhci
, "overrun event on endpoint\n");
1829 if (!list_empty(&ep_ring
->td_list
))
1830 xhci_dbg(xhci
, "Overrun Event for slot %d ep %d "
1831 "still with TDs queued?\n",
1832 TRB_TO_SLOT_ID(event
->flags
), ep_index
);
1834 case COMP_MISSED_INT
:
1836 * When encounter missed service error, one or more isoc tds
1837 * may be missed by xHC.
1838 * Set skip flag of the ep_ring; Complete the missed tds as
1839 * short transfer when process the ep_ring next time.
1842 xhci_dbg(xhci
, "Miss service interval error, set skip flag\n");
1845 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
1849 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably "
1855 /* This TRB should be in the TD at the head of this ring's
1858 if (list_empty(&ep_ring
->td_list
)) {
1859 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d "
1860 "with no TDs queued?\n",
1861 TRB_TO_SLOT_ID(event
->flags
), ep_index
);
1862 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
1863 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
1864 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
1867 xhci_dbg(xhci
, "td_list is empty while skip "
1868 "flag set. Clear skip flag.\n");
1874 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
1875 /* Is this a TRB in the currently executing TD? */
1876 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
1877 td
->last_trb
, event_dma
);
1878 if (event_seg
&& ep
->skip
) {
1879 xhci_dbg(xhci
, "Found td. Clear skip flag.\n");
1883 (!ep
->skip
|| !usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))) {
1884 /* HC is busted, give up! */
1885 xhci_err(xhci
, "ERROR Transfer event TRB DMA ptr not "
1886 "part of current TD\n");
1891 event_trb
= &event_seg
->trbs
[(event_dma
-
1892 event_seg
->dma
) / sizeof(*event_trb
)];
1894 * No-op TRB should not trigger interrupts.
1895 * If event_trb is a no-op TRB, it means the
1896 * corresponding TD has been cancelled. Just ignore
1899 if ((event_trb
->generic
.field
[3] & TRB_TYPE_BITMASK
)
1900 == TRB_TYPE(TRB_TR_NOOP
)) {
1901 xhci_dbg(xhci
, "event_trb is a no-op TRB. "
1907 /* Now update the urb's actual_length and give back to
1910 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
))
1911 ret
= process_ctrl_td(xhci
, td
, event_trb
, event
, ep
,
1913 else if (usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))
1914 ret
= process_isoc_td(xhci
, td
, event_trb
, event
, ep
,
1917 ret
= process_bulk_intr_td(xhci
, td
, event_trb
, event
,
1922 * Do not update event ring dequeue pointer if ep->skip is set.
1923 * Will roll back to continue process missed tds.
1925 if (trb_comp_code
== COMP_MISSED_INT
|| !ep
->skip
) {
1926 inc_deq(xhci
, xhci
->event_ring
, true);
1927 xhci_set_hc_event_deq(xhci
);
1932 urb_priv
= urb
->hcpriv
;
1933 /* Leave the TD around for the reset endpoint function
1934 * to use(but only if it's not a control endpoint,
1935 * since we already queued the Set TR dequeue pointer
1936 * command for stalled control endpoints).
1938 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
1939 (trb_comp_code
!= COMP_STALL
&&
1940 trb_comp_code
!= COMP_BABBLE
))
1941 xhci_urb_free_priv(xhci
, urb_priv
);
1943 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), urb
);
1944 xhci_dbg(xhci
, "Giveback URB %p, len = %d, "
1946 urb
, urb
->actual_length
, status
);
1947 spin_unlock(&xhci
->lock
);
1948 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), urb
, status
);
1949 spin_lock(&xhci
->lock
);
1953 * If ep->skip is set, it means there are missed tds on the
1954 * endpoint ring need to take care of.
1955 * Process them as short transfer until reach the td pointed by
1958 } while (ep
->skip
&& trb_comp_code
!= COMP_MISSED_INT
);
1964 * This function handles all OS-owned events on the event ring. It may drop
1965 * xhci->lock between event processing (e.g. to pass up port status changes).
1967 static void xhci_handle_event(struct xhci_hcd
*xhci
)
1969 union xhci_trb
*event
;
1970 int update_ptrs
= 1;
1973 xhci_dbg(xhci
, "In %s\n", __func__
);
1974 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
1975 xhci
->error_bitmask
|= 1 << 1;
1979 event
= xhci
->event_ring
->dequeue
;
1980 /* Does the HC or OS own the TRB? */
1981 if ((event
->event_cmd
.flags
& TRB_CYCLE
) !=
1982 xhci
->event_ring
->cycle_state
) {
1983 xhci
->error_bitmask
|= 1 << 2;
1986 xhci_dbg(xhci
, "%s - OS owns TRB\n", __func__
);
1988 /* FIXME: Handle more event types. */
1989 switch ((event
->event_cmd
.flags
& TRB_TYPE_BITMASK
)) {
1990 case TRB_TYPE(TRB_COMPLETION
):
1991 xhci_dbg(xhci
, "%s - calling handle_cmd_completion\n", __func__
);
1992 handle_cmd_completion(xhci
, &event
->event_cmd
);
1993 xhci_dbg(xhci
, "%s - returned from handle_cmd_completion\n", __func__
);
1995 case TRB_TYPE(TRB_PORT_STATUS
):
1996 xhci_dbg(xhci
, "%s - calling handle_port_status\n", __func__
);
1997 handle_port_status(xhci
, event
);
1998 xhci_dbg(xhci
, "%s - returned from handle_port_status\n", __func__
);
2001 case TRB_TYPE(TRB_TRANSFER
):
2002 xhci_dbg(xhci
, "%s - calling handle_tx_event\n", __func__
);
2003 ret
= handle_tx_event(xhci
, &event
->trans_event
);
2004 xhci_dbg(xhci
, "%s - returned from handle_tx_event\n", __func__
);
2006 xhci
->error_bitmask
|= 1 << 9;
2011 if ((event
->event_cmd
.flags
& TRB_TYPE_BITMASK
) >= TRB_TYPE(48))
2012 handle_vendor_event(xhci
, event
);
2014 xhci
->error_bitmask
|= 1 << 3;
2016 /* Any of the above functions may drop and re-acquire the lock, so check
2017 * to make sure a watchdog timer didn't mark the host as non-responsive.
2019 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2020 xhci_dbg(xhci
, "xHCI host dying, returning from "
2021 "event handler.\n");
2026 /* Update SW and HC event ring dequeue pointer */
2027 inc_deq(xhci
, xhci
->event_ring
, true);
2028 xhci_set_hc_event_deq(xhci
);
2030 /* Are there more items on the event ring? */
2031 xhci_handle_event(xhci
);
2035 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2036 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2037 * indicators of an event TRB error, but we check the status *first* to be safe.
2039 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
)
2041 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
2042 u32 status
, irq_pending
;
2043 union xhci_trb
*trb
;
2046 spin_lock(&xhci
->lock
);
2047 trb
= xhci
->event_ring
->dequeue
;
2048 /* Check if the xHC generated the interrupt, or the irq is shared */
2049 status
= xhci_readl(xhci
, &xhci
->op_regs
->status
);
2050 irq_pending
= xhci_readl(xhci
, &xhci
->ir_set
->irq_pending
);
2051 if (status
== 0xffffffff && irq_pending
== 0xffffffff)
2054 if (!(status
& STS_EINT
) && !ER_IRQ_PENDING(irq_pending
)) {
2055 spin_unlock(&xhci
->lock
);
2056 xhci_warn(xhci
, "Spurious interrupt.\n");
2059 xhci_dbg(xhci
, "op reg status = %08x\n", status
);
2060 xhci_dbg(xhci
, "ir set irq_pending = %08x\n", irq_pending
);
2061 xhci_dbg(xhci
, "Event ring dequeue ptr:\n");
2062 xhci_dbg(xhci
, "@%llx %08x %08x %08x %08x\n",
2063 (unsigned long long)
2064 xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
, trb
),
2065 lower_32_bits(trb
->link
.segment_ptr
),
2066 upper_32_bits(trb
->link
.segment_ptr
),
2067 (unsigned int) trb
->link
.intr_target
,
2068 (unsigned int) trb
->link
.control
);
2070 if (status
& STS_FATAL
) {
2071 xhci_warn(xhci
, "WARNING: Host System Error\n");
2074 xhci_to_hcd(xhci
)->state
= HC_STATE_HALT
;
2075 spin_unlock(&xhci
->lock
);
2080 * Clear the op reg interrupt status first,
2081 * so we can receive interrupts from other MSI-X interrupters.
2082 * Write 1 to clear the interrupt status.
2085 xhci_writel(xhci
, status
, &xhci
->op_regs
->status
);
2086 /* FIXME when MSI-X is supported and there are multiple vectors */
2087 /* Clear the MSI-X event interrupt status */
2089 /* Acknowledge the interrupt */
2091 xhci_writel(xhci
, irq_pending
, &xhci
->ir_set
->irq_pending
);
2093 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
2094 xhci_dbg(xhci
, "xHCI dying, ignoring interrupt. "
2095 "Shouldn't IRQs be disabled?\n");
2097 /* FIXME this should be a delayed service routine
2098 * that clears the EHB.
2100 xhci_handle_event(xhci
);
2102 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2103 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2104 xhci_write_64(xhci
, temp_64
| ERST_EHB
, &xhci
->ir_set
->erst_dequeue
);
2105 spin_unlock(&xhci
->lock
);
2110 irqreturn_t
xhci_msi_irq(int irq
, struct usb_hcd
*hcd
)
2114 set_bit(HCD_FLAG_SAW_IRQ
, &hcd
->flags
);
2116 ret
= xhci_irq(hcd
);
2121 /**** Endpoint Ring Operations ****/
2124 * Generic function for queueing a TRB on a ring.
2125 * The caller must have checked to make sure there's room on the ring.
2127 * @more_trbs_coming: Will you enqueue more TRBs before calling
2128 * prepare_transfer()?
2130 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
2131 bool consumer
, bool more_trbs_coming
,
2132 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
2134 struct xhci_generic_trb
*trb
;
2136 trb
= &ring
->enqueue
->generic
;
2137 trb
->field
[0] = field1
;
2138 trb
->field
[1] = field2
;
2139 trb
->field
[2] = field3
;
2140 trb
->field
[3] = field4
;
2141 inc_enq(xhci
, ring
, consumer
, more_trbs_coming
);
2145 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2146 * FIXME allocate segments if the ring is full.
2148 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
2149 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
2151 /* Make sure the endpoint has been added to xHC schedule */
2152 xhci_dbg(xhci
, "Endpoint state = 0x%x\n", ep_state
);
2154 case EP_STATE_DISABLED
:
2156 * USB core changed config/interfaces without notifying us,
2157 * or hardware is reporting the wrong state.
2159 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
2161 case EP_STATE_ERROR
:
2162 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
2163 /* FIXME event handling code for error needs to clear it */
2164 /* XXX not sure if this should be -ENOENT or not */
2166 case EP_STATE_HALTED
:
2167 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
2168 case EP_STATE_STOPPED
:
2169 case EP_STATE_RUNNING
:
2172 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
2174 * FIXME issue Configure Endpoint command to try to get the HC
2175 * back into a known state.
2179 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
2180 /* FIXME allocate more room */
2181 xhci_err(xhci
, "ERROR no room on ep ring\n");
2185 if (enqueue_is_link_trb(ep_ring
)) {
2186 struct xhci_ring
*ring
= ep_ring
;
2187 union xhci_trb
*next
;
2189 xhci_dbg(xhci
, "prepare_ring: pointing to link trb\n");
2190 next
= ring
->enqueue
;
2192 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
2194 /* If we're not dealing with 0.95 hardware,
2195 * clear the chain bit.
2197 if (!xhci_link_trb_quirk(xhci
))
2198 next
->link
.control
&= ~TRB_CHAIN
;
2200 next
->link
.control
|= TRB_CHAIN
;
2203 next
->link
.control
^= (u32
) TRB_CYCLE
;
2205 /* Toggle the cycle bit after the last ring segment. */
2206 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
2207 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
2208 if (!in_interrupt()) {
2209 xhci_dbg(xhci
, "queue_trb: Toggle cycle "
2210 "state for ring %p = %i\n",
2211 ring
, (unsigned int)ring
->cycle_state
);
2214 ring
->enq_seg
= ring
->enq_seg
->next
;
2215 ring
->enqueue
= ring
->enq_seg
->trbs
;
2216 next
= ring
->enqueue
;
2223 static int prepare_transfer(struct xhci_hcd
*xhci
,
2224 struct xhci_virt_device
*xdev
,
2225 unsigned int ep_index
,
2226 unsigned int stream_id
,
2227 unsigned int num_trbs
,
2229 unsigned int td_index
,
2233 struct urb_priv
*urb_priv
;
2235 struct xhci_ring
*ep_ring
;
2236 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2238 ep_ring
= xhci_stream_id_to_ring(xdev
, ep_index
, stream_id
);
2240 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
2245 ret
= prepare_ring(xhci
, ep_ring
,
2246 ep_ctx
->ep_info
& EP_STATE_MASK
,
2247 num_trbs
, mem_flags
);
2251 urb_priv
= urb
->hcpriv
;
2252 td
= urb_priv
->td
[td_index
];
2254 INIT_LIST_HEAD(&td
->td_list
);
2255 INIT_LIST_HEAD(&td
->cancelled_td_list
);
2257 if (td_index
== 0) {
2258 ret
= usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci
), urb
);
2259 if (unlikely(ret
)) {
2260 xhci_urb_free_priv(xhci
, urb_priv
);
2267 /* Add this TD to the tail of the endpoint ring's TD list */
2268 list_add_tail(&td
->td_list
, &ep_ring
->td_list
);
2269 td
->start_seg
= ep_ring
->enq_seg
;
2270 td
->first_trb
= ep_ring
->enqueue
;
2272 urb_priv
->td
[td_index
] = td
;
2277 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
2279 int num_sgs
, num_trbs
, running_total
, temp
, i
;
2280 struct scatterlist
*sg
;
2283 num_sgs
= urb
->num_sgs
;
2284 temp
= urb
->transfer_buffer_length
;
2286 xhci_dbg(xhci
, "count sg list trbs: \n");
2288 for_each_sg(urb
->sg
, sg
, num_sgs
, i
) {
2289 unsigned int previous_total_trbs
= num_trbs
;
2290 unsigned int len
= sg_dma_len(sg
);
2292 /* Scatter gather list entries may cross 64KB boundaries */
2293 running_total
= TRB_MAX_BUFF_SIZE
-
2294 (sg_dma_address(sg
) & ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
2295 if (running_total
!= 0)
2298 /* How many more 64KB chunks to transfer, how many more TRBs? */
2299 while (running_total
< sg_dma_len(sg
)) {
2301 running_total
+= TRB_MAX_BUFF_SIZE
;
2303 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2304 i
, (unsigned long long)sg_dma_address(sg
),
2305 len
, len
, num_trbs
- previous_total_trbs
);
2307 len
= min_t(int, len
, temp
);
2312 xhci_dbg(xhci
, "\n");
2313 if (!in_interrupt())
2314 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
2315 urb
->ep
->desc
.bEndpointAddress
,
2316 urb
->transfer_buffer_length
,
2321 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
2324 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
2325 "TRBs, %d left\n", __func__
,
2326 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
2327 if (running_total
!= urb
->transfer_buffer_length
)
2328 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
2329 "queued %#x (%d), asked for %#x (%d)\n",
2331 urb
->ep
->desc
.bEndpointAddress
,
2332 running_total
, running_total
,
2333 urb
->transfer_buffer_length
,
2334 urb
->transfer_buffer_length
);
2337 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
2338 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
2339 struct xhci_generic_trb
*start_trb
, struct xhci_td
*td
)
2342 * Pass all the TRBs to the hardware at once and make sure this write
2346 start_trb
->field
[3] |= start_cycle
;
2347 ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
2351 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2352 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2353 * (comprised of sg list entries) can take several service intervals to
2356 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2357 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2359 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
2360 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
2364 xhci_interval
= EP_INTERVAL_TO_UFRAMES(ep_ctx
->ep_info
);
2365 ep_interval
= urb
->interval
;
2366 /* Convert to microframes */
2367 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2368 urb
->dev
->speed
== USB_SPEED_FULL
)
2370 /* FIXME change this to a warning and a suggestion to use the new API
2371 * to set the polling interval (once the API is added).
2373 if (xhci_interval
!= ep_interval
) {
2374 if (!printk_ratelimit())
2375 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
2376 " (%d microframe%s) than xHCI "
2377 "(%d microframe%s)\n",
2379 ep_interval
== 1 ? "" : "s",
2381 xhci_interval
== 1 ? "" : "s");
2382 urb
->interval
= xhci_interval
;
2383 /* Convert back to frames for LS/FS devices */
2384 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2385 urb
->dev
->speed
== USB_SPEED_FULL
)
2388 return xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
2392 * The TD size is the number of bytes remaining in the TD (including this TRB),
2393 * right shifted by 10.
2394 * It must fit in bits 21:17, so it can't be bigger than 31.
2396 static u32
xhci_td_remainder(unsigned int remainder
)
2398 u32 max
= (1 << (21 - 17 + 1)) - 1;
2400 if ((remainder
>> 10) >= max
)
2403 return (remainder
>> 10) << 17;
2406 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2407 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2409 struct xhci_ring
*ep_ring
;
2410 unsigned int num_trbs
;
2411 struct urb_priv
*urb_priv
;
2413 struct scatterlist
*sg
;
2415 int trb_buff_len
, this_sg_len
, running_total
;
2418 bool more_trbs_coming
;
2420 struct xhci_generic_trb
*start_trb
;
2423 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2427 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
2428 num_sgs
= urb
->num_sgs
;
2430 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2431 ep_index
, urb
->stream_id
,
2432 num_trbs
, urb
, 0, mem_flags
);
2433 if (trb_buff_len
< 0)
2434 return trb_buff_len
;
2436 urb_priv
= urb
->hcpriv
;
2437 td
= urb_priv
->td
[0];
2440 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2441 * until we've finished creating all the other TRBs. The ring's cycle
2442 * state may change as we enqueue the other TRBs, so save it too.
2444 start_trb
= &ep_ring
->enqueue
->generic
;
2445 start_cycle
= ep_ring
->cycle_state
;
2449 * How much data is in the first TRB?
2451 * There are three forces at work for TRB buffer pointers and lengths:
2452 * 1. We don't want to walk off the end of this sg-list entry buffer.
2453 * 2. The transfer length that the driver requested may be smaller than
2454 * the amount of memory allocated for this scatter-gather list.
2455 * 3. TRBs buffers can't cross 64KB boundaries.
2458 addr
= (u64
) sg_dma_address(sg
);
2459 this_sg_len
= sg_dma_len(sg
);
2460 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2461 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
2462 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2463 if (trb_buff_len
> urb
->transfer_buffer_length
)
2464 trb_buff_len
= urb
->transfer_buffer_length
;
2465 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
2469 /* Queue the first TRB, even if it's zero-length */
2472 u32 length_field
= 0;
2475 /* Don't change the cycle bit of the first TRB until later */
2479 field
|= ep_ring
->cycle_state
;
2481 /* Chain all the TRBs together; clear the chain bit in the last
2482 * TRB to indicate it's the last TRB in the chain.
2487 /* FIXME - add check for ZERO_PACKET flag before this */
2488 td
->last_trb
= ep_ring
->enqueue
;
2491 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
2492 "64KB boundary at %#x, end dma = %#x\n",
2493 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
2494 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
2495 (unsigned int) addr
+ trb_buff_len
);
2496 if (TRB_MAX_BUFF_SIZE
-
2497 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1)) < trb_buff_len
) {
2498 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2499 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
2500 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
2501 (unsigned int) addr
+ trb_buff_len
);
2503 remainder
= xhci_td_remainder(urb
->transfer_buffer_length
-
2505 length_field
= TRB_LEN(trb_buff_len
) |
2509 more_trbs_coming
= true;
2511 more_trbs_coming
= false;
2512 queue_trb(xhci
, ep_ring
, false, more_trbs_coming
,
2513 lower_32_bits(addr
),
2514 upper_32_bits(addr
),
2516 /* We always want to know if the TRB was short,
2517 * or we won't get an event when it completes.
2518 * (Unless we use event data TRBs, which are a
2519 * waste of space and HC resources.)
2521 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
2523 running_total
+= trb_buff_len
;
2525 /* Calculate length for next transfer --
2526 * Are we done queueing all the TRBs for this sg entry?
2528 this_sg_len
-= trb_buff_len
;
2529 if (this_sg_len
== 0) {
2534 addr
= (u64
) sg_dma_address(sg
);
2535 this_sg_len
= sg_dma_len(sg
);
2537 addr
+= trb_buff_len
;
2540 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2541 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
2542 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2543 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
2545 urb
->transfer_buffer_length
- running_total
;
2546 } while (running_total
< urb
->transfer_buffer_length
);
2548 check_trb_math(urb
, num_trbs
, running_total
);
2549 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
2550 start_cycle
, start_trb
, td
);
2554 /* This is very similar to what ehci-q.c qtd_fill() does */
2555 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2556 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2558 struct xhci_ring
*ep_ring
;
2559 struct urb_priv
*urb_priv
;
2562 struct xhci_generic_trb
*start_trb
;
2564 bool more_trbs_coming
;
2566 u32 field
, length_field
;
2568 int running_total
, trb_buff_len
, ret
;
2572 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
2574 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2579 /* How much data is (potentially) left before the 64KB boundary? */
2580 running_total
= TRB_MAX_BUFF_SIZE
-
2581 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
2583 /* If there's some data on this 64KB chunk, or we have to send a
2584 * zero-length transfer, we need at least one TRB
2586 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
2588 /* How many more 64KB chunks to transfer, how many more TRBs? */
2589 while (running_total
< urb
->transfer_buffer_length
) {
2591 running_total
+= TRB_MAX_BUFF_SIZE
;
2593 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2595 if (!in_interrupt())
2596 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
2597 urb
->ep
->desc
.bEndpointAddress
,
2598 urb
->transfer_buffer_length
,
2599 urb
->transfer_buffer_length
,
2600 (unsigned long long)urb
->transfer_dma
,
2603 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2604 ep_index
, urb
->stream_id
,
2605 num_trbs
, urb
, 0, mem_flags
);
2609 urb_priv
= urb
->hcpriv
;
2610 td
= urb_priv
->td
[0];
2613 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2614 * until we've finished creating all the other TRBs. The ring's cycle
2615 * state may change as we enqueue the other TRBs, so save it too.
2617 start_trb
= &ep_ring
->enqueue
->generic
;
2618 start_cycle
= ep_ring
->cycle_state
;
2621 /* How much data is in the first TRB? */
2622 addr
= (u64
) urb
->transfer_dma
;
2623 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2624 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
2625 if (urb
->transfer_buffer_length
< trb_buff_len
)
2626 trb_buff_len
= urb
->transfer_buffer_length
;
2630 /* Queue the first TRB, even if it's zero-length */
2635 /* Don't change the cycle bit of the first TRB until later */
2639 field
|= ep_ring
->cycle_state
;
2641 /* Chain all the TRBs together; clear the chain bit in the last
2642 * TRB to indicate it's the last TRB in the chain.
2647 /* FIXME - add check for ZERO_PACKET flag before this */
2648 td
->last_trb
= ep_ring
->enqueue
;
2651 remainder
= xhci_td_remainder(urb
->transfer_buffer_length
-
2653 length_field
= TRB_LEN(trb_buff_len
) |
2657 more_trbs_coming
= true;
2659 more_trbs_coming
= false;
2660 queue_trb(xhci
, ep_ring
, false, more_trbs_coming
,
2661 lower_32_bits(addr
),
2662 upper_32_bits(addr
),
2664 /* We always want to know if the TRB was short,
2665 * or we won't get an event when it completes.
2666 * (Unless we use event data TRBs, which are a
2667 * waste of space and HC resources.)
2669 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
2671 running_total
+= trb_buff_len
;
2673 /* Calculate length for next transfer */
2674 addr
+= trb_buff_len
;
2675 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
2676 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
2677 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
2678 } while (running_total
< urb
->transfer_buffer_length
);
2680 check_trb_math(urb
, num_trbs
, running_total
);
2681 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
2682 start_cycle
, start_trb
, td
);
2686 /* Caller must have locked xhci->lock */
2687 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2688 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2690 struct xhci_ring
*ep_ring
;
2693 struct usb_ctrlrequest
*setup
;
2694 struct xhci_generic_trb
*start_trb
;
2696 u32 field
, length_field
;
2697 struct urb_priv
*urb_priv
;
2700 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2705 * Need to copy setup packet into setup TRB, so we can't use the setup
2708 if (!urb
->setup_packet
)
2711 if (!in_interrupt())
2712 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
2714 /* 1 TRB for setup, 1 for status */
2717 * Don't need to check if we need additional event data and normal TRBs,
2718 * since data in control transfers will never get bigger than 16MB
2719 * XXX: can we get a buffer that crosses 64KB boundaries?
2721 if (urb
->transfer_buffer_length
> 0)
2723 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2724 ep_index
, urb
->stream_id
,
2725 num_trbs
, urb
, 0, mem_flags
);
2729 urb_priv
= urb
->hcpriv
;
2730 td
= urb_priv
->td
[0];
2733 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2734 * until we've finished creating all the other TRBs. The ring's cycle
2735 * state may change as we enqueue the other TRBs, so save it too.
2737 start_trb
= &ep_ring
->enqueue
->generic
;
2738 start_cycle
= ep_ring
->cycle_state
;
2740 /* Queue setup TRB - see section 6.4.1.2.1 */
2741 /* FIXME better way to translate setup_packet into two u32 fields? */
2742 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
2743 queue_trb(xhci
, ep_ring
, false, true,
2744 /* FIXME endianness is probably going to bite my ass here. */
2745 setup
->bRequestType
| setup
->bRequest
<< 8 | setup
->wValue
<< 16,
2746 setup
->wIndex
| setup
->wLength
<< 16,
2747 TRB_LEN(8) | TRB_INTR_TARGET(0),
2748 /* Immediate data in pointer */
2749 TRB_IDT
| TRB_TYPE(TRB_SETUP
));
2751 /* If there's data, queue data TRBs */
2753 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
2754 xhci_td_remainder(urb
->transfer_buffer_length
) |
2756 if (urb
->transfer_buffer_length
> 0) {
2757 if (setup
->bRequestType
& USB_DIR_IN
)
2758 field
|= TRB_DIR_IN
;
2759 queue_trb(xhci
, ep_ring
, false, true,
2760 lower_32_bits(urb
->transfer_dma
),
2761 upper_32_bits(urb
->transfer_dma
),
2763 /* Event on short tx */
2764 field
| TRB_ISP
| TRB_TYPE(TRB_DATA
) | ep_ring
->cycle_state
);
2767 /* Save the DMA address of the last TRB in the TD */
2768 td
->last_trb
= ep_ring
->enqueue
;
2770 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2771 /* If the device sent data, the status stage is an OUT transfer */
2772 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
2776 queue_trb(xhci
, ep_ring
, false, false,
2780 /* Event on completion */
2781 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
2783 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
2784 start_cycle
, start_trb
, td
);
2788 static int count_isoc_trbs_needed(struct xhci_hcd
*xhci
,
2789 struct urb
*urb
, int i
)
2792 u64 addr
, td_len
, running_total
;
2794 addr
= (u64
) (urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
2795 td_len
= urb
->iso_frame_desc
[i
].length
;
2797 running_total
= TRB_MAX_BUFF_SIZE
-
2798 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
2799 if (running_total
!= 0)
2802 while (running_total
< td_len
) {
2804 running_total
+= TRB_MAX_BUFF_SIZE
;
2810 /* This is for isoc transfer */
2811 static int xhci_queue_isoc_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2812 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2814 struct xhci_ring
*ep_ring
;
2815 struct urb_priv
*urb_priv
;
2817 int num_tds
, trbs_per_td
;
2818 struct xhci_generic_trb
*start_trb
;
2821 u32 field
, length_field
;
2822 int running_total
, trb_buff_len
, td_len
, td_remain_len
, ret
;
2823 u64 start_addr
, addr
;
2826 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
2828 num_tds
= urb
->number_of_packets
;
2830 xhci_dbg(xhci
, "Isoc URB with zero packets?\n");
2834 if (!in_interrupt())
2835 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %#x (%d),"
2836 " addr = %#llx, num_tds = %d\n",
2837 urb
->ep
->desc
.bEndpointAddress
,
2838 urb
->transfer_buffer_length
,
2839 urb
->transfer_buffer_length
,
2840 (unsigned long long)urb
->transfer_dma
,
2843 start_addr
= (u64
) urb
->transfer_dma
;
2844 start_trb
= &ep_ring
->enqueue
->generic
;
2845 start_cycle
= ep_ring
->cycle_state
;
2847 /* Queue the first TRB, even if it's zero-length */
2848 for (i
= 0; i
< num_tds
; i
++) {
2852 addr
= start_addr
+ urb
->iso_frame_desc
[i
].offset
;
2853 td_len
= urb
->iso_frame_desc
[i
].length
;
2854 td_remain_len
= td_len
;
2856 trbs_per_td
= count_isoc_trbs_needed(xhci
, urb
, i
);
2858 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
2859 urb
->stream_id
, trbs_per_td
, urb
, i
, mem_flags
);
2863 urb_priv
= urb
->hcpriv
;
2864 td
= urb_priv
->td
[i
];
2866 for (j
= 0; j
< trbs_per_td
; j
++) {
2871 /* Queue the isoc TRB */
2872 field
|= TRB_TYPE(TRB_ISOC
);
2873 /* Assume URB_ISO_ASAP is set */
2876 field
|= ep_ring
->cycle_state
;
2879 /* Queue other normal TRBs */
2880 field
|= TRB_TYPE(TRB_NORMAL
);
2881 field
|= ep_ring
->cycle_state
;
2884 /* Chain all the TRBs together; clear the chain bit in
2885 * the last TRB to indicate it's the last TRB in the
2888 if (j
< trbs_per_td
- 1) {
2891 td
->last_trb
= ep_ring
->enqueue
;
2895 /* Calculate TRB length */
2896 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2897 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
2898 if (trb_buff_len
> td_remain_len
)
2899 trb_buff_len
= td_remain_len
;
2901 remainder
= xhci_td_remainder(td_len
- running_total
);
2902 length_field
= TRB_LEN(trb_buff_len
) |
2905 queue_trb(xhci
, ep_ring
, false, false,
2906 lower_32_bits(addr
),
2907 upper_32_bits(addr
),
2909 /* We always want to know if the TRB was short,
2910 * or we won't get an event when it completes.
2911 * (Unless we use event data TRBs, which are a
2912 * waste of space and HC resources.)
2915 running_total
+= trb_buff_len
;
2917 addr
+= trb_buff_len
;
2918 td_remain_len
-= trb_buff_len
;
2921 /* Check TD length */
2922 if (running_total
!= td_len
) {
2923 xhci_err(xhci
, "ISOC TD length unmatch\n");
2929 start_trb
->field
[3] |= start_cycle
;
2931 ring_ep_doorbell(xhci
, slot_id
, ep_index
, urb
->stream_id
);
2936 * Check transfer ring to guarantee there is enough room for the urb.
2937 * Update ISO URB start_frame and interval.
2938 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
2939 * update the urb->start_frame by now.
2940 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
2942 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2943 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2945 struct xhci_virt_device
*xdev
;
2946 struct xhci_ring
*ep_ring
;
2947 struct xhci_ep_ctx
*ep_ctx
;
2951 int num_tds
, num_trbs
, i
;
2954 xdev
= xhci
->devs
[slot_id
];
2955 ep_ring
= xdev
->eps
[ep_index
].ring
;
2956 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2959 num_tds
= urb
->number_of_packets
;
2960 for (i
= 0; i
< num_tds
; i
++)
2961 num_trbs
+= count_isoc_trbs_needed(xhci
, urb
, i
);
2963 /* Check the ring to guarantee there is enough room for the whole urb.
2964 * Do not insert any td of the urb to the ring if the check failed.
2966 ret
= prepare_ring(xhci
, ep_ring
, ep_ctx
->ep_info
& EP_STATE_MASK
,
2967 num_trbs
, mem_flags
);
2971 start_frame
= xhci_readl(xhci
, &xhci
->run_regs
->microframe_index
);
2972 start_frame
&= 0x3fff;
2974 urb
->start_frame
= start_frame
;
2975 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2976 urb
->dev
->speed
== USB_SPEED_FULL
)
2977 urb
->start_frame
>>= 3;
2979 xhci_interval
= EP_INTERVAL_TO_UFRAMES(ep_ctx
->ep_info
);
2980 ep_interval
= urb
->interval
;
2981 /* Convert to microframes */
2982 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2983 urb
->dev
->speed
== USB_SPEED_FULL
)
2985 /* FIXME change this to a warning and a suggestion to use the new API
2986 * to set the polling interval (once the API is added).
2988 if (xhci_interval
!= ep_interval
) {
2989 if (!printk_ratelimit())
2990 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
2991 " (%d microframe%s) than xHCI "
2992 "(%d microframe%s)\n",
2994 ep_interval
== 1 ? "" : "s",
2996 xhci_interval
== 1 ? "" : "s");
2997 urb
->interval
= xhci_interval
;
2998 /* Convert back to frames for LS/FS devices */
2999 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3000 urb
->dev
->speed
== USB_SPEED_FULL
)
3003 return xhci_queue_isoc_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
3006 /**** Command Ring Operations ****/
3008 /* Generic function for queueing a command TRB on the command ring.
3009 * Check to make sure there's room on the command ring for one command TRB.
3010 * Also check that there's room reserved for commands that must not fail.
3011 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3012 * then only check for the number of reserved spots.
3013 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3014 * because the command event handler may want to resubmit a failed command.
3016 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
3017 u32 field3
, u32 field4
, bool command_must_succeed
)
3019 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
3022 if (!command_must_succeed
)
3025 ret
= prepare_ring(xhci
, xhci
->cmd_ring
, EP_STATE_RUNNING
,
3026 reserved_trbs
, GFP_ATOMIC
);
3028 xhci_err(xhci
, "ERR: No room for command on command ring\n");
3029 if (command_must_succeed
)
3030 xhci_err(xhci
, "ERR: Reserved TRB counting for "
3031 "unfailable commands failed.\n");
3034 queue_trb(xhci
, xhci
->cmd_ring
, false, false, field1
, field2
, field3
,
3035 field4
| xhci
->cmd_ring
->cycle_state
);
3039 /* Queue a no-op command on the command ring */
3040 static int queue_cmd_noop(struct xhci_hcd
*xhci
)
3042 return queue_command(xhci
, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP
), false);
3046 * Place a no-op command on the command ring to test the command and
3049 void *xhci_setup_one_noop(struct xhci_hcd
*xhci
)
3051 if (queue_cmd_noop(xhci
) < 0)
3053 xhci
->noops_submitted
++;
3054 return xhci_ring_cmd_db
;
3057 /* Queue a slot enable or disable request on the command ring */
3058 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
3060 return queue_command(xhci
, 0, 0, 0,
3061 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
3064 /* Queue an address device command TRB */
3065 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3068 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3069 upper_32_bits(in_ctx_ptr
), 0,
3070 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3074 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
,
3075 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
3077 return queue_command(xhci
, field1
, field2
, field3
, field4
, false);
3080 /* Queue a reset device command TRB */
3081 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, u32 slot_id
)
3083 return queue_command(xhci
, 0, 0, 0,
3084 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3088 /* Queue a configure endpoint command TRB */
3089 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3090 u32 slot_id
, bool command_must_succeed
)
3092 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3093 upper_32_bits(in_ctx_ptr
), 0,
3094 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
3095 command_must_succeed
);
3098 /* Queue an evaluate context command TRB */
3099 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3102 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3103 upper_32_bits(in_ctx_ptr
), 0,
3104 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
3108 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
3109 unsigned int ep_index
)
3111 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3112 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3113 u32 type
= TRB_TYPE(TRB_STOP_RING
);
3115 return queue_command(xhci
, 0, 0, 0,
3116 trb_slot_id
| trb_ep_index
| type
, false);
3119 /* Set Transfer Ring Dequeue Pointer command.
3120 * This should not be used for endpoints that have streams enabled.
3122 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
3123 unsigned int ep_index
, unsigned int stream_id
,
3124 struct xhci_segment
*deq_seg
,
3125 union xhci_trb
*deq_ptr
, u32 cycle_state
)
3128 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3129 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3130 u32 trb_stream_id
= STREAM_ID_FOR_TRB(stream_id
);
3131 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
3133 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
3135 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3136 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
3140 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
3141 upper_32_bits(addr
), trb_stream_id
,
3142 trb_slot_id
| trb_ep_index
| type
, false);
3145 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
3146 unsigned int ep_index
)
3148 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3149 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3150 u32 type
= TRB_TYPE(TRB_RESET_EP
);
3152 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,