arch/x86_64/kernel/i8259.c

   1 #include <linux/linkage.h>
   2 #include <linux/config.h>
   3 #include <linux/errno.h>
   4 #include <linux/signal.h>
   5 #include <linux/sched.h>
   6 #include <linux/ioport.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/timex.h>
   9 #include <linux/slab.h>
  10 #include <linux/random.h>
  11 #include <linux/smp_lock.h>
  12 #include <linux/init.h>
  13 #include <linux/kernel_stat.h>
  14 #include <linux/sysdev.h>
  15 #include <linux/bitops.h>
  16
  17 #include <asm/acpi.h>
  18 #include <asm/atomic.h>
  19 #include <asm/system.h>
  20 #include <asm/io.h>
  21 #include <asm/hw_irq.h>
  22 #include <asm/pgtable.h>
  23 #include <asm/delay.h>
  24 #include <asm/desc.h>
  25 #include <asm/apic.h>
  26
  27 /*
  28  * Common place to define all x86 IRQ vectors
  29  *
  30  * This builds up the IRQ handler stubs using some ugly macros in irq.h
  31  *
  32  * These macros create the low-level assembly IRQ routines that save
  33  * register context and call do_IRQ(). do_IRQ() then does all the
  34  * operations that are needed to keep the AT (or SMP IOAPIC)
  35  * interrupt-controller happy.
  36  */
  37
  38 #define BI(x,y) \
  39         BUILD_IRQ(x##y)
  40
  41 #define BUILD_16_IRQS(x) \
  42         BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
  43         BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
  44         BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
  45         BI(x,c) BI(x,d) BI(x,e) BI(x,f)
  46
  47 #define BUILD_14_IRQS(x) \
  48         BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
  49         BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
  50         BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
  51         BI(x,c) BI(x,d)
  52
  53 /*
  54  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  55  * (these are usually mapped to vectors 0x20-0x2f)
  56  */
  57 BUILD_16_IRQS(0x0)
  58
  59 #ifdef CONFIG_X86_LOCAL_APIC
  60 /*
  61  * The IO-APIC gives us many more interrupt sources. Most of these
  62  * are unused but an SMP system is supposed to have enough memory ...
  63  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  64  * across the spectrum, so we really want to be prepared to get all
  65  * of these. Plus, more powerful systems might have more than 64
  66  * IO-APIC registers.
  67  *
  68  * (these are usually mapped into the 0x30-0xff vector range)
  69  */
  70                    BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
  71 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
  72 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
  73 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd)
  74
  75 #ifdef CONFIG_PCI_MSI
  76         BUILD_14_IRQS(0xe)
  77 #endif
  78
  79 #endif
  80
  81 #undef BUILD_16_IRQS
  82 #undef BUILD_14_IRQS
  83 #undef BI
  84
  85
  86 #define IRQ(x,y) \
  87         IRQ##x##y##_interrupt
  88
  89 #define IRQLIST_16(x) \
  90         IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
  91         IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
  92         IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
  93         IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
  94
  95 #define IRQLIST_14(x) \
  96         IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
  97         IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
  98         IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
  99         IRQ(x,c), IRQ(x,d)
 100
 101 void (*interrupt[NR_IRQS])(void) = {
 102         IRQLIST_16(0x0),
 103
 104 #ifdef CONFIG_X86_IO_APIC
 105                          IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
 106         IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
 107         IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
 108         IRQLIST_16(0xc), IRQLIST_16(0xd)
 109
 110 #ifdef CONFIG_PCI_MSI
 111         , IRQLIST_14(0xe)
 112 #endif
 113
 114 #endif
 115 };
 116
 117 #undef IRQ
 118 #undef IRQLIST_16
 119 #undef IRQLIST_14
 120
 121 /*
 122  * This is the 'legacy' 8259A Programmable Interrupt Controller,
 123  * present in the majority of PC/AT boxes.
 124  * plus some generic x86 specific things if generic specifics makes
 125  * any sense at all.
 126  * this file should become arch/i386/kernel/irq.c when the old irq.c
 127  * moves to arch independent land
 128  */
 129
 130 DEFINE_SPINLOCK(i8259A_lock);
 131
 132 static void end_8259A_irq (unsigned int irq)
 133 {
 134         if (irq > 256) {
 135                 char var;
 136                 printk("return %p stack %p ti %p\n", __builtin_return_address(0), &var, current->thread_info);
 137
 138                 BUG();
 139         }
 140
 141         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
 142             irq_desc[irq].action)
 143                 enable_8259A_irq(irq);
 144 }
 145
 146 #define shutdown_8259A_irq      disable_8259A_irq
 147
 148 static void mask_and_ack_8259A(unsigned int);
 149
 150 static unsigned int startup_8259A_irq(unsigned int irq)
 151 {
 152         enable_8259A_irq(irq);
 153         return 0; /* never anything pending */
 154 }
 155
 156 static struct hw_interrupt_type i8259A_irq_type = {
 157         .typename = "XT-PIC",
 158         .startup = startup_8259A_irq,
 159         .shutdown = shutdown_8259A_irq,
 160         .enable = enable_8259A_irq,
 161         .disable = disable_8259A_irq,
 162         .ack = mask_and_ack_8259A,
 163         .end = end_8259A_irq,
 164 };
 165
 166 /*
 167  * 8259A PIC functions to handle ISA devices:
 168  */
 169
 170 /*
 171  * This contains the irq mask for both 8259A irq controllers,
 172  */
 173 static unsigned int cached_irq_mask = 0xffff;
 174
 175 #define __byte(x,y)     (((unsigned char *)&(y))[x])
 176 #define cached_21       (__byte(0,cached_irq_mask))
 177 #define cached_A1       (__byte(1,cached_irq_mask))
 178
 179 /*
 180  * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 181  * boards the timer interrupt is not really connected to any IO-APIC pin,
 182  * it's fed to the master 8259A's IR0 line only.
 183  *
 184  * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 185  * this 'mixed mode' IRQ handling costs nothing because it's only used
 186  * at IRQ setup time.
 187  */
 188 unsigned long io_apic_irqs;
 189
 190 void disable_8259A_irq(unsigned int irq)
 191 {
 192         unsigned int mask = 1 << irq;
 193         unsigned long flags;
 194
 195         spin_lock_irqsave(&i8259A_lock, flags);
 196         cached_irq_mask |= mask;
 197         if (irq & 8)
 198                 outb(cached_A1,0xA1);
 199         else
 200                 outb(cached_21,0x21);
 201         spin_unlock_irqrestore(&i8259A_lock, flags);
 202 }
 203
 204 void enable_8259A_irq(unsigned int irq)
 205 {
 206         unsigned int mask = ~(1 << irq);
 207         unsigned long flags;
 208
 209         spin_lock_irqsave(&i8259A_lock, flags);
 210         cached_irq_mask &= mask;
 211         if (irq & 8)
 212                 outb(cached_A1,0xA1);
 213         else
 214                 outb(cached_21,0x21);
 215         spin_unlock_irqrestore(&i8259A_lock, flags);
 216 }
 217
 218 int i8259A_irq_pending(unsigned int irq)
 219 {
 220         unsigned int mask = 1<<irq;
 221         unsigned long flags;
 222         int ret;
 223
 224         spin_lock_irqsave(&i8259A_lock, flags);
 225         if (irq < 8)
 226                 ret = inb(0x20) & mask;
 227         else
 228                 ret = inb(0xA0) & (mask >> 8);
 229         spin_unlock_irqrestore(&i8259A_lock, flags);
 230
 231         return ret;
 232 }
 233
 234 void make_8259A_irq(unsigned int irq)
 235 {
 236         disable_irq_nosync(irq);
 237         io_apic_irqs &= ~(1<<irq);
 238         irq_desc[irq].handler = &i8259A_irq_type;
 239         enable_irq(irq);
 240 }
 241
 242 /*
 243  * This function assumes to be called rarely. Switching between
 244  * 8259A registers is slow.
 245  * This has to be protected by the irq controller spinlock
 246  * before being called.
 247  */
 248 static inline int i8259A_irq_real(unsigned int irq)
 249 {
 250         int value;
 251         int irqmask = 1<<irq;
 252
 253         if (irq < 8) {
 254                 outb(0x0B,0x20);                /* ISR register */
 255                 value = inb(0x20) & irqmask;
 256                 outb(0x0A,0x20);                /* back to the IRR register */
 257                 return value;
 258         }
 259         outb(0x0B,0xA0);                /* ISR register */
 260         value = inb(0xA0) & (irqmask >> 8);
 261         outb(0x0A,0xA0);                /* back to the IRR register */
 262         return value;
 263 }
 264
 265 /*
 266  * Careful! The 8259A is a fragile beast, it pretty
 267  * much _has_ to be done exactly like this (mask it
 268  * first, _then_ send the EOI, and the order of EOI
 269  * to the two 8259s is important!
 270  */
 271 static void mask_and_ack_8259A(unsigned int irq)
 272 {
 273         unsigned int irqmask = 1 << irq;
 274         unsigned long flags;
 275
 276         spin_lock_irqsave(&i8259A_lock, flags);
 277         /*
 278          * Lightweight spurious IRQ detection. We do not want
 279          * to overdo spurious IRQ handling - it's usually a sign
 280          * of hardware problems, so we only do the checks we can
 281          * do without slowing down good hardware unnecesserily.
 282          *
 283          * Note that IRQ7 and IRQ15 (the two spurious IRQs
 284          * usually resulting from the 8259A-1|2 PICs) occur
 285          * even if the IRQ is masked in the 8259A. Thus we
 286          * can check spurious 8259A IRQs without doing the
 287          * quite slow i8259A_irq_real() call for every IRQ.
 288          * This does not cover 100% of spurious interrupts,
 289          * but should be enough to warn the user that there
 290          * is something bad going on ...
 291          */
 292         if (cached_irq_mask & irqmask)
 293                 goto spurious_8259A_irq;
 294         cached_irq_mask |= irqmask;
 295
 296 handle_real_irq:
 297         if (irq & 8) {
 298                 inb(0xA1);              /* DUMMY - (do we need this?) */
 299                 outb(cached_A1,0xA1);
 300                 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
 301                 outb(0x62,0x20);        /* 'Specific EOI' to master-IRQ2 */
 302         } else {
 303                 inb(0x21);              /* DUMMY - (do we need this?) */
 304                 outb(cached_21,0x21);
 305                 outb(0x60+irq,0x20);    /* 'Specific EOI' to master */
 306         }
 307         spin_unlock_irqrestore(&i8259A_lock, flags);
 308         return;
 309
 310 spurious_8259A_irq:
 311         /*
 312          * this is the slow path - should happen rarely.
 313          */
 314         if (i8259A_irq_real(irq))
 315                 /*
 316                  * oops, the IRQ _is_ in service according to the
 317                  * 8259A - not spurious, go handle it.
 318                  */
 319                 goto handle_real_irq;
 320
 321         {
 322                 static int spurious_irq_mask;
 323                 /*
 324                  * At this point we can be sure the IRQ is spurious,
 325                  * lets ACK and report it. [once per IRQ]
 326                  */
 327                 if (!(spurious_irq_mask & irqmask)) {
 328                         printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
 329                         spurious_irq_mask |= irqmask;
 330                 }
 331                 atomic_inc(&irq_err_count);
 332                 /*
 333                  * Theoretically we do not have to handle this IRQ,
 334                  * but in Linux this does not cause problems and is
 335                  * simpler for us.
 336                  */
 337                 goto handle_real_irq;
 338         }
 339 }
 340
 341 void init_8259A(int auto_eoi)
 342 {
 343         unsigned long flags;
 344
 345         spin_lock_irqsave(&i8259A_lock, flags);
 346
 347         outb(0xff, 0x21);       /* mask all of 8259A-1 */
 348         outb(0xff, 0xA1);       /* mask all of 8259A-2 */
 349
 350         /*
 351          * outb_p - this has to work on a wide range of PC hardware.
 352          */
 353         outb_p(0x11, 0x20);     /* ICW1: select 8259A-1 init */
 354         outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
 355         outb_p(0x04, 0x21);     /* 8259A-1 (the master) has a slave on IR2 */
 356         if (auto_eoi)
 357                 outb_p(0x03, 0x21);     /* master does Auto EOI */
 358         else
 359                 outb_p(0x01, 0x21);     /* master expects normal EOI */
 360
 361         outb_p(0x11, 0xA0);     /* ICW1: select 8259A-2 init */
 362         outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
 363         outb_p(0x02, 0xA1);     /* 8259A-2 is a slave on master's IR2 */
 364         outb_p(0x01, 0xA1);     /* (slave's support for AEOI in flat mode
 365                                     is to be investigated) */
 366
 367         if (auto_eoi)
 368                 /*
 369                  * in AEOI mode we just have to mask the interrupt
 370                  * when acking.
 371                  */
 372                 i8259A_irq_type.ack = disable_8259A_irq;
 373         else
 374                 i8259A_irq_type.ack = mask_and_ack_8259A;
 375
 376         udelay(100);            /* wait for 8259A to initialize */
 377
 378         outb(cached_21, 0x21);  /* restore master IRQ mask */
 379         outb(cached_A1, 0xA1);  /* restore slave IRQ mask */
 380
 381         spin_unlock_irqrestore(&i8259A_lock, flags);
 382 }
 383
 384 static char irq_trigger[2];
 385 /**
 386  * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
 387  */
 388 static void restore_ELCR(char *trigger)
 389 {
 390         outb(trigger[0], 0x4d0);
 391         outb(trigger[1], 0x4d1);
 392 }
 393
 394 static void save_ELCR(char *trigger)
 395 {
 396         /* IRQ 0,1,2,8,13 are marked as reserved */
 397         trigger[0] = inb(0x4d0) & 0xF8;
 398         trigger[1] = inb(0x4d1) & 0xDE;
 399 }
 400
 401 static int i8259A_resume(struct sys_device *dev)
 402 {
 403         init_8259A(0);
 404         restore_ELCR(irq_trigger);
 405         return 0;
 406 }
 407
 408 static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
 409 {
 410         save_ELCR(irq_trigger);
 411         return 0;
 412 }
 413
 414 static int i8259A_shutdown(struct sys_device *dev)
 415 {
 416         /* Put the i8259A into a quiescent state that
 417          * the kernel initialization code can get it
 418          * out of.
 419          */
 420         outb(0xff, 0x21);       /* mask all of 8259A-1 */
 421         outb(0xff, 0xA1);       /* mask all of 8259A-1 */
 422         return 0;
 423 }
 424
 425 static struct sysdev_class i8259_sysdev_class = {
 426         set_kset_name("i8259"),
 427         .suspend = i8259A_suspend,
 428         .resume = i8259A_resume,
 429         .shutdown = i8259A_shutdown,
 430 };
 431
 432 static struct sys_device device_i8259A = {
 433         .id     = 0,
 434         .cls    = &i8259_sysdev_class,
 435 };
 436
 437 static int __init i8259A_init_sysfs(void)
 438 {
 439         int error = sysdev_class_register(&i8259_sysdev_class);
 440         if (!error)
 441                 error = sysdev_register(&device_i8259A);
 442         return error;
 443 }
 444
 445 device_initcall(i8259A_init_sysfs);
 446
 447 /*
 448  * IRQ2 is cascade interrupt to second interrupt controller
 449  */
 450
 451 static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
 452
 453 void __init init_ISA_irqs (void)
 454 {
 455         int i;
 456
 457 #ifdef CONFIG_X86_LOCAL_APIC
 458         init_bsp_APIC();
 459 #endif
 460         init_8259A(0);
 461
 462         for (i = 0; i < NR_IRQS; i++) {
 463                 irq_desc[i].status = IRQ_DISABLED;
 464                 irq_desc[i].action = NULL;
 465                 irq_desc[i].depth = 1;
 466
 467                 if (i < 16) {
 468                         /*
 469                          * 16 old-style INTA-cycle interrupts:
 470                          */
 471                         irq_desc[i].handler = &i8259A_irq_type;
 472                 } else {
 473                         /*
 474                          * 'high' PCI IRQs filled in on demand
 475                          */
 476                         irq_desc[i].handler = &no_irq_type;
 477                 }
 478         }
 479 }
 480
 481 void apic_timer_interrupt(void);
 482 void spurious_interrupt(void);
 483 void error_interrupt(void);
 484 void reschedule_interrupt(void);
 485 void call_function_interrupt(void);
 486 void invalidate_interrupt0(void);
 487 void invalidate_interrupt1(void);
 488 void invalidate_interrupt2(void);
 489 void invalidate_interrupt3(void);
 490 void invalidate_interrupt4(void);
 491 void invalidate_interrupt5(void);
 492 void invalidate_interrupt6(void);
 493 void invalidate_interrupt7(void);
 494 void thermal_interrupt(void);
 495 void i8254_timer_resume(void);
 496
 497 static void setup_timer_hardware(void)
 498 {
 499         outb_p(0x34,0x43);              /* binary, mode 2, LSB/MSB, ch 0 */
 500         udelay(10);
 501         outb_p(LATCH & 0xff , 0x40);    /* LSB */
 502         udelay(10);
 503         outb(LATCH >> 8 , 0x40);        /* MSB */
 504 }
 505
 506 static int timer_resume(struct sys_device *dev)
 507 {
 508         setup_timer_hardware();
 509         return 0;
 510 }
 511
 512 void i8254_timer_resume(void)
 513 {
 514         setup_timer_hardware();
 515 }
 516
 517 static struct sysdev_class timer_sysclass = {
 518         set_kset_name("timer_pit"),
 519         .resume         = timer_resume,
 520 };
 521
 522 static struct sys_device device_timer = {
 523         .id             = 0,
 524         .cls            = &timer_sysclass,
 525 };
 526
 527 static int __init init_timer_sysfs(void)
 528 {
 529         int error = sysdev_class_register(&timer_sysclass);
 530         if (!error)
 531                 error = sysdev_register(&device_timer);
 532         return error;
 533 }
 534
 535 device_initcall(init_timer_sysfs);
 536
 537 void __init init_IRQ(void)
 538 {
 539         int i;
 540
 541         init_ISA_irqs();
 542         /*
 543          * Cover the whole vector space, no vector can escape
 544          * us. (some of these will be overridden and become
 545          * 'special' SMP interrupts)
 546          */
 547         for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
 548                 int vector = FIRST_EXTERNAL_VECTOR + i;
 549                 if (i >= NR_IRQS)
 550                         break;
 551                 if (vector != IA32_SYSCALL_VECTOR && vector != KDB_VECTOR) {
 552                         set_intr_gate(vector, interrupt[i]);
 553         }
 554         }
 555
 556 #ifdef CONFIG_SMP
 557         /*
 558          * IRQ0 must be given a fixed assignment and initialized,
 559          * because it's used before the IO-APIC is set up.
 560          */
 561         set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
 562
 563         /*
 564          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 565          * IPI, driven by wakeup.
 566          */
 567         set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 568
 569         /* IPIs for invalidation */
 570         set_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
 571         set_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
 572         set_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
 573         set_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
 574         set_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
 575         set_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
 576         set_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
 577         set_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
 578
 579         /* IPI for generic function call */
 580         set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 581 #endif
 582         set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 583
 584 #ifdef CONFIG_X86_LOCAL_APIC
 585         /* self generated IPI for local APIC timer */
 586         set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 587
 588         /* IPI vectors for APIC spurious and error interrupts */
 589         set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 590         set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 591 #endif
 592
 593         /*
 594          * Set the clock to HZ Hz, we already have a valid
 595          * vector now:
 596          */
 597         setup_timer_hardware();
 598
 599         if (!acpi_ioapic)
 600                 setup_irq(2, &irq2);
 601 }