drivers/scsi/sata_vsc.c

   1 /*
   2  *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
   3  *
   4  *  Maintained by:  Jeremy Higdon @ SGI
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2004 SGI
   9  *
  10  *  Bits from Jeff Garzik, Copyright RedHat, Inc.
  11  *
  12  *
  13  *  This program is free software; you can redistribute it and/or modify
  14  *  it under the terms of the GNU General Public License as published by
  15  *  the Free Software Foundation; either version 2, or (at your option)
  16  *  any later version.
  17  *
  18  *  This program is distributed in the hope that it will be useful,
  19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *  GNU General Public License for more details.
  22  *
  23  *  You should have received a copy of the GNU General Public License
  24  *  along with this program; see the file COPYING.  If not, write to
  25  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *
  28  *  libata documentation is available via 'make {ps|pdf}docs',
  29  *  as Documentation/DocBook/libata.*
  30  *
  31  *  Vitesse hardware documentation presumably available under NDA.
  32  *  Intel 31244 (same hardware interface) documentation presumably
  33  *  available from http://developer.intel.com/
  34  *
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/pci.h>
  40 #include <linux/init.h>
  41 #include <linux/blkdev.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/device.h>
  46 #include <scsi/scsi_host.h>
  47 #include <linux/libata.h>
  48
  49 #define DRV_NAME        "sata_vsc"
  50 #define DRV_VERSION     "1.2"
  51
  52 enum {
  53         /* Interrupt register offsets (from chip base address) */
  54         VSC_SATA_INT_STAT_OFFSET        = 0x00,
  55         VSC_SATA_INT_MASK_OFFSET        = 0x04,
  56
  57         /* Taskfile registers offsets */
  58         VSC_SATA_TF_CMD_OFFSET          = 0x00,
  59         VSC_SATA_TF_DATA_OFFSET         = 0x00,
  60         VSC_SATA_TF_ERROR_OFFSET        = 0x04,
  61         VSC_SATA_TF_FEATURE_OFFSET      = 0x06,
  62         VSC_SATA_TF_NSECT_OFFSET        = 0x08,
  63         VSC_SATA_TF_LBAL_OFFSET         = 0x0c,
  64         VSC_SATA_TF_LBAM_OFFSET         = 0x10,
  65         VSC_SATA_TF_LBAH_OFFSET         = 0x14,
  66         VSC_SATA_TF_DEVICE_OFFSET       = 0x18,
  67         VSC_SATA_TF_STATUS_OFFSET       = 0x1c,
  68         VSC_SATA_TF_COMMAND_OFFSET      = 0x1d,
  69         VSC_SATA_TF_ALTSTATUS_OFFSET    = 0x28,
  70         VSC_SATA_TF_CTL_OFFSET          = 0x29,
  71
  72         /* DMA base */
  73         VSC_SATA_UP_DESCRIPTOR_OFFSET   = 0x64,
  74         VSC_SATA_UP_DATA_BUFFER_OFFSET  = 0x6C,
  75         VSC_SATA_DMA_CMD_OFFSET         = 0x70,
  76
  77         /* SCRs base */
  78         VSC_SATA_SCR_STATUS_OFFSET      = 0x100,
  79         VSC_SATA_SCR_ERROR_OFFSET       = 0x104,
  80         VSC_SATA_SCR_CONTROL_OFFSET     = 0x108,
  81
  82         /* Port stride */
  83         VSC_SATA_PORT_OFFSET            = 0x200,
  84
  85         /* Error interrupt status bit offsets */
  86         VSC_SATA_INT_ERROR_CRC          = 0x40,
  87         VSC_SATA_INT_ERROR_T            = 0x20,
  88         VSC_SATA_INT_ERROR_P            = 0x10,
  89         VSC_SATA_INT_ERROR_R            = 0x8,
  90         VSC_SATA_INT_ERROR_E            = 0x4,
  91         VSC_SATA_INT_ERROR_M            = 0x2,
  92         VSC_SATA_INT_PHY_CHANGE         = 0x1,
  93         VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC  | VSC_SATA_INT_ERROR_T | \
  94                               VSC_SATA_INT_ERROR_P    | VSC_SATA_INT_ERROR_R | \
  95                               VSC_SATA_INT_ERROR_E    | VSC_SATA_INT_ERROR_M | \
  96                               VSC_SATA_INT_PHY_CHANGE),
  97 };
  98
  99
 100 #define is_vsc_sata_int_err(port_idx, int_status) \
 101          (int_status & (VSC_SATA_INT_ERROR << (8 * port_idx)))
 102
 103
 104 static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
 105 {
 106         if (sc_reg > SCR_CONTROL)
 107                 return 0xffffffffU;
 108         return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
 109 }
 110
 111
 112 static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
 113                                u32 val)
 114 {
 115         if (sc_reg > SCR_CONTROL)
 116                 return;
 117         writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
 118 }
 119
 120
 121 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
 122 {
 123         void __iomem *mask_addr;
 124         u8 mask;
 125
 126         mask_addr = ap->host_set->mmio_base +
 127                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
 128         mask = readb(mask_addr);
 129         if (ctl & ATA_NIEN)
 130                 mask |= 0x80;
 131         else
 132                 mask &= 0x7F;
 133         writeb(mask, mask_addr);
 134 }
 135
 136
 137 static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
 138 {
 139         struct ata_ioports *ioaddr = &ap->ioaddr;
 140         unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
 141
 142         /*
 143          * The only thing the ctl register is used for is SRST.
 144          * That is not enabled or disabled via tf_load.
 145          * However, if ATA_NIEN is changed, then we need to change the interrupt register.
 146          */
 147         if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
 148                 ap->last_ctl = tf->ctl;
 149                 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
 150         }
 151         if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
 152                 writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
 153                 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
 154                 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
 155                 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
 156                 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
 157         } else if (is_addr) {
 158                 writew(tf->feature, ioaddr->feature_addr);
 159                 writew(tf->nsect, ioaddr->nsect_addr);
 160                 writew(tf->lbal, ioaddr->lbal_addr);
 161                 writew(tf->lbam, ioaddr->lbam_addr);
 162                 writew(tf->lbah, ioaddr->lbah_addr);
 163         }
 164
 165         if (tf->flags & ATA_TFLAG_DEVICE)
 166                 writeb(tf->device, ioaddr->device_addr);
 167
 168         ata_wait_idle(ap);
 169 }
 170
 171
 172 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 173 {
 174         struct ata_ioports *ioaddr = &ap->ioaddr;
 175         u16 nsect, lbal, lbam, lbah, feature;
 176
 177         tf->command = ata_check_status(ap);
 178         tf->device = readw(ioaddr->device_addr);
 179         feature = readw(ioaddr->error_addr);
 180         nsect = readw(ioaddr->nsect_addr);
 181         lbal = readw(ioaddr->lbal_addr);
 182         lbam = readw(ioaddr->lbam_addr);
 183         lbah = readw(ioaddr->lbah_addr);
 184
 185         tf->feature = feature;
 186         tf->nsect = nsect;
 187         tf->lbal = lbal;
 188         tf->lbam = lbam;
 189         tf->lbah = lbah;
 190
 191         if (tf->flags & ATA_TFLAG_LBA48) {
 192                 tf->hob_feature = feature >> 8;
 193                 tf->hob_nsect = nsect >> 8;
 194                 tf->hob_lbal = lbal >> 8;
 195                 tf->hob_lbam = lbam >> 8;
 196                 tf->hob_lbah = lbah >> 8;
 197         }
 198 }
 199
 200
 201 /*
 202  * vsc_sata_interrupt
 203  *
 204  * Read the interrupt register and process for the devices that have them pending.
 205  */
 206 static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance,
 207                                        struct pt_regs *regs)
 208 {
 209         struct ata_host_set *host_set = dev_instance;
 210         unsigned int i;
 211         unsigned int handled = 0;
 212         u32 int_status;
 213
 214         spin_lock(&host_set->lock);
 215
 216         int_status = readl(host_set->mmio_base + VSC_SATA_INT_STAT_OFFSET);
 217
 218         for (i = 0; i < host_set->n_ports; i++) {
 219                 if (int_status & ((u32) 0xFF << (8 * i))) {
 220                         struct ata_port *ap;
 221
 222                         ap = host_set->ports[i];
 223
 224                         if (ap && !(ap->flags &
 225                                     (ATA_FLAG_PORT_DISABLED|ATA_FLAG_NOINTR))) {
 226                                 struct ata_queued_cmd *qc;
 227
 228                                 qc = ata_qc_from_tag(ap, ap->active_tag);
 229                                 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
 230                                         handled += ata_host_intr(ap, qc);
 231                                 } else if (is_vsc_sata_int_err(i, int_status)) {
 232                                         /*
 233                                          * On some chips (i.e. Intel 31244), an error
 234                                          * interrupt will sneak in at initialization
 235                                          * time (phy state changes).  Clearing the SCR
 236                                          * error register is not required, but it prevents
 237                                          * the phy state change interrupts from recurring
 238                                          * later.
 239                                          */
 240                                         u32 err_status;
 241                                         err_status = vsc_sata_scr_read(ap, SCR_ERROR);
 242                                         printk(KERN_DEBUG "%s: clearing interrupt, "
 243                                                "status %x; sata err status %x\n",
 244                                                __FUNCTION__,
 245                                                int_status, err_status);
 246                                         vsc_sata_scr_write(ap, SCR_ERROR, err_status);
 247                                         /* Clear interrupt status */
 248                                         ata_chk_status(ap);
 249                                         handled++;
 250                                 }
 251                         }
 252                 }
 253         }
 254
 255         spin_unlock(&host_set->lock);
 256
 257         return IRQ_RETVAL(handled);
 258 }
 259
 260
 261 static struct scsi_host_template vsc_sata_sht = {
 262         .module                 = THIS_MODULE,
 263         .name                   = DRV_NAME,
 264         .ioctl                  = ata_scsi_ioctl,
 265         .queuecommand           = ata_scsi_queuecmd,
 266         .can_queue              = ATA_DEF_QUEUE,
 267         .this_id                = ATA_SHT_THIS_ID,
 268         .sg_tablesize           = LIBATA_MAX_PRD,
 269         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 270         .emulated               = ATA_SHT_EMULATED,
 271         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 272         .proc_name              = DRV_NAME,
 273         .dma_boundary           = ATA_DMA_BOUNDARY,
 274         .slave_configure        = ata_scsi_slave_config,
 275         .bios_param             = ata_std_bios_param,
 276 };
 277
 278
 279 static const struct ata_port_operations vsc_sata_ops = {
 280         .port_disable           = ata_port_disable,
 281         .tf_load                = vsc_sata_tf_load,
 282         .tf_read                = vsc_sata_tf_read,
 283         .exec_command           = ata_exec_command,
 284         .check_status           = ata_check_status,
 285         .dev_select             = ata_std_dev_select,
 286         .phy_reset              = sata_phy_reset,
 287         .bmdma_setup            = ata_bmdma_setup,
 288         .bmdma_start            = ata_bmdma_start,
 289         .bmdma_stop             = ata_bmdma_stop,
 290         .bmdma_status           = ata_bmdma_status,
 291         .qc_prep                = ata_qc_prep,
 292         .qc_issue               = ata_qc_issue_prot,
 293         .eng_timeout            = ata_eng_timeout,
 294         .irq_handler            = vsc_sata_interrupt,
 295         .irq_clear              = ata_bmdma_irq_clear,
 296         .scr_read               = vsc_sata_scr_read,
 297         .scr_write              = vsc_sata_scr_write,
 298         .port_start             = ata_port_start,
 299         .port_stop              = ata_port_stop,
 300         .host_stop              = ata_pci_host_stop,
 301 };
 302
 303 static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
 304 {
 305         port->cmd_addr          = base + VSC_SATA_TF_CMD_OFFSET;
 306         port->data_addr         = base + VSC_SATA_TF_DATA_OFFSET;
 307         port->error_addr        = base + VSC_SATA_TF_ERROR_OFFSET;
 308         port->feature_addr      = base + VSC_SATA_TF_FEATURE_OFFSET;
 309         port->nsect_addr        = base + VSC_SATA_TF_NSECT_OFFSET;
 310         port->lbal_addr         = base + VSC_SATA_TF_LBAL_OFFSET;
 311         port->lbam_addr         = base + VSC_SATA_TF_LBAM_OFFSET;
 312         port->lbah_addr         = base + VSC_SATA_TF_LBAH_OFFSET;
 313         port->device_addr       = base + VSC_SATA_TF_DEVICE_OFFSET;
 314         port->status_addr       = base + VSC_SATA_TF_STATUS_OFFSET;
 315         port->command_addr      = base + VSC_SATA_TF_COMMAND_OFFSET;
 316         port->altstatus_addr    = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
 317         port->ctl_addr          = base + VSC_SATA_TF_CTL_OFFSET;
 318         port->bmdma_addr        = base + VSC_SATA_DMA_CMD_OFFSET;
 319         port->scr_addr          = base + VSC_SATA_SCR_STATUS_OFFSET;
 320         writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
 321         writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
 322 }
 323
 324
 325 static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 326 {
 327         static int printed_version;
 328         struct ata_probe_ent *probe_ent = NULL;
 329         unsigned long base;
 330         int pci_dev_busy = 0;
 331         void __iomem *mmio_base;
 332         int rc;
 333
 334         if (!printed_version++)
 335                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
 336
 337         rc = pci_enable_device(pdev);
 338         if (rc)
 339                 return rc;
 340
 341         /*
 342          * Check if we have needed resource mapped.
 343          */
 344         if (pci_resource_len(pdev, 0) == 0) {
 345                 rc = -ENODEV;
 346                 goto err_out;
 347         }
 348
 349         rc = pci_request_regions(pdev, DRV_NAME);
 350         if (rc) {
 351                 pci_dev_busy = 1;
 352                 goto err_out;
 353         }
 354
 355         /*
 356          * Use 32 bit DMA mask, because 64 bit address support is poor.
 357          */
 358         rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 359         if (rc)
 360                 goto err_out_regions;
 361         rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
 362         if (rc)
 363                 goto err_out_regions;
 364
 365         probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
 366         if (probe_ent == NULL) {
 367                 rc = -ENOMEM;
 368                 goto err_out_regions;
 369         }
 370         memset(probe_ent, 0, sizeof(*probe_ent));
 371         probe_ent->dev = pci_dev_to_dev(pdev);
 372         INIT_LIST_HEAD(&probe_ent->node);
 373
 374         mmio_base = pci_iomap(pdev, 0, 0);
 375         if (mmio_base == NULL) {
 376                 rc = -ENOMEM;
 377                 goto err_out_free_ent;
 378         }
 379         base = (unsigned long) mmio_base;
 380
 381         /*
 382          * Due to a bug in the chip, the default cache line size can't be used
 383          */
 384         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
 385
 386         probe_ent->sht = &vsc_sata_sht;
 387         probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 388                                 ATA_FLAG_MMIO | ATA_FLAG_SATA_RESET;
 389         probe_ent->port_ops = &vsc_sata_ops;
 390         probe_ent->n_ports = 4;
 391         probe_ent->irq = pdev->irq;
 392         probe_ent->irq_flags = SA_SHIRQ;
 393         probe_ent->mmio_base = mmio_base;
 394
 395         /* We don't care much about the PIO/UDMA masks, but the core won't like us
 396          * if we don't fill these
 397          */
 398         probe_ent->pio_mask = 0x1f;
 399         probe_ent->mwdma_mask = 0x07;
 400         probe_ent->udma_mask = 0x7f;
 401
 402         /* We have 4 ports per PCI function */
 403         vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
 404         vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
 405         vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
 406         vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);
 407
 408         pci_set_master(pdev);
 409
 410         /*
 411          * Config offset 0x98 is "Extended Control and Status Register 0"
 412          * Default value is (1 << 28).  All bits except bit 28 are reserved in
 413          * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.
 414          * If bit 28 is clear, each port has its own LED.
 415          */
 416         pci_write_config_dword(pdev, 0x98, 0);
 417
 418         /* FIXME: check ata_device_add return value */
 419         ata_device_add(probe_ent);
 420         kfree(probe_ent);
 421
 422         return 0;
 423
 424 err_out_free_ent:
 425         kfree(probe_ent);
 426 err_out_regions:
 427         pci_release_regions(pdev);
 428 err_out:
 429         if (!pci_dev_busy)
 430                 pci_disable_device(pdev);
 431         return rc;
 432 }
 433
 434
 435 /*
 436  * 0x1725/0x7174 is the Vitesse VSC-7174
 437  * 0x8086/0x3200 is the Intel 31244, which is supposed to be identical
 438  * compatibility is untested as of yet
 439  */
 440 static const struct pci_device_id vsc_sata_pci_tbl[] = {
 441         { 0x1725, 0x7174, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
 442         { 0x8086, 0x3200, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
 443         { }
 444 };
 445
 446
 447 static struct pci_driver vsc_sata_pci_driver = {
 448         .name                   = DRV_NAME,
 449         .id_table               = vsc_sata_pci_tbl,
 450         .probe                  = vsc_sata_init_one,
 451         .remove                 = ata_pci_remove_one,
 452 };
 453
 454
 455 static int __init vsc_sata_init(void)
 456 {
 457         return pci_module_init(&vsc_sata_pci_driver);
 458 }
 459
 460
 461 static void __exit vsc_sata_exit(void)
 462 {
 463         pci_unregister_driver(&vsc_sata_pci_driver);
 464 }
 465
 466
 467 MODULE_AUTHOR("Jeremy Higdon");
 468 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
 469 MODULE_LICENSE("GPL");
 470 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
 471 MODULE_VERSION(DRV_VERSION);
 472
 473 module_init(vsc_sata_init);
 474 module_exit(vsc_sata_exit);