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Merge remote branch 'nouveau/for-airlied' into drm-linus
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / nouveau / nouveau_state.c
blob58b46807de23a99ea31e5b874db84199a14ab9cf
1 /*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <linux/swab.h>
27 #include "drmP.h"
28 #include "drm.h"
29 #include "drm_sarea.h"
30 #include "drm_crtc_helper.h"
31 #include <linux/vgaarb.h>
32 #include <linux/vga_switcheroo.h>
33
34 #include "nouveau_drv.h"
35 #include "nouveau_drm.h"
36 #include "nv50_display.h"
37
38 static void nouveau_stub_takedown(struct drm_device *dev) {}
39
40 static int nouveau_init_engine_ptrs(struct drm_device *dev)
41 {
42 struct drm_nouveau_private *dev_priv = dev->dev_private;
43 struct nouveau_engine *engine = &dev_priv->engine;
44
45 switch (dev_priv->chipset & 0xf0) {
46 case 0x00:
47 engine->instmem.init = nv04_instmem_init;
48 engine->instmem.takedown = nv04_instmem_takedown;
49 engine->instmem.suspend = nv04_instmem_suspend;
50 engine->instmem.resume = nv04_instmem_resume;
51 engine->instmem.populate = nv04_instmem_populate;
52 engine->instmem.clear = nv04_instmem_clear;
53 engine->instmem.bind = nv04_instmem_bind;
54 engine->instmem.unbind = nv04_instmem_unbind;
55 engine->instmem.prepare_access = nv04_instmem_prepare_access;
56 engine->instmem.finish_access = nv04_instmem_finish_access;
57 engine->mc.init = nv04_mc_init;
58 engine->mc.takedown = nv04_mc_takedown;
59 engine->timer.init = nv04_timer_init;
60 engine->timer.read = nv04_timer_read;
61 engine->timer.takedown = nv04_timer_takedown;
62 engine->fb.init = nv04_fb_init;
63 engine->fb.takedown = nv04_fb_takedown;
64 engine->graph.grclass = nv04_graph_grclass;
65 engine->graph.init = nv04_graph_init;
66 engine->graph.takedown = nv04_graph_takedown;
67 engine->graph.fifo_access = nv04_graph_fifo_access;
68 engine->graph.channel = nv04_graph_channel;
69 engine->graph.create_context = nv04_graph_create_context;
70 engine->graph.destroy_context = nv04_graph_destroy_context;
71 engine->graph.load_context = nv04_graph_load_context;
72 engine->graph.unload_context = nv04_graph_unload_context;
73 engine->fifo.channels = 16;
74 engine->fifo.init = nv04_fifo_init;
75 engine->fifo.takedown = nouveau_stub_takedown;
76 engine->fifo.disable = nv04_fifo_disable;
77 engine->fifo.enable = nv04_fifo_enable;
78 engine->fifo.reassign = nv04_fifo_reassign;
79 engine->fifo.cache_flush = nv04_fifo_cache_flush;
80 engine->fifo.cache_pull = nv04_fifo_cache_pull;
81 engine->fifo.channel_id = nv04_fifo_channel_id;
82 engine->fifo.create_context = nv04_fifo_create_context;
83 engine->fifo.destroy_context = nv04_fifo_destroy_context;
84 engine->fifo.load_context = nv04_fifo_load_context;
85 engine->fifo.unload_context = nv04_fifo_unload_context;
86 break;
87 case 0x10:
88 engine->instmem.init = nv04_instmem_init;
89 engine->instmem.takedown = nv04_instmem_takedown;
90 engine->instmem.suspend = nv04_instmem_suspend;
91 engine->instmem.resume = nv04_instmem_resume;
92 engine->instmem.populate = nv04_instmem_populate;
93 engine->instmem.clear = nv04_instmem_clear;
94 engine->instmem.bind = nv04_instmem_bind;
95 engine->instmem.unbind = nv04_instmem_unbind;
96 engine->instmem.prepare_access = nv04_instmem_prepare_access;
97 engine->instmem.finish_access = nv04_instmem_finish_access;
98 engine->mc.init = nv04_mc_init;
99 engine->mc.takedown = nv04_mc_takedown;
100 engine->timer.init = nv04_timer_init;
101 engine->timer.read = nv04_timer_read;
102 engine->timer.takedown = nv04_timer_takedown;
103 engine->fb.init = nv10_fb_init;
104 engine->fb.takedown = nv10_fb_takedown;
105 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
106 engine->graph.grclass = nv10_graph_grclass;
107 engine->graph.init = nv10_graph_init;
108 engine->graph.takedown = nv10_graph_takedown;
109 engine->graph.channel = nv10_graph_channel;
110 engine->graph.create_context = nv10_graph_create_context;
111 engine->graph.destroy_context = nv10_graph_destroy_context;
112 engine->graph.fifo_access = nv04_graph_fifo_access;
113 engine->graph.load_context = nv10_graph_load_context;
114 engine->graph.unload_context = nv10_graph_unload_context;
115 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
116 engine->fifo.channels = 32;
117 engine->fifo.init = nv10_fifo_init;
118 engine->fifo.takedown = nouveau_stub_takedown;
119 engine->fifo.disable = nv04_fifo_disable;
120 engine->fifo.enable = nv04_fifo_enable;
121 engine->fifo.reassign = nv04_fifo_reassign;
122 engine->fifo.cache_flush = nv04_fifo_cache_flush;
123 engine->fifo.cache_pull = nv04_fifo_cache_pull;
124 engine->fifo.channel_id = nv10_fifo_channel_id;
125 engine->fifo.create_context = nv10_fifo_create_context;
126 engine->fifo.destroy_context = nv10_fifo_destroy_context;
127 engine->fifo.load_context = nv10_fifo_load_context;
128 engine->fifo.unload_context = nv10_fifo_unload_context;
129 break;
130 case 0x20:
131 engine->instmem.init = nv04_instmem_init;
132 engine->instmem.takedown = nv04_instmem_takedown;
133 engine->instmem.suspend = nv04_instmem_suspend;
134 engine->instmem.resume = nv04_instmem_resume;
135 engine->instmem.populate = nv04_instmem_populate;
136 engine->instmem.clear = nv04_instmem_clear;
137 engine->instmem.bind = nv04_instmem_bind;
138 engine->instmem.unbind = nv04_instmem_unbind;
139 engine->instmem.prepare_access = nv04_instmem_prepare_access;
140 engine->instmem.finish_access = nv04_instmem_finish_access;
141 engine->mc.init = nv04_mc_init;
142 engine->mc.takedown = nv04_mc_takedown;
143 engine->timer.init = nv04_timer_init;
144 engine->timer.read = nv04_timer_read;
145 engine->timer.takedown = nv04_timer_takedown;
146 engine->fb.init = nv10_fb_init;
147 engine->fb.takedown = nv10_fb_takedown;
148 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
149 engine->graph.grclass = nv20_graph_grclass;
150 engine->graph.init = nv20_graph_init;
151 engine->graph.takedown = nv20_graph_takedown;
152 engine->graph.channel = nv10_graph_channel;
153 engine->graph.create_context = nv20_graph_create_context;
154 engine->graph.destroy_context = nv20_graph_destroy_context;
155 engine->graph.fifo_access = nv04_graph_fifo_access;
156 engine->graph.load_context = nv20_graph_load_context;
157 engine->graph.unload_context = nv20_graph_unload_context;
158 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
159 engine->fifo.channels = 32;
160 engine->fifo.init = nv10_fifo_init;
161 engine->fifo.takedown = nouveau_stub_takedown;
162 engine->fifo.disable = nv04_fifo_disable;
163 engine->fifo.enable = nv04_fifo_enable;
164 engine->fifo.reassign = nv04_fifo_reassign;
165 engine->fifo.cache_flush = nv04_fifo_cache_flush;
166 engine->fifo.cache_pull = nv04_fifo_cache_pull;
167 engine->fifo.channel_id = nv10_fifo_channel_id;
168 engine->fifo.create_context = nv10_fifo_create_context;
169 engine->fifo.destroy_context = nv10_fifo_destroy_context;
170 engine->fifo.load_context = nv10_fifo_load_context;
171 engine->fifo.unload_context = nv10_fifo_unload_context;
172 break;
173 case 0x30:
174 engine->instmem.init = nv04_instmem_init;
175 engine->instmem.takedown = nv04_instmem_takedown;
176 engine->instmem.suspend = nv04_instmem_suspend;
177 engine->instmem.resume = nv04_instmem_resume;
178 engine->instmem.populate = nv04_instmem_populate;
179 engine->instmem.clear = nv04_instmem_clear;
180 engine->instmem.bind = nv04_instmem_bind;
181 engine->instmem.unbind = nv04_instmem_unbind;
182 engine->instmem.prepare_access = nv04_instmem_prepare_access;
183 engine->instmem.finish_access = nv04_instmem_finish_access;
184 engine->mc.init = nv04_mc_init;
185 engine->mc.takedown = nv04_mc_takedown;
186 engine->timer.init = nv04_timer_init;
187 engine->timer.read = nv04_timer_read;
188 engine->timer.takedown = nv04_timer_takedown;
189 engine->fb.init = nv10_fb_init;
190 engine->fb.takedown = nv10_fb_takedown;
191 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
192 engine->graph.grclass = nv30_graph_grclass;
193 engine->graph.init = nv30_graph_init;
194 engine->graph.takedown = nv20_graph_takedown;
195 engine->graph.fifo_access = nv04_graph_fifo_access;
196 engine->graph.channel = nv10_graph_channel;
197 engine->graph.create_context = nv20_graph_create_context;
198 engine->graph.destroy_context = nv20_graph_destroy_context;
199 engine->graph.load_context = nv20_graph_load_context;
200 engine->graph.unload_context = nv20_graph_unload_context;
201 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
202 engine->fifo.channels = 32;
203 engine->fifo.init = nv10_fifo_init;
204 engine->fifo.takedown = nouveau_stub_takedown;
205 engine->fifo.disable = nv04_fifo_disable;
206 engine->fifo.enable = nv04_fifo_enable;
207 engine->fifo.reassign = nv04_fifo_reassign;
208 engine->fifo.cache_flush = nv04_fifo_cache_flush;
209 engine->fifo.cache_pull = nv04_fifo_cache_pull;
210 engine->fifo.channel_id = nv10_fifo_channel_id;
211 engine->fifo.create_context = nv10_fifo_create_context;
212 engine->fifo.destroy_context = nv10_fifo_destroy_context;
213 engine->fifo.load_context = nv10_fifo_load_context;
214 engine->fifo.unload_context = nv10_fifo_unload_context;
215 break;
216 case 0x40:
217 case 0x60:
218 engine->instmem.init = nv04_instmem_init;
219 engine->instmem.takedown = nv04_instmem_takedown;
220 engine->instmem.suspend = nv04_instmem_suspend;
221 engine->instmem.resume = nv04_instmem_resume;
222 engine->instmem.populate = nv04_instmem_populate;
223 engine->instmem.clear = nv04_instmem_clear;
224 engine->instmem.bind = nv04_instmem_bind;
225 engine->instmem.unbind = nv04_instmem_unbind;
226 engine->instmem.prepare_access = nv04_instmem_prepare_access;
227 engine->instmem.finish_access = nv04_instmem_finish_access;
228 engine->mc.init = nv40_mc_init;
229 engine->mc.takedown = nv40_mc_takedown;
230 engine->timer.init = nv04_timer_init;
231 engine->timer.read = nv04_timer_read;
232 engine->timer.takedown = nv04_timer_takedown;
233 engine->fb.init = nv40_fb_init;
234 engine->fb.takedown = nv40_fb_takedown;
235 engine->fb.set_region_tiling = nv40_fb_set_region_tiling;
236 engine->graph.grclass = nv40_graph_grclass;
237 engine->graph.init = nv40_graph_init;
238 engine->graph.takedown = nv40_graph_takedown;
239 engine->graph.fifo_access = nv04_graph_fifo_access;
240 engine->graph.channel = nv40_graph_channel;
241 engine->graph.create_context = nv40_graph_create_context;
242 engine->graph.destroy_context = nv40_graph_destroy_context;
243 engine->graph.load_context = nv40_graph_load_context;
244 engine->graph.unload_context = nv40_graph_unload_context;
245 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
246 engine->fifo.channels = 32;
247 engine->fifo.init = nv40_fifo_init;
248 engine->fifo.takedown = nouveau_stub_takedown;
249 engine->fifo.disable = nv04_fifo_disable;
250 engine->fifo.enable = nv04_fifo_enable;
251 engine->fifo.reassign = nv04_fifo_reassign;
252 engine->fifo.cache_flush = nv04_fifo_cache_flush;
253 engine->fifo.cache_pull = nv04_fifo_cache_pull;
254 engine->fifo.channel_id = nv10_fifo_channel_id;
255 engine->fifo.create_context = nv40_fifo_create_context;
256 engine->fifo.destroy_context = nv40_fifo_destroy_context;
257 engine->fifo.load_context = nv40_fifo_load_context;
258 engine->fifo.unload_context = nv40_fifo_unload_context;
259 break;
260 case 0x50:
261 case 0x80: /* gotta love NVIDIA's consistency.. */
262 case 0x90:
263 case 0xA0:
264 engine->instmem.init = nv50_instmem_init;
265 engine->instmem.takedown = nv50_instmem_takedown;
266 engine->instmem.suspend = nv50_instmem_suspend;
267 engine->instmem.resume = nv50_instmem_resume;
268 engine->instmem.populate = nv50_instmem_populate;
269 engine->instmem.clear = nv50_instmem_clear;
270 engine->instmem.bind = nv50_instmem_bind;
271 engine->instmem.unbind = nv50_instmem_unbind;
272 engine->instmem.prepare_access = nv50_instmem_prepare_access;
273 engine->instmem.finish_access = nv50_instmem_finish_access;
274 engine->mc.init = nv50_mc_init;
275 engine->mc.takedown = nv50_mc_takedown;
276 engine->timer.init = nv04_timer_init;
277 engine->timer.read = nv04_timer_read;
278 engine->timer.takedown = nv04_timer_takedown;
279 engine->fb.init = nv50_fb_init;
280 engine->fb.takedown = nv50_fb_takedown;
281 engine->graph.grclass = nv50_graph_grclass;
282 engine->graph.init = nv50_graph_init;
283 engine->graph.takedown = nv50_graph_takedown;
284 engine->graph.fifo_access = nv50_graph_fifo_access;
285 engine->graph.channel = nv50_graph_channel;
286 engine->graph.create_context = nv50_graph_create_context;
287 engine->graph.destroy_context = nv50_graph_destroy_context;
288 engine->graph.load_context = nv50_graph_load_context;
289 engine->graph.unload_context = nv50_graph_unload_context;
290 engine->fifo.channels = 128;
291 engine->fifo.init = nv50_fifo_init;
292 engine->fifo.takedown = nv50_fifo_takedown;
293 engine->fifo.disable = nv04_fifo_disable;
294 engine->fifo.enable = nv04_fifo_enable;
295 engine->fifo.reassign = nv04_fifo_reassign;
296 engine->fifo.channel_id = nv50_fifo_channel_id;
297 engine->fifo.create_context = nv50_fifo_create_context;
298 engine->fifo.destroy_context = nv50_fifo_destroy_context;
299 engine->fifo.load_context = nv50_fifo_load_context;
300 engine->fifo.unload_context = nv50_fifo_unload_context;
301 break;
302 default:
303 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
304 return 1;
305 }
306
307 return 0;
308 }
309
310 static unsigned int
311 nouveau_vga_set_decode(void *priv, bool state)
312 {
313 struct drm_device *dev = priv;
314 struct drm_nouveau_private *dev_priv = dev->dev_private;
315
316 if (dev_priv->chipset >= 0x40)
317 nv_wr32(dev, 0x88054, state);
318 else
319 nv_wr32(dev, 0x1854, state);
320
321 if (state)
322 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
323 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
324 else
325 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
326 }
327
328 static int
329 nouveau_card_init_channel(struct drm_device *dev)
330 {
331 struct drm_nouveau_private *dev_priv = dev->dev_private;
332 struct nouveau_gpuobj *gpuobj;
333 int ret;
334
335 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
336 (struct drm_file *)-2,
337 NvDmaFB, NvDmaTT);
338 if (ret)
339 return ret;
340
341 gpuobj = NULL;
342 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
343 0, nouveau_mem_fb_amount(dev),
344 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
345 &gpuobj);
346 if (ret)
347 goto out_err;
348
349 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
350 gpuobj, NULL);
351 if (ret)
352 goto out_err;
353
354 gpuobj = NULL;
355 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
356 dev_priv->gart_info.aper_size,
357 NV_DMA_ACCESS_RW, &gpuobj, NULL);
358 if (ret)
359 goto out_err;
360
361 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
362 gpuobj, NULL);
363 if (ret)
364 goto out_err;
365
366 return 0;
367 out_err:
368 nouveau_gpuobj_del(dev, &gpuobj);
369 nouveau_channel_free(dev_priv->channel);
370 dev_priv->channel = NULL;
371 return ret;
372 }
373
374 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
375 enum vga_switcheroo_state state)
376 {
377 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
378 if (state == VGA_SWITCHEROO_ON) {
379 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
380 nouveau_pci_resume(pdev);
381 } else {
382 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
383 nouveau_pci_suspend(pdev, pmm);
384 }
385 }
386
387 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
388 {
389 struct drm_device *dev = pci_get_drvdata(pdev);
390 bool can_switch;
391
392 spin_lock(&dev->count_lock);
393 can_switch = (dev->open_count == 0);
394 spin_unlock(&dev->count_lock);
395 return can_switch;
396 }
397
398 int
399 nouveau_card_init(struct drm_device *dev)
400 {
401 struct drm_nouveau_private *dev_priv = dev->dev_private;
402 struct nouveau_engine *engine;
403 int ret;
404
405 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
406
407 if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
408 return 0;
409
410 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
411 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
412 nouveau_switcheroo_can_switch);
413
414 /* Initialise internal driver API hooks */
415 ret = nouveau_init_engine_ptrs(dev);
416 if (ret)
417 goto out;
418 engine = &dev_priv->engine;
419 dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
420 spin_lock_init(&dev_priv->context_switch_lock);
421
422 /* Parse BIOS tables / Run init tables if card not POSTed */
423 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
424 ret = nouveau_bios_init(dev);
425 if (ret)
426 goto out;
427 }
428
429 ret = nouveau_gpuobj_early_init(dev);
430 if (ret)
431 goto out_bios;
432
433 /* Initialise instance memory, must happen before mem_init so we
434 * know exactly how much VRAM we're able to use for "normal"
435 * purposes.
436 */
437 ret = engine->instmem.init(dev);
438 if (ret)
439 goto out_gpuobj_early;
440
441 /* Setup the memory manager */
442 ret = nouveau_mem_init(dev);
443 if (ret)
444 goto out_instmem;
445
446 ret = nouveau_gpuobj_init(dev);
447 if (ret)
448 goto out_mem;
449
450 /* PMC */
451 ret = engine->mc.init(dev);
452 if (ret)
453 goto out_gpuobj;
454
455 /* PTIMER */
456 ret = engine->timer.init(dev);
457 if (ret)
458 goto out_mc;
459
460 /* PFB */
461 ret = engine->fb.init(dev);
462 if (ret)
463 goto out_timer;
464
465 if (nouveau_noaccel)
466 engine->graph.accel_blocked = true;
467 else {
468 /* PGRAPH */
469 ret = engine->graph.init(dev);
470 if (ret)
471 goto out_fb;
472
473 /* PFIFO */
474 ret = engine->fifo.init(dev);
475 if (ret)
476 goto out_graph;
477 }
478
479 /* this call irq_preinstall, register irq handler and
480 * call irq_postinstall
481 */
482 ret = drm_irq_install(dev);
483 if (ret)
484 goto out_fifo;
485
486 ret = drm_vblank_init(dev, 0);
487 if (ret)
488 goto out_irq;
489
490 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
491
492 if (!engine->graph.accel_blocked) {
493 ret = nouveau_card_init_channel(dev);
494 if (ret)
495 goto out_irq;
496 }
497
498 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
499 if (dev_priv->card_type >= NV_50)
500 ret = nv50_display_create(dev);
501 else
502 ret = nv04_display_create(dev);
503 if (ret)
504 goto out_irq;
505 }
506
507 ret = nouveau_backlight_init(dev);
508 if (ret)
509 NV_ERROR(dev, "Error %d registering backlight\n", ret);
510
511 dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
512
513 if (drm_core_check_feature(dev, DRIVER_MODESET))
514 drm_helper_initial_config(dev);
515
516 return 0;
517
518 out_irq:
519 drm_irq_uninstall(dev);
520 out_fifo:
521 if (!nouveau_noaccel)
522 engine->fifo.takedown(dev);
523 out_graph:
524 if (!nouveau_noaccel)
525 engine->graph.takedown(dev);
526 out_fb:
527 engine->fb.takedown(dev);
528 out_timer:
529 engine->timer.takedown(dev);
530 out_mc:
531 engine->mc.takedown(dev);
532 out_gpuobj:
533 nouveau_gpuobj_takedown(dev);
534 out_mem:
535 nouveau_mem_close(dev);
536 out_instmem:
537 engine->instmem.takedown(dev);
538 out_gpuobj_early:
539 nouveau_gpuobj_late_takedown(dev);
540 out_bios:
541 nouveau_bios_takedown(dev);
542 out:
543 vga_client_register(dev->pdev, NULL, NULL, NULL);
544 return ret;
545 }
546
547 static void nouveau_card_takedown(struct drm_device *dev)
548 {
549 struct drm_nouveau_private *dev_priv = dev->dev_private;
550 struct nouveau_engine *engine = &dev_priv->engine;
551
552 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
553
554 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
555 nouveau_backlight_exit(dev);
556
557 if (dev_priv->channel) {
558 nouveau_channel_free(dev_priv->channel);
559 dev_priv->channel = NULL;
560 }
561
562 if (!nouveau_noaccel) {
563 engine->fifo.takedown(dev);
564 engine->graph.takedown(dev);
565 }
566 engine->fb.takedown(dev);
567 engine->timer.takedown(dev);
568 engine->mc.takedown(dev);
569
570 mutex_lock(&dev->struct_mutex);
571 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
572 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
573 mutex_unlock(&dev->struct_mutex);
574 nouveau_sgdma_takedown(dev);
575
576 nouveau_gpuobj_takedown(dev);
577 nouveau_mem_close(dev);
578 engine->instmem.takedown(dev);
579
580 if (drm_core_check_feature(dev, DRIVER_MODESET))
581 drm_irq_uninstall(dev);
582
583 nouveau_gpuobj_late_takedown(dev);
584 nouveau_bios_takedown(dev);
585
586 vga_client_register(dev->pdev, NULL, NULL, NULL);
587
588 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
589 }
590 }
591
592 /* here a client dies, release the stuff that was allocated for its
593 * file_priv */
594 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
595 {
596 nouveau_channel_cleanup(dev, file_priv);
597 }
598
599 /* first module load, setup the mmio/fb mapping */
600 /* KMS: we need mmio at load time, not when the first drm client opens. */
601 int nouveau_firstopen(struct drm_device *dev)
602 {
603 return 0;
604 }
605
606 /* if we have an OF card, copy vbios to RAMIN */
607 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
608 {
609 #if defined(__powerpc__)
610 int size, i;
611 const uint32_t *bios;
612 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
613 if (!dn) {
614 NV_INFO(dev, "Unable to get the OF node\n");
615 return;
616 }
617
618 bios = of_get_property(dn, "NVDA,BMP", &size);
619 if (bios) {
620 for (i = 0; i < size; i += 4)
621 nv_wi32(dev, i, bios[i/4]);
622 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
623 } else {
624 NV_INFO(dev, "Unable to get the OF bios\n");
625 }
626 #endif
627 }
628
629 int nouveau_load(struct drm_device *dev, unsigned long flags)
630 {
631 struct drm_nouveau_private *dev_priv;
632 uint32_t reg0;
633 resource_size_t mmio_start_offs;
634
635 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
636 if (!dev_priv)
637 return -ENOMEM;
638 dev->dev_private = dev_priv;
639 dev_priv->dev = dev;
640
641 dev_priv->flags = flags & NOUVEAU_FLAGS;
642 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
643
644 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
645 dev->pci_vendor, dev->pci_device, dev->pdev->class);
646
647 dev_priv->wq = create_workqueue("nouveau");
648 if (!dev_priv->wq)
649 return -EINVAL;
650
651 /* resource 0 is mmio regs */
652 /* resource 1 is linear FB */
653 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
654 /* resource 6 is bios */
655
656 /* map the mmio regs */
657 mmio_start_offs = pci_resource_start(dev->pdev, 0);
658 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
659 if (!dev_priv->mmio) {
660 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
661 "Please report your setup to " DRIVER_EMAIL "\n");
662 return -EINVAL;
663 }
664 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
665 (unsigned long long)mmio_start_offs);
666
667 #ifdef __BIG_ENDIAN
668 /* Put the card in BE mode if it's not */
669 if (nv_rd32(dev, NV03_PMC_BOOT_1))
670 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
671
672 DRM_MEMORYBARRIER();
673 #endif
674
675 /* Time to determine the card architecture */
676 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
677
678 /* We're dealing with >=NV10 */
679 if ((reg0 & 0x0f000000) > 0) {
680 /* Bit 27-20 contain the architecture in hex */
681 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
682 /* NV04 or NV05 */
683 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
684 if (reg0 & 0x00f00000)
685 dev_priv->chipset = 0x05;
686 else
687 dev_priv->chipset = 0x04;
688 } else
689 dev_priv->chipset = 0xff;
690
691 switch (dev_priv->chipset & 0xf0) {
692 case 0x00:
693 case 0x10:
694 case 0x20:
695 case 0x30:
696 dev_priv->card_type = dev_priv->chipset & 0xf0;
697 break;
698 case 0x40:
699 case 0x60:
700 dev_priv->card_type = NV_40;
701 break;
702 case 0x50:
703 case 0x80:
704 case 0x90:
705 case 0xa0:
706 dev_priv->card_type = NV_50;
707 break;
708 default:
709 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
710 return -EINVAL;
711 }
712
713 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
714 dev_priv->card_type, reg0);
715
716 /* map larger RAMIN aperture on NV40 cards */
717 dev_priv->ramin = NULL;
718 if (dev_priv->card_type >= NV_40) {
719 int ramin_bar = 2;
720 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
721 ramin_bar = 3;
722
723 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
724 dev_priv->ramin = ioremap(
725 pci_resource_start(dev->pdev, ramin_bar),
726 dev_priv->ramin_size);
727 if (!dev_priv->ramin) {
728 NV_ERROR(dev, "Failed to init RAMIN mapping, "
729 "limited instance memory available\n");
730 }
731 }
732
733 /* On older cards (or if the above failed), create a map covering
734 * the BAR0 PRAMIN aperture */
735 if (!dev_priv->ramin) {
736 dev_priv->ramin_size = 1 * 1024 * 1024;
737 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
738 dev_priv->ramin_size);
739 if (!dev_priv->ramin) {
740 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
741 return -ENOMEM;
742 }
743 }
744
745 nouveau_OF_copy_vbios_to_ramin(dev);
746
747 /* Special flags */
748 if (dev->pci_device == 0x01a0)
749 dev_priv->flags |= NV_NFORCE;
750 else if (dev->pci_device == 0x01f0)
751 dev_priv->flags |= NV_NFORCE2;
752
753 /* For kernel modesetting, init card now and bring up fbcon */
754 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
755 int ret = nouveau_card_init(dev);
756 if (ret)
757 return ret;
758 }
759
760 return 0;
761 }
762
763 static void nouveau_close(struct drm_device *dev)
764 {
765 struct drm_nouveau_private *dev_priv = dev->dev_private;
766
767 /* In the case of an error dev_priv may not be allocated yet */
768 if (dev_priv)
769 nouveau_card_takedown(dev);
770 }
771
772 /* KMS: we need mmio at load time, not when the first drm client opens. */
773 void nouveau_lastclose(struct drm_device *dev)
774 {
775 if (drm_core_check_feature(dev, DRIVER_MODESET))
776 return;
777
778 nouveau_close(dev);
779 }
780
781 int nouveau_unload(struct drm_device *dev)
782 {
783 struct drm_nouveau_private *dev_priv = dev->dev_private;
784
785 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
786 if (dev_priv->card_type >= NV_50)
787 nv50_display_destroy(dev);
788 else
789 nv04_display_destroy(dev);
790 nouveau_close(dev);
791 }
792
793 iounmap(dev_priv->mmio);
794 iounmap(dev_priv->ramin);
795
796 kfree(dev_priv);
797 dev->dev_private = NULL;
798 return 0;
799 }
800
801 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
802 struct drm_file *file_priv)
803 {
804 struct drm_nouveau_private *dev_priv = dev->dev_private;
805 struct drm_nouveau_getparam *getparam = data;
806
807 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
808
809 switch (getparam->param) {
810 case NOUVEAU_GETPARAM_CHIPSET_ID:
811 getparam->value = dev_priv->chipset;
812 break;
813 case NOUVEAU_GETPARAM_PCI_VENDOR:
814 getparam->value = dev->pci_vendor;
815 break;
816 case NOUVEAU_GETPARAM_PCI_DEVICE:
817 getparam->value = dev->pci_device;
818 break;
819 case NOUVEAU_GETPARAM_BUS_TYPE:
820 if (drm_device_is_agp(dev))
821 getparam->value = NV_AGP;
822 else if (drm_device_is_pcie(dev))
823 getparam->value = NV_PCIE;
824 else
825 getparam->value = NV_PCI;
826 break;
827 case NOUVEAU_GETPARAM_FB_PHYSICAL:
828 getparam->value = dev_priv->fb_phys;
829 break;
830 case NOUVEAU_GETPARAM_AGP_PHYSICAL:
831 getparam->value = dev_priv->gart_info.aper_base;
832 break;
833 case NOUVEAU_GETPARAM_PCI_PHYSICAL:
834 if (dev->sg) {
835 getparam->value = (unsigned long)dev->sg->virtual;
836 } else {
837 NV_ERROR(dev, "Requested PCIGART address, "
838 "while no PCIGART was created\n");
839 return -EINVAL;
840 }
841 break;
842 case NOUVEAU_GETPARAM_FB_SIZE:
843 getparam->value = dev_priv->fb_available_size;
844 break;
845 case NOUVEAU_GETPARAM_AGP_SIZE:
846 getparam->value = dev_priv->gart_info.aper_size;
847 break;
848 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
849 getparam->value = dev_priv->vm_vram_base;
850 break;
851 case NOUVEAU_GETPARAM_GRAPH_UNITS:
852 /* NV40 and NV50 versions are quite different, but register
853 * address is the same. User is supposed to know the card
854 * family anyway... */
855 if (dev_priv->chipset >= 0x40) {
856 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
857 break;
858 }
859 /* FALLTHRU */
860 default:
861 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
862 return -EINVAL;
863 }
864
865 return 0;
866 }
867
868 int
869 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
870 struct drm_file *file_priv)
871 {
872 struct drm_nouveau_setparam *setparam = data;
873
874 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
875
876 switch (setparam->param) {
877 default:
878 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
879 return -EINVAL;
880 }
881
882 return 0;
883 }
884
885 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
886 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
887 uint32_t reg, uint32_t mask, uint32_t val)
888 {
889 struct drm_nouveau_private *dev_priv = dev->dev_private;
890 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
891 uint64_t start = ptimer->read(dev);
892
893 do {
894 if ((nv_rd32(dev, reg) & mask) == val)
895 return true;
896 } while (ptimer->read(dev) - start < timeout);
897
898 return false;
899 }
900
901 /* Waits for PGRAPH to go completely idle */
902 bool nouveau_wait_for_idle(struct drm_device *dev)
903 {
904 if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
905 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
906 nv_rd32(dev, NV04_PGRAPH_STATUS));
907 return false;
908 }
909
910 return true;
911 }
912
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