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[ARM] omap: convert mcbsp to use ioremap()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / plat-omap / mcbsp.c
blobe63990fd923f2e96311f9a77b6424b643ba5aeeb
1 /*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26
27 #include <mach/dma.h>
28 #include <mach/mcbsp.h>
29
30 static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
31
32 #define omap_mcbsp_check_valid_id(id) (mcbsp[id].pdata && \
33 mcbsp[id].pdata->ops && \
34 mcbsp[id].pdata->ops->check && \
35 (mcbsp[id].pdata->ops->check(id) == 0))
36
37 static void omap_mcbsp_dump_reg(u8 id)
38 {
39 dev_dbg(mcbsp[id].dev, "**** McBSP%d regs ****\n", mcbsp[id].id);
40 dev_dbg(mcbsp[id].dev, "DRR2: 0x%04x\n",
41 OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
42 dev_dbg(mcbsp[id].dev, "DRR1: 0x%04x\n",
43 OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
44 dev_dbg(mcbsp[id].dev, "DXR2: 0x%04x\n",
45 OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
46 dev_dbg(mcbsp[id].dev, "DXR1: 0x%04x\n",
47 OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
48 dev_dbg(mcbsp[id].dev, "SPCR2: 0x%04x\n",
49 OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
50 dev_dbg(mcbsp[id].dev, "SPCR1: 0x%04x\n",
51 OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
52 dev_dbg(mcbsp[id].dev, "RCR2: 0x%04x\n",
53 OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
54 dev_dbg(mcbsp[id].dev, "RCR1: 0x%04x\n",
55 OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
56 dev_dbg(mcbsp[id].dev, "XCR2: 0x%04x\n",
57 OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
58 dev_dbg(mcbsp[id].dev, "XCR1: 0x%04x\n",
59 OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
60 dev_dbg(mcbsp[id].dev, "SRGR2: 0x%04x\n",
61 OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
62 dev_dbg(mcbsp[id].dev, "SRGR1: 0x%04x\n",
63 OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
64 dev_dbg(mcbsp[id].dev, "PCR0: 0x%04x\n",
65 OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
66 dev_dbg(mcbsp[id].dev, "***********************\n");
67 }
68
69 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
70 {
71 struct omap_mcbsp *mcbsp_tx = dev_id;
72
73 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n",
74 OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
75
76 complete(&mcbsp_tx->tx_irq_completion);
77
78 return IRQ_HANDLED;
79 }
80
81 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
82 {
83 struct omap_mcbsp *mcbsp_rx = dev_id;
84
85 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n",
86 OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
87
88 complete(&mcbsp_rx->rx_irq_completion);
89
90 return IRQ_HANDLED;
91 }
92
93 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
94 {
95 struct omap_mcbsp *mcbsp_dma_tx = data;
96
97 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
98 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
99
100 /* We can free the channels */
101 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
102 mcbsp_dma_tx->dma_tx_lch = -1;
103
104 complete(&mcbsp_dma_tx->tx_dma_completion);
105 }
106
107 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
108 {
109 struct omap_mcbsp *mcbsp_dma_rx = data;
110
111 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
112 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
113
114 /* We can free the channels */
115 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
116 mcbsp_dma_rx->dma_rx_lch = -1;
117
118 complete(&mcbsp_dma_rx->rx_dma_completion);
119 }
120
121 /*
122 * omap_mcbsp_config simply write a config to the
123 * appropriate McBSP.
124 * You either call this function or set the McBSP registers
125 * by yourself before calling omap_mcbsp_start().
126 */
127 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
128 {
129 void __iomem *io_base;
130
131 if (!omap_mcbsp_check_valid_id(id)) {
132 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
133 return;
134 }
135
136 io_base = mcbsp[id].io_base;
137 dev_dbg(mcbsp[id].dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
138 mcbsp[id].id, mcbsp[id].phys_base);
139
140 /* We write the given config */
141 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
142 OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
143 OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
144 OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
145 OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
146 OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
147 OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
148 OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
149 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
150 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
151 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
152 }
153 EXPORT_SYMBOL(omap_mcbsp_config);
154
155 /*
156 * We can choose between IRQ based or polled IO.
157 * This needs to be called before omap_mcbsp_request().
158 */
159 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
160 {
161 if (!omap_mcbsp_check_valid_id(id)) {
162 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
163 return -ENODEV;
164 }
165
166 spin_lock(&mcbsp[id].lock);
167
168 if (!mcbsp[id].free) {
169 dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
170 mcbsp[id].id);
171 spin_unlock(&mcbsp[id].lock);
172 return -EINVAL;
173 }
174
175 mcbsp[id].io_type = io_type;
176
177 spin_unlock(&mcbsp[id].lock);
178
179 return 0;
180 }
181 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
182
183 int omap_mcbsp_request(unsigned int id)
184 {
185 int err;
186
187 if (!omap_mcbsp_check_valid_id(id)) {
188 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
189 return -ENODEV;
190 }
191
192 if (mcbsp[id].pdata->ops->request)
193 mcbsp[id].pdata->ops->request(id);
194
195 clk_enable(mcbsp[id].clk);
196
197 spin_lock(&mcbsp[id].lock);
198 if (!mcbsp[id].free) {
199 dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
200 mcbsp[id].id);
201 spin_unlock(&mcbsp[id].lock);
202 return -1;
203 }
204
205 mcbsp[id].free = 0;
206 spin_unlock(&mcbsp[id].lock);
207
208 if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
209 /* We need to get IRQs here */
210 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler,
211 0, "McBSP", (void *) (&mcbsp[id]));
212 if (err != 0) {
213 dev_err(mcbsp[id].dev, "Unable to request TX IRQ %d "
214 "for McBSP%d\n", mcbsp[id].tx_irq,
215 mcbsp[id].id);
216 return err;
217 }
218
219 init_completion(&(mcbsp[id].tx_irq_completion));
220
221 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler,
222 0, "McBSP", (void *) (&mcbsp[id]));
223 if (err != 0) {
224 dev_err(mcbsp[id].dev, "Unable to request RX IRQ %d "
225 "for McBSP%d\n", mcbsp[id].rx_irq,
226 mcbsp[id].id);
227 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
228 return err;
229 }
230
231 init_completion(&(mcbsp[id].rx_irq_completion));
232 }
233
234 return 0;
235 }
236 EXPORT_SYMBOL(omap_mcbsp_request);
237
238 void omap_mcbsp_free(unsigned int id)
239 {
240 if (!omap_mcbsp_check_valid_id(id)) {
241 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
242 return;
243 }
244
245 if (mcbsp[id].pdata->ops->free)
246 mcbsp[id].pdata->ops->free(id);
247
248 clk_disable(mcbsp[id].clk);
249
250 spin_lock(&mcbsp[id].lock);
251 if (mcbsp[id].free) {
252 dev_err(mcbsp[id].dev, "McBSP%d was not reserved\n",
253 mcbsp[id].id);
254 spin_unlock(&mcbsp[id].lock);
255 return;
256 }
257
258 mcbsp[id].free = 1;
259 spin_unlock(&mcbsp[id].lock);
260
261 if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
262 /* Free IRQs */
263 free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
264 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
265 }
266 }
267 EXPORT_SYMBOL(omap_mcbsp_free);
268
269 /*
270 * Here we start the McBSP, by enabling the sample
271 * generator, both transmitter and receivers,
272 * and the frame sync.
273 */
274 void omap_mcbsp_start(unsigned int id)
275 {
276 void __iomem *io_base;
277 u16 w;
278
279 if (!omap_mcbsp_check_valid_id(id)) {
280 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
281 return;
282 }
283
284 io_base = mcbsp[id].io_base;
285
286 mcbsp[id].rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
287 mcbsp[id].tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
288
289 /* Start the sample generator */
290 w = OMAP_MCBSP_READ(io_base, SPCR2);
291 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
292
293 /* Enable transmitter and receiver */
294 w = OMAP_MCBSP_READ(io_base, SPCR2);
295 OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
296
297 w = OMAP_MCBSP_READ(io_base, SPCR1);
298 OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
299
300 udelay(100);
301
302 /* Start frame sync */
303 w = OMAP_MCBSP_READ(io_base, SPCR2);
304 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
305
306 /* Dump McBSP Regs */
307 omap_mcbsp_dump_reg(id);
308 }
309 EXPORT_SYMBOL(omap_mcbsp_start);
310
311 void omap_mcbsp_stop(unsigned int id)
312 {
313 void __iomem *io_base;
314 u16 w;
315
316 if (!omap_mcbsp_check_valid_id(id)) {
317 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
318 return;
319 }
320
321 io_base = mcbsp[id].io_base;
322
323 /* Reset transmitter */
324 w = OMAP_MCBSP_READ(io_base, SPCR2);
325 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
326
327 /* Reset receiver */
328 w = OMAP_MCBSP_READ(io_base, SPCR1);
329 OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
330
331 /* Reset the sample rate generator */
332 w = OMAP_MCBSP_READ(io_base, SPCR2);
333 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
334 }
335 EXPORT_SYMBOL(omap_mcbsp_stop);
336
337 /* polled mcbsp i/o operations */
338 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
339 {
340 void __iomem *base;
341
342 if (!omap_mcbsp_check_valid_id(id)) {
343 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
344 return -ENODEV;
345 }
346
347 base = mcbsp[id].io_base;
348 writew(buf, base + OMAP_MCBSP_REG_DXR1);
349 /* if frame sync error - clear the error */
350 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
351 /* clear error */
352 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
353 base + OMAP_MCBSP_REG_SPCR2);
354 /* resend */
355 return -1;
356 } else {
357 /* wait for transmit confirmation */
358 int attemps = 0;
359 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
360 if (attemps++ > 1000) {
361 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
362 (~XRST),
363 base + OMAP_MCBSP_REG_SPCR2);
364 udelay(10);
365 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
366 (XRST),
367 base + OMAP_MCBSP_REG_SPCR2);
368 udelay(10);
369 dev_err(mcbsp[id].dev, "Could not write to"
370 " McBSP%d Register\n", mcbsp[id].id);
371 return -2;
372 }
373 }
374 }
375
376 return 0;
377 }
378 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
379
380 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
381 {
382 void __iomem *base;
383
384 if (!omap_mcbsp_check_valid_id(id)) {
385 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
386 return -ENODEV;
387 }
388
389 base = mcbsp[id].io_base;
390 /* if frame sync error - clear the error */
391 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
392 /* clear error */
393 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
394 base + OMAP_MCBSP_REG_SPCR1);
395 /* resend */
396 return -1;
397 } else {
398 /* wait for recieve confirmation */
399 int attemps = 0;
400 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
401 if (attemps++ > 1000) {
402 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
403 (~RRST),
404 base + OMAP_MCBSP_REG_SPCR1);
405 udelay(10);
406 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
407 (RRST),
408 base + OMAP_MCBSP_REG_SPCR1);
409 udelay(10);
410 dev_err(mcbsp[id].dev, "Could not read from"
411 " McBSP%d Register\n", mcbsp[id].id);
412 return -2;
413 }
414 }
415 }
416 *buf = readw(base + OMAP_MCBSP_REG_DRR1);
417
418 return 0;
419 }
420 EXPORT_SYMBOL(omap_mcbsp_pollread);
421
422 /*
423 * IRQ based word transmission.
424 */
425 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
426 {
427 void __iomem *io_base;
428 omap_mcbsp_word_length word_length;
429
430 if (!omap_mcbsp_check_valid_id(id)) {
431 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
432 return;
433 }
434
435 io_base = mcbsp[id].io_base;
436 word_length = mcbsp[id].tx_word_length;
437
438 wait_for_completion(&(mcbsp[id].tx_irq_completion));
439
440 if (word_length > OMAP_MCBSP_WORD_16)
441 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
442 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
443 }
444 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
445
446 u32 omap_mcbsp_recv_word(unsigned int id)
447 {
448 void __iomem *io_base;
449 u16 word_lsb, word_msb = 0;
450 omap_mcbsp_word_length word_length;
451
452 if (!omap_mcbsp_check_valid_id(id)) {
453 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
454 return -ENODEV;
455 }
456
457 word_length = mcbsp[id].rx_word_length;
458 io_base = mcbsp[id].io_base;
459
460 wait_for_completion(&(mcbsp[id].rx_irq_completion));
461
462 if (word_length > OMAP_MCBSP_WORD_16)
463 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
464 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
465
466 return (word_lsb | (word_msb << 16));
467 }
468 EXPORT_SYMBOL(omap_mcbsp_recv_word);
469
470 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
471 {
472 void __iomem *io_base;
473 omap_mcbsp_word_length tx_word_length;
474 omap_mcbsp_word_length rx_word_length;
475 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
476
477 if (!omap_mcbsp_check_valid_id(id)) {
478 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
479 return -ENODEV;
480 }
481
482 io_base = mcbsp[id].io_base;
483 tx_word_length = mcbsp[id].tx_word_length;
484 rx_word_length = mcbsp[id].rx_word_length;
485
486 if (tx_word_length != rx_word_length)
487 return -EINVAL;
488
489 /* First we wait for the transmitter to be ready */
490 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
491 while (!(spcr2 & XRDY)) {
492 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
493 if (attempts++ > 1000) {
494 /* We must reset the transmitter */
495 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
496 udelay(10);
497 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
498 udelay(10);
499 dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
500 "ready\n", mcbsp[id].id);
501 return -EAGAIN;
502 }
503 }
504
505 /* Now we can push the data */
506 if (tx_word_length > OMAP_MCBSP_WORD_16)
507 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
508 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
509
510 /* We wait for the receiver to be ready */
511 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
512 while (!(spcr1 & RRDY)) {
513 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
514 if (attempts++ > 1000) {
515 /* We must reset the receiver */
516 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
517 udelay(10);
518 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
519 udelay(10);
520 dev_err(mcbsp[id].dev, "McBSP%d receiver not "
521 "ready\n", mcbsp[id].id);
522 return -EAGAIN;
523 }
524 }
525
526 /* Receiver is ready, let's read the dummy data */
527 if (rx_word_length > OMAP_MCBSP_WORD_16)
528 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
529 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
530
531 return 0;
532 }
533 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
534
535 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
536 {
537 u32 clock_word = 0;
538 void __iomem *io_base;
539 omap_mcbsp_word_length tx_word_length;
540 omap_mcbsp_word_length rx_word_length;
541 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
542
543 if (!omap_mcbsp_check_valid_id(id)) {
544 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
545 return -ENODEV;
546 }
547
548 io_base = mcbsp[id].io_base;
549 tx_word_length = mcbsp[id].tx_word_length;
550 rx_word_length = mcbsp[id].rx_word_length;
551
552 if (tx_word_length != rx_word_length)
553 return -EINVAL;
554
555 /* First we wait for the transmitter to be ready */
556 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
557 while (!(spcr2 & XRDY)) {
558 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
559 if (attempts++ > 1000) {
560 /* We must reset the transmitter */
561 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
562 udelay(10);
563 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
564 udelay(10);
565 dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
566 "ready\n", mcbsp[id].id);
567 return -EAGAIN;
568 }
569 }
570
571 /* We first need to enable the bus clock */
572 if (tx_word_length > OMAP_MCBSP_WORD_16)
573 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
574 OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
575
576 /* We wait for the receiver to be ready */
577 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
578 while (!(spcr1 & RRDY)) {
579 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
580 if (attempts++ > 1000) {
581 /* We must reset the receiver */
582 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
583 udelay(10);
584 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
585 udelay(10);
586 dev_err(mcbsp[id].dev, "McBSP%d receiver not "
587 "ready\n", mcbsp[id].id);
588 return -EAGAIN;
589 }
590 }
591
592 /* Receiver is ready, there is something for us */
593 if (rx_word_length > OMAP_MCBSP_WORD_16)
594 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
595 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
596
597 word[0] = (word_lsb | (word_msb << 16));
598
599 return 0;
600 }
601 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
602
603 /*
604 * Simple DMA based buffer rx/tx routines.
605 * Nothing fancy, just a single buffer tx/rx through DMA.
606 * The DMA resources are released once the transfer is done.
607 * For anything fancier, you should use your own customized DMA
608 * routines and callbacks.
609 */
610 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
611 unsigned int length)
612 {
613 int dma_tx_ch;
614 int src_port = 0;
615 int dest_port = 0;
616 int sync_dev = 0;
617
618 if (!omap_mcbsp_check_valid_id(id)) {
619 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
620 return -ENODEV;
621 }
622
623 if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX",
624 omap_mcbsp_tx_dma_callback,
625 &mcbsp[id],
626 &dma_tx_ch)) {
627 dev_err(mcbsp[id].dev, " Unable to request DMA channel for "
628 "McBSP%d TX. Trying IRQ based TX\n",
629 mcbsp[id].id);
630 return -EAGAIN;
631 }
632 mcbsp[id].dma_tx_lch = dma_tx_ch;
633
634 dev_err(mcbsp[id].dev, "McBSP%d TX DMA on channel %d\n", mcbsp[id].id,
635 dma_tx_ch);
636
637 init_completion(&(mcbsp[id].tx_dma_completion));
638
639 if (cpu_class_is_omap1()) {
640 src_port = OMAP_DMA_PORT_TIPB;
641 dest_port = OMAP_DMA_PORT_EMIFF;
642 }
643 if (cpu_class_is_omap2())
644 sync_dev = mcbsp[id].dma_tx_sync;
645
646 omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
647 OMAP_DMA_DATA_TYPE_S16,
648 length >> 1, 1,
649 OMAP_DMA_SYNC_ELEMENT,
650 sync_dev, 0);
651
652 omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
653 src_port,
654 OMAP_DMA_AMODE_CONSTANT,
655 mcbsp[id].phys_base + OMAP_MCBSP_REG_DXR1,
656 0, 0);
657
658 omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
659 dest_port,
660 OMAP_DMA_AMODE_POST_INC,
661 buffer,
662 0, 0);
663
664 omap_start_dma(mcbsp[id].dma_tx_lch);
665 wait_for_completion(&(mcbsp[id].tx_dma_completion));
666
667 return 0;
668 }
669 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
670
671 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
672 unsigned int length)
673 {
674 int dma_rx_ch;
675 int src_port = 0;
676 int dest_port = 0;
677 int sync_dev = 0;
678
679 if (!omap_mcbsp_check_valid_id(id)) {
680 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
681 return -ENODEV;
682 }
683
684 if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX",
685 omap_mcbsp_rx_dma_callback,
686 &mcbsp[id],
687 &dma_rx_ch)) {
688 dev_err(mcbsp[id].dev, "Unable to request DMA channel for "
689 "McBSP%d RX. Trying IRQ based RX\n",
690 mcbsp[id].id);
691 return -EAGAIN;
692 }
693 mcbsp[id].dma_rx_lch = dma_rx_ch;
694
695 dev_err(mcbsp[id].dev, "McBSP%d RX DMA on channel %d\n", mcbsp[id].id,
696 dma_rx_ch);
697
698 init_completion(&(mcbsp[id].rx_dma_completion));
699
700 if (cpu_class_is_omap1()) {
701 src_port = OMAP_DMA_PORT_TIPB;
702 dest_port = OMAP_DMA_PORT_EMIFF;
703 }
704 if (cpu_class_is_omap2())
705 sync_dev = mcbsp[id].dma_rx_sync;
706
707 omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
708 OMAP_DMA_DATA_TYPE_S16,
709 length >> 1, 1,
710 OMAP_DMA_SYNC_ELEMENT,
711 sync_dev, 0);
712
713 omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
714 src_port,
715 OMAP_DMA_AMODE_CONSTANT,
716 mcbsp[id].phys_base + OMAP_MCBSP_REG_DRR1,
717 0, 0);
718
719 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
720 dest_port,
721 OMAP_DMA_AMODE_POST_INC,
722 buffer,
723 0, 0);
724
725 omap_start_dma(mcbsp[id].dma_rx_lch);
726 wait_for_completion(&(mcbsp[id].rx_dma_completion));
727
728 return 0;
729 }
730 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
731
732 /*
733 * SPI wrapper.
734 * Since SPI setup is much simpler than the generic McBSP one,
735 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
736 * Once this is done, you can call omap_mcbsp_start().
737 */
738 void omap_mcbsp_set_spi_mode(unsigned int id,
739 const struct omap_mcbsp_spi_cfg *spi_cfg)
740 {
741 struct omap_mcbsp_reg_cfg mcbsp_cfg;
742
743 if (!omap_mcbsp_check_valid_id(id)) {
744 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
745 return;
746 }
747
748 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
749
750 /* SPI has only one frame */
751 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
752 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
753
754 /* Clock stop mode */
755 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
756 mcbsp_cfg.spcr1 |= (1 << 12);
757 else
758 mcbsp_cfg.spcr1 |= (3 << 11);
759
760 /* Set clock parities */
761 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
762 mcbsp_cfg.pcr0 |= CLKRP;
763 else
764 mcbsp_cfg.pcr0 &= ~CLKRP;
765
766 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
767 mcbsp_cfg.pcr0 &= ~CLKXP;
768 else
769 mcbsp_cfg.pcr0 |= CLKXP;
770
771 /* Set SCLKME to 0 and CLKSM to 1 */
772 mcbsp_cfg.pcr0 &= ~SCLKME;
773 mcbsp_cfg.srgr2 |= CLKSM;
774
775 /* Set FSXP */
776 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
777 mcbsp_cfg.pcr0 &= ~FSXP;
778 else
779 mcbsp_cfg.pcr0 |= FSXP;
780
781 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
782 mcbsp_cfg.pcr0 |= CLKXM;
783 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
784 mcbsp_cfg.pcr0 |= FSXM;
785 mcbsp_cfg.srgr2 &= ~FSGM;
786 mcbsp_cfg.xcr2 |= XDATDLY(1);
787 mcbsp_cfg.rcr2 |= RDATDLY(1);
788 } else {
789 mcbsp_cfg.pcr0 &= ~CLKXM;
790 mcbsp_cfg.srgr1 |= CLKGDV(1);
791 mcbsp_cfg.pcr0 &= ~FSXM;
792 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
793 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
794 }
795
796 mcbsp_cfg.xcr2 &= ~XPHASE;
797 mcbsp_cfg.rcr2 &= ~RPHASE;
798
799 omap_mcbsp_config(id, &mcbsp_cfg);
800 }
801 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
802
803 /*
804 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
805 * 730 has only 2 McBSP, and both of them are MPU peripherals.
806 */
807 static int __init omap_mcbsp_probe(struct platform_device *pdev)
808 {
809 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
810 int id = pdev->id - 1;
811 int ret = 0;
812
813 if (!pdata) {
814 dev_err(&pdev->dev, "McBSP device initialized without"
815 "platform data\n");
816 ret = -EINVAL;
817 goto exit;
818 }
819
820 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
821
822 if (id >= OMAP_MAX_MCBSP_COUNT) {
823 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
824 ret = -EINVAL;
825 goto exit;
826 }
827
828 spin_lock_init(&mcbsp[id].lock);
829 mcbsp[id].id = id + 1;
830 mcbsp[id].free = 1;
831 mcbsp[id].dma_tx_lch = -1;
832 mcbsp[id].dma_rx_lch = -1;
833
834 mcbsp[id].phys_base = pdata->phys_base;
835 mcbsp[id].io_base = ioremap(pdata->phys_base, SZ_4K);
836 if (!mcbsp[id].io_base) {
837 ret = -ENOMEM;
838 goto err_ioremap;
839 }
840
841 /* Default I/O is IRQ based */
842 mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO;
843 mcbsp[id].tx_irq = pdata->tx_irq;
844 mcbsp[id].rx_irq = pdata->rx_irq;
845 mcbsp[id].dma_rx_sync = pdata->dma_rx_sync;
846 mcbsp[id].dma_tx_sync = pdata->dma_tx_sync;
847
848 if (pdata->clk_name)
849 mcbsp[id].clk = clk_get(&pdev->dev, pdata->clk_name);
850 if (IS_ERR(mcbsp[id].clk)) {
851 dev_err(&pdev->dev,
852 "Invalid clock configuration for McBSP%d.\n",
853 mcbsp[id].id);
854 ret = PTR_ERR(mcbsp[id].clk);
855 goto err_clk;
856 }
857
858 mcbsp[id].pdata = pdata;
859 mcbsp[id].dev = &pdev->dev;
860 platform_set_drvdata(pdev, &mcbsp[id]);
861 return 0;
862
863 err_clk:
864 iounmap(mcbsp[id].io_base);
865 err_ioremap:
866 mcbsp[id].free = 0;
867 exit:
868 return ret;
869 }
870
871 static int omap_mcbsp_remove(struct platform_device *pdev)
872 {
873 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
874
875 platform_set_drvdata(pdev, NULL);
876 if (mcbsp) {
877
878 if (mcbsp->pdata && mcbsp->pdata->ops &&
879 mcbsp->pdata->ops->free)
880 mcbsp->pdata->ops->free(mcbsp->id);
881
882 clk_disable(mcbsp->clk);
883 clk_put(mcbsp->clk);
884
885 iounmap(mcbsp->io_base);
886
887 mcbsp->clk = NULL;
888 mcbsp->free = 0;
889 mcbsp->dev = NULL;
890 }
891
892 return 0;
893 }
894
895 static struct platform_driver omap_mcbsp_driver = {
896 .probe = omap_mcbsp_probe,
897 .remove = omap_mcbsp_remove,
898 .driver = {
899 .name = "omap-mcbsp",
900 },
901 };
902
903 int __init omap_mcbsp_init(void)
904 {
905 /* Register the McBSP driver */
906 return platform_driver_register(&omap_mcbsp_driver);
907 }
908
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