arch/blackfin/mach-bf537/include/mach/mem_map.h

   1 /*
   2  * BF537 memory map
   3  *
   4  * Copyright 2004-2009 Analog Devices Inc.
   5  * Licensed under the GPL-2 or later.
   6  */
   7
   8 #ifndef __BFIN_MACH_MEM_MAP_H__
   9 #define __BFIN_MACH_MEM_MAP_H__
  10
  11 #ifndef __BFIN_MEM_MAP_H__
  12 # error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
  13 #endif
  14
  15 /* Async Memory Banks */
  16 #define ASYNC_BANK3_BASE        0x20300000       /* Async Bank 3 */
  17 #define ASYNC_BANK3_SIZE        0x00100000      /* 1M */
  18 #define ASYNC_BANK2_BASE        0x20200000       /* Async Bank 2 */
  19 #define ASYNC_BANK2_SIZE        0x00100000      /* 1M */
  20 #define ASYNC_BANK1_BASE        0x20100000       /* Async Bank 1 */
  21 #define ASYNC_BANK1_SIZE        0x00100000      /* 1M */
  22 #define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
  23 #define ASYNC_BANK0_SIZE        0x00100000      /* 1M */
  24
  25 /* Boot ROM Memory */
  26
  27 #define BOOT_ROM_START          0xEF000000
  28 #define BOOT_ROM_LENGTH         0x800
  29
  30 /* Level 1 Memory */
  31
  32 /* Memory Map for ADSP-BF537 processors */
  33
  34 #ifdef CONFIG_BFIN_ICACHE
  35 #define BFIN_ICACHESIZE (16*1024)
  36 #else
  37 #define BFIN_ICACHESIZE (0*1024)
  38 #endif
  39
  40
  41 #ifdef CONFIG_BF537
  42 #define L1_CODE_START       0xFFA00000
  43 #define L1_DATA_A_START     0xFF800000
  44 #define L1_DATA_B_START     0xFF900000
  45
  46 #define L1_CODE_LENGTH      0xC000
  47
  48 #ifdef CONFIG_BFIN_DCACHE
  49
  50 #ifdef CONFIG_BFIN_DCACHE_BANKA
  51 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
  52 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
  53 #define L1_DATA_B_LENGTH      0x8000
  54 #define BFIN_DCACHESIZE (16*1024)
  55 #define BFIN_DSUPBANKS  1
  56 #else
  57 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
  58 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
  59 #define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
  60 #define BFIN_DCACHESIZE (32*1024)
  61 #define BFIN_DSUPBANKS  2
  62 #endif
  63
  64 #else
  65 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
  66 #define L1_DATA_A_LENGTH      0x8000
  67 #define L1_DATA_B_LENGTH      0x8000
  68 #define BFIN_DCACHESIZE (0*1024)
  69 #define BFIN_DSUPBANKS  0
  70 #endif /*CONFIG_BFIN_DCACHE*/
  71
  72 #endif /*CONFIG_BF537*/
  73
  74 /* Memory Map for ADSP-BF536 processors */
  75
  76 #ifdef CONFIG_BF536
  77 #define L1_CODE_START       0xFFA00000
  78 #define L1_DATA_A_START     0xFF804000
  79 #define L1_DATA_B_START     0xFF904000
  80
  81 #define L1_CODE_LENGTH      0xC000
  82
  83
  84 #ifdef CONFIG_BFIN_DCACHE
  85
  86 #ifdef CONFIG_BFIN_DCACHE_BANKA
  87 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
  88 #define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
  89 #define L1_DATA_B_LENGTH      0x4000
  90 #define BFIN_DCACHESIZE (16*1024)
  91 #define BFIN_DSUPBANKS  1
  92
  93 #else
  94 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
  95 #define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
  96 #define L1_DATA_B_LENGTH      (0x4000 - 0x4000)
  97 #define BFIN_DCACHESIZE (32*1024)
  98 #define BFIN_DSUPBANKS  2
  99 #endif
 100
 101 #else
 102 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
 103 #define L1_DATA_A_LENGTH      0x4000
 104 #define L1_DATA_B_LENGTH      0x4000
 105 #define BFIN_DCACHESIZE (0*1024)
 106 #define BFIN_DSUPBANKS  0
 107 #endif /*CONFIG_BFIN_DCACHE*/
 108
 109 #endif
 110
 111 /* Memory Map for ADSP-BF534 processors */
 112
 113 #ifdef CONFIG_BF534
 114 #define L1_CODE_START       0xFFA00000
 115 #define L1_DATA_A_START     0xFF800000
 116 #define L1_DATA_B_START     0xFF900000
 117
 118 #define L1_CODE_LENGTH      0xC000
 119
 120 #ifdef CONFIG_BFIN_DCACHE
 121
 122 #ifdef CONFIG_BFIN_DCACHE_BANKA
 123 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
 124 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
 125 #define L1_DATA_B_LENGTH      0x8000
 126 #define BFIN_DCACHESIZE (16*1024)
 127 #define BFIN_DSUPBANKS  1
 128
 129 #else
 130 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
 131 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
 132 #define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
 133 #define BFIN_DCACHESIZE (32*1024)
 134 #define BFIN_DSUPBANKS  2
 135 #endif
 136
 137 #else
 138 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
 139 #define L1_DATA_A_LENGTH      0x8000
 140 #define L1_DATA_B_LENGTH      0x8000
 141 #define BFIN_DCACHESIZE (0*1024)
 142 #define BFIN_DSUPBANKS  0
 143 #endif /*CONFIG_BFIN_DCACHE*/
 144
 145 #endif
 146
 147 #endif