arch/x86/kernel/tsc_64.c

   1 #include <linux/kernel.h>
   2 #include <linux/sched.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/init.h>
   5 #include <linux/clocksource.h>
   6 #include <linux/time.h>
   7 #include <linux/acpi.h>
   8 #include <linux/cpufreq.h>
   9 #include <linux/acpi_pmtmr.h>
  10
  11 #include <asm/hpet.h>
  12 #include <asm/timex.h>
  13
  14 static int notsc __initdata = 0;
  15
  16 unsigned int cpu_khz;           /* TSC clocks / usec, not used here */
  17 EXPORT_SYMBOL(cpu_khz);
  18 unsigned int tsc_khz;
  19 EXPORT_SYMBOL(tsc_khz);
  20
  21 static unsigned int cyc2ns_scale __read_mostly;
  22
  23 void set_cyc2ns_scale(unsigned long khz)
  24 {
  25         cyc2ns_scale = (NSEC_PER_MSEC << NS_SCALE) / khz;
  26 }
  27
  28 static unsigned long long cycles_2_ns(unsigned long long cyc)
  29 {
  30         return (cyc * cyc2ns_scale) >> NS_SCALE;
  31 }
  32
  33 unsigned long long sched_clock(void)
  34 {
  35         unsigned long a = 0;
  36
  37         /* Could do CPU core sync here. Opteron can execute rdtsc speculatively,
  38          * which means it is not completely exact and may not be monotonous
  39          * between CPUs. But the errors should be too small to matter for
  40          * scheduling purposes.
  41          */
  42
  43         rdtscll(a);
  44         return cycles_2_ns(a);
  45 }
  46
  47 static int tsc_unstable;
  48
  49 inline int check_tsc_unstable(void)
  50 {
  51         return tsc_unstable;
  52 }
  53 #ifdef CONFIG_CPU_FREQ
  54
  55 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
  56  * changes.
  57  *
  58  * RED-PEN: On SMP we assume all CPUs run with the same frequency.  It's
  59  * not that important because current Opteron setups do not support
  60  * scaling on SMP anyroads.
  61  *
  62  * Should fix up last_tsc too. Currently gettimeofday in the
  63  * first tick after the change will be slightly wrong.
  64  */
  65
  66 static unsigned int  ref_freq;
  67 static unsigned long loops_per_jiffy_ref;
  68 static unsigned long tsc_khz_ref;
  69
  70 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
  71                                  void *data)
  72 {
  73         struct cpufreq_freqs *freq = data;
  74         unsigned long *lpj, dummy;
  75
  76         if (cpu_has(&cpu_data[freq->cpu], X86_FEATURE_CONSTANT_TSC))
  77                 return 0;
  78
  79         lpj = &dummy;
  80         if (!(freq->flags & CPUFREQ_CONST_LOOPS))
  81 #ifdef CONFIG_SMP
  82                 lpj = &cpu_data[freq->cpu].loops_per_jiffy;
  83 #else
  84                 lpj = &boot_cpu_data.loops_per_jiffy;
  85 #endif
  86
  87         if (!ref_freq) {
  88                 ref_freq = freq->old;
  89                 loops_per_jiffy_ref = *lpj;
  90                 tsc_khz_ref = tsc_khz;
  91         }
  92         if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
  93                 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
  94                 (val == CPUFREQ_RESUMECHANGE)) {
  95                 *lpj =
  96                 cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
  97
  98                 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
  99                 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
 100                         mark_tsc_unstable("cpufreq changes");
 101         }
 102
 103         set_cyc2ns_scale(tsc_khz_ref);
 104
 105         return 0;
 106 }
 107
 108 static struct notifier_block time_cpufreq_notifier_block = {
 109         .notifier_call  = time_cpufreq_notifier
 110 };
 111
 112 static int __init cpufreq_tsc(void)
 113 {
 114         cpufreq_register_notifier(&time_cpufreq_notifier_block,
 115                                   CPUFREQ_TRANSITION_NOTIFIER);
 116         return 0;
 117 }
 118
 119 core_initcall(cpufreq_tsc);
 120
 121 #endif
 122
 123 #define MAX_RETRIES     5
 124 #define SMI_TRESHOLD    50000
 125
 126 /*
 127  * Read TSC and the reference counters. Take care of SMI disturbance
 128  */
 129 static unsigned long __init tsc_read_refs(unsigned long *pm,
 130                                           unsigned long *hpet)
 131 {
 132         unsigned long t1, t2;
 133         int i;
 134
 135         for (i = 0; i < MAX_RETRIES; i++) {
 136                 t1 = get_cycles_sync();
 137                 if (hpet)
 138                         *hpet = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
 139                 else
 140                         *pm = acpi_pm_read_early();
 141                 t2 = get_cycles_sync();
 142                 if ((t2 - t1) < SMI_TRESHOLD)
 143                         return t2;
 144         }
 145         return ULONG_MAX;
 146 }
 147
 148 /**
 149  * tsc_calibrate - calibrate the tsc on boot
 150  */
 151 void __init tsc_calibrate(void)
 152 {
 153         unsigned long flags, tsc1, tsc2, tr1, tr2, pm1, pm2, hpet1, hpet2;
 154         int hpet = is_hpet_enabled();
 155
 156         local_irq_save(flags);
 157
 158         tsc1 = tsc_read_refs(&pm1, hpet ? &hpet1 : NULL);
 159
 160         outb((inb(0x61) & ~0x02) | 0x01, 0x61);
 161
 162         outb(0xb0, 0x43);
 163         outb((CLOCK_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
 164         outb((CLOCK_TICK_RATE / (1000 / 50)) >> 8, 0x42);
 165         tr1 = get_cycles_sync();
 166         while ((inb(0x61) & 0x20) == 0);
 167         tr2 = get_cycles_sync();
 168
 169         tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL);
 170
 171         local_irq_restore(flags);
 172
 173         /*
 174          * Preset the result with the raw and inaccurate PIT
 175          * calibration value
 176          */
 177         tsc_khz = (tr2 - tr1) / 50;
 178
 179         /* hpet or pmtimer available ? */
 180         if (!hpet && !pm1 && !pm2) {
 181                 printk(KERN_INFO "TSC calibrated against PIT\n");
 182                 return;
 183         }
 184
 185         /* Check, whether the sampling was disturbed by an SMI */
 186         if (tsc1 == ULONG_MAX || tsc2 == ULONG_MAX) {
 187                 printk(KERN_WARNING "TSC calibration disturbed by SMI, "
 188                        "using PIT calibration result\n");
 189                 return;
 190         }
 191
 192         tsc2 = (tsc2 - tsc1) * 1000000L;
 193
 194         if (hpet) {
 195                 printk(KERN_INFO "TSC calibrated against HPET\n");
 196                 if (hpet2 < hpet1)
 197                         hpet2 += 0x100000000;
 198                 hpet2 -= hpet1;
 199                 tsc1 = (hpet2 * hpet_readl(HPET_PERIOD)) / 1000000;
 200         } else {
 201                 printk(KERN_INFO "TSC calibrated against PM_TIMER\n");
 202                 if (pm2 < pm1)
 203                         pm2 += ACPI_PM_OVRRUN;
 204                 pm2 -= pm1;
 205                 tsc1 = (pm2 * 1000000000) / PMTMR_TICKS_PER_SEC;
 206         }
 207
 208         tsc_khz = tsc2 / tsc1;
 209 }
 210
 211 /*
 212  * Make an educated guess if the TSC is trustworthy and synchronized
 213  * over all CPUs.
 214  */
 215 __cpuinit int unsynchronized_tsc(void)
 216 {
 217         if (tsc_unstable)
 218                 return 1;
 219
 220 #ifdef CONFIG_SMP
 221         if (apic_is_clustered_box())
 222                 return 1;
 223 #endif
 224         /* Most intel systems have synchronized TSCs except for
 225            multi node systems */
 226         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
 227 #ifdef CONFIG_ACPI
 228                 /* But TSC doesn't tick in C3 so don't use it there */
 229                 if (acpi_gbl_FADT.header.length > 0 &&
 230                     acpi_gbl_FADT.C3latency < 1000)
 231                         return 1;
 232 #endif
 233                 return 0;
 234         }
 235
 236         /* Assume multi socket systems are not synchronized */
 237         return num_present_cpus() > 1;
 238 }
 239
 240 int __init notsc_setup(char *s)
 241 {
 242         notsc = 1;
 243         return 1;
 244 }
 245
 246 __setup("notsc", notsc_setup);
 247
 248
 249 /* clock source code: */
 250 static cycle_t read_tsc(void)
 251 {
 252         cycle_t ret = (cycle_t)get_cycles_sync();
 253         return ret;
 254 }
 255
 256 static cycle_t __vsyscall_fn vread_tsc(void)
 257 {
 258         cycle_t ret = (cycle_t)get_cycles_sync();
 259         return ret;
 260 }
 261
 262 static struct clocksource clocksource_tsc = {
 263         .name                   = "tsc",
 264         .rating                 = 300,
 265         .read                   = read_tsc,
 266         .mask                   = CLOCKSOURCE_MASK(64),
 267         .shift                  = 22,
 268         .flags                  = CLOCK_SOURCE_IS_CONTINUOUS |
 269                                   CLOCK_SOURCE_MUST_VERIFY,
 270         .vread                  = vread_tsc,
 271 };
 272
 273 void mark_tsc_unstable(char *reason)
 274 {
 275         if (!tsc_unstable) {
 276                 tsc_unstable = 1;
 277                 printk("Marking TSC unstable due to %s\n", reason);
 278                 /* Change only the rating, when not registered */
 279                 if (clocksource_tsc.mult)
 280                         clocksource_change_rating(&clocksource_tsc, 0);
 281                 else
 282                         clocksource_tsc.rating = 0;
 283         }
 284 }
 285 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
 286
 287 void __init init_tsc_clocksource(void)
 288 {
 289         if (!notsc) {
 290                 clocksource_tsc.mult = clocksource_khz2mult(tsc_khz,
 291                                                         clocksource_tsc.shift);
 292                 if (check_tsc_unstable())
 293                         clocksource_tsc.rating = 0;
 294
 295                 clocksource_register(&clocksource_tsc);
 296         }
 297 }