2 * linux/arch/m68k/mm/cache.c
4 * Instruction cache handling
6 * Copyright (C) 1995 Hamish Macdonald
9 #include <linux/module.h>
10 #include <asm/pgalloc.h>
11 #include <asm/traps.h>
14 static unsigned long virt_to_phys_slow(unsigned long vaddr
)
19 /* The PLPAR instruction causes an access error if the translation
20 * is not possible. To catch this we use the same exception mechanism
21 * as for user space accesses in <asm/uaccess.h>. */
22 asm volatile (".chip 68060\n"
26 ".section .fixup,\"ax\"\n"
31 ".section __ex_table,\"a\"\n"
38 } else if (CPU_IS_040
) {
41 asm volatile (".chip 68040\n\t"
43 "movec %%mmusr, %0\n\t"
48 if (mmusr
& MMU_R_040
)
49 return (mmusr
& PAGE_MASK
) | (vaddr
& ~PAGE_MASK
);
52 unsigned long *descaddr
;
54 asm volatile ("ptestr %3,%2@,#7,%0\n\t"
57 : "a" (&mmusr
), "a" (vaddr
), "d" (get_fs().seg
));
58 if (mmusr
& (MMU_I
|MMU_B
|MMU_L
))
60 descaddr
= phys_to_virt((unsigned long)descaddr
);
61 switch (mmusr
& MMU_NUM
) {
63 return (*descaddr
& 0xfe000000) | (vaddr
& 0x01ffffff);
65 return (*descaddr
& 0xfffc0000) | (vaddr
& 0x0003ffff);
67 return (*descaddr
& PAGE_MASK
) | (vaddr
& ~PAGE_MASK
);
73 /* Push n pages at kernel virtual address and clear the icache */
74 /* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
75 void flush_icache_range(unsigned long address
, unsigned long endaddr
)
78 if (CPU_IS_040_OR_060
) {
82 asm volatile ("nop\n\t"
84 "cpushp %%bc,(%0)\n\t"
86 : : "a" (virt_to_phys_slow(address
)));
88 } while (address
< endaddr
);
91 asm volatile ("movec %%cacr,%0\n\t"
98 EXPORT_SYMBOL(flush_icache_range
);
100 void flush_icache_user_range(struct vm_area_struct
*vma
, struct page
*page
,
101 unsigned long addr
, int len
)
103 if (CPU_IS_040_OR_060
) {
104 asm volatile ("nop\n\t"
106 "cpushp %%bc,(%0)\n\t"
108 : : "a" (page_to_phys(page
)));
111 asm volatile ("movec %%cacr,%0\n\t"