2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
21 static char *dev_info
= "ath9k";
23 MODULE_AUTHOR("Atheros Communications");
24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26 MODULE_LICENSE("Dual BSD/GPL");
28 static int modparam_nohwcrypt
;
29 module_param_named(nohwcrypt
, modparam_nohwcrypt
, int, 0444);
30 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption");
32 static unsigned int ath9k_debug
= ATH_DBG_DEFAULT
;
33 module_param_named(debug
, ath9k_debug
, uint
, 0);
34 MODULE_PARM_DESC(debug
, "Debugging mask");
36 /* We use the hw_value as an index into our private channel structure */
38 #define CHAN2G(_freq, _idx) { \
39 .center_freq = (_freq), \
44 #define CHAN5G(_freq, _idx) { \
45 .band = IEEE80211_BAND_5GHZ, \
46 .center_freq = (_freq), \
51 /* Some 2 GHz radios are actually tunable on 2312-2732
52 * on 5 MHz steps, we support the channels which we know
53 * we have calibration data for all cards though to make
55 static struct ieee80211_channel ath9k_2ghz_chantable
[] = {
56 CHAN2G(2412, 0), /* Channel 1 */
57 CHAN2G(2417, 1), /* Channel 2 */
58 CHAN2G(2422, 2), /* Channel 3 */
59 CHAN2G(2427, 3), /* Channel 4 */
60 CHAN2G(2432, 4), /* Channel 5 */
61 CHAN2G(2437, 5), /* Channel 6 */
62 CHAN2G(2442, 6), /* Channel 7 */
63 CHAN2G(2447, 7), /* Channel 8 */
64 CHAN2G(2452, 8), /* Channel 9 */
65 CHAN2G(2457, 9), /* Channel 10 */
66 CHAN2G(2462, 10), /* Channel 11 */
67 CHAN2G(2467, 11), /* Channel 12 */
68 CHAN2G(2472, 12), /* Channel 13 */
69 CHAN2G(2484, 13), /* Channel 14 */
72 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
73 * on 5 MHz steps, we support the channels which we know
74 * we have calibration data for all cards though to make
76 static struct ieee80211_channel ath9k_5ghz_chantable
[] = {
77 /* _We_ call this UNII 1 */
78 CHAN5G(5180, 14), /* Channel 36 */
79 CHAN5G(5200, 15), /* Channel 40 */
80 CHAN5G(5220, 16), /* Channel 44 */
81 CHAN5G(5240, 17), /* Channel 48 */
82 /* _We_ call this UNII 2 */
83 CHAN5G(5260, 18), /* Channel 52 */
84 CHAN5G(5280, 19), /* Channel 56 */
85 CHAN5G(5300, 20), /* Channel 60 */
86 CHAN5G(5320, 21), /* Channel 64 */
87 /* _We_ call this "Middle band" */
88 CHAN5G(5500, 22), /* Channel 100 */
89 CHAN5G(5520, 23), /* Channel 104 */
90 CHAN5G(5540, 24), /* Channel 108 */
91 CHAN5G(5560, 25), /* Channel 112 */
92 CHAN5G(5580, 26), /* Channel 116 */
93 CHAN5G(5600, 27), /* Channel 120 */
94 CHAN5G(5620, 28), /* Channel 124 */
95 CHAN5G(5640, 29), /* Channel 128 */
96 CHAN5G(5660, 30), /* Channel 132 */
97 CHAN5G(5680, 31), /* Channel 136 */
98 CHAN5G(5700, 32), /* Channel 140 */
99 /* _We_ call this UNII 3 */
100 CHAN5G(5745, 33), /* Channel 149 */
101 CHAN5G(5765, 34), /* Channel 153 */
102 CHAN5G(5785, 35), /* Channel 157 */
103 CHAN5G(5805, 36), /* Channel 161 */
104 CHAN5G(5825, 37), /* Channel 165 */
107 /* Atheros hardware rate code addition for short premble */
108 #define SHPCHECK(__hw_rate, __flags) \
109 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
111 #define RATE(_bitrate, _hw_rate, _flags) { \
112 .bitrate = (_bitrate), \
114 .hw_value = (_hw_rate), \
115 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
118 static struct ieee80211_rate ath9k_legacy_rates
[] = {
120 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE
),
121 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE
),
122 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE
),
133 static void ath_cache_conf_rate(struct ath_softc
*sc
,
134 struct ieee80211_conf
*conf
)
136 switch (conf
->channel
->band
) {
137 case IEEE80211_BAND_2GHZ
:
138 if (conf_is_ht20(conf
))
139 sc
->cur_rate_mode
= ATH9K_MODE_11NG_HT20
;
140 else if (conf_is_ht40_minus(conf
))
141 sc
->cur_rate_mode
= ATH9K_MODE_11NG_HT40MINUS
;
142 else if (conf_is_ht40_plus(conf
))
143 sc
->cur_rate_mode
= ATH9K_MODE_11NG_HT40PLUS
;
145 sc
->cur_rate_mode
= ATH9K_MODE_11G
;
147 case IEEE80211_BAND_5GHZ
:
148 if (conf_is_ht20(conf
))
149 sc
->cur_rate_mode
= ATH9K_MODE_11NA_HT20
;
150 else if (conf_is_ht40_minus(conf
))
151 sc
->cur_rate_mode
= ATH9K_MODE_11NA_HT40MINUS
;
152 else if (conf_is_ht40_plus(conf
))
153 sc
->cur_rate_mode
= ATH9K_MODE_11NA_HT40PLUS
;
155 sc
->cur_rate_mode
= ATH9K_MODE_11A
;
163 static void ath_update_txpow(struct ath_softc
*sc
)
165 struct ath_hw
*ah
= sc
->sc_ah
;
168 if (sc
->curtxpow
!= sc
->config
.txpowlimit
) {
169 ath9k_hw_set_txpowerlimit(ah
, sc
->config
.txpowlimit
);
170 /* read back in case value is clamped */
171 ath9k_hw_getcapability(ah
, ATH9K_CAP_TXPOW
, 1, &txpow
);
172 sc
->curtxpow
= txpow
;
176 static u8
parse_mpdudensity(u8 mpdudensity
)
179 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
180 * 0 for no restriction
189 switch (mpdudensity
) {
195 /* Our lower layer calculations limit our precision to
211 static struct ath9k_channel
*ath_get_curchannel(struct ath_softc
*sc
,
212 struct ieee80211_hw
*hw
)
214 struct ieee80211_channel
*curchan
= hw
->conf
.channel
;
215 struct ath9k_channel
*channel
;
218 chan_idx
= curchan
->hw_value
;
219 channel
= &sc
->sc_ah
->channels
[chan_idx
];
220 ath9k_update_ichannel(sc
, hw
, channel
);
224 static bool ath9k_setpower(struct ath_softc
*sc
, enum ath9k_power_mode mode
)
229 spin_lock_irqsave(&sc
->sc_pm_lock
, flags
);
230 ret
= ath9k_hw_setpower(sc
->sc_ah
, mode
);
231 spin_unlock_irqrestore(&sc
->sc_pm_lock
, flags
);
236 void ath9k_ps_wakeup(struct ath_softc
*sc
)
240 spin_lock_irqsave(&sc
->sc_pm_lock
, flags
);
241 if (++sc
->ps_usecount
!= 1)
244 ath9k_hw_setpower(sc
->sc_ah
, ATH9K_PM_AWAKE
);
247 spin_unlock_irqrestore(&sc
->sc_pm_lock
, flags
);
250 void ath9k_ps_restore(struct ath_softc
*sc
)
254 spin_lock_irqsave(&sc
->sc_pm_lock
, flags
);
255 if (--sc
->ps_usecount
!= 0)
258 if (sc
->ps_enabled
&&
259 !(sc
->sc_flags
& (SC_OP_WAIT_FOR_BEACON
|
261 SC_OP_WAIT_FOR_PSPOLL_DATA
|
262 SC_OP_WAIT_FOR_TX_ACK
)))
263 ath9k_hw_setpower(sc
->sc_ah
, ATH9K_PM_NETWORK_SLEEP
);
266 spin_unlock_irqrestore(&sc
->sc_pm_lock
, flags
);
270 * Set/change channels. If the channel is really being changed, it's done
271 * by reseting the chip. To accomplish this we must first cleanup any pending
272 * DMA, then restart stuff.
274 int ath_set_channel(struct ath_softc
*sc
, struct ieee80211_hw
*hw
,
275 struct ath9k_channel
*hchan
)
277 struct ath_hw
*ah
= sc
->sc_ah
;
278 struct ath_common
*common
= ath9k_hw_common(ah
);
279 struct ieee80211_conf
*conf
= &common
->hw
->conf
;
280 bool fastcc
= true, stopped
;
281 struct ieee80211_channel
*channel
= hw
->conf
.channel
;
284 if (sc
->sc_flags
& SC_OP_INVALID
)
290 * This is only performed if the channel settings have
293 * To switch channels clear any pending DMA operations;
294 * wait long enough for the RX fifo to drain, reset the
295 * hardware at the new frequency, and then re-enable
296 * the relevant bits of the h/w.
298 ath9k_hw_set_interrupts(ah
, 0);
299 ath_drain_all_txq(sc
, false);
300 stopped
= ath_stoprecv(sc
);
302 /* XXX: do not flush receive queue here. We don't want
303 * to flush data frames already in queue because of
304 * changing channel. */
306 if (!stopped
|| (sc
->sc_flags
& SC_OP_FULL_RESET
))
309 ath_print(common
, ATH_DBG_CONFIG
,
310 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
311 sc
->sc_ah
->curchan
->channel
,
312 channel
->center_freq
, conf_is_ht40(conf
));
314 spin_lock_bh(&sc
->sc_resetlock
);
316 r
= ath9k_hw_reset(ah
, hchan
, fastcc
);
318 ath_print(common
, ATH_DBG_FATAL
,
319 "Unable to reset channel (%u Mhz) "
321 channel
->center_freq
, r
);
322 spin_unlock_bh(&sc
->sc_resetlock
);
325 spin_unlock_bh(&sc
->sc_resetlock
);
327 sc
->sc_flags
&= ~SC_OP_FULL_RESET
;
329 if (ath_startrecv(sc
) != 0) {
330 ath_print(common
, ATH_DBG_FATAL
,
331 "Unable to restart recv logic\n");
336 ath_cache_conf_rate(sc
, &hw
->conf
);
337 ath_update_txpow(sc
);
338 ath9k_hw_set_interrupts(ah
, sc
->imask
);
341 ath9k_ps_restore(sc
);
346 * This routine performs the periodic noise floor calibration function
347 * that is used to adjust and optimize the chip performance. This
348 * takes environmental changes (location, temperature) into account.
349 * When the task is complete, it reschedules itself depending on the
350 * appropriate interval that was calculated.
352 static void ath_ani_calibrate(unsigned long data
)
354 struct ath_softc
*sc
= (struct ath_softc
*)data
;
355 struct ath_hw
*ah
= sc
->sc_ah
;
356 struct ath_common
*common
= ath9k_hw_common(ah
);
357 bool longcal
= false;
358 bool shortcal
= false;
359 bool aniflag
= false;
360 unsigned int timestamp
= jiffies_to_msecs(jiffies
);
361 u32 cal_interval
, short_cal_interval
;
363 short_cal_interval
= (ah
->opmode
== NL80211_IFTYPE_AP
) ?
364 ATH_AP_SHORT_CALINTERVAL
: ATH_STA_SHORT_CALINTERVAL
;
366 /* Only calibrate if awake */
367 if (sc
->sc_ah
->power_mode
!= ATH9K_PM_AWAKE
)
372 /* Long calibration runs independently of short calibration. */
373 if ((timestamp
- common
->ani
.longcal_timer
) >= ATH_LONG_CALINTERVAL
) {
375 ath_print(common
, ATH_DBG_ANI
, "longcal @%lu\n", jiffies
);
376 common
->ani
.longcal_timer
= timestamp
;
379 /* Short calibration applies only while caldone is false */
380 if (!common
->ani
.caldone
) {
381 if ((timestamp
- common
->ani
.shortcal_timer
) >= short_cal_interval
) {
383 ath_print(common
, ATH_DBG_ANI
,
384 "shortcal @%lu\n", jiffies
);
385 common
->ani
.shortcal_timer
= timestamp
;
386 common
->ani
.resetcal_timer
= timestamp
;
389 if ((timestamp
- common
->ani
.resetcal_timer
) >=
390 ATH_RESTART_CALINTERVAL
) {
391 common
->ani
.caldone
= ath9k_hw_reset_calvalid(ah
);
392 if (common
->ani
.caldone
)
393 common
->ani
.resetcal_timer
= timestamp
;
397 /* Verify whether we must check ANI */
398 if ((timestamp
- common
->ani
.checkani_timer
) >= ATH_ANI_POLLINTERVAL
) {
400 common
->ani
.checkani_timer
= timestamp
;
403 /* Skip all processing if there's nothing to do. */
404 if (longcal
|| shortcal
|| aniflag
) {
405 /* Call ANI routine if necessary */
407 ath9k_hw_ani_monitor(ah
, ah
->curchan
);
409 /* Perform calibration if necessary */
410 if (longcal
|| shortcal
) {
411 common
->ani
.caldone
=
412 ath9k_hw_calibrate(ah
,
414 common
->rx_chainmask
,
418 common
->ani
.noise_floor
= ath9k_hw_getchan_noise(ah
,
421 ath_print(common
, ATH_DBG_ANI
,
422 " calibrate chan %u/%x nf: %d\n",
423 ah
->curchan
->channel
,
424 ah
->curchan
->channelFlags
,
425 common
->ani
.noise_floor
);
429 ath9k_ps_restore(sc
);
433 * Set timer interval based on previous results.
434 * The interval must be the shortest necessary to satisfy ANI,
435 * short calibration and long calibration.
437 cal_interval
= ATH_LONG_CALINTERVAL
;
438 if (sc
->sc_ah
->config
.enable_ani
)
439 cal_interval
= min(cal_interval
, (u32
)ATH_ANI_POLLINTERVAL
);
440 if (!common
->ani
.caldone
)
441 cal_interval
= min(cal_interval
, (u32
)short_cal_interval
);
443 mod_timer(&common
->ani
.timer
, jiffies
+ msecs_to_jiffies(cal_interval
));
446 static void ath_start_ani(struct ath_common
*common
)
448 unsigned long timestamp
= jiffies_to_msecs(jiffies
);
450 common
->ani
.longcal_timer
= timestamp
;
451 common
->ani
.shortcal_timer
= timestamp
;
452 common
->ani
.checkani_timer
= timestamp
;
454 mod_timer(&common
->ani
.timer
,
455 jiffies
+ msecs_to_jiffies(ATH_ANI_POLLINTERVAL
));
459 * Update tx/rx chainmask. For legacy association,
460 * hard code chainmask to 1x1, for 11n association, use
461 * the chainmask configuration, for bt coexistence, use
462 * the chainmask configuration even in legacy mode.
464 void ath_update_chainmask(struct ath_softc
*sc
, int is_ht
)
466 struct ath_hw
*ah
= sc
->sc_ah
;
467 struct ath_common
*common
= ath9k_hw_common(ah
);
469 if ((sc
->sc_flags
& SC_OP_SCANNING
) || is_ht
||
470 (ah
->btcoex_hw
.scheme
!= ATH_BTCOEX_CFG_NONE
)) {
471 common
->tx_chainmask
= ah
->caps
.tx_chainmask
;
472 common
->rx_chainmask
= ah
->caps
.rx_chainmask
;
474 common
->tx_chainmask
= 1;
475 common
->rx_chainmask
= 1;
478 ath_print(common
, ATH_DBG_CONFIG
,
479 "tx chmask: %d, rx chmask: %d\n",
480 common
->tx_chainmask
,
481 common
->rx_chainmask
);
484 static void ath_node_attach(struct ath_softc
*sc
, struct ieee80211_sta
*sta
)
488 an
= (struct ath_node
*)sta
->drv_priv
;
490 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
491 ath_tx_node_init(sc
, an
);
492 an
->maxampdu
= 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR
+
493 sta
->ht_cap
.ampdu_factor
);
494 an
->mpdudensity
= parse_mpdudensity(sta
->ht_cap
.ampdu_density
);
495 an
->last_rssi
= ATH_RSSI_DUMMY_MARKER
;
499 static void ath_node_detach(struct ath_softc
*sc
, struct ieee80211_sta
*sta
)
501 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
503 if (sc
->sc_flags
& SC_OP_TXAGGR
)
504 ath_tx_node_cleanup(sc
, an
);
507 static void ath9k_tasklet(unsigned long data
)
509 struct ath_softc
*sc
= (struct ath_softc
*)data
;
510 struct ath_hw
*ah
= sc
->sc_ah
;
511 struct ath_common
*common
= ath9k_hw_common(ah
);
513 u32 status
= sc
->intrstatus
;
517 if (status
& ATH9K_INT_FATAL
) {
518 ath_reset(sc
, false);
519 ath9k_ps_restore(sc
);
523 if (status
& (ATH9K_INT_RX
| ATH9K_INT_RXEOL
| ATH9K_INT_RXORN
)) {
524 spin_lock_bh(&sc
->rx
.rxflushlock
);
525 ath_rx_tasklet(sc
, 0);
526 spin_unlock_bh(&sc
->rx
.rxflushlock
);
529 if (status
& ATH9K_INT_TX
)
532 if ((status
& ATH9K_INT_TSFOOR
) && sc
->ps_enabled
) {
534 * TSF sync does not look correct; remain awake to sync with
537 ath_print(common
, ATH_DBG_PS
,
538 "TSFOOR - Sync with next Beacon\n");
539 sc
->sc_flags
|= SC_OP_WAIT_FOR_BEACON
| SC_OP_BEACON_SYNC
;
542 if (ah
->btcoex_hw
.scheme
== ATH_BTCOEX_CFG_3WIRE
)
543 if (status
& ATH9K_INT_GENTIMER
)
544 ath_gen_timer_isr(sc
->sc_ah
);
546 /* re-enable hardware interrupt */
547 ath9k_hw_set_interrupts(ah
, sc
->imask
);
548 ath9k_ps_restore(sc
);
551 irqreturn_t
ath_isr(int irq
, void *dev
)
553 #define SCHED_INTR ( \
564 struct ath_softc
*sc
= dev
;
565 struct ath_hw
*ah
= sc
->sc_ah
;
566 enum ath9k_int status
;
570 * The hardware is not ready/present, don't
571 * touch anything. Note this can happen early
572 * on if the IRQ is shared.
574 if (sc
->sc_flags
& SC_OP_INVALID
)
578 /* shared irq, not for us */
580 if (!ath9k_hw_intrpend(ah
))
584 * Figure out the reason(s) for the interrupt. Note
585 * that the hal returns a pseudo-ISR that may include
586 * bits we haven't explicitly enabled so we mask the
587 * value to insure we only process bits we requested.
589 ath9k_hw_getisr(ah
, &status
); /* NB: clears ISR too */
590 status
&= sc
->imask
; /* discard unasked-for bits */
593 * If there are no status bits set, then this interrupt was not
594 * for me (should have been caught above).
599 /* Cache the status */
600 sc
->intrstatus
= status
;
602 if (status
& SCHED_INTR
)
606 * If a FATAL or RXORN interrupt is received, we have to reset the
609 if (status
& (ATH9K_INT_FATAL
| ATH9K_INT_RXORN
))
612 if (status
& ATH9K_INT_SWBA
)
613 tasklet_schedule(&sc
->bcon_tasklet
);
615 if (status
& ATH9K_INT_TXURN
)
616 ath9k_hw_updatetxtriglevel(ah
, true);
618 if (status
& ATH9K_INT_MIB
) {
620 * Disable interrupts until we service the MIB
621 * interrupt; otherwise it will continue to
624 ath9k_hw_set_interrupts(ah
, 0);
626 * Let the hal handle the event. We assume
627 * it will clear whatever condition caused
630 ath9k_hw_procmibevent(ah
);
631 ath9k_hw_set_interrupts(ah
, sc
->imask
);
634 if (!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
))
635 if (status
& ATH9K_INT_TIM_TIMER
) {
636 /* Clear RxAbort bit so that we can
638 ath9k_setpower(sc
, ATH9K_PM_AWAKE
);
639 ath9k_hw_setrxabort(sc
->sc_ah
, 0);
640 sc
->sc_flags
|= SC_OP_WAIT_FOR_BEACON
;
645 ath_debug_stat_interrupt(sc
, status
);
648 /* turn off every interrupt except SWBA */
649 ath9k_hw_set_interrupts(ah
, (sc
->imask
& ATH9K_INT_SWBA
));
650 tasklet_schedule(&sc
->intr_tq
);
658 static u32
ath_get_extchanmode(struct ath_softc
*sc
,
659 struct ieee80211_channel
*chan
,
660 enum nl80211_channel_type channel_type
)
664 switch (chan
->band
) {
665 case IEEE80211_BAND_2GHZ
:
666 switch(channel_type
) {
667 case NL80211_CHAN_NO_HT
:
668 case NL80211_CHAN_HT20
:
669 chanmode
= CHANNEL_G_HT20
;
671 case NL80211_CHAN_HT40PLUS
:
672 chanmode
= CHANNEL_G_HT40PLUS
;
674 case NL80211_CHAN_HT40MINUS
:
675 chanmode
= CHANNEL_G_HT40MINUS
;
679 case IEEE80211_BAND_5GHZ
:
680 switch(channel_type
) {
681 case NL80211_CHAN_NO_HT
:
682 case NL80211_CHAN_HT20
:
683 chanmode
= CHANNEL_A_HT20
;
685 case NL80211_CHAN_HT40PLUS
:
686 chanmode
= CHANNEL_A_HT40PLUS
;
688 case NL80211_CHAN_HT40MINUS
:
689 chanmode
= CHANNEL_A_HT40MINUS
;
700 static int ath_setkey_tkip(struct ath_common
*common
, u16 keyix
, const u8
*key
,
701 struct ath9k_keyval
*hk
, const u8
*addr
,
704 struct ath_hw
*ah
= common
->ah
;
708 key_txmic
= key
+ NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY
;
709 key_rxmic
= key
+ NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY
;
713 * Group key installation - only two key cache entries are used
714 * regardless of splitmic capability since group key is only
715 * used either for TX or RX.
718 memcpy(hk
->kv_mic
, key_txmic
, sizeof(hk
->kv_mic
));
719 memcpy(hk
->kv_txmic
, key_txmic
, sizeof(hk
->kv_mic
));
721 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
722 memcpy(hk
->kv_txmic
, key_rxmic
, sizeof(hk
->kv_mic
));
724 return ath9k_hw_set_keycache_entry(ah
, keyix
, hk
, addr
);
726 if (!common
->splitmic
) {
727 /* TX and RX keys share the same key cache entry. */
728 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
729 memcpy(hk
->kv_txmic
, key_txmic
, sizeof(hk
->kv_txmic
));
730 return ath9k_hw_set_keycache_entry(ah
, keyix
, hk
, addr
);
733 /* Separate key cache entries for TX and RX */
735 /* TX key goes at first index, RX key at +32. */
736 memcpy(hk
->kv_mic
, key_txmic
, sizeof(hk
->kv_mic
));
737 if (!ath9k_hw_set_keycache_entry(ah
, keyix
, hk
, NULL
)) {
738 /* TX MIC entry failed. No need to proceed further */
739 ath_print(common
, ATH_DBG_FATAL
,
740 "Setting TX MIC Key Failed\n");
744 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
745 /* XXX delete tx key on failure? */
746 return ath9k_hw_set_keycache_entry(ah
, keyix
+ 32, hk
, addr
);
749 static int ath_reserve_key_cache_slot_tkip(struct ath_common
*common
)
753 for (i
= IEEE80211_WEP_NKID
; i
< common
->keymax
/ 2; i
++) {
754 if (test_bit(i
, common
->keymap
) ||
755 test_bit(i
+ 64, common
->keymap
))
756 continue; /* At least one part of TKIP key allocated */
757 if (common
->splitmic
&&
758 (test_bit(i
+ 32, common
->keymap
) ||
759 test_bit(i
+ 64 + 32, common
->keymap
)))
760 continue; /* At least one part of TKIP key allocated */
762 /* Found a free slot for a TKIP key */
768 static int ath_reserve_key_cache_slot(struct ath_common
*common
)
772 /* First, try to find slots that would not be available for TKIP. */
773 if (common
->splitmic
) {
774 for (i
= IEEE80211_WEP_NKID
; i
< common
->keymax
/ 4; i
++) {
775 if (!test_bit(i
, common
->keymap
) &&
776 (test_bit(i
+ 32, common
->keymap
) ||
777 test_bit(i
+ 64, common
->keymap
) ||
778 test_bit(i
+ 64 + 32, common
->keymap
)))
780 if (!test_bit(i
+ 32, common
->keymap
) &&
781 (test_bit(i
, common
->keymap
) ||
782 test_bit(i
+ 64, common
->keymap
) ||
783 test_bit(i
+ 64 + 32, common
->keymap
)))
785 if (!test_bit(i
+ 64, common
->keymap
) &&
786 (test_bit(i
, common
->keymap
) ||
787 test_bit(i
+ 32, common
->keymap
) ||
788 test_bit(i
+ 64 + 32, common
->keymap
)))
790 if (!test_bit(i
+ 64 + 32, common
->keymap
) &&
791 (test_bit(i
, common
->keymap
) ||
792 test_bit(i
+ 32, common
->keymap
) ||
793 test_bit(i
+ 64, common
->keymap
)))
797 for (i
= IEEE80211_WEP_NKID
; i
< common
->keymax
/ 2; i
++) {
798 if (!test_bit(i
, common
->keymap
) &&
799 test_bit(i
+ 64, common
->keymap
))
801 if (test_bit(i
, common
->keymap
) &&
802 !test_bit(i
+ 64, common
->keymap
))
807 /* No partially used TKIP slots, pick any available slot */
808 for (i
= IEEE80211_WEP_NKID
; i
< common
->keymax
; i
++) {
809 /* Do not allow slots that could be needed for TKIP group keys
810 * to be used. This limitation could be removed if we know that
811 * TKIP will not be used. */
812 if (i
>= 64 && i
< 64 + IEEE80211_WEP_NKID
)
814 if (common
->splitmic
) {
815 if (i
>= 32 && i
< 32 + IEEE80211_WEP_NKID
)
817 if (i
>= 64 + 32 && i
< 64 + 32 + IEEE80211_WEP_NKID
)
821 if (!test_bit(i
, common
->keymap
))
822 return i
; /* Found a free slot for a key */
825 /* No free slot found */
829 static int ath_key_config(struct ath_common
*common
,
830 struct ieee80211_vif
*vif
,
831 struct ieee80211_sta
*sta
,
832 struct ieee80211_key_conf
*key
)
834 struct ath_hw
*ah
= common
->ah
;
835 struct ath9k_keyval hk
;
836 const u8
*mac
= NULL
;
840 memset(&hk
, 0, sizeof(hk
));
844 hk
.kv_type
= ATH9K_CIPHER_WEP
;
847 hk
.kv_type
= ATH9K_CIPHER_TKIP
;
850 hk
.kv_type
= ATH9K_CIPHER_AES_CCM
;
856 hk
.kv_len
= key
->keylen
;
857 memcpy(hk
.kv_val
, key
->key
, key
->keylen
);
859 if (!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
)) {
860 /* For now, use the default keys for broadcast keys. This may
861 * need to change with virtual interfaces. */
863 } else if (key
->keyidx
) {
868 if (vif
->type
!= NL80211_IFTYPE_AP
) {
869 /* Only keyidx 0 should be used with unicast key, but
870 * allow this for client mode for now. */
879 if (key
->alg
== ALG_TKIP
)
880 idx
= ath_reserve_key_cache_slot_tkip(common
);
882 idx
= ath_reserve_key_cache_slot(common
);
884 return -ENOSPC
; /* no free key cache entries */
887 if (key
->alg
== ALG_TKIP
)
888 ret
= ath_setkey_tkip(common
, idx
, key
->key
, &hk
, mac
,
889 vif
->type
== NL80211_IFTYPE_AP
);
891 ret
= ath9k_hw_set_keycache_entry(ah
, idx
, &hk
, mac
);
896 set_bit(idx
, common
->keymap
);
897 if (key
->alg
== ALG_TKIP
) {
898 set_bit(idx
+ 64, common
->keymap
);
899 if (common
->splitmic
) {
900 set_bit(idx
+ 32, common
->keymap
);
901 set_bit(idx
+ 64 + 32, common
->keymap
);
908 static void ath_key_delete(struct ath_common
*common
, struct ieee80211_key_conf
*key
)
910 struct ath_hw
*ah
= common
->ah
;
912 ath9k_hw_keyreset(ah
, key
->hw_key_idx
);
913 if (key
->hw_key_idx
< IEEE80211_WEP_NKID
)
916 clear_bit(key
->hw_key_idx
, common
->keymap
);
917 if (key
->alg
!= ALG_TKIP
)
920 clear_bit(key
->hw_key_idx
+ 64, common
->keymap
);
921 if (common
->splitmic
) {
922 clear_bit(key
->hw_key_idx
+ 32, common
->keymap
);
923 clear_bit(key
->hw_key_idx
+ 64 + 32, common
->keymap
);
927 static void setup_ht_cap(struct ath_softc
*sc
,
928 struct ieee80211_sta_ht_cap
*ht_info
)
930 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
931 u8 tx_streams
, rx_streams
;
933 ht_info
->ht_supported
= true;
934 ht_info
->cap
= IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
935 IEEE80211_HT_CAP_SM_PS
|
936 IEEE80211_HT_CAP_SGI_40
|
937 IEEE80211_HT_CAP_DSSSCCK40
;
939 ht_info
->ampdu_factor
= IEEE80211_HT_MAX_AMPDU_64K
;
940 ht_info
->ampdu_density
= IEEE80211_HT_MPDU_DENSITY_8
;
942 /* set up supported mcs set */
943 memset(&ht_info
->mcs
, 0, sizeof(ht_info
->mcs
));
944 tx_streams
= !(common
->tx_chainmask
& (common
->tx_chainmask
- 1)) ?
946 rx_streams
= !(common
->rx_chainmask
& (common
->rx_chainmask
- 1)) ?
949 if (tx_streams
!= rx_streams
) {
950 ath_print(common
, ATH_DBG_CONFIG
,
951 "TX streams %d, RX streams: %d\n",
952 tx_streams
, rx_streams
);
953 ht_info
->mcs
.tx_params
|= IEEE80211_HT_MCS_TX_RX_DIFF
;
954 ht_info
->mcs
.tx_params
|= ((tx_streams
- 1) <<
955 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
958 ht_info
->mcs
.rx_mask
[0] = 0xff;
960 ht_info
->mcs
.rx_mask
[1] = 0xff;
962 ht_info
->mcs
.tx_params
|= IEEE80211_HT_MCS_TX_DEFINED
;
965 static void ath9k_bss_assoc_info(struct ath_softc
*sc
,
966 struct ieee80211_vif
*vif
,
967 struct ieee80211_bss_conf
*bss_conf
)
969 struct ath_hw
*ah
= sc
->sc_ah
;
970 struct ath_common
*common
= ath9k_hw_common(ah
);
972 if (bss_conf
->assoc
) {
973 ath_print(common
, ATH_DBG_CONFIG
,
974 "Bss Info ASSOC %d, bssid: %pM\n",
975 bss_conf
->aid
, common
->curbssid
);
977 /* New association, store aid */
978 common
->curaid
= bss_conf
->aid
;
979 ath9k_hw_write_associd(ah
);
982 * Request a re-configuration of Beacon related timers
983 * on the receipt of the first Beacon frame (i.e.,
984 * after time sync with the AP).
986 sc
->sc_flags
|= SC_OP_BEACON_SYNC
;
988 /* Configure the beacon */
989 ath_beacon_config(sc
, vif
);
991 /* Reset rssi stats */
992 sc
->sc_ah
->stats
.avgbrssi
= ATH_RSSI_DUMMY_MARKER
;
994 ath_start_ani(common
);
996 ath_print(common
, ATH_DBG_CONFIG
, "Bss Info DISASSOC\n");
999 del_timer_sync(&common
->ani
.timer
);
1003 /********************************/
1005 /********************************/
1007 static void ath_led_blink_work(struct work_struct
*work
)
1009 struct ath_softc
*sc
= container_of(work
, struct ath_softc
,
1010 ath_led_blink_work
.work
);
1012 if (!(sc
->sc_flags
& SC_OP_LED_ASSOCIATED
))
1015 if ((sc
->led_on_duration
== ATH_LED_ON_DURATION_IDLE
) ||
1016 (sc
->led_off_duration
== ATH_LED_OFF_DURATION_IDLE
))
1017 ath9k_hw_set_gpio(sc
->sc_ah
, sc
->sc_ah
->led_pin
, 0);
1019 ath9k_hw_set_gpio(sc
->sc_ah
, sc
->sc_ah
->led_pin
,
1020 (sc
->sc_flags
& SC_OP_LED_ON
) ? 1 : 0);
1022 ieee80211_queue_delayed_work(sc
->hw
,
1023 &sc
->ath_led_blink_work
,
1024 (sc
->sc_flags
& SC_OP_LED_ON
) ?
1025 msecs_to_jiffies(sc
->led_off_duration
) :
1026 msecs_to_jiffies(sc
->led_on_duration
));
1028 sc
->led_on_duration
= sc
->led_on_cnt
?
1029 max((ATH_LED_ON_DURATION_IDLE
- sc
->led_on_cnt
), 25) :
1030 ATH_LED_ON_DURATION_IDLE
;
1031 sc
->led_off_duration
= sc
->led_off_cnt
?
1032 max((ATH_LED_OFF_DURATION_IDLE
- sc
->led_off_cnt
), 10) :
1033 ATH_LED_OFF_DURATION_IDLE
;
1034 sc
->led_on_cnt
= sc
->led_off_cnt
= 0;
1035 if (sc
->sc_flags
& SC_OP_LED_ON
)
1036 sc
->sc_flags
&= ~SC_OP_LED_ON
;
1038 sc
->sc_flags
|= SC_OP_LED_ON
;
1041 static void ath_led_brightness(struct led_classdev
*led_cdev
,
1042 enum led_brightness brightness
)
1044 struct ath_led
*led
= container_of(led_cdev
, struct ath_led
, led_cdev
);
1045 struct ath_softc
*sc
= led
->sc
;
1047 switch (brightness
) {
1049 if (led
->led_type
== ATH_LED_ASSOC
||
1050 led
->led_type
== ATH_LED_RADIO
) {
1051 ath9k_hw_set_gpio(sc
->sc_ah
, sc
->sc_ah
->led_pin
,
1052 (led
->led_type
== ATH_LED_RADIO
));
1053 sc
->sc_flags
&= ~SC_OP_LED_ASSOCIATED
;
1054 if (led
->led_type
== ATH_LED_RADIO
)
1055 sc
->sc_flags
&= ~SC_OP_LED_ON
;
1061 if (led
->led_type
== ATH_LED_ASSOC
) {
1062 sc
->sc_flags
|= SC_OP_LED_ASSOCIATED
;
1063 ieee80211_queue_delayed_work(sc
->hw
,
1064 &sc
->ath_led_blink_work
, 0);
1065 } else if (led
->led_type
== ATH_LED_RADIO
) {
1066 ath9k_hw_set_gpio(sc
->sc_ah
, sc
->sc_ah
->led_pin
, 0);
1067 sc
->sc_flags
|= SC_OP_LED_ON
;
1077 static int ath_register_led(struct ath_softc
*sc
, struct ath_led
*led
,
1083 led
->led_cdev
.name
= led
->name
;
1084 led
->led_cdev
.default_trigger
= trigger
;
1085 led
->led_cdev
.brightness_set
= ath_led_brightness
;
1087 ret
= led_classdev_register(wiphy_dev(sc
->hw
->wiphy
), &led
->led_cdev
);
1089 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_FATAL
,
1090 "Failed to register led:%s", led
->name
);
1092 led
->registered
= 1;
1096 static void ath_unregister_led(struct ath_led
*led
)
1098 if (led
->registered
) {
1099 led_classdev_unregister(&led
->led_cdev
);
1100 led
->registered
= 0;
1104 static void ath_deinit_leds(struct ath_softc
*sc
)
1106 ath_unregister_led(&sc
->assoc_led
);
1107 sc
->sc_flags
&= ~SC_OP_LED_ASSOCIATED
;
1108 ath_unregister_led(&sc
->tx_led
);
1109 ath_unregister_led(&sc
->rx_led
);
1110 ath_unregister_led(&sc
->radio_led
);
1111 ath9k_hw_set_gpio(sc
->sc_ah
, sc
->sc_ah
->led_pin
, 1);
1114 static void ath_init_leds(struct ath_softc
*sc
)
1119 if (AR_SREV_9287(sc
->sc_ah
))
1120 sc
->sc_ah
->led_pin
= ATH_LED_PIN_9287
;
1122 sc
->sc_ah
->led_pin
= ATH_LED_PIN_DEF
;
1124 /* Configure gpio 1 for output */
1125 ath9k_hw_cfg_output(sc
->sc_ah
, sc
->sc_ah
->led_pin
,
1126 AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
1127 /* LED off, active low */
1128 ath9k_hw_set_gpio(sc
->sc_ah
, sc
->sc_ah
->led_pin
, 1);
1130 INIT_DELAYED_WORK(&sc
->ath_led_blink_work
, ath_led_blink_work
);
1132 trigger
= ieee80211_get_radio_led_name(sc
->hw
);
1133 snprintf(sc
->radio_led
.name
, sizeof(sc
->radio_led
.name
),
1134 "ath9k-%s::radio", wiphy_name(sc
->hw
->wiphy
));
1135 ret
= ath_register_led(sc
, &sc
->radio_led
, trigger
);
1136 sc
->radio_led
.led_type
= ATH_LED_RADIO
;
1140 trigger
= ieee80211_get_assoc_led_name(sc
->hw
);
1141 snprintf(sc
->assoc_led
.name
, sizeof(sc
->assoc_led
.name
),
1142 "ath9k-%s::assoc", wiphy_name(sc
->hw
->wiphy
));
1143 ret
= ath_register_led(sc
, &sc
->assoc_led
, trigger
);
1144 sc
->assoc_led
.led_type
= ATH_LED_ASSOC
;
1148 trigger
= ieee80211_get_tx_led_name(sc
->hw
);
1149 snprintf(sc
->tx_led
.name
, sizeof(sc
->tx_led
.name
),
1150 "ath9k-%s::tx", wiphy_name(sc
->hw
->wiphy
));
1151 ret
= ath_register_led(sc
, &sc
->tx_led
, trigger
);
1152 sc
->tx_led
.led_type
= ATH_LED_TX
;
1156 trigger
= ieee80211_get_rx_led_name(sc
->hw
);
1157 snprintf(sc
->rx_led
.name
, sizeof(sc
->rx_led
.name
),
1158 "ath9k-%s::rx", wiphy_name(sc
->hw
->wiphy
));
1159 ret
= ath_register_led(sc
, &sc
->rx_led
, trigger
);
1160 sc
->rx_led
.led_type
= ATH_LED_RX
;
1167 cancel_delayed_work_sync(&sc
->ath_led_blink_work
);
1168 ath_deinit_leds(sc
);
1171 void ath_radio_enable(struct ath_softc
*sc
, struct ieee80211_hw
*hw
)
1173 struct ath_hw
*ah
= sc
->sc_ah
;
1174 struct ath_common
*common
= ath9k_hw_common(ah
);
1175 struct ieee80211_channel
*channel
= hw
->conf
.channel
;
1178 ath9k_ps_wakeup(sc
);
1179 ath9k_hw_configpcipowersave(ah
, 0, 0);
1182 ah
->curchan
= ath_get_curchannel(sc
, sc
->hw
);
1184 spin_lock_bh(&sc
->sc_resetlock
);
1185 r
= ath9k_hw_reset(ah
, ah
->curchan
, false);
1187 ath_print(common
, ATH_DBG_FATAL
,
1188 "Unable to reset channel %u (%uMhz) ",
1189 "reset status %d\n",
1190 channel
->center_freq
, r
);
1192 spin_unlock_bh(&sc
->sc_resetlock
);
1194 ath_update_txpow(sc
);
1195 if (ath_startrecv(sc
) != 0) {
1196 ath_print(common
, ATH_DBG_FATAL
,
1197 "Unable to restart recv logic\n");
1201 if (sc
->sc_flags
& SC_OP_BEACONS
)
1202 ath_beacon_config(sc
, NULL
); /* restart beacons */
1204 /* Re-Enable interrupts */
1205 ath9k_hw_set_interrupts(ah
, sc
->imask
);
1208 ath9k_hw_cfg_output(ah
, ah
->led_pin
,
1209 AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
1210 ath9k_hw_set_gpio(ah
, ah
->led_pin
, 0);
1212 ieee80211_wake_queues(hw
);
1213 ath9k_ps_restore(sc
);
1216 void ath_radio_disable(struct ath_softc
*sc
, struct ieee80211_hw
*hw
)
1218 struct ath_hw
*ah
= sc
->sc_ah
;
1219 struct ieee80211_channel
*channel
= hw
->conf
.channel
;
1222 ath9k_ps_wakeup(sc
);
1223 ieee80211_stop_queues(hw
);
1226 ath9k_hw_set_gpio(ah
, ah
->led_pin
, 1);
1227 ath9k_hw_cfg_gpio_input(ah
, ah
->led_pin
);
1229 /* Disable interrupts */
1230 ath9k_hw_set_interrupts(ah
, 0);
1232 ath_drain_all_txq(sc
, false); /* clear pending tx frames */
1233 ath_stoprecv(sc
); /* turn off frame recv */
1234 ath_flushrecv(sc
); /* flush recv queue */
1237 ah
->curchan
= ath_get_curchannel(sc
, hw
);
1239 spin_lock_bh(&sc
->sc_resetlock
);
1240 r
= ath9k_hw_reset(ah
, ah
->curchan
, false);
1242 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_FATAL
,
1243 "Unable to reset channel %u (%uMhz) "
1244 "reset status %d\n",
1245 channel
->center_freq
, r
);
1247 spin_unlock_bh(&sc
->sc_resetlock
);
1249 ath9k_hw_phy_disable(ah
);
1250 ath9k_hw_configpcipowersave(ah
, 1, 1);
1251 ath9k_ps_restore(sc
);
1252 ath9k_setpower(sc
, ATH9K_PM_FULL_SLEEP
);
1255 /*******************/
1257 /*******************/
1259 static bool ath_is_rfkill_set(struct ath_softc
*sc
)
1261 struct ath_hw
*ah
= sc
->sc_ah
;
1263 return ath9k_hw_gpio_get(ah
, ah
->rfkill_gpio
) ==
1264 ah
->rfkill_polarity
;
1267 static void ath9k_rfkill_poll_state(struct ieee80211_hw
*hw
)
1269 struct ath_wiphy
*aphy
= hw
->priv
;
1270 struct ath_softc
*sc
= aphy
->sc
;
1271 bool blocked
= !!ath_is_rfkill_set(sc
);
1273 wiphy_rfkill_set_hw_state(hw
->wiphy
, blocked
);
1276 static void ath_start_rfkill_poll(struct ath_softc
*sc
)
1278 struct ath_hw
*ah
= sc
->sc_ah
;
1280 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1281 wiphy_rfkill_start_polling(sc
->hw
->wiphy
);
1284 static void ath9k_uninit_hw(struct ath_softc
*sc
)
1286 struct ath_hw
*ah
= sc
->sc_ah
;
1290 ath9k_exit_debug(ah
);
1291 ath9k_hw_detach(ah
);
1295 static void ath_clean_core(struct ath_softc
*sc
)
1297 struct ieee80211_hw
*hw
= sc
->hw
;
1298 struct ath_hw
*ah
= sc
->sc_ah
;
1301 ath9k_ps_wakeup(sc
);
1303 dev_dbg(sc
->dev
, "Detach ATH hw\n");
1305 ath_deinit_leds(sc
);
1306 wiphy_rfkill_stop_polling(sc
->hw
->wiphy
);
1308 for (i
= 0; i
< sc
->num_sec_wiphy
; i
++) {
1309 struct ath_wiphy
*aphy
= sc
->sec_wiphy
[i
];
1312 sc
->sec_wiphy
[i
] = NULL
;
1313 ieee80211_unregister_hw(aphy
->hw
);
1314 ieee80211_free_hw(aphy
->hw
);
1316 ieee80211_unregister_hw(hw
);
1320 tasklet_kill(&sc
->intr_tq
);
1321 tasklet_kill(&sc
->bcon_tasklet
);
1323 if (!(sc
->sc_flags
& SC_OP_INVALID
))
1324 ath9k_setpower(sc
, ATH9K_PM_AWAKE
);
1326 /* cleanup tx queues */
1327 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1328 if (ATH_TXQ_SETUP(sc
, i
))
1329 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
1331 if ((sc
->btcoex
.no_stomp_timer
) &&
1332 ah
->btcoex_hw
.scheme
== ATH_BTCOEX_CFG_3WIRE
)
1333 ath_gen_timer_free(ah
, sc
->btcoex
.no_stomp_timer
);
1336 void ath_detach(struct ath_softc
*sc
)
1339 ath9k_uninit_hw(sc
);
1342 void ath_cleanup(struct ath_softc
*sc
)
1344 struct ath_hw
*ah
= sc
->sc_ah
;
1345 struct ath_common
*common
= ath9k_hw_common(ah
);
1348 free_irq(sc
->irq
, sc
);
1349 ath_bus_cleanup(common
);
1350 kfree(sc
->sec_wiphy
);
1351 ieee80211_free_hw(sc
->hw
);
1353 ath9k_uninit_hw(sc
);
1356 static int ath9k_reg_notifier(struct wiphy
*wiphy
,
1357 struct regulatory_request
*request
)
1359 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
1360 struct ath_wiphy
*aphy
= hw
->priv
;
1361 struct ath_softc
*sc
= aphy
->sc
;
1362 struct ath_regulatory
*reg
= ath9k_hw_regulatory(sc
->sc_ah
);
1364 return ath_reg_notifier_apply(wiphy
, request
, reg
);
1368 * Detects if there is any priority bt traffic
1370 static void ath_detect_bt_priority(struct ath_softc
*sc
)
1372 struct ath_btcoex
*btcoex
= &sc
->btcoex
;
1373 struct ath_hw
*ah
= sc
->sc_ah
;
1375 if (ath9k_hw_gpio_get(sc
->sc_ah
, ah
->btcoex_hw
.btpriority_gpio
))
1376 btcoex
->bt_priority_cnt
++;
1378 if (time_after(jiffies
, btcoex
->bt_priority_time
+
1379 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD
))) {
1380 if (btcoex
->bt_priority_cnt
>= ATH_BT_CNT_THRESHOLD
) {
1381 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_BTCOEX
,
1382 "BT priority traffic detected");
1383 sc
->sc_flags
|= SC_OP_BT_PRIORITY_DETECTED
;
1385 sc
->sc_flags
&= ~SC_OP_BT_PRIORITY_DETECTED
;
1388 btcoex
->bt_priority_cnt
= 0;
1389 btcoex
->bt_priority_time
= jiffies
;
1394 * Configures appropriate weight based on stomp type.
1396 static void ath9k_btcoex_bt_stomp(struct ath_softc
*sc
,
1397 enum ath_stomp_type stomp_type
)
1399 struct ath_hw
*ah
= sc
->sc_ah
;
1401 switch (stomp_type
) {
1402 case ATH_BTCOEX_STOMP_ALL
:
1403 ath9k_hw_btcoex_set_weight(ah
, AR_BT_COEX_WGHT
,
1404 AR_STOMP_ALL_WLAN_WGHT
);
1406 case ATH_BTCOEX_STOMP_LOW
:
1407 ath9k_hw_btcoex_set_weight(ah
, AR_BT_COEX_WGHT
,
1408 AR_STOMP_LOW_WLAN_WGHT
);
1410 case ATH_BTCOEX_STOMP_NONE
:
1411 ath9k_hw_btcoex_set_weight(ah
, AR_BT_COEX_WGHT
,
1412 AR_STOMP_NONE_WLAN_WGHT
);
1415 ath_print(ath9k_hw_common(ah
), ATH_DBG_BTCOEX
,
1416 "Invalid Stomptype\n");
1420 ath9k_hw_btcoex_enable(ah
);
1423 static void ath9k_gen_timer_start(struct ath_hw
*ah
,
1424 struct ath_gen_timer
*timer
,
1428 struct ath_common
*common
= ath9k_hw_common(ah
);
1429 struct ath_softc
*sc
= (struct ath_softc
*) common
->priv
;
1431 ath9k_hw_gen_timer_start(ah
, timer
, timer_next
, timer_period
);
1433 if ((sc
->imask
& ATH9K_INT_GENTIMER
) == 0) {
1434 ath9k_hw_set_interrupts(ah
, 0);
1435 sc
->imask
|= ATH9K_INT_GENTIMER
;
1436 ath9k_hw_set_interrupts(ah
, sc
->imask
);
1440 static void ath9k_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
1442 struct ath_common
*common
= ath9k_hw_common(ah
);
1443 struct ath_softc
*sc
= (struct ath_softc
*) common
->priv
;
1444 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
1446 ath9k_hw_gen_timer_stop(ah
, timer
);
1448 /* if no timer is enabled, turn off interrupt mask */
1449 if (timer_table
->timer_mask
.val
== 0) {
1450 ath9k_hw_set_interrupts(ah
, 0);
1451 sc
->imask
&= ~ATH9K_INT_GENTIMER
;
1452 ath9k_hw_set_interrupts(ah
, sc
->imask
);
1457 * This is the master bt coex timer which runs for every
1458 * 45ms, bt traffic will be given priority during 55% of this
1459 * period while wlan gets remaining 45%
1461 static void ath_btcoex_period_timer(unsigned long data
)
1463 struct ath_softc
*sc
= (struct ath_softc
*) data
;
1464 struct ath_hw
*ah
= sc
->sc_ah
;
1465 struct ath_btcoex
*btcoex
= &sc
->btcoex
;
1467 ath_detect_bt_priority(sc
);
1469 spin_lock_bh(&btcoex
->btcoex_lock
);
1471 ath9k_btcoex_bt_stomp(sc
, btcoex
->bt_stomp_type
);
1473 spin_unlock_bh(&btcoex
->btcoex_lock
);
1475 if (btcoex
->btcoex_period
!= btcoex
->btcoex_no_stomp
) {
1476 if (btcoex
->hw_timer_enabled
)
1477 ath9k_gen_timer_stop(ah
, btcoex
->no_stomp_timer
);
1479 ath9k_gen_timer_start(ah
,
1480 btcoex
->no_stomp_timer
,
1481 (ath9k_hw_gettsf32(ah
) +
1482 btcoex
->btcoex_no_stomp
),
1483 btcoex
->btcoex_no_stomp
* 10);
1484 btcoex
->hw_timer_enabled
= true;
1487 mod_timer(&btcoex
->period_timer
, jiffies
+
1488 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD
));
1492 * Generic tsf based hw timer which configures weight
1493 * registers to time slice between wlan and bt traffic
1495 static void ath_btcoex_no_stomp_timer(void *arg
)
1497 struct ath_softc
*sc
= (struct ath_softc
*)arg
;
1498 struct ath_hw
*ah
= sc
->sc_ah
;
1499 struct ath_btcoex
*btcoex
= &sc
->btcoex
;
1501 ath_print(ath9k_hw_common(ah
), ATH_DBG_BTCOEX
,
1502 "no stomp timer running \n");
1504 spin_lock_bh(&btcoex
->btcoex_lock
);
1506 if (btcoex
->bt_stomp_type
== ATH_BTCOEX_STOMP_LOW
)
1507 ath9k_btcoex_bt_stomp(sc
, ATH_BTCOEX_STOMP_NONE
);
1508 else if (btcoex
->bt_stomp_type
== ATH_BTCOEX_STOMP_ALL
)
1509 ath9k_btcoex_bt_stomp(sc
, ATH_BTCOEX_STOMP_LOW
);
1511 spin_unlock_bh(&btcoex
->btcoex_lock
);
1514 static int ath_init_btcoex_timer(struct ath_softc
*sc
)
1516 struct ath_btcoex
*btcoex
= &sc
->btcoex
;
1518 btcoex
->btcoex_period
= ATH_BTCOEX_DEF_BT_PERIOD
* 1000;
1519 btcoex
->btcoex_no_stomp
= (100 - ATH_BTCOEX_DEF_DUTY_CYCLE
) *
1520 btcoex
->btcoex_period
/ 100;
1522 setup_timer(&btcoex
->period_timer
, ath_btcoex_period_timer
,
1523 (unsigned long) sc
);
1525 spin_lock_init(&btcoex
->btcoex_lock
);
1527 btcoex
->no_stomp_timer
= ath_gen_timer_alloc(sc
->sc_ah
,
1528 ath_btcoex_no_stomp_timer
,
1529 ath_btcoex_no_stomp_timer
,
1530 (void *) sc
, AR_FIRST_NDP_TIMER
);
1532 if (!btcoex
->no_stomp_timer
)
1539 * Read and write, they both share the same lock. We do this to serialize
1540 * reads and writes on Atheros 802.11n PCI devices only. This is required
1541 * as the FIFO on these devices can only accept sanely 2 requests. After
1542 * that the device goes bananas. Serializing the reads/writes prevents this
1546 static void ath9k_iowrite32(void *hw_priv
, u32 val
, u32 reg_offset
)
1548 struct ath_hw
*ah
= (struct ath_hw
*) hw_priv
;
1549 struct ath_common
*common
= ath9k_hw_common(ah
);
1550 struct ath_softc
*sc
= (struct ath_softc
*) common
->priv
;
1552 if (ah
->config
.serialize_regmode
== SER_REG_MODE_ON
) {
1553 unsigned long flags
;
1554 spin_lock_irqsave(&sc
->sc_serial_rw
, flags
);
1555 iowrite32(val
, sc
->mem
+ reg_offset
);
1556 spin_unlock_irqrestore(&sc
->sc_serial_rw
, flags
);
1558 iowrite32(val
, sc
->mem
+ reg_offset
);
1561 static unsigned int ath9k_ioread32(void *hw_priv
, u32 reg_offset
)
1563 struct ath_hw
*ah
= (struct ath_hw
*) hw_priv
;
1564 struct ath_common
*common
= ath9k_hw_common(ah
);
1565 struct ath_softc
*sc
= (struct ath_softc
*) common
->priv
;
1568 if (ah
->config
.serialize_regmode
== SER_REG_MODE_ON
) {
1569 unsigned long flags
;
1570 spin_lock_irqsave(&sc
->sc_serial_rw
, flags
);
1571 val
= ioread32(sc
->mem
+ reg_offset
);
1572 spin_unlock_irqrestore(&sc
->sc_serial_rw
, flags
);
1574 val
= ioread32(sc
->mem
+ reg_offset
);
1578 static const struct ath_ops ath9k_common_ops
= {
1579 .read
= ath9k_ioread32
,
1580 .write
= ath9k_iowrite32
,
1584 * Initialize and fill ath_softc, ath_sofct is the
1585 * "Software Carrier" struct. Historically it has existed
1586 * to allow the separation between hardware specific
1587 * variables (now in ath_hw) and driver specific variables.
1589 static int ath_init_softc(u16 devid
, struct ath_softc
*sc
, u16 subsysid
,
1590 const struct ath_bus_ops
*bus_ops
)
1592 struct ath_hw
*ah
= NULL
;
1593 struct ath_common
*common
;
1598 /* XXX: hardware will not be ready until ath_open() being called */
1599 sc
->sc_flags
|= SC_OP_INVALID
;
1601 spin_lock_init(&sc
->wiphy_lock
);
1602 spin_lock_init(&sc
->sc_resetlock
);
1603 spin_lock_init(&sc
->sc_serial_rw
);
1604 spin_lock_init(&sc
->sc_pm_lock
);
1605 mutex_init(&sc
->mutex
);
1606 tasklet_init(&sc
->intr_tq
, ath9k_tasklet
, (unsigned long)sc
);
1607 tasklet_init(&sc
->bcon_tasklet
, ath_beacon_tasklet
,
1610 ah
= kzalloc(sizeof(struct ath_hw
), GFP_KERNEL
);
1614 ah
->hw_version
.devid
= devid
;
1615 ah
->hw_version
.subsysid
= subsysid
;
1618 common
= ath9k_hw_common(ah
);
1619 common
->ops
= &ath9k_common_ops
;
1620 common
->bus_ops
= bus_ops
;
1622 common
->hw
= sc
->hw
;
1624 common
->debug_mask
= ath9k_debug
;
1627 * Cache line size is used to size and align various
1628 * structures used to communicate with the hardware.
1630 ath_read_cachesize(common
, &csz
);
1631 /* XXX assert csz is non-zero */
1632 common
->cachelsz
= csz
<< 2; /* convert to bytes */
1634 r
= ath9k_hw_init(ah
);
1636 ath_print(common
, ATH_DBG_FATAL
,
1637 "Unable to initialize hardware; "
1638 "initialization status: %d\n", r
);
1642 if (ath9k_init_debug(ah
) < 0) {
1643 ath_print(common
, ATH_DBG_FATAL
,
1644 "Unable to create debugfs files\n");
1648 /* Get the hardware key cache size. */
1649 common
->keymax
= ah
->caps
.keycache_size
;
1650 if (common
->keymax
> ATH_KEYMAX
) {
1651 ath_print(common
, ATH_DBG_ANY
,
1652 "Warning, using only %u entries in %u key cache\n",
1653 ATH_KEYMAX
, common
->keymax
);
1654 common
->keymax
= ATH_KEYMAX
;
1658 * Reset the key cache since some parts do not
1659 * reset the contents on initial power up.
1661 for (i
= 0; i
< common
->keymax
; i
++)
1662 ath9k_hw_keyreset(ah
, (u16
) i
);
1664 /* default to MONITOR mode */
1665 sc
->sc_ah
->opmode
= NL80211_IFTYPE_MONITOR
;
1668 * Allocate hardware transmit queues: one queue for
1669 * beacon frames and one data queue for each QoS
1670 * priority. Note that the hal handles reseting
1671 * these queues at the needed time.
1673 sc
->beacon
.beaconq
= ath9k_hw_beaconq_setup(ah
);
1674 if (sc
->beacon
.beaconq
== -1) {
1675 ath_print(common
, ATH_DBG_FATAL
,
1676 "Unable to setup a beacon xmit queue\n");
1680 sc
->beacon
.cabq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_CAB
, 0);
1681 if (sc
->beacon
.cabq
== NULL
) {
1682 ath_print(common
, ATH_DBG_FATAL
,
1683 "Unable to setup CAB xmit queue\n");
1688 sc
->config
.cabqReadytime
= ATH_CABQ_READY_TIME
;
1689 ath_cabq_update(sc
);
1691 for (i
= 0; i
< ARRAY_SIZE(sc
->tx
.hwq_map
); i
++)
1692 sc
->tx
.hwq_map
[i
] = -1;
1694 /* Setup data queues */
1695 /* NB: ensure BK queue is the lowest priority h/w queue */
1696 if (!ath_tx_setup(sc
, ATH9K_WME_AC_BK
)) {
1697 ath_print(common
, ATH_DBG_FATAL
,
1698 "Unable to setup xmit queue for BK traffic\n");
1703 if (!ath_tx_setup(sc
, ATH9K_WME_AC_BE
)) {
1704 ath_print(common
, ATH_DBG_FATAL
,
1705 "Unable to setup xmit queue for BE traffic\n");
1709 if (!ath_tx_setup(sc
, ATH9K_WME_AC_VI
)) {
1710 ath_print(common
, ATH_DBG_FATAL
,
1711 "Unable to setup xmit queue for VI traffic\n");
1715 if (!ath_tx_setup(sc
, ATH9K_WME_AC_VO
)) {
1716 ath_print(common
, ATH_DBG_FATAL
,
1717 "Unable to setup xmit queue for VO traffic\n");
1722 /* Initializes the noise floor to a reasonable default value.
1723 * Later on this will be updated during ANI processing. */
1725 common
->ani
.noise_floor
= ATH_DEFAULT_NOISE_FLOOR
;
1726 setup_timer(&common
->ani
.timer
, ath_ani_calibrate
, (unsigned long)sc
);
1728 if (ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1729 ATH9K_CIPHER_TKIP
, NULL
)) {
1731 * Whether we should enable h/w TKIP MIC.
1732 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1733 * report WMM capable, so it's always safe to turn on
1734 * TKIP MIC in this case.
1736 ath9k_hw_setcapability(sc
->sc_ah
, ATH9K_CAP_TKIP_MIC
,
1741 * Check whether the separate key cache entries
1742 * are required to handle both tx+rx MIC keys.
1743 * With split mic keys the number of stations is limited
1744 * to 27 otherwise 59.
1746 if (ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1747 ATH9K_CIPHER_TKIP
, NULL
)
1748 && ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1749 ATH9K_CIPHER_MIC
, NULL
)
1750 && ath9k_hw_getcapability(ah
, ATH9K_CAP_TKIP_SPLIT
,
1752 common
->splitmic
= 1;
1754 /* turn on mcast key search if possible */
1755 if (!ath9k_hw_getcapability(ah
, ATH9K_CAP_MCAST_KEYSRCH
, 0, NULL
))
1756 (void)ath9k_hw_setcapability(ah
, ATH9K_CAP_MCAST_KEYSRCH
, 1,
1759 sc
->config
.txpowlimit
= ATH_TXPOWER_MAX
;
1761 /* 11n Capabilities */
1762 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
) {
1763 sc
->sc_flags
|= SC_OP_TXAGGR
;
1764 sc
->sc_flags
|= SC_OP_RXAGGR
;
1767 common
->tx_chainmask
= ah
->caps
.tx_chainmask
;
1768 common
->rx_chainmask
= ah
->caps
.rx_chainmask
;
1770 ath9k_hw_setcapability(ah
, ATH9K_CAP_DIVERSITY
, 1, true, NULL
);
1771 sc
->rx
.defant
= ath9k_hw_getdefantenna(ah
);
1773 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
)
1774 memcpy(common
->bssidmask
, ath_bcast_mac
, ETH_ALEN
);
1776 sc
->beacon
.slottime
= ATH9K_SLOT_TIME_9
; /* default to short slot time */
1778 /* initialize beacon slots */
1779 for (i
= 0; i
< ARRAY_SIZE(sc
->beacon
.bslot
); i
++) {
1780 sc
->beacon
.bslot
[i
] = NULL
;
1781 sc
->beacon
.bslot_aphy
[i
] = NULL
;
1784 /* setup channels and rates */
1786 if (test_bit(ATH9K_MODE_11G
, sc
->sc_ah
->caps
.wireless_modes
)) {
1787 sc
->sbands
[IEEE80211_BAND_2GHZ
].channels
= ath9k_2ghz_chantable
;
1788 sc
->sbands
[IEEE80211_BAND_2GHZ
].band
= IEEE80211_BAND_2GHZ
;
1789 sc
->sbands
[IEEE80211_BAND_2GHZ
].n_channels
=
1790 ARRAY_SIZE(ath9k_2ghz_chantable
);
1791 sc
->sbands
[IEEE80211_BAND_2GHZ
].bitrates
= ath9k_legacy_rates
;
1792 sc
->sbands
[IEEE80211_BAND_2GHZ
].n_bitrates
=
1793 ARRAY_SIZE(ath9k_legacy_rates
);
1796 if (test_bit(ATH9K_MODE_11A
, sc
->sc_ah
->caps
.wireless_modes
)) {
1797 sc
->sbands
[IEEE80211_BAND_5GHZ
].channels
= ath9k_5ghz_chantable
;
1798 sc
->sbands
[IEEE80211_BAND_5GHZ
].band
= IEEE80211_BAND_5GHZ
;
1799 sc
->sbands
[IEEE80211_BAND_5GHZ
].n_channels
=
1800 ARRAY_SIZE(ath9k_5ghz_chantable
);
1801 sc
->sbands
[IEEE80211_BAND_5GHZ
].bitrates
=
1802 ath9k_legacy_rates
+ 4;
1803 sc
->sbands
[IEEE80211_BAND_5GHZ
].n_bitrates
=
1804 ARRAY_SIZE(ath9k_legacy_rates
) - 4;
1807 switch (ah
->btcoex_hw
.scheme
) {
1808 case ATH_BTCOEX_CFG_NONE
:
1810 case ATH_BTCOEX_CFG_2WIRE
:
1811 ath9k_hw_btcoex_init_2wire(ah
);
1813 case ATH_BTCOEX_CFG_3WIRE
:
1814 ath9k_hw_btcoex_init_3wire(ah
);
1815 r
= ath_init_btcoex_timer(sc
);
1818 qnum
= ath_tx_get_qnum(sc
, ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BE
);
1819 ath9k_hw_init_btcoex_hw(ah
, qnum
);
1820 sc
->btcoex
.bt_stomp_type
= ATH_BTCOEX_STOMP_LOW
;
1829 /* cleanup tx queues */
1830 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1831 if (ATH_TXQ_SETUP(sc
, i
))
1832 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
1835 ath9k_uninit_hw(sc
);
1839 void ath_set_hw_capab(struct ath_softc
*sc
, struct ieee80211_hw
*hw
)
1841 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
1842 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1843 IEEE80211_HW_SIGNAL_DBM
|
1844 IEEE80211_HW_AMPDU_AGGREGATION
|
1845 IEEE80211_HW_SUPPORTS_PS
|
1846 IEEE80211_HW_PS_NULLFUNC_STACK
|
1847 IEEE80211_HW_SPECTRUM_MGMT
;
1849 if (AR_SREV_9160_10_OR_LATER(sc
->sc_ah
) || modparam_nohwcrypt
)
1850 hw
->flags
|= IEEE80211_HW_MFP_CAPABLE
;
1852 hw
->wiphy
->interface_modes
=
1853 BIT(NL80211_IFTYPE_AP
) |
1854 BIT(NL80211_IFTYPE_STATION
) |
1855 BIT(NL80211_IFTYPE_ADHOC
) |
1856 BIT(NL80211_IFTYPE_MESH_POINT
);
1858 hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
1862 hw
->channel_change_time
= 5000;
1863 hw
->max_listen_interval
= 10;
1864 /* Hardware supports 10 but we use 4 */
1865 hw
->max_rate_tries
= 4;
1866 hw
->sta_data_size
= sizeof(struct ath_node
);
1867 hw
->vif_data_size
= sizeof(struct ath_vif
);
1869 hw
->rate_control_algorithm
= "ath9k_rate_control";
1871 if (test_bit(ATH9K_MODE_11G
, sc
->sc_ah
->caps
.wireless_modes
))
1872 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] =
1873 &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1874 if (test_bit(ATH9K_MODE_11A
, sc
->sc_ah
->caps
.wireless_modes
))
1875 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] =
1876 &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1879 /* Device driver core initialization */
1880 int ath_init_device(u16 devid
, struct ath_softc
*sc
, u16 subsysid
,
1881 const struct ath_bus_ops
*bus_ops
)
1883 struct ieee80211_hw
*hw
= sc
->hw
;
1884 struct ath_common
*common
;
1887 struct ath_regulatory
*reg
;
1889 dev_dbg(sc
->dev
, "Attach ATH hw\n");
1891 error
= ath_init_softc(devid
, sc
, subsysid
, bus_ops
);
1896 common
= ath9k_hw_common(ah
);
1898 /* get mac address from hardware and set in mac80211 */
1900 SET_IEEE80211_PERM_ADDR(hw
, common
->macaddr
);
1902 ath_set_hw_capab(sc
, hw
);
1904 error
= ath_regd_init(&common
->regulatory
, sc
->hw
->wiphy
,
1905 ath9k_reg_notifier
);
1909 reg
= &common
->regulatory
;
1911 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
) {
1912 if (test_bit(ATH9K_MODE_11G
, ah
->caps
.wireless_modes
))
1914 &sc
->sbands
[IEEE80211_BAND_2GHZ
].ht_cap
);
1915 if (test_bit(ATH9K_MODE_11A
, ah
->caps
.wireless_modes
))
1917 &sc
->sbands
[IEEE80211_BAND_5GHZ
].ht_cap
);
1920 /* initialize tx/rx engine */
1921 error
= ath_tx_init(sc
, ATH_TXBUF
);
1925 error
= ath_rx_init(sc
, ATH_RXBUF
);
1929 INIT_WORK(&sc
->chan_work
, ath9k_wiphy_chan_work
);
1930 INIT_DELAYED_WORK(&sc
->wiphy_work
, ath9k_wiphy_work
);
1931 sc
->wiphy_scheduler_int
= msecs_to_jiffies(500);
1933 error
= ieee80211_register_hw(hw
);
1935 if (!ath_is_world_regd(reg
)) {
1936 error
= regulatory_hint(hw
->wiphy
, reg
->alpha2
);
1941 /* Initialize LED control */
1944 ath_start_rfkill_poll(sc
);
1949 /* cleanup tx queues */
1950 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1951 if (ATH_TXQ_SETUP(sc
, i
))
1952 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
1954 ath9k_uninit_hw(sc
);
1959 int ath_reset(struct ath_softc
*sc
, bool retry_tx
)
1961 struct ath_hw
*ah
= sc
->sc_ah
;
1962 struct ath_common
*common
= ath9k_hw_common(ah
);
1963 struct ieee80211_hw
*hw
= sc
->hw
;
1967 del_timer_sync(&common
->ani
.timer
);
1969 ath9k_hw_set_interrupts(ah
, 0);
1970 ath_drain_all_txq(sc
, retry_tx
);
1974 spin_lock_bh(&sc
->sc_resetlock
);
1975 r
= ath9k_hw_reset(ah
, sc
->sc_ah
->curchan
, false);
1977 ath_print(common
, ATH_DBG_FATAL
,
1978 "Unable to reset hardware; reset status %d\n", r
);
1979 spin_unlock_bh(&sc
->sc_resetlock
);
1981 if (ath_startrecv(sc
) != 0)
1982 ath_print(common
, ATH_DBG_FATAL
,
1983 "Unable to start recv logic\n");
1986 * We may be doing a reset in response to a request
1987 * that changes the channel so update any state that
1988 * might change as a result.
1990 ath_cache_conf_rate(sc
, &hw
->conf
);
1992 ath_update_txpow(sc
);
1994 if (sc
->sc_flags
& SC_OP_BEACONS
)
1995 ath_beacon_config(sc
, NULL
); /* restart beacons */
1997 ath9k_hw_set_interrupts(ah
, sc
->imask
);
2001 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2002 if (ATH_TXQ_SETUP(sc
, i
)) {
2003 spin_lock_bh(&sc
->tx
.txq
[i
].axq_lock
);
2004 ath_txq_schedule(sc
, &sc
->tx
.txq
[i
]);
2005 spin_unlock_bh(&sc
->tx
.txq
[i
].axq_lock
);
2011 ath_start_ani(common
);
2017 * This function will allocate both the DMA descriptor structure, and the
2018 * buffers it contains. These are used to contain the descriptors used
2021 int ath_descdma_setup(struct ath_softc
*sc
, struct ath_descdma
*dd
,
2022 struct list_head
*head
, const char *name
,
2023 int nbuf
, int ndesc
)
2025 #define DS2PHYS(_dd, _ds) \
2026 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2027 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2028 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
2029 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2030 struct ath_desc
*ds
;
2032 int i
, bsize
, error
;
2034 ath_print(common
, ATH_DBG_CONFIG
, "%s DMA: %u buffers %u desc/buf\n",
2037 INIT_LIST_HEAD(head
);
2038 /* ath_desc must be a multiple of DWORDs */
2039 if ((sizeof(struct ath_desc
) % 4) != 0) {
2040 ath_print(common
, ATH_DBG_FATAL
,
2041 "ath_desc not DWORD aligned\n");
2042 BUG_ON((sizeof(struct ath_desc
) % 4) != 0);
2047 dd
->dd_desc_len
= sizeof(struct ath_desc
) * nbuf
* ndesc
;
2050 * Need additional DMA memory because we can't use
2051 * descriptors that cross the 4K page boundary. Assume
2052 * one skipped descriptor per 4K page.
2054 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_4KB_SPLITTRANS
)) {
2056 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd
->dd_desc_len
);
2059 while (ndesc_skipped
) {
2060 dma_len
= ndesc_skipped
* sizeof(struct ath_desc
);
2061 dd
->dd_desc_len
+= dma_len
;
2063 ndesc_skipped
= ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len
);
2067 /* allocate descriptors */
2068 dd
->dd_desc
= dma_alloc_coherent(sc
->dev
, dd
->dd_desc_len
,
2069 &dd
->dd_desc_paddr
, GFP_KERNEL
);
2070 if (dd
->dd_desc
== NULL
) {
2075 ath_print(common
, ATH_DBG_CONFIG
, "%s DMA map: %p (%u) -> %llx (%u)\n",
2076 name
, ds
, (u32
) dd
->dd_desc_len
,
2077 ito64(dd
->dd_desc_paddr
), /*XXX*/(u32
) dd
->dd_desc_len
);
2079 /* allocate buffers */
2080 bsize
= sizeof(struct ath_buf
) * nbuf
;
2081 bf
= kzalloc(bsize
, GFP_KERNEL
);
2088 for (i
= 0; i
< nbuf
; i
++, bf
++, ds
+= ndesc
) {
2090 bf
->bf_daddr
= DS2PHYS(dd
, ds
);
2092 if (!(sc
->sc_ah
->caps
.hw_caps
&
2093 ATH9K_HW_CAP_4KB_SPLITTRANS
)) {
2095 * Skip descriptor addresses which can cause 4KB
2096 * boundary crossing (addr + length) with a 32 dword
2099 while (ATH_DESC_4KB_BOUND_CHECK(bf
->bf_daddr
)) {
2100 BUG_ON((caddr_t
) bf
->bf_desc
>=
2101 ((caddr_t
) dd
->dd_desc
+
2106 bf
->bf_daddr
= DS2PHYS(dd
, ds
);
2109 list_add_tail(&bf
->list
, head
);
2113 dma_free_coherent(sc
->dev
, dd
->dd_desc_len
, dd
->dd_desc
,
2116 memset(dd
, 0, sizeof(*dd
));
2118 #undef ATH_DESC_4KB_BOUND_CHECK
2119 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2123 void ath_descdma_cleanup(struct ath_softc
*sc
,
2124 struct ath_descdma
*dd
,
2125 struct list_head
*head
)
2127 dma_free_coherent(sc
->dev
, dd
->dd_desc_len
, dd
->dd_desc
,
2130 INIT_LIST_HEAD(head
);
2131 kfree(dd
->dd_bufptr
);
2132 memset(dd
, 0, sizeof(*dd
));
2135 int ath_get_hal_qnum(u16 queue
, struct ath_softc
*sc
)
2141 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_VO
];
2144 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_VI
];
2147 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BE
];
2150 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BK
];
2153 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BE
];
2160 int ath_get_mac80211_qnum(u32 queue
, struct ath_softc
*sc
)
2165 case ATH9K_WME_AC_VO
:
2168 case ATH9K_WME_AC_VI
:
2171 case ATH9K_WME_AC_BE
:
2174 case ATH9K_WME_AC_BK
:
2185 /* XXX: Remove me once we don't depend on ath9k_channel for all
2186 * this redundant data */
2187 void ath9k_update_ichannel(struct ath_softc
*sc
, struct ieee80211_hw
*hw
,
2188 struct ath9k_channel
*ichan
)
2190 struct ieee80211_channel
*chan
= hw
->conf
.channel
;
2191 struct ieee80211_conf
*conf
= &hw
->conf
;
2193 ichan
->channel
= chan
->center_freq
;
2196 if (chan
->band
== IEEE80211_BAND_2GHZ
) {
2197 ichan
->chanmode
= CHANNEL_G
;
2198 ichan
->channelFlags
= CHANNEL_2GHZ
| CHANNEL_OFDM
| CHANNEL_G
;
2200 ichan
->chanmode
= CHANNEL_A
;
2201 ichan
->channelFlags
= CHANNEL_5GHZ
| CHANNEL_OFDM
;
2204 if (conf_is_ht(conf
))
2205 ichan
->chanmode
= ath_get_extchanmode(sc
, chan
,
2206 conf
->channel_type
);
2209 /**********************/
2210 /* mac80211 callbacks */
2211 /**********************/
2214 * (Re)start btcoex timers
2216 static void ath9k_btcoex_timer_resume(struct ath_softc
*sc
)
2218 struct ath_btcoex
*btcoex
= &sc
->btcoex
;
2219 struct ath_hw
*ah
= sc
->sc_ah
;
2221 ath_print(ath9k_hw_common(ah
), ATH_DBG_BTCOEX
,
2222 "Starting btcoex timers");
2224 /* make sure duty cycle timer is also stopped when resuming */
2225 if (btcoex
->hw_timer_enabled
)
2226 ath9k_gen_timer_stop(sc
->sc_ah
, btcoex
->no_stomp_timer
);
2228 btcoex
->bt_priority_cnt
= 0;
2229 btcoex
->bt_priority_time
= jiffies
;
2230 sc
->sc_flags
&= ~SC_OP_BT_PRIORITY_DETECTED
;
2232 mod_timer(&btcoex
->period_timer
, jiffies
);
2235 static int ath9k_start(struct ieee80211_hw
*hw
)
2237 struct ath_wiphy
*aphy
= hw
->priv
;
2238 struct ath_softc
*sc
= aphy
->sc
;
2239 struct ath_hw
*ah
= sc
->sc_ah
;
2240 struct ath_common
*common
= ath9k_hw_common(ah
);
2241 struct ieee80211_channel
*curchan
= hw
->conf
.channel
;
2242 struct ath9k_channel
*init_channel
;
2245 ath_print(common
, ATH_DBG_CONFIG
,
2246 "Starting driver with initial channel: %d MHz\n",
2247 curchan
->center_freq
);
2249 mutex_lock(&sc
->mutex
);
2251 if (ath9k_wiphy_started(sc
)) {
2252 if (sc
->chan_idx
== curchan
->hw_value
) {
2254 * Already on the operational channel, the new wiphy
2255 * can be marked active.
2257 aphy
->state
= ATH_WIPHY_ACTIVE
;
2258 ieee80211_wake_queues(hw
);
2261 * Another wiphy is on another channel, start the new
2262 * wiphy in paused state.
2264 aphy
->state
= ATH_WIPHY_PAUSED
;
2265 ieee80211_stop_queues(hw
);
2267 mutex_unlock(&sc
->mutex
);
2270 aphy
->state
= ATH_WIPHY_ACTIVE
;
2272 /* setup initial channel */
2274 sc
->chan_idx
= curchan
->hw_value
;
2276 init_channel
= ath_get_curchannel(sc
, hw
);
2278 /* Reset SERDES registers */
2279 ath9k_hw_configpcipowersave(ah
, 0, 0);
2282 * The basic interface to setting the hardware in a good
2283 * state is ``reset''. On return the hardware is known to
2284 * be powered up and with interrupts disabled. This must
2285 * be followed by initialization of the appropriate bits
2286 * and then setup of the interrupt mask.
2288 spin_lock_bh(&sc
->sc_resetlock
);
2289 r
= ath9k_hw_reset(ah
, init_channel
, false);
2291 ath_print(common
, ATH_DBG_FATAL
,
2292 "Unable to reset hardware; reset status %d "
2293 "(freq %u MHz)\n", r
,
2294 curchan
->center_freq
);
2295 spin_unlock_bh(&sc
->sc_resetlock
);
2298 spin_unlock_bh(&sc
->sc_resetlock
);
2301 * This is needed only to setup initial state
2302 * but it's best done after a reset.
2304 ath_update_txpow(sc
);
2307 * Setup the hardware after reset:
2308 * The receive engine is set going.
2309 * Frame transmit is handled entirely
2310 * in the frame output path; there's nothing to do
2311 * here except setup the interrupt mask.
2313 if (ath_startrecv(sc
) != 0) {
2314 ath_print(common
, ATH_DBG_FATAL
,
2315 "Unable to start recv logic\n");
2320 /* Setup our intr mask. */
2321 sc
->imask
= ATH9K_INT_RX
| ATH9K_INT_TX
2322 | ATH9K_INT_RXEOL
| ATH9K_INT_RXORN
2323 | ATH9K_INT_FATAL
| ATH9K_INT_GLOBAL
;
2325 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_GTT
)
2326 sc
->imask
|= ATH9K_INT_GTT
;
2328 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
)
2329 sc
->imask
|= ATH9K_INT_CST
;
2331 ath_cache_conf_rate(sc
, &hw
->conf
);
2333 sc
->sc_flags
&= ~SC_OP_INVALID
;
2335 /* Disable BMISS interrupt when we're not associated */
2336 sc
->imask
&= ~(ATH9K_INT_SWBA
| ATH9K_INT_BMISS
);
2337 ath9k_hw_set_interrupts(ah
, sc
->imask
);
2339 ieee80211_wake_queues(hw
);
2341 ieee80211_queue_delayed_work(sc
->hw
, &sc
->tx_complete_work
, 0);
2343 if ((ah
->btcoex_hw
.scheme
!= ATH_BTCOEX_CFG_NONE
) &&
2344 !ah
->btcoex_hw
.enabled
) {
2345 ath9k_hw_btcoex_set_weight(ah
, AR_BT_COEX_WGHT
,
2346 AR_STOMP_LOW_WLAN_WGHT
);
2347 ath9k_hw_btcoex_enable(ah
);
2349 if (common
->bus_ops
->bt_coex_prep
)
2350 common
->bus_ops
->bt_coex_prep(common
);
2351 if (ah
->btcoex_hw
.scheme
== ATH_BTCOEX_CFG_3WIRE
)
2352 ath9k_btcoex_timer_resume(sc
);
2356 mutex_unlock(&sc
->mutex
);
2361 static int ath9k_tx(struct ieee80211_hw
*hw
,
2362 struct sk_buff
*skb
)
2364 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2365 struct ath_wiphy
*aphy
= hw
->priv
;
2366 struct ath_softc
*sc
= aphy
->sc
;
2367 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2368 struct ath_tx_control txctl
;
2369 int padpos
, padsize
;
2370 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2372 if (aphy
->state
!= ATH_WIPHY_ACTIVE
&& aphy
->state
!= ATH_WIPHY_SCAN
) {
2373 ath_print(common
, ATH_DBG_XMIT
,
2374 "ath9k: %s: TX in unexpected wiphy state "
2375 "%d\n", wiphy_name(hw
->wiphy
), aphy
->state
);
2379 if (sc
->ps_enabled
) {
2381 * mac80211 does not set PM field for normal data frames, so we
2382 * need to update that based on the current PS mode.
2384 if (ieee80211_is_data(hdr
->frame_control
) &&
2385 !ieee80211_is_nullfunc(hdr
->frame_control
) &&
2386 !ieee80211_has_pm(hdr
->frame_control
)) {
2387 ath_print(common
, ATH_DBG_PS
, "Add PM=1 for a TX frame "
2388 "while in PS mode\n");
2389 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_PM
);
2393 if (unlikely(sc
->sc_ah
->power_mode
!= ATH9K_PM_AWAKE
)) {
2395 * We are using PS-Poll and mac80211 can request TX while in
2396 * power save mode. Need to wake up hardware for the TX to be
2397 * completed and if needed, also for RX of buffered frames.
2399 ath9k_ps_wakeup(sc
);
2400 ath9k_hw_setrxabort(sc
->sc_ah
, 0);
2401 if (ieee80211_is_pspoll(hdr
->frame_control
)) {
2402 ath_print(common
, ATH_DBG_PS
,
2403 "Sending PS-Poll to pick a buffered frame\n");
2404 sc
->sc_flags
|= SC_OP_WAIT_FOR_PSPOLL_DATA
;
2406 ath_print(common
, ATH_DBG_PS
,
2407 "Wake up to complete TX\n");
2408 sc
->sc_flags
|= SC_OP_WAIT_FOR_TX_ACK
;
2411 * The actual restore operation will happen only after
2412 * the sc_flags bit is cleared. We are just dropping
2413 * the ps_usecount here.
2415 ath9k_ps_restore(sc
);
2418 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
2421 * As a temporary workaround, assign seq# here; this will likely need
2422 * to be cleaned up to work better with Beacon transmission and virtual
2425 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
2426 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2427 sc
->tx
.seq_no
+= 0x10;
2428 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2429 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
2432 /* Add the padding after the header if this is not already done */
2433 padpos
= ath9k_cmn_padpos(hdr
->frame_control
);
2434 padsize
= padpos
& 3;
2435 if (padsize
&& skb
->len
>padpos
) {
2436 if (skb_headroom(skb
) < padsize
)
2438 skb_push(skb
, padsize
);
2439 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
2442 /* Check if a tx queue is available */
2444 txctl
.txq
= ath_test_get_txq(sc
, skb
);
2448 ath_print(common
, ATH_DBG_XMIT
, "transmitting packet, skb: %p\n", skb
);
2450 if (ath_tx_start(hw
, skb
, &txctl
) != 0) {
2451 ath_print(common
, ATH_DBG_XMIT
, "TX failed\n");
2457 dev_kfree_skb_any(skb
);
2462 * Pause btcoex timer and bt duty cycle timer
2464 static void ath9k_btcoex_timer_pause(struct ath_softc
*sc
)
2466 struct ath_btcoex
*btcoex
= &sc
->btcoex
;
2467 struct ath_hw
*ah
= sc
->sc_ah
;
2469 del_timer_sync(&btcoex
->period_timer
);
2471 if (btcoex
->hw_timer_enabled
)
2472 ath9k_gen_timer_stop(ah
, btcoex
->no_stomp_timer
);
2474 btcoex
->hw_timer_enabled
= false;
2477 static void ath9k_stop(struct ieee80211_hw
*hw
)
2479 struct ath_wiphy
*aphy
= hw
->priv
;
2480 struct ath_softc
*sc
= aphy
->sc
;
2481 struct ath_hw
*ah
= sc
->sc_ah
;
2482 struct ath_common
*common
= ath9k_hw_common(ah
);
2484 mutex_lock(&sc
->mutex
);
2486 aphy
->state
= ATH_WIPHY_INACTIVE
;
2488 cancel_delayed_work_sync(&sc
->ath_led_blink_work
);
2489 cancel_delayed_work_sync(&sc
->tx_complete_work
);
2491 if (!sc
->num_sec_wiphy
) {
2492 cancel_delayed_work_sync(&sc
->wiphy_work
);
2493 cancel_work_sync(&sc
->chan_work
);
2496 if (sc
->sc_flags
& SC_OP_INVALID
) {
2497 ath_print(common
, ATH_DBG_ANY
, "Device not present\n");
2498 mutex_unlock(&sc
->mutex
);
2502 if (ath9k_wiphy_started(sc
)) {
2503 mutex_unlock(&sc
->mutex
);
2504 return; /* another wiphy still in use */
2507 if (ah
->btcoex_hw
.enabled
) {
2508 ath9k_hw_btcoex_disable(ah
);
2509 if (ah
->btcoex_hw
.scheme
== ATH_BTCOEX_CFG_3WIRE
)
2510 ath9k_btcoex_timer_pause(sc
);
2513 /* make sure h/w will not generate any interrupt
2514 * before setting the invalid flag. */
2515 ath9k_hw_set_interrupts(ah
, 0);
2517 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
2518 ath_drain_all_txq(sc
, false);
2520 ath9k_hw_phy_disable(ah
);
2522 sc
->rx
.rxlink
= NULL
;
2524 /* disable HAL and put h/w to sleep */
2525 ath9k_hw_disable(ah
);
2526 ath9k_hw_configpcipowersave(ah
, 1, 1);
2527 ath9k_setpower(sc
, ATH9K_PM_FULL_SLEEP
);
2529 sc
->sc_flags
|= SC_OP_INVALID
;
2531 mutex_unlock(&sc
->mutex
);
2533 ath_print(common
, ATH_DBG_CONFIG
, "Driver halt\n");
2536 static int ath9k_add_interface(struct ieee80211_hw
*hw
,
2537 struct ieee80211_if_init_conf
*conf
)
2539 struct ath_wiphy
*aphy
= hw
->priv
;
2540 struct ath_softc
*sc
= aphy
->sc
;
2541 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2542 struct ath_vif
*avp
= (void *)conf
->vif
->drv_priv
;
2543 enum nl80211_iftype ic_opmode
= NL80211_IFTYPE_UNSPECIFIED
;
2546 mutex_lock(&sc
->mutex
);
2548 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
) &&
2554 switch (conf
->type
) {
2555 case NL80211_IFTYPE_STATION
:
2556 ic_opmode
= NL80211_IFTYPE_STATION
;
2558 case NL80211_IFTYPE_ADHOC
:
2559 case NL80211_IFTYPE_AP
:
2560 case NL80211_IFTYPE_MESH_POINT
:
2561 if (sc
->nbcnvifs
>= ATH_BCBUF
) {
2565 ic_opmode
= conf
->type
;
2568 ath_print(common
, ATH_DBG_FATAL
,
2569 "Interface type %d not yet supported\n", conf
->type
);
2574 ath_print(common
, ATH_DBG_CONFIG
,
2575 "Attach a VIF of type: %d\n", ic_opmode
);
2577 /* Set the VIF opmode */
2578 avp
->av_opmode
= ic_opmode
;
2583 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
)
2584 ath9k_set_bssid_mask(hw
);
2587 goto out
; /* skip global settings for secondary vif */
2589 if (ic_opmode
== NL80211_IFTYPE_AP
) {
2590 ath9k_hw_set_tsfadjust(sc
->sc_ah
, 1);
2591 sc
->sc_flags
|= SC_OP_TSF_RESET
;
2594 /* Set the device opmode */
2595 sc
->sc_ah
->opmode
= ic_opmode
;
2598 * Enable MIB interrupts when there are hardware phy counters.
2599 * Note we only do this (at the moment) for station mode.
2601 if ((conf
->type
== NL80211_IFTYPE_STATION
) ||
2602 (conf
->type
== NL80211_IFTYPE_ADHOC
) ||
2603 (conf
->type
== NL80211_IFTYPE_MESH_POINT
)) {
2604 sc
->imask
|= ATH9K_INT_MIB
;
2605 sc
->imask
|= ATH9K_INT_TSFOOR
;
2608 ath9k_hw_set_interrupts(sc
->sc_ah
, sc
->imask
);
2610 if (conf
->type
== NL80211_IFTYPE_AP
||
2611 conf
->type
== NL80211_IFTYPE_ADHOC
||
2612 conf
->type
== NL80211_IFTYPE_MONITOR
)
2613 ath_start_ani(common
);
2616 mutex_unlock(&sc
->mutex
);
2620 static void ath9k_remove_interface(struct ieee80211_hw
*hw
,
2621 struct ieee80211_if_init_conf
*conf
)
2623 struct ath_wiphy
*aphy
= hw
->priv
;
2624 struct ath_softc
*sc
= aphy
->sc
;
2625 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2626 struct ath_vif
*avp
= (void *)conf
->vif
->drv_priv
;
2629 ath_print(common
, ATH_DBG_CONFIG
, "Detach Interface\n");
2631 mutex_lock(&sc
->mutex
);
2634 del_timer_sync(&common
->ani
.timer
);
2636 /* Reclaim beacon resources */
2637 if ((sc
->sc_ah
->opmode
== NL80211_IFTYPE_AP
) ||
2638 (sc
->sc_ah
->opmode
== NL80211_IFTYPE_ADHOC
) ||
2639 (sc
->sc_ah
->opmode
== NL80211_IFTYPE_MESH_POINT
)) {
2640 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
2641 ath_beacon_return(sc
, avp
);
2644 sc
->sc_flags
&= ~SC_OP_BEACONS
;
2646 for (i
= 0; i
< ARRAY_SIZE(sc
->beacon
.bslot
); i
++) {
2647 if (sc
->beacon
.bslot
[i
] == conf
->vif
) {
2648 printk(KERN_DEBUG
"%s: vif had allocated beacon "
2649 "slot\n", __func__
);
2650 sc
->beacon
.bslot
[i
] = NULL
;
2651 sc
->beacon
.bslot_aphy
[i
] = NULL
;
2657 mutex_unlock(&sc
->mutex
);
2660 static int ath9k_config(struct ieee80211_hw
*hw
, u32 changed
)
2662 struct ath_wiphy
*aphy
= hw
->priv
;
2663 struct ath_softc
*sc
= aphy
->sc
;
2664 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2665 struct ieee80211_conf
*conf
= &hw
->conf
;
2666 struct ath_hw
*ah
= sc
->sc_ah
;
2669 mutex_lock(&sc
->mutex
);
2672 * Leave this as the first check because we need to turn on the
2673 * radio if it was disabled before prior to processing the rest
2674 * of the changes. Likewise we must only disable the radio towards
2677 if (changed
& IEEE80211_CONF_CHANGE_IDLE
) {
2679 bool all_wiphys_idle
;
2680 bool idle
= !!(conf
->flags
& IEEE80211_CONF_IDLE
);
2682 spin_lock_bh(&sc
->wiphy_lock
);
2683 all_wiphys_idle
= ath9k_all_wiphys_idle(sc
);
2684 ath9k_set_wiphy_idle(aphy
, idle
);
2686 if (!idle
&& all_wiphys_idle
)
2687 enable_radio
= true;
2690 * After we unlock here its possible another wiphy
2691 * can be re-renabled so to account for that we will
2692 * only disable the radio toward the end of this routine
2693 * if by then all wiphys are still idle.
2695 spin_unlock_bh(&sc
->wiphy_lock
);
2698 ath_radio_enable(sc
, hw
);
2699 ath_print(common
, ATH_DBG_CONFIG
,
2700 "not-idle: enabling radio\n");
2705 * We just prepare to enable PS. We have to wait until our AP has
2706 * ACK'd our null data frame to disable RX otherwise we'll ignore
2707 * those ACKs and end up retransmitting the same null data frames.
2708 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
2710 if (changed
& IEEE80211_CONF_CHANGE_PS
) {
2711 if (conf
->flags
& IEEE80211_CONF_PS
) {
2712 sc
->sc_flags
|= SC_OP_PS_ENABLED
;
2713 if (!(ah
->caps
.hw_caps
&
2714 ATH9K_HW_CAP_AUTOSLEEP
)) {
2715 if ((sc
->imask
& ATH9K_INT_TIM_TIMER
) == 0) {
2716 sc
->imask
|= ATH9K_INT_TIM_TIMER
;
2717 ath9k_hw_set_interrupts(sc
->sc_ah
,
2722 * At this point we know hardware has received an ACK
2723 * of a previously sent null data frame.
2725 if ((sc
->sc_flags
& SC_OP_NULLFUNC_COMPLETED
)) {
2726 sc
->sc_flags
&= ~SC_OP_NULLFUNC_COMPLETED
;
2727 sc
->ps_enabled
= true;
2728 ath9k_hw_setrxabort(sc
->sc_ah
, 1);
2731 sc
->ps_enabled
= false;
2732 sc
->sc_flags
&= ~(SC_OP_PS_ENABLED
|
2733 SC_OP_NULLFUNC_COMPLETED
);
2734 ath9k_setpower(sc
, ATH9K_PM_AWAKE
);
2735 if (!(ah
->caps
.hw_caps
&
2736 ATH9K_HW_CAP_AUTOSLEEP
)) {
2737 ath9k_hw_setrxabort(sc
->sc_ah
, 0);
2738 sc
->sc_flags
&= ~(SC_OP_WAIT_FOR_BEACON
|
2739 SC_OP_WAIT_FOR_CAB
|
2740 SC_OP_WAIT_FOR_PSPOLL_DATA
|
2741 SC_OP_WAIT_FOR_TX_ACK
);
2742 if (sc
->imask
& ATH9K_INT_TIM_TIMER
) {
2743 sc
->imask
&= ~ATH9K_INT_TIM_TIMER
;
2744 ath9k_hw_set_interrupts(sc
->sc_ah
,
2751 if (changed
& IEEE80211_CONF_CHANGE_CHANNEL
) {
2752 struct ieee80211_channel
*curchan
= hw
->conf
.channel
;
2753 int pos
= curchan
->hw_value
;
2755 aphy
->chan_idx
= pos
;
2756 aphy
->chan_is_ht
= conf_is_ht(conf
);
2758 if (aphy
->state
== ATH_WIPHY_SCAN
||
2759 aphy
->state
== ATH_WIPHY_ACTIVE
)
2760 ath9k_wiphy_pause_all_forced(sc
, aphy
);
2763 * Do not change operational channel based on a paused
2766 goto skip_chan_change
;
2769 ath_print(common
, ATH_DBG_CONFIG
, "Set channel: %d MHz\n",
2770 curchan
->center_freq
);
2772 /* XXX: remove me eventualy */
2773 ath9k_update_ichannel(sc
, hw
, &sc
->sc_ah
->channels
[pos
]);
2775 ath_update_chainmask(sc
, conf_is_ht(conf
));
2777 if (ath_set_channel(sc
, hw
, &sc
->sc_ah
->channels
[pos
]) < 0) {
2778 ath_print(common
, ATH_DBG_FATAL
,
2779 "Unable to set channel\n");
2780 mutex_unlock(&sc
->mutex
);
2786 if (changed
& IEEE80211_CONF_CHANGE_POWER
)
2787 sc
->config
.txpowlimit
= 2 * conf
->power_level
;
2789 spin_lock_bh(&sc
->wiphy_lock
);
2790 disable_radio
= ath9k_all_wiphys_idle(sc
);
2791 spin_unlock_bh(&sc
->wiphy_lock
);
2793 if (disable_radio
) {
2794 ath_print(common
, ATH_DBG_CONFIG
, "idle: disabling radio\n");
2795 ath_radio_disable(sc
, hw
);
2798 mutex_unlock(&sc
->mutex
);
2803 #define SUPPORTED_FILTERS \
2804 (FIF_PROMISC_IN_BSS | \
2809 FIF_BCN_PRBRESP_PROMISC | \
2812 /* FIXME: sc->sc_full_reset ? */
2813 static void ath9k_configure_filter(struct ieee80211_hw
*hw
,
2814 unsigned int changed_flags
,
2815 unsigned int *total_flags
,
2818 struct ath_wiphy
*aphy
= hw
->priv
;
2819 struct ath_softc
*sc
= aphy
->sc
;
2822 changed_flags
&= SUPPORTED_FILTERS
;
2823 *total_flags
&= SUPPORTED_FILTERS
;
2825 sc
->rx
.rxfilter
= *total_flags
;
2826 ath9k_ps_wakeup(sc
);
2827 rfilt
= ath_calcrxfilter(sc
);
2828 ath9k_hw_setrxfilter(sc
->sc_ah
, rfilt
);
2829 ath9k_ps_restore(sc
);
2831 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_CONFIG
,
2832 "Set HW RX filter: 0x%x\n", rfilt
);
2835 static void ath9k_sta_notify(struct ieee80211_hw
*hw
,
2836 struct ieee80211_vif
*vif
,
2837 enum sta_notify_cmd cmd
,
2838 struct ieee80211_sta
*sta
)
2840 struct ath_wiphy
*aphy
= hw
->priv
;
2841 struct ath_softc
*sc
= aphy
->sc
;
2844 case STA_NOTIFY_ADD
:
2845 ath_node_attach(sc
, sta
);
2847 case STA_NOTIFY_REMOVE
:
2848 ath_node_detach(sc
, sta
);
2855 static int ath9k_conf_tx(struct ieee80211_hw
*hw
, u16 queue
,
2856 const struct ieee80211_tx_queue_params
*params
)
2858 struct ath_wiphy
*aphy
= hw
->priv
;
2859 struct ath_softc
*sc
= aphy
->sc
;
2860 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2861 struct ath9k_tx_queue_info qi
;
2864 if (queue
>= WME_NUM_AC
)
2867 mutex_lock(&sc
->mutex
);
2869 memset(&qi
, 0, sizeof(struct ath9k_tx_queue_info
));
2871 qi
.tqi_aifs
= params
->aifs
;
2872 qi
.tqi_cwmin
= params
->cw_min
;
2873 qi
.tqi_cwmax
= params
->cw_max
;
2874 qi
.tqi_burstTime
= params
->txop
;
2875 qnum
= ath_get_hal_qnum(queue
, sc
);
2877 ath_print(common
, ATH_DBG_CONFIG
,
2878 "Configure tx [queue/halq] [%d/%d], "
2879 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2880 queue
, qnum
, params
->aifs
, params
->cw_min
,
2881 params
->cw_max
, params
->txop
);
2883 ret
= ath_txq_update(sc
, qnum
, &qi
);
2885 ath_print(common
, ATH_DBG_FATAL
, "TXQ Update failed\n");
2887 if (sc
->sc_ah
->opmode
== NL80211_IFTYPE_ADHOC
)
2888 if ((qnum
== sc
->tx
.hwq_map
[ATH9K_WME_AC_BE
]) && !ret
)
2889 ath_beaconq_config(sc
);
2891 mutex_unlock(&sc
->mutex
);
2896 static int ath9k_set_key(struct ieee80211_hw
*hw
,
2897 enum set_key_cmd cmd
,
2898 struct ieee80211_vif
*vif
,
2899 struct ieee80211_sta
*sta
,
2900 struct ieee80211_key_conf
*key
)
2902 struct ath_wiphy
*aphy
= hw
->priv
;
2903 struct ath_softc
*sc
= aphy
->sc
;
2904 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2907 if (modparam_nohwcrypt
)
2910 mutex_lock(&sc
->mutex
);
2911 ath9k_ps_wakeup(sc
);
2912 ath_print(common
, ATH_DBG_CONFIG
, "Set HW Key\n");
2916 ret
= ath_key_config(common
, vif
, sta
, key
);
2918 key
->hw_key_idx
= ret
;
2919 /* push IV and Michael MIC generation to stack */
2920 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
2921 if (key
->alg
== ALG_TKIP
)
2922 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_MMIC
;
2923 if (sc
->sc_ah
->sw_mgmt_crypto
&& key
->alg
== ALG_CCMP
)
2924 key
->flags
|= IEEE80211_KEY_FLAG_SW_MGMT
;
2929 ath_key_delete(common
, key
);
2935 ath9k_ps_restore(sc
);
2936 mutex_unlock(&sc
->mutex
);
2941 static void ath9k_bss_info_changed(struct ieee80211_hw
*hw
,
2942 struct ieee80211_vif
*vif
,
2943 struct ieee80211_bss_conf
*bss_conf
,
2946 struct ath_wiphy
*aphy
= hw
->priv
;
2947 struct ath_softc
*sc
= aphy
->sc
;
2948 struct ath_hw
*ah
= sc
->sc_ah
;
2949 struct ath_common
*common
= ath9k_hw_common(ah
);
2950 struct ath_vif
*avp
= (void *)vif
->drv_priv
;
2953 mutex_lock(&sc
->mutex
);
2955 if (changed
& BSS_CHANGED_BSSID
) {
2957 memcpy(common
->curbssid
, bss_conf
->bssid
, ETH_ALEN
);
2958 memcpy(avp
->bssid
, bss_conf
->bssid
, ETH_ALEN
);
2960 ath9k_hw_write_associd(ah
);
2962 /* Set aggregation protection mode parameters */
2963 sc
->config
.ath_aggr_prot
= 0;
2965 /* Only legacy IBSS for now */
2966 if (vif
->type
== NL80211_IFTYPE_ADHOC
)
2967 ath_update_chainmask(sc
, 0);
2969 ath_print(common
, ATH_DBG_CONFIG
,
2970 "BSSID: %pM aid: 0x%x\n",
2971 common
->curbssid
, common
->curaid
);
2973 /* need to reconfigure the beacon */
2974 sc
->sc_flags
&= ~SC_OP_BEACONS
;
2977 /* Enable transmission of beacons (AP, IBSS, MESH) */
2978 if ((changed
& BSS_CHANGED_BEACON
) ||
2979 ((changed
& BSS_CHANGED_BEACON_ENABLED
) && bss_conf
->enable_beacon
)) {
2980 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
2981 error
= ath_beacon_alloc(aphy
, vif
);
2983 ath_beacon_config(sc
, vif
);
2986 /* Disable transmission of beacons */
2987 if ((changed
& BSS_CHANGED_BEACON_ENABLED
) && !bss_conf
->enable_beacon
)
2988 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
2990 if (changed
& BSS_CHANGED_BEACON_INT
) {
2991 sc
->beacon_interval
= bss_conf
->beacon_int
;
2993 * In case of AP mode, the HW TSF has to be reset
2994 * when the beacon interval changes.
2996 if (vif
->type
== NL80211_IFTYPE_AP
) {
2997 sc
->sc_flags
|= SC_OP_TSF_RESET
;
2998 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
2999 error
= ath_beacon_alloc(aphy
, vif
);
3001 ath_beacon_config(sc
, vif
);
3003 ath_beacon_config(sc
, vif
);
3007 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
3008 ath_print(common
, ATH_DBG_CONFIG
, "BSS Changed PREAMBLE %d\n",
3009 bss_conf
->use_short_preamble
);
3010 if (bss_conf
->use_short_preamble
)
3011 sc
->sc_flags
|= SC_OP_PREAMBLE_SHORT
;
3013 sc
->sc_flags
&= ~SC_OP_PREAMBLE_SHORT
;
3016 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
3017 ath_print(common
, ATH_DBG_CONFIG
, "BSS Changed CTS PROT %d\n",
3018 bss_conf
->use_cts_prot
);
3019 if (bss_conf
->use_cts_prot
&&
3020 hw
->conf
.channel
->band
!= IEEE80211_BAND_5GHZ
)
3021 sc
->sc_flags
|= SC_OP_PROTECT_ENABLE
;
3023 sc
->sc_flags
&= ~SC_OP_PROTECT_ENABLE
;
3026 if (changed
& BSS_CHANGED_ASSOC
) {
3027 ath_print(common
, ATH_DBG_CONFIG
, "BSS Changed ASSOC %d\n",
3029 ath9k_bss_assoc_info(sc
, vif
, bss_conf
);
3032 mutex_unlock(&sc
->mutex
);
3035 static u64
ath9k_get_tsf(struct ieee80211_hw
*hw
)
3038 struct ath_wiphy
*aphy
= hw
->priv
;
3039 struct ath_softc
*sc
= aphy
->sc
;
3041 mutex_lock(&sc
->mutex
);
3042 tsf
= ath9k_hw_gettsf64(sc
->sc_ah
);
3043 mutex_unlock(&sc
->mutex
);
3048 static void ath9k_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
)
3050 struct ath_wiphy
*aphy
= hw
->priv
;
3051 struct ath_softc
*sc
= aphy
->sc
;
3053 mutex_lock(&sc
->mutex
);
3054 ath9k_hw_settsf64(sc
->sc_ah
, tsf
);
3055 mutex_unlock(&sc
->mutex
);
3058 static void ath9k_reset_tsf(struct ieee80211_hw
*hw
)
3060 struct ath_wiphy
*aphy
= hw
->priv
;
3061 struct ath_softc
*sc
= aphy
->sc
;
3063 mutex_lock(&sc
->mutex
);
3065 ath9k_ps_wakeup(sc
);
3066 ath9k_hw_reset_tsf(sc
->sc_ah
);
3067 ath9k_ps_restore(sc
);
3069 mutex_unlock(&sc
->mutex
);
3072 static int ath9k_ampdu_action(struct ieee80211_hw
*hw
,
3073 struct ieee80211_vif
*vif
,
3074 enum ieee80211_ampdu_mlme_action action
,
3075 struct ieee80211_sta
*sta
,
3078 struct ath_wiphy
*aphy
= hw
->priv
;
3079 struct ath_softc
*sc
= aphy
->sc
;
3083 case IEEE80211_AMPDU_RX_START
:
3084 if (!(sc
->sc_flags
& SC_OP_RXAGGR
))
3087 case IEEE80211_AMPDU_RX_STOP
:
3089 case IEEE80211_AMPDU_TX_START
:
3090 ath_tx_aggr_start(sc
, sta
, tid
, ssn
);
3091 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
3093 case IEEE80211_AMPDU_TX_STOP
:
3094 ath_tx_aggr_stop(sc
, sta
, tid
);
3095 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
3097 case IEEE80211_AMPDU_TX_OPERATIONAL
:
3098 ath_tx_aggr_resume(sc
, sta
, tid
);
3101 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_FATAL
,
3102 "Unknown AMPDU action\n");
3108 static void ath9k_sw_scan_start(struct ieee80211_hw
*hw
)
3110 struct ath_wiphy
*aphy
= hw
->priv
;
3111 struct ath_softc
*sc
= aphy
->sc
;
3112 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
3114 mutex_lock(&sc
->mutex
);
3115 if (ath9k_wiphy_scanning(sc
)) {
3116 printk(KERN_DEBUG
"ath9k: Two wiphys trying to scan at the "
3119 * Do not allow the concurrent scanning state for now. This
3120 * could be improved with scanning control moved into ath9k.
3122 mutex_unlock(&sc
->mutex
);
3126 aphy
->state
= ATH_WIPHY_SCAN
;
3127 ath9k_wiphy_pause_all_forced(sc
, aphy
);
3128 sc
->sc_flags
|= SC_OP_SCANNING
;
3129 del_timer_sync(&common
->ani
.timer
);
3130 cancel_delayed_work_sync(&sc
->tx_complete_work
);
3131 mutex_unlock(&sc
->mutex
);
3134 static void ath9k_sw_scan_complete(struct ieee80211_hw
*hw
)
3136 struct ath_wiphy
*aphy
= hw
->priv
;
3137 struct ath_softc
*sc
= aphy
->sc
;
3138 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
3140 mutex_lock(&sc
->mutex
);
3141 aphy
->state
= ATH_WIPHY_ACTIVE
;
3142 sc
->sc_flags
&= ~SC_OP_SCANNING
;
3143 sc
->sc_flags
|= SC_OP_FULL_RESET
;
3144 ath_start_ani(common
);
3145 ieee80211_queue_delayed_work(sc
->hw
, &sc
->tx_complete_work
, 0);
3146 ath_beacon_config(sc
, NULL
);
3147 mutex_unlock(&sc
->mutex
);
3150 struct ieee80211_ops ath9k_ops
= {
3152 .start
= ath9k_start
,
3154 .add_interface
= ath9k_add_interface
,
3155 .remove_interface
= ath9k_remove_interface
,
3156 .config
= ath9k_config
,
3157 .configure_filter
= ath9k_configure_filter
,
3158 .sta_notify
= ath9k_sta_notify
,
3159 .conf_tx
= ath9k_conf_tx
,
3160 .bss_info_changed
= ath9k_bss_info_changed
,
3161 .set_key
= ath9k_set_key
,
3162 .get_tsf
= ath9k_get_tsf
,
3163 .set_tsf
= ath9k_set_tsf
,
3164 .reset_tsf
= ath9k_reset_tsf
,
3165 .ampdu_action
= ath9k_ampdu_action
,
3166 .sw_scan_start
= ath9k_sw_scan_start
,
3167 .sw_scan_complete
= ath9k_sw_scan_complete
,
3168 .rfkill_poll
= ath9k_rfkill_poll_state
,
3171 static int __init
ath9k_init(void)
3175 /* Register rate control algorithm */
3176 error
= ath_rate_control_register();
3179 "ath9k: Unable to register rate control "
3185 error
= ath9k_debug_create_root();
3188 "ath9k: Unable to create debugfs root: %d\n",
3190 goto err_rate_unregister
;
3193 error
= ath_pci_init();
3196 "ath9k: No PCI devices found, driver not installed.\n");
3198 goto err_remove_root
;
3201 error
= ath_ahb_init();
3213 ath9k_debug_remove_root();
3214 err_rate_unregister
:
3215 ath_rate_control_unregister();
3219 module_init(ath9k_init
);
3221 static void __exit
ath9k_exit(void)
3225 ath9k_debug_remove_root();
3226 ath_rate_control_unregister();
3227 printk(KERN_INFO
"%s: Driver unloaded\n", dev_info
);
3229 module_exit(ath9k_exit
);