1 /* Wrapper for DMA channel allocator that starts clocks etc */
3 #include <linux/kernel.h>
4 #include <linux/spinlock.h>
6 #include <asm/arch/hwregs/reg_map.h>
7 #include <asm/arch/hwregs/reg_rdwr.h>
8 #include <asm/arch/hwregs/marb_defs.h>
9 #include <asm/arch/hwregs/config_defs.h>
10 #include <asm/arch/hwregs/strmux_defs.h>
11 #include <linux/errno.h>
12 #include <asm/system.h>
13 #include <asm/arch/arbiter.h>
15 static char used_dma_channels
[MAX_DMA_CHANNELS
];
16 static const char * used_dma_channels_users
[MAX_DMA_CHANNELS
];
18 static DEFINE_SPINLOCK(dma_lock
);
20 int crisv32_request_dma(unsigned int dmanr
, const char * device_id
,
21 unsigned options
, unsigned int bandwidth
,
25 reg_config_rw_clk_ctrl clk_ctrl
;
26 reg_strmux_rw_cfg strmux_cfg
;
28 if (crisv32_arbiter_allocate_bandwidth(dmanr
,
29 options
& DMA_INT_MEM
? INT_REGION
: EXT_REGION
,
33 spin_lock_irqsave(&dma_lock
, flags
);
35 if (used_dma_channels
[dmanr
]) {
36 spin_unlock_irqrestore(&dma_lock
, flags
);
37 if (options
& DMA_VERBOSE_ON_ERROR
) {
38 printk("Failed to request DMA %i for %s, already allocated by %s\n", dmanr
, device_id
, used_dma_channels_users
[dmanr
]);
40 if (options
& DMA_PANIC_ON_ERROR
)
41 panic("request_dma error!");
44 clk_ctrl
= REG_RD(config
, regi_config
, rw_clk_ctrl
);
45 strmux_cfg
= REG_RD(strmux
, regi_strmux
, rw_cfg
);
51 clk_ctrl
.dma01_eth0
= 1;
67 clk_ctrl
.dma89_strcop
= 1;
69 #if MAX_DMA_CHANNELS-1 != 9
73 spin_unlock_irqrestore(&dma_lock
, flags
);
74 if (options
& DMA_VERBOSE_ON_ERROR
) {
75 printk("Failed to request DMA %i for %s, only 0-%i valid)\n", dmanr
, device_id
, MAX_DMA_CHANNELS
-1);
78 if (options
& DMA_PANIC_ON_ERROR
)
79 panic("request_dma error!");
87 strmux_cfg
.dma0
= regk_strmux_eth0
;
89 strmux_cfg
.dma1
= regk_strmux_eth0
;
91 panic("Invalid DMA channel for eth0\n");
95 strmux_cfg
.dma6
= regk_strmux_eth1
;
97 strmux_cfg
.dma7
= regk_strmux_eth1
;
99 panic("Invalid DMA channel for eth1\n");
103 strmux_cfg
.dma2
= regk_strmux_iop0
;
105 strmux_cfg
.dma3
= regk_strmux_iop0
;
107 panic("Invalid DMA channel for iop0\n");
111 strmux_cfg
.dma4
= regk_strmux_iop1
;
113 strmux_cfg
.dma5
= regk_strmux_iop1
;
115 panic("Invalid DMA channel for iop1\n");
119 strmux_cfg
.dma6
= regk_strmux_ser0
;
121 strmux_cfg
.dma7
= regk_strmux_ser0
;
123 panic("Invalid DMA channel for ser0\n");
127 strmux_cfg
.dma4
= regk_strmux_ser1
;
129 strmux_cfg
.dma5
= regk_strmux_ser1
;
131 panic("Invalid DMA channel for ser1\n");
135 strmux_cfg
.dma2
= regk_strmux_ser2
;
137 strmux_cfg
.dma3
= regk_strmux_ser2
;
139 panic("Invalid DMA channel for ser2\n");
143 strmux_cfg
.dma8
= regk_strmux_ser3
;
145 strmux_cfg
.dma9
= regk_strmux_ser3
;
147 panic("Invalid DMA channel for ser3\n");
151 strmux_cfg
.dma4
= regk_strmux_sser0
;
153 strmux_cfg
.dma5
= regk_strmux_sser0
;
155 panic("Invalid DMA channel for sser0\n");
159 strmux_cfg
.dma6
= regk_strmux_sser1
;
161 strmux_cfg
.dma7
= regk_strmux_sser1
;
163 panic("Invalid DMA channel for sser1\n");
167 strmux_cfg
.dma2
= regk_strmux_ata
;
169 strmux_cfg
.dma3
= regk_strmux_ata
;
171 panic("Invalid DMA channel for ata\n");
175 strmux_cfg
.dma8
= regk_strmux_strcop
;
177 strmux_cfg
.dma9
= regk_strmux_strcop
;
179 panic("Invalid DMA channel for strp\n");
183 strmux_cfg
.dma6
= regk_strmux_ext0
;
185 panic("Invalid DMA channel for ext0\n");
189 strmux_cfg
.dma7
= regk_strmux_ext1
;
191 panic("Invalid DMA channel for ext1\n");
195 strmux_cfg
.dma2
= regk_strmux_ext2
;
197 strmux_cfg
.dma8
= regk_strmux_ext2
;
199 panic("Invalid DMA channel for ext2\n");
203 strmux_cfg
.dma3
= regk_strmux_ext3
;
205 strmux_cfg
.dma9
= regk_strmux_ext2
;
207 panic("Invalid DMA channel for ext2\n");
211 used_dma_channels
[dmanr
] = 1;
212 used_dma_channels_users
[dmanr
] = device_id
;
213 REG_WR(config
, regi_config
, rw_clk_ctrl
, clk_ctrl
);
214 REG_WR(strmux
, regi_strmux
, rw_cfg
, strmux_cfg
);
215 spin_unlock_irqrestore(&dma_lock
,flags
);
219 void crisv32_free_dma(unsigned int dmanr
)
221 spin_lock(&dma_lock
);
222 used_dma_channels
[dmanr
] = 0;
223 spin_unlock(&dma_lock
);