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drm/i915: make sure eDP PLL is enabled at the right time
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
blob14c45b1e8778b08b4e47bbd16b3b1779e4f2573d
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static const intel_limit_t intel_limits_i8xx_dvo = {
346 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
347 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
348 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
349 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
350 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
351 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
352 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
353 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
354 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
355 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
356 .find_pll = intel_find_best_PLL,
357 };
358
359 static const intel_limit_t intel_limits_i8xx_lvds = {
360 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
361 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
362 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
363 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
364 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
365 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
366 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
367 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
368 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
369 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
370 .find_pll = intel_find_best_PLL,
371 };
372
373 static const intel_limit_t intel_limits_i9xx_sdvo = {
374 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
375 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
376 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
377 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
378 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
379 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
380 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
381 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
382 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
383 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
384 .find_pll = intel_find_best_PLL,
385 };
386
387 static const intel_limit_t intel_limits_i9xx_lvds = {
388 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
389 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
390 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
391 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
392 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
393 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
394 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
395 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
396 /* The single-channel range is 25-112Mhz, and dual-channel
397 * is 80-224Mhz. Prefer single channel as much as possible.
398 */
399 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
400 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
401 .find_pll = intel_find_best_PLL,
402 };
403
404 /* below parameter and function is for G4X Chipset Family*/
405 static const intel_limit_t intel_limits_g4x_sdvo = {
406 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
407 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
408 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
409 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
410 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
411 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
412 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
413 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
414 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
415 .p2_slow = G4X_P2_SDVO_SLOW,
416 .p2_fast = G4X_P2_SDVO_FAST
417 },
418 .find_pll = intel_g4x_find_best_PLL,
419 };
420
421 static const intel_limit_t intel_limits_g4x_hdmi = {
422 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
423 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
424 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
425 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
426 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
427 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
428 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
429 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
430 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
431 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
432 .p2_fast = G4X_P2_HDMI_DAC_FAST
433 },
434 .find_pll = intel_g4x_find_best_PLL,
435 };
436
437 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
438 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
439 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
440 .vco = { .min = G4X_VCO_MIN,
441 .max = G4X_VCO_MAX },
442 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
443 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
444 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
445 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
446 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
447 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
448 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
450 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
451 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
452 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
454 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
455 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
456 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
457 },
458 .find_pll = intel_g4x_find_best_PLL,
459 };
460
461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
462 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
463 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
464 .vco = { .min = G4X_VCO_MIN,
465 .max = G4X_VCO_MAX },
466 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
467 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
468 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
469 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
470 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
471 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
472 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
474 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
475 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
476 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
478 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
479 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
480 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
481 },
482 .find_pll = intel_g4x_find_best_PLL,
483 };
484
485 static const intel_limit_t intel_limits_g4x_display_port = {
486 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
487 .max = G4X_DOT_DISPLAY_PORT_MAX },
488 .vco = { .min = G4X_VCO_MIN,
489 .max = G4X_VCO_MAX},
490 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
491 .max = G4X_N_DISPLAY_PORT_MAX },
492 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
493 .max = G4X_M_DISPLAY_PORT_MAX },
494 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
495 .max = G4X_M1_DISPLAY_PORT_MAX },
496 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
497 .max = G4X_M2_DISPLAY_PORT_MAX },
498 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
499 .max = G4X_P_DISPLAY_PORT_MAX },
500 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
501 .max = G4X_P1_DISPLAY_PORT_MAX},
502 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
503 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
504 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
505 .find_pll = intel_find_pll_g4x_dp,
506 };
507
508 static const intel_limit_t intel_limits_pineview_sdvo = {
509 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
510 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
511 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
512 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
513 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
514 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
515 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
516 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
517 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
518 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
519 .find_pll = intel_find_best_PLL,
520 };
521
522 static const intel_limit_t intel_limits_pineview_lvds = {
523 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
524 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
525 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
526 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
527 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
528 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
529 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
530 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
531 /* Pineview only supports single-channel mode. */
532 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
533 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
534 .find_pll = intel_find_best_PLL,
535 };
536
537 static const intel_limit_t intel_limits_ironlake_dac = {
538 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
539 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
540 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
541 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
542 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
543 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
544 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
545 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
546 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
547 .p2_slow = IRONLAKE_DAC_P2_SLOW,
548 .p2_fast = IRONLAKE_DAC_P2_FAST },
549 .find_pll = intel_g4x_find_best_PLL,
550 };
551
552 static const intel_limit_t intel_limits_ironlake_single_lvds = {
553 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
554 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
555 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
556 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
557 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
558 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
559 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
560 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
561 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
562 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
563 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
564 .find_pll = intel_g4x_find_best_PLL,
565 };
566
567 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
568 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
569 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
570 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
571 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
572 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
573 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
574 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
575 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
576 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
577 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
578 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
579 .find_pll = intel_g4x_find_best_PLL,
580 };
581
582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
583 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
584 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
585 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
586 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
587 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
588 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
589 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
590 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
591 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
592 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
593 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
594 .find_pll = intel_g4x_find_best_PLL,
595 };
596
597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
598 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
599 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
600 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
601 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
602 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
603 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
604 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
605 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
606 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
607 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
608 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
609 .find_pll = intel_g4x_find_best_PLL,
610 };
611
612 static const intel_limit_t intel_limits_ironlake_display_port = {
613 .dot = { .min = IRONLAKE_DOT_MIN,
614 .max = IRONLAKE_DOT_MAX },
615 .vco = { .min = IRONLAKE_VCO_MIN,
616 .max = IRONLAKE_VCO_MAX},
617 .n = { .min = IRONLAKE_DP_N_MIN,
618 .max = IRONLAKE_DP_N_MAX },
619 .m = { .min = IRONLAKE_DP_M_MIN,
620 .max = IRONLAKE_DP_M_MAX },
621 .m1 = { .min = IRONLAKE_M1_MIN,
622 .max = IRONLAKE_M1_MAX },
623 .m2 = { .min = IRONLAKE_M2_MIN,
624 .max = IRONLAKE_M2_MAX },
625 .p = { .min = IRONLAKE_DP_P_MIN,
626 .max = IRONLAKE_DP_P_MAX },
627 .p1 = { .min = IRONLAKE_DP_P1_MIN,
628 .max = IRONLAKE_DP_P1_MAX},
629 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
630 .p2_slow = IRONLAKE_DP_P2_SLOW,
631 .p2_fast = IRONLAKE_DP_P2_FAST },
632 .find_pll = intel_find_pll_ironlake_dp,
633 };
634
635 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
636 {
637 struct drm_device *dev = crtc->dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 const intel_limit_t *limit;
640 int refclk = 120;
641
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
643 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
644 refclk = 100;
645
646 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
647 LVDS_CLKB_POWER_UP) {
648 /* LVDS dual channel */
649 if (refclk == 100)
650 limit = &intel_limits_ironlake_dual_lvds_100m;
651 else
652 limit = &intel_limits_ironlake_dual_lvds;
653 } else {
654 if (refclk == 100)
655 limit = &intel_limits_ironlake_single_lvds_100m;
656 else
657 limit = &intel_limits_ironlake_single_lvds;
658 }
659 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
660 HAS_eDP)
661 limit = &intel_limits_ironlake_display_port;
662 else
663 limit = &intel_limits_ironlake_dac;
664
665 return limit;
666 }
667
668 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
669 {
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 const intel_limit_t *limit;
673
674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
675 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
676 LVDS_CLKB_POWER_UP)
677 /* LVDS with dual channel */
678 limit = &intel_limits_g4x_dual_channel_lvds;
679 else
680 /* LVDS with dual channel */
681 limit = &intel_limits_g4x_single_channel_lvds;
682 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
683 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
684 limit = &intel_limits_g4x_hdmi;
685 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
686 limit = &intel_limits_g4x_sdvo;
687 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
688 limit = &intel_limits_g4x_display_port;
689 } else /* The option is for other outputs */
690 limit = &intel_limits_i9xx_sdvo;
691
692 return limit;
693 }
694
695 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
696 {
697 struct drm_device *dev = crtc->dev;
698 const intel_limit_t *limit;
699
700 if (HAS_PCH_SPLIT(dev))
701 limit = intel_ironlake_limit(crtc);
702 else if (IS_G4X(dev)) {
703 limit = intel_g4x_limit(crtc);
704 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
705 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
706 limit = &intel_limits_i9xx_lvds;
707 else
708 limit = &intel_limits_i9xx_sdvo;
709 } else if (IS_PINEVIEW(dev)) {
710 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
711 limit = &intel_limits_pineview_lvds;
712 else
713 limit = &intel_limits_pineview_sdvo;
714 } else {
715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
716 limit = &intel_limits_i8xx_lvds;
717 else
718 limit = &intel_limits_i8xx_dvo;
719 }
720 return limit;
721 }
722
723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
724 static void pineview_clock(int refclk, intel_clock_t *clock)
725 {
726 clock->m = clock->m2 + 2;
727 clock->p = clock->p1 * clock->p2;
728 clock->vco = refclk * clock->m / clock->n;
729 clock->dot = clock->vco / clock->p;
730 }
731
732 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
733 {
734 if (IS_PINEVIEW(dev)) {
735 pineview_clock(refclk, clock);
736 return;
737 }
738 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
739 clock->p = clock->p1 * clock->p2;
740 clock->vco = refclk * clock->m / (clock->n + 2);
741 clock->dot = clock->vco / clock->p;
742 }
743
744 /**
745 * Returns whether any output on the specified pipe is of the specified type
746 */
747 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
748 {
749 struct drm_device *dev = crtc->dev;
750 struct drm_mode_config *mode_config = &dev->mode_config;
751 struct drm_encoder *l_entry;
752
753 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
754 if (l_entry && l_entry->crtc == crtc) {
755 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
756 if (intel_encoder->type == type)
757 return true;
758 }
759 }
760 return false;
761 }
762
763 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
764 /**
765 * Returns whether the given set of divisors are valid for a given refclk with
766 * the given connectors.
767 */
768
769 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
770 {
771 const intel_limit_t *limit = intel_limit (crtc);
772 struct drm_device *dev = crtc->dev;
773
774 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
775 INTELPllInvalid ("p1 out of range\n");
776 if (clock->p < limit->p.min || limit->p.max < clock->p)
777 INTELPllInvalid ("p out of range\n");
778 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
779 INTELPllInvalid ("m2 out of range\n");
780 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
781 INTELPllInvalid ("m1 out of range\n");
782 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
783 INTELPllInvalid ("m1 <= m2\n");
784 if (clock->m < limit->m.min || limit->m.max < clock->m)
785 INTELPllInvalid ("m out of range\n");
786 if (clock->n < limit->n.min || limit->n.max < clock->n)
787 INTELPllInvalid ("n out of range\n");
788 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
789 INTELPllInvalid ("vco out of range\n");
790 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
791 * connector, etc., rather than just a single range.
792 */
793 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
794 INTELPllInvalid ("dot out of range\n");
795
796 return true;
797 }
798
799 static bool
800 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
801 int target, int refclk, intel_clock_t *best_clock)
802
803 {
804 struct drm_device *dev = crtc->dev;
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 intel_clock_t clock;
807 int err = target;
808
809 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
810 (I915_READ(LVDS)) != 0) {
811 /*
812 * For LVDS, if the panel is on, just rely on its current
813 * settings for dual-channel. We haven't figured out how to
814 * reliably set up different single/dual channel state, if we
815 * even can.
816 */
817 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
818 LVDS_CLKB_POWER_UP)
819 clock.p2 = limit->p2.p2_fast;
820 else
821 clock.p2 = limit->p2.p2_slow;
822 } else {
823 if (target < limit->p2.dot_limit)
824 clock.p2 = limit->p2.p2_slow;
825 else
826 clock.p2 = limit->p2.p2_fast;
827 }
828
829 memset (best_clock, 0, sizeof (*best_clock));
830
831 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
832 clock.m1++) {
833 for (clock.m2 = limit->m2.min;
834 clock.m2 <= limit->m2.max; clock.m2++) {
835 /* m1 is always 0 in Pineview */
836 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
837 break;
838 for (clock.n = limit->n.min;
839 clock.n <= limit->n.max; clock.n++) {
840 for (clock.p1 = limit->p1.min;
841 clock.p1 <= limit->p1.max; clock.p1++) {
842 int this_err;
843
844 intel_clock(dev, refclk, &clock);
845
846 if (!intel_PLL_is_valid(crtc, &clock))
847 continue;
848
849 this_err = abs(clock.dot - target);
850 if (this_err < err) {
851 *best_clock = clock;
852 err = this_err;
853 }
854 }
855 }
856 }
857 }
858
859 return (err != target);
860 }
861
862 static bool
863 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
864 int target, int refclk, intel_clock_t *best_clock)
865 {
866 struct drm_device *dev = crtc->dev;
867 struct drm_i915_private *dev_priv = dev->dev_private;
868 intel_clock_t clock;
869 int max_n;
870 bool found;
871 /* approximately equals target * 0.00585 */
872 int err_most = (target >> 8) + (target >> 9);
873 found = false;
874
875 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
876 int lvds_reg;
877
878 if (HAS_PCH_SPLIT(dev))
879 lvds_reg = PCH_LVDS;
880 else
881 lvds_reg = LVDS;
882 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
883 LVDS_CLKB_POWER_UP)
884 clock.p2 = limit->p2.p2_fast;
885 else
886 clock.p2 = limit->p2.p2_slow;
887 } else {
888 if (target < limit->p2.dot_limit)
889 clock.p2 = limit->p2.p2_slow;
890 else
891 clock.p2 = limit->p2.p2_fast;
892 }
893
894 memset(best_clock, 0, sizeof(*best_clock));
895 max_n = limit->n.max;
896 /* based on hardware requirement, prefer smaller n to precision */
897 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
898 /* based on hardware requirement, prefere larger m1,m2 */
899 for (clock.m1 = limit->m1.max;
900 clock.m1 >= limit->m1.min; clock.m1--) {
901 for (clock.m2 = limit->m2.max;
902 clock.m2 >= limit->m2.min; clock.m2--) {
903 for (clock.p1 = limit->p1.max;
904 clock.p1 >= limit->p1.min; clock.p1--) {
905 int this_err;
906
907 intel_clock(dev, refclk, &clock);
908 if (!intel_PLL_is_valid(crtc, &clock))
909 continue;
910 this_err = abs(clock.dot - target) ;
911 if (this_err < err_most) {
912 *best_clock = clock;
913 err_most = this_err;
914 max_n = clock.n;
915 found = true;
916 }
917 }
918 }
919 }
920 }
921 return found;
922 }
923
924 static bool
925 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
926 int target, int refclk, intel_clock_t *best_clock)
927 {
928 struct drm_device *dev = crtc->dev;
929 intel_clock_t clock;
930
931 /* return directly when it is eDP */
932 if (HAS_eDP)
933 return true;
934
935 if (target < 200000) {
936 clock.n = 1;
937 clock.p1 = 2;
938 clock.p2 = 10;
939 clock.m1 = 12;
940 clock.m2 = 9;
941 } else {
942 clock.n = 2;
943 clock.p1 = 1;
944 clock.p2 = 10;
945 clock.m1 = 14;
946 clock.m2 = 8;
947 }
948 intel_clock(dev, refclk, &clock);
949 memcpy(best_clock, &clock, sizeof(intel_clock_t));
950 return true;
951 }
952
953 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
954 static bool
955 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
956 int target, int refclk, intel_clock_t *best_clock)
957 {
958 intel_clock_t clock;
959 if (target < 200000) {
960 clock.p1 = 2;
961 clock.p2 = 10;
962 clock.n = 2;
963 clock.m1 = 23;
964 clock.m2 = 8;
965 } else {
966 clock.p1 = 1;
967 clock.p2 = 10;
968 clock.n = 1;
969 clock.m1 = 14;
970 clock.m2 = 2;
971 }
972 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
973 clock.p = (clock.p1 * clock.p2);
974 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
975 clock.vco = 0;
976 memcpy(best_clock, &clock, sizeof(intel_clock_t));
977 return true;
978 }
979
980 void
981 intel_wait_for_vblank(struct drm_device *dev)
982 {
983 /* Wait for 20ms, i.e. one cycle at 50hz. */
984 if (in_dbg_master())
985 mdelay(20); /* The kernel debugger cannot call msleep() */
986 else
987 msleep(20);
988 }
989
990 /* Parameters have changed, update FBC info */
991 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
992 {
993 struct drm_device *dev = crtc->dev;
994 struct drm_i915_private *dev_priv = dev->dev_private;
995 struct drm_framebuffer *fb = crtc->fb;
996 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
997 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
999 int plane, i;
1000 u32 fbc_ctl, fbc_ctl2;
1001
1002 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1003
1004 if (fb->pitch < dev_priv->cfb_pitch)
1005 dev_priv->cfb_pitch = fb->pitch;
1006
1007 /* FBC_CTL wants 64B units */
1008 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1009 dev_priv->cfb_fence = obj_priv->fence_reg;
1010 dev_priv->cfb_plane = intel_crtc->plane;
1011 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1012
1013 /* Clear old tags */
1014 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1015 I915_WRITE(FBC_TAG + (i * 4), 0);
1016
1017 /* Set it up... */
1018 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1019 if (obj_priv->tiling_mode != I915_TILING_NONE)
1020 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1021 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1022 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1023
1024 /* enable it... */
1025 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1026 if (IS_I945GM(dev))
1027 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1028 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1029 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1030 if (obj_priv->tiling_mode != I915_TILING_NONE)
1031 fbc_ctl |= dev_priv->cfb_fence;
1032 I915_WRITE(FBC_CONTROL, fbc_ctl);
1033
1034 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1035 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1036 }
1037
1038 void i8xx_disable_fbc(struct drm_device *dev)
1039 {
1040 struct drm_i915_private *dev_priv = dev->dev_private;
1041 u32 fbc_ctl;
1042
1043 if (!I915_HAS_FBC(dev))
1044 return;
1045
1046 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1047 return; /* Already off, just return */
1048
1049 /* Disable compression */
1050 fbc_ctl = I915_READ(FBC_CONTROL);
1051 fbc_ctl &= ~FBC_CTL_EN;
1052 I915_WRITE(FBC_CONTROL, fbc_ctl);
1053
1054 /* Wait for compressing bit to clear */
1055 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) {
1056 DRM_DEBUG_KMS("FBC idle timed out\n");
1057 return;
1058 }
1059
1060 intel_wait_for_vblank(dev);
1061
1062 DRM_DEBUG_KMS("disabled FBC\n");
1063 }
1064
1065 static bool i8xx_fbc_enabled(struct drm_device *dev)
1066 {
1067 struct drm_i915_private *dev_priv = dev->dev_private;
1068
1069 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1070 }
1071
1072 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1073 {
1074 struct drm_device *dev = crtc->dev;
1075 struct drm_i915_private *dev_priv = dev->dev_private;
1076 struct drm_framebuffer *fb = crtc->fb;
1077 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1078 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1080 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1081 DPFC_CTL_PLANEB);
1082 unsigned long stall_watermark = 200;
1083 u32 dpfc_ctl;
1084
1085 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1086 dev_priv->cfb_fence = obj_priv->fence_reg;
1087 dev_priv->cfb_plane = intel_crtc->plane;
1088
1089 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1090 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1091 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1092 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1093 } else {
1094 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1095 }
1096
1097 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1098 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1099 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1100 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1101 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1102
1103 /* enable it... */
1104 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1105
1106 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1107 }
1108
1109 void g4x_disable_fbc(struct drm_device *dev)
1110 {
1111 struct drm_i915_private *dev_priv = dev->dev_private;
1112 u32 dpfc_ctl;
1113
1114 /* Disable compression */
1115 dpfc_ctl = I915_READ(DPFC_CONTROL);
1116 dpfc_ctl &= ~DPFC_CTL_EN;
1117 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1118 intel_wait_for_vblank(dev);
1119
1120 DRM_DEBUG_KMS("disabled FBC\n");
1121 }
1122
1123 static bool g4x_fbc_enabled(struct drm_device *dev)
1124 {
1125 struct drm_i915_private *dev_priv = dev->dev_private;
1126
1127 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1128 }
1129
1130 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1131 {
1132 struct drm_device *dev = crtc->dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 struct drm_framebuffer *fb = crtc->fb;
1135 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1136 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1138 int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1139 DPFC_CTL_PLANEB;
1140 unsigned long stall_watermark = 200;
1141 u32 dpfc_ctl;
1142
1143 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1144 dev_priv->cfb_fence = obj_priv->fence_reg;
1145 dev_priv->cfb_plane = intel_crtc->plane;
1146
1147 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1148 dpfc_ctl &= DPFC_RESERVED;
1149 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1150 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1151 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1152 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1153 } else {
1154 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1155 }
1156
1157 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1158 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1159 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1160 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1161 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1162 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1163 /* enable it... */
1164 I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1165 DPFC_CTL_EN);
1166
1167 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1168 }
1169
1170 void ironlake_disable_fbc(struct drm_device *dev)
1171 {
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 u32 dpfc_ctl;
1174
1175 /* Disable compression */
1176 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1177 dpfc_ctl &= ~DPFC_CTL_EN;
1178 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1179 intel_wait_for_vblank(dev);
1180
1181 DRM_DEBUG_KMS("disabled FBC\n");
1182 }
1183
1184 static bool ironlake_fbc_enabled(struct drm_device *dev)
1185 {
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1187
1188 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1189 }
1190
1191 bool intel_fbc_enabled(struct drm_device *dev)
1192 {
1193 struct drm_i915_private *dev_priv = dev->dev_private;
1194
1195 if (!dev_priv->display.fbc_enabled)
1196 return false;
1197
1198 return dev_priv->display.fbc_enabled(dev);
1199 }
1200
1201 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1202 {
1203 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1204
1205 if (!dev_priv->display.enable_fbc)
1206 return;
1207
1208 dev_priv->display.enable_fbc(crtc, interval);
1209 }
1210
1211 void intel_disable_fbc(struct drm_device *dev)
1212 {
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215 if (!dev_priv->display.disable_fbc)
1216 return;
1217
1218 dev_priv->display.disable_fbc(dev);
1219 }
1220
1221 /**
1222 * intel_update_fbc - enable/disable FBC as needed
1223 * @crtc: CRTC to point the compressor at
1224 * @mode: mode in use
1225 *
1226 * Set up the framebuffer compression hardware at mode set time. We
1227 * enable it if possible:
1228 * - plane A only (on pre-965)
1229 * - no pixel mulitply/line duplication
1230 * - no alpha buffer discard
1231 * - no dual wide
1232 * - framebuffer <= 2048 in width, 1536 in height
1233 *
1234 * We can't assume that any compression will take place (worst case),
1235 * so the compressed buffer has to be the same size as the uncompressed
1236 * one. It also must reside (along with the line length buffer) in
1237 * stolen memory.
1238 *
1239 * We need to enable/disable FBC on a global basis.
1240 */
1241 static void intel_update_fbc(struct drm_crtc *crtc,
1242 struct drm_display_mode *mode)
1243 {
1244 struct drm_device *dev = crtc->dev;
1245 struct drm_i915_private *dev_priv = dev->dev_private;
1246 struct drm_framebuffer *fb = crtc->fb;
1247 struct intel_framebuffer *intel_fb;
1248 struct drm_i915_gem_object *obj_priv;
1249 struct drm_crtc *tmp_crtc;
1250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1251 int plane = intel_crtc->plane;
1252 int crtcs_enabled = 0;
1253
1254 DRM_DEBUG_KMS("\n");
1255
1256 if (!i915_powersave)
1257 return;
1258
1259 if (!I915_HAS_FBC(dev))
1260 return;
1261
1262 if (!crtc->fb)
1263 return;
1264
1265 intel_fb = to_intel_framebuffer(fb);
1266 obj_priv = to_intel_bo(intel_fb->obj);
1267
1268 /*
1269 * If FBC is already on, we just have to verify that we can
1270 * keep it that way...
1271 * Need to disable if:
1272 * - more than one pipe is active
1273 * - changing FBC params (stride, fence, mode)
1274 * - new fb is too large to fit in compressed buffer
1275 * - going to an unsupported config (interlace, pixel multiply, etc.)
1276 */
1277 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1278 if (tmp_crtc->enabled)
1279 crtcs_enabled++;
1280 }
1281 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1282 if (crtcs_enabled > 1) {
1283 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1284 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1285 goto out_disable;
1286 }
1287 if (intel_fb->obj->size > dev_priv->cfb_size) {
1288 DRM_DEBUG_KMS("framebuffer too large, disabling "
1289 "compression\n");
1290 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1291 goto out_disable;
1292 }
1293 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1294 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1295 DRM_DEBUG_KMS("mode incompatible with compression, "
1296 "disabling\n");
1297 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1298 goto out_disable;
1299 }
1300 if ((mode->hdisplay > 2048) ||
1301 (mode->vdisplay > 1536)) {
1302 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1303 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1304 goto out_disable;
1305 }
1306 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1307 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1308 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1309 goto out_disable;
1310 }
1311 if (obj_priv->tiling_mode != I915_TILING_X) {
1312 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1313 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1314 goto out_disable;
1315 }
1316
1317 /* If the kernel debugger is active, always disable compression */
1318 if (in_dbg_master())
1319 goto out_disable;
1320
1321 if (intel_fbc_enabled(dev)) {
1322 /* We can re-enable it in this case, but need to update pitch */
1323 if ((fb->pitch > dev_priv->cfb_pitch) ||
1324 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1325 (plane != dev_priv->cfb_plane))
1326 intel_disable_fbc(dev);
1327 }
1328
1329 /* Now try to turn it back on if possible */
1330 if (!intel_fbc_enabled(dev))
1331 intel_enable_fbc(crtc, 500);
1332
1333 return;
1334
1335 out_disable:
1336 /* Multiple disables should be harmless */
1337 if (intel_fbc_enabled(dev)) {
1338 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1339 intel_disable_fbc(dev);
1340 }
1341 }
1342
1343 int
1344 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1345 {
1346 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1347 u32 alignment;
1348 int ret;
1349
1350 switch (obj_priv->tiling_mode) {
1351 case I915_TILING_NONE:
1352 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1353 alignment = 128 * 1024;
1354 else if (IS_I965G(dev))
1355 alignment = 4 * 1024;
1356 else
1357 alignment = 64 * 1024;
1358 break;
1359 case I915_TILING_X:
1360 /* pin() will align the object as required by fence */
1361 alignment = 0;
1362 break;
1363 case I915_TILING_Y:
1364 /* FIXME: Is this true? */
1365 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1366 return -EINVAL;
1367 default:
1368 BUG();
1369 }
1370
1371 ret = i915_gem_object_pin(obj, alignment);
1372 if (ret != 0)
1373 return ret;
1374
1375 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1376 * fence, whereas 965+ only requires a fence if using
1377 * framebuffer compression. For simplicity, we always install
1378 * a fence as the cost is not that onerous.
1379 */
1380 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1381 obj_priv->tiling_mode != I915_TILING_NONE) {
1382 ret = i915_gem_object_get_fence_reg(obj);
1383 if (ret != 0) {
1384 i915_gem_object_unpin(obj);
1385 return ret;
1386 }
1387 }
1388
1389 return 0;
1390 }
1391
1392 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1393 static int
1394 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1395 int x, int y)
1396 {
1397 struct drm_device *dev = crtc->dev;
1398 struct drm_i915_private *dev_priv = dev->dev_private;
1399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1400 struct intel_framebuffer *intel_fb;
1401 struct drm_i915_gem_object *obj_priv;
1402 struct drm_gem_object *obj;
1403 int plane = intel_crtc->plane;
1404 unsigned long Start, Offset;
1405 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1406 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1407 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1408 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1409 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1410 u32 dspcntr;
1411
1412 switch (plane) {
1413 case 0:
1414 case 1:
1415 break;
1416 default:
1417 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1418 return -EINVAL;
1419 }
1420
1421 intel_fb = to_intel_framebuffer(fb);
1422 obj = intel_fb->obj;
1423 obj_priv = to_intel_bo(obj);
1424
1425 dspcntr = I915_READ(dspcntr_reg);
1426 /* Mask out pixel format bits in case we change it */
1427 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1428 switch (fb->bits_per_pixel) {
1429 case 8:
1430 dspcntr |= DISPPLANE_8BPP;
1431 break;
1432 case 16:
1433 if (fb->depth == 15)
1434 dspcntr |= DISPPLANE_15_16BPP;
1435 else
1436 dspcntr |= DISPPLANE_16BPP;
1437 break;
1438 case 24:
1439 case 32:
1440 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1441 break;
1442 default:
1443 DRM_ERROR("Unknown color depth\n");
1444 return -EINVAL;
1445 }
1446 if (IS_I965G(dev)) {
1447 if (obj_priv->tiling_mode != I915_TILING_NONE)
1448 dspcntr |= DISPPLANE_TILED;
1449 else
1450 dspcntr &= ~DISPPLANE_TILED;
1451 }
1452
1453 if (IS_IRONLAKE(dev))
1454 /* must disable */
1455 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1456
1457 I915_WRITE(dspcntr_reg, dspcntr);
1458
1459 Start = obj_priv->gtt_offset;
1460 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1461
1462 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1463 I915_WRITE(dspstride, fb->pitch);
1464 if (IS_I965G(dev)) {
1465 I915_WRITE(dspbase, Offset);
1466 I915_READ(dspbase);
1467 I915_WRITE(dspsurf, Start);
1468 I915_READ(dspsurf);
1469 I915_WRITE(dsptileoff, (y << 16) | x);
1470 } else {
1471 I915_WRITE(dspbase, Start + Offset);
1472 I915_READ(dspbase);
1473 }
1474
1475 if ((IS_I965G(dev) || plane == 0))
1476 intel_update_fbc(crtc, &crtc->mode);
1477
1478 intel_wait_for_vblank(dev);
1479 intel_increase_pllclock(crtc, true);
1480
1481 return 0;
1482 }
1483
1484 static int
1485 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1486 struct drm_framebuffer *old_fb)
1487 {
1488 struct drm_device *dev = crtc->dev;
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490 struct drm_i915_master_private *master_priv;
1491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1492 struct intel_framebuffer *intel_fb;
1493 struct drm_i915_gem_object *obj_priv;
1494 struct drm_gem_object *obj;
1495 int pipe = intel_crtc->pipe;
1496 int plane = intel_crtc->plane;
1497 unsigned long Start, Offset;
1498 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1499 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1500 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1501 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1502 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1503 u32 dspcntr;
1504 int ret;
1505
1506 /* no fb bound */
1507 if (!crtc->fb) {
1508 DRM_DEBUG_KMS("No FB bound\n");
1509 return 0;
1510 }
1511
1512 switch (plane) {
1513 case 0:
1514 case 1:
1515 break;
1516 default:
1517 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1518 return -EINVAL;
1519 }
1520
1521 intel_fb = to_intel_framebuffer(crtc->fb);
1522 obj = intel_fb->obj;
1523 obj_priv = to_intel_bo(obj);
1524
1525 mutex_lock(&dev->struct_mutex);
1526 ret = intel_pin_and_fence_fb_obj(dev, obj);
1527 if (ret != 0) {
1528 mutex_unlock(&dev->struct_mutex);
1529 return ret;
1530 }
1531
1532 ret = i915_gem_object_set_to_display_plane(obj);
1533 if (ret != 0) {
1534 i915_gem_object_unpin(obj);
1535 mutex_unlock(&dev->struct_mutex);
1536 return ret;
1537 }
1538
1539 dspcntr = I915_READ(dspcntr_reg);
1540 /* Mask out pixel format bits in case we change it */
1541 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1542 switch (crtc->fb->bits_per_pixel) {
1543 case 8:
1544 dspcntr |= DISPPLANE_8BPP;
1545 break;
1546 case 16:
1547 if (crtc->fb->depth == 15)
1548 dspcntr |= DISPPLANE_15_16BPP;
1549 else
1550 dspcntr |= DISPPLANE_16BPP;
1551 break;
1552 case 24:
1553 case 32:
1554 if (crtc->fb->depth == 30)
1555 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1556 else
1557 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1558 break;
1559 default:
1560 DRM_ERROR("Unknown color depth\n");
1561 i915_gem_object_unpin(obj);
1562 mutex_unlock(&dev->struct_mutex);
1563 return -EINVAL;
1564 }
1565 if (IS_I965G(dev)) {
1566 if (obj_priv->tiling_mode != I915_TILING_NONE)
1567 dspcntr |= DISPPLANE_TILED;
1568 else
1569 dspcntr &= ~DISPPLANE_TILED;
1570 }
1571
1572 if (HAS_PCH_SPLIT(dev))
1573 /* must disable */
1574 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1575
1576 I915_WRITE(dspcntr_reg, dspcntr);
1577
1578 Start = obj_priv->gtt_offset;
1579 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1580
1581 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1582 Start, Offset, x, y, crtc->fb->pitch);
1583 I915_WRITE(dspstride, crtc->fb->pitch);
1584 if (IS_I965G(dev)) {
1585 I915_WRITE(dspsurf, Start);
1586 I915_WRITE(dsptileoff, (y << 16) | x);
1587 I915_WRITE(dspbase, Offset);
1588 } else {
1589 I915_WRITE(dspbase, Start + Offset);
1590 }
1591 POSTING_READ(dspbase);
1592
1593 if ((IS_I965G(dev) || plane == 0))
1594 intel_update_fbc(crtc, &crtc->mode);
1595
1596 intel_wait_for_vblank(dev);
1597
1598 if (old_fb) {
1599 intel_fb = to_intel_framebuffer(old_fb);
1600 obj_priv = to_intel_bo(intel_fb->obj);
1601 i915_gem_object_unpin(intel_fb->obj);
1602 }
1603 intel_increase_pllclock(crtc, true);
1604
1605 mutex_unlock(&dev->struct_mutex);
1606
1607 if (!dev->primary->master)
1608 return 0;
1609
1610 master_priv = dev->primary->master->driver_priv;
1611 if (!master_priv->sarea_priv)
1612 return 0;
1613
1614 if (pipe) {
1615 master_priv->sarea_priv->pipeB_x = x;
1616 master_priv->sarea_priv->pipeB_y = y;
1617 } else {
1618 master_priv->sarea_priv->pipeA_x = x;
1619 master_priv->sarea_priv->pipeA_y = y;
1620 }
1621
1622 return 0;
1623 }
1624
1625 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1626 {
1627 struct drm_device *dev = crtc->dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 u32 dpa_ctl;
1630
1631 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1632 dpa_ctl = I915_READ(DP_A);
1633 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1634
1635 if (clock < 200000) {
1636 u32 temp;
1637 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1638 /* workaround for 160Mhz:
1639 1) program 0x4600c bits 15:0 = 0x8124
1640 2) program 0x46010 bit 0 = 1
1641 3) program 0x46034 bit 24 = 1
1642 4) program 0x64000 bit 14 = 1
1643 */
1644 temp = I915_READ(0x4600c);
1645 temp &= 0xffff0000;
1646 I915_WRITE(0x4600c, temp | 0x8124);
1647
1648 temp = I915_READ(0x46010);
1649 I915_WRITE(0x46010, temp | 1);
1650
1651 temp = I915_READ(0x46034);
1652 I915_WRITE(0x46034, temp | (1 << 24));
1653 } else {
1654 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1655 }
1656 I915_WRITE(DP_A, dpa_ctl);
1657
1658 udelay(500);
1659 }
1660
1661 /* The FDI link training functions for ILK/Ibexpeak. */
1662 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1663 {
1664 struct drm_device *dev = crtc->dev;
1665 struct drm_i915_private *dev_priv = dev->dev_private;
1666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1667 int pipe = intel_crtc->pipe;
1668 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1669 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1670 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1671 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1672 u32 temp, tries = 0;
1673
1674 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1675 for train result */
1676 temp = I915_READ(fdi_rx_imr_reg);
1677 temp &= ~FDI_RX_SYMBOL_LOCK;
1678 temp &= ~FDI_RX_BIT_LOCK;
1679 I915_WRITE(fdi_rx_imr_reg, temp);
1680 I915_READ(fdi_rx_imr_reg);
1681 udelay(150);
1682
1683 /* enable CPU FDI TX and PCH FDI RX */
1684 temp = I915_READ(fdi_tx_reg);
1685 temp |= FDI_TX_ENABLE;
1686 temp &= ~(7 << 19);
1687 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1688 temp &= ~FDI_LINK_TRAIN_NONE;
1689 temp |= FDI_LINK_TRAIN_PATTERN_1;
1690 I915_WRITE(fdi_tx_reg, temp);
1691 I915_READ(fdi_tx_reg);
1692
1693 temp = I915_READ(fdi_rx_reg);
1694 temp &= ~FDI_LINK_TRAIN_NONE;
1695 temp |= FDI_LINK_TRAIN_PATTERN_1;
1696 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1697 I915_READ(fdi_rx_reg);
1698 udelay(150);
1699
1700 for (tries = 0; tries < 5; tries++) {
1701 temp = I915_READ(fdi_rx_iir_reg);
1702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1703
1704 if ((temp & FDI_RX_BIT_LOCK)) {
1705 DRM_DEBUG_KMS("FDI train 1 done.\n");
1706 I915_WRITE(fdi_rx_iir_reg,
1707 temp | FDI_RX_BIT_LOCK);
1708 break;
1709 }
1710 }
1711 if (tries == 5)
1712 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1713
1714 /* Train 2 */
1715 temp = I915_READ(fdi_tx_reg);
1716 temp &= ~FDI_LINK_TRAIN_NONE;
1717 temp |= FDI_LINK_TRAIN_PATTERN_2;
1718 I915_WRITE(fdi_tx_reg, temp);
1719
1720 temp = I915_READ(fdi_rx_reg);
1721 temp &= ~FDI_LINK_TRAIN_NONE;
1722 temp |= FDI_LINK_TRAIN_PATTERN_2;
1723 I915_WRITE(fdi_rx_reg, temp);
1724 udelay(150);
1725
1726 tries = 0;
1727
1728 for (tries = 0; tries < 5; tries++) {
1729 temp = I915_READ(fdi_rx_iir_reg);
1730 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1731
1732 if (temp & FDI_RX_SYMBOL_LOCK) {
1733 I915_WRITE(fdi_rx_iir_reg,
1734 temp | FDI_RX_SYMBOL_LOCK);
1735 DRM_DEBUG_KMS("FDI train 2 done.\n");
1736 break;
1737 }
1738 }
1739 if (tries == 5)
1740 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1741
1742 DRM_DEBUG_KMS("FDI train done\n");
1743 }
1744
1745 static int snb_b_fdi_train_param [] = {
1746 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1747 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1748 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1749 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1750 };
1751
1752 /* The FDI link training functions for SNB/Cougarpoint. */
1753 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1754 {
1755 struct drm_device *dev = crtc->dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1758 int pipe = intel_crtc->pipe;
1759 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1760 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1761 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1762 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1763 u32 temp, i;
1764
1765 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1766 for train result */
1767 temp = I915_READ(fdi_rx_imr_reg);
1768 temp &= ~FDI_RX_SYMBOL_LOCK;
1769 temp &= ~FDI_RX_BIT_LOCK;
1770 I915_WRITE(fdi_rx_imr_reg, temp);
1771 I915_READ(fdi_rx_imr_reg);
1772 udelay(150);
1773
1774 /* enable CPU FDI TX and PCH FDI RX */
1775 temp = I915_READ(fdi_tx_reg);
1776 temp |= FDI_TX_ENABLE;
1777 temp &= ~(7 << 19);
1778 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1779 temp &= ~FDI_LINK_TRAIN_NONE;
1780 temp |= FDI_LINK_TRAIN_PATTERN_1;
1781 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1782 /* SNB-B */
1783 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1784 I915_WRITE(fdi_tx_reg, temp);
1785 I915_READ(fdi_tx_reg);
1786
1787 temp = I915_READ(fdi_rx_reg);
1788 if (HAS_PCH_CPT(dev)) {
1789 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1790 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1791 } else {
1792 temp &= ~FDI_LINK_TRAIN_NONE;
1793 temp |= FDI_LINK_TRAIN_PATTERN_1;
1794 }
1795 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1796 I915_READ(fdi_rx_reg);
1797 udelay(150);
1798
1799 for (i = 0; i < 4; i++ ) {
1800 temp = I915_READ(fdi_tx_reg);
1801 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1802 temp |= snb_b_fdi_train_param[i];
1803 I915_WRITE(fdi_tx_reg, temp);
1804 udelay(500);
1805
1806 temp = I915_READ(fdi_rx_iir_reg);
1807 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1808
1809 if (temp & FDI_RX_BIT_LOCK) {
1810 I915_WRITE(fdi_rx_iir_reg,
1811 temp | FDI_RX_BIT_LOCK);
1812 DRM_DEBUG_KMS("FDI train 1 done.\n");
1813 break;
1814 }
1815 }
1816 if (i == 4)
1817 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1818
1819 /* Train 2 */
1820 temp = I915_READ(fdi_tx_reg);
1821 temp &= ~FDI_LINK_TRAIN_NONE;
1822 temp |= FDI_LINK_TRAIN_PATTERN_2;
1823 if (IS_GEN6(dev)) {
1824 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1825 /* SNB-B */
1826 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1827 }
1828 I915_WRITE(fdi_tx_reg, temp);
1829
1830 temp = I915_READ(fdi_rx_reg);
1831 if (HAS_PCH_CPT(dev)) {
1832 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1833 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1834 } else {
1835 temp &= ~FDI_LINK_TRAIN_NONE;
1836 temp |= FDI_LINK_TRAIN_PATTERN_2;
1837 }
1838 I915_WRITE(fdi_rx_reg, temp);
1839 udelay(150);
1840
1841 for (i = 0; i < 4; i++ ) {
1842 temp = I915_READ(fdi_tx_reg);
1843 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1844 temp |= snb_b_fdi_train_param[i];
1845 I915_WRITE(fdi_tx_reg, temp);
1846 udelay(500);
1847
1848 temp = I915_READ(fdi_rx_iir_reg);
1849 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1850
1851 if (temp & FDI_RX_SYMBOL_LOCK) {
1852 I915_WRITE(fdi_rx_iir_reg,
1853 temp | FDI_RX_SYMBOL_LOCK);
1854 DRM_DEBUG_KMS("FDI train 2 done.\n");
1855 break;
1856 }
1857 }
1858 if (i == 4)
1859 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1860
1861 DRM_DEBUG_KMS("FDI train done.\n");
1862 }
1863
1864 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1865 {
1866 struct drm_device *dev = crtc->dev;
1867 struct drm_i915_private *dev_priv = dev->dev_private;
1868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1869 int pipe = intel_crtc->pipe;
1870 int plane = intel_crtc->plane;
1871 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1872 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1873 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1874 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1875 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1876 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1877 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1878 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1879 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1880 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1881 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1882 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1883 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1884 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1885 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1886 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1887 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1888 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1889 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1890 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1891 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1892 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1893 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1894 u32 temp;
1895 u32 pipe_bpc;
1896
1897 temp = I915_READ(pipeconf_reg);
1898 pipe_bpc = temp & PIPE_BPC_MASK;
1899
1900 /* XXX: When our outputs are all unaware of DPMS modes other than off
1901 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1902 */
1903 switch (mode) {
1904 case DRM_MODE_DPMS_ON:
1905 case DRM_MODE_DPMS_STANDBY:
1906 case DRM_MODE_DPMS_SUSPEND:
1907 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1908
1909 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1910 temp = I915_READ(PCH_LVDS);
1911 if ((temp & LVDS_PORT_EN) == 0) {
1912 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1913 POSTING_READ(PCH_LVDS);
1914 }
1915 }
1916
1917 if (!HAS_eDP) {
1918
1919 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1920 temp = I915_READ(fdi_rx_reg);
1921 /*
1922 * make the BPC in FDI Rx be consistent with that in
1923 * pipeconf reg.
1924 */
1925 temp &= ~(0x7 << 16);
1926 temp |= (pipe_bpc << 11);
1927 temp &= ~(7 << 19);
1928 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1929 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1930 I915_READ(fdi_rx_reg);
1931 udelay(200);
1932
1933 /* Switch from Rawclk to PCDclk */
1934 temp = I915_READ(fdi_rx_reg);
1935 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1936 I915_READ(fdi_rx_reg);
1937 udelay(200);
1938
1939 /* Enable CPU FDI TX PLL, always on for Ironlake */
1940 temp = I915_READ(fdi_tx_reg);
1941 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1942 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1943 I915_READ(fdi_tx_reg);
1944 udelay(100);
1945 }
1946 }
1947
1948 /* Enable panel fitting for LVDS */
1949 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1950 || HAS_eDP || intel_pch_has_edp(crtc)) {
1951 if (dev_priv->pch_pf_size) {
1952 temp = I915_READ(pf_ctl_reg);
1953 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1954 I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
1955 I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
1956 } else
1957 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1958 }
1959
1960 /* Enable CPU pipe */
1961 temp = I915_READ(pipeconf_reg);
1962 if ((temp & PIPEACONF_ENABLE) == 0) {
1963 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1964 I915_READ(pipeconf_reg);
1965 udelay(100);
1966 }
1967
1968 /* configure and enable CPU plane */
1969 temp = I915_READ(dspcntr_reg);
1970 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1971 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1972 /* Flush the plane changes */
1973 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1974 }
1975
1976 if (!HAS_eDP) {
1977 /* For PCH output, training FDI link */
1978 if (IS_GEN6(dev))
1979 gen6_fdi_link_train(crtc);
1980 else
1981 ironlake_fdi_link_train(crtc);
1982
1983 /* enable PCH DPLL */
1984 temp = I915_READ(pch_dpll_reg);
1985 if ((temp & DPLL_VCO_ENABLE) == 0) {
1986 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1987 I915_READ(pch_dpll_reg);
1988 }
1989 udelay(200);
1990
1991 if (HAS_PCH_CPT(dev)) {
1992 /* Be sure PCH DPLL SEL is set */
1993 temp = I915_READ(PCH_DPLL_SEL);
1994 if (trans_dpll_sel == 0 &&
1995 (temp & TRANSA_DPLL_ENABLE) == 0)
1996 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1997 else if (trans_dpll_sel == 1 &&
1998 (temp & TRANSB_DPLL_ENABLE) == 0)
1999 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2000 I915_WRITE(PCH_DPLL_SEL, temp);
2001 I915_READ(PCH_DPLL_SEL);
2002 }
2003
2004 /* set transcoder timing */
2005 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2006 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2007 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2008
2009 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2010 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2011 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2012
2013 /* enable normal train */
2014 temp = I915_READ(fdi_tx_reg);
2015 temp &= ~FDI_LINK_TRAIN_NONE;
2016 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2017 FDI_TX_ENHANCE_FRAME_ENABLE);
2018 I915_READ(fdi_tx_reg);
2019
2020 temp = I915_READ(fdi_rx_reg);
2021 if (HAS_PCH_CPT(dev)) {
2022 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2023 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2024 } else {
2025 temp &= ~FDI_LINK_TRAIN_NONE;
2026 temp |= FDI_LINK_TRAIN_NONE;
2027 }
2028 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2029 I915_READ(fdi_rx_reg);
2030
2031 /* wait one idle pattern time */
2032 udelay(100);
2033
2034 /* For PCH DP, enable TRANS_DP_CTL */
2035 if (HAS_PCH_CPT(dev) &&
2036 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2037 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2038 int reg;
2039
2040 reg = I915_READ(trans_dp_ctl);
2041 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2042 TRANS_DP_SYNC_MASK);
2043 reg |= (TRANS_DP_OUTPUT_ENABLE |
2044 TRANS_DP_ENH_FRAMING);
2045
2046 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2047 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2048 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2049 reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2050
2051 switch (intel_trans_dp_port_sel(crtc)) {
2052 case PCH_DP_B:
2053 reg |= TRANS_DP_PORT_SEL_B;
2054 break;
2055 case PCH_DP_C:
2056 reg |= TRANS_DP_PORT_SEL_C;
2057 break;
2058 case PCH_DP_D:
2059 reg |= TRANS_DP_PORT_SEL_D;
2060 break;
2061 default:
2062 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2063 reg |= TRANS_DP_PORT_SEL_B;
2064 break;
2065 }
2066
2067 I915_WRITE(trans_dp_ctl, reg);
2068 POSTING_READ(trans_dp_ctl);
2069 }
2070
2071 /* enable PCH transcoder */
2072 temp = I915_READ(transconf_reg);
2073 /*
2074 * make the BPC in transcoder be consistent with
2075 * that in pipeconf reg.
2076 */
2077 temp &= ~PIPE_BPC_MASK;
2078 temp |= pipe_bpc;
2079 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2080 I915_READ(transconf_reg);
2081
2082 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 10, 0))
2083 DRM_ERROR("failed to enable transcoder\n");
2084 }
2085
2086 intel_crtc_load_lut(crtc);
2087
2088 intel_update_fbc(crtc, &crtc->mode);
2089 break;
2090
2091 case DRM_MODE_DPMS_OFF:
2092 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2093
2094 drm_vblank_off(dev, pipe);
2095 /* Disable display plane */
2096 temp = I915_READ(dspcntr_reg);
2097 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2098 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2099 /* Flush the plane changes */
2100 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2101 I915_READ(dspbase_reg);
2102 }
2103
2104 if (dev_priv->cfb_plane == plane &&
2105 dev_priv->display.disable_fbc)
2106 dev_priv->display.disable_fbc(dev);
2107
2108 /* disable cpu pipe, disable after all planes disabled */
2109 temp = I915_READ(pipeconf_reg);
2110 if ((temp & PIPEACONF_ENABLE) != 0) {
2111 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2112
2113 /* wait for cpu pipe off, pipe state */
2114 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1))
2115 DRM_ERROR("failed to turn off cpu pipe\n");
2116 } else
2117 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2118
2119 udelay(100);
2120
2121 /* Disable PF */
2122 temp = I915_READ(pf_ctl_reg);
2123 if ((temp & PF_ENABLE) != 0) {
2124 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2125 I915_READ(pf_ctl_reg);
2126 }
2127 I915_WRITE(pf_win_size, 0);
2128 POSTING_READ(pf_win_size);
2129
2130
2131 /* disable CPU FDI tx and PCH FDI rx */
2132 temp = I915_READ(fdi_tx_reg);
2133 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2134 I915_READ(fdi_tx_reg);
2135
2136 temp = I915_READ(fdi_rx_reg);
2137 /* BPC in FDI rx is consistent with that in pipeconf */
2138 temp &= ~(0x07 << 16);
2139 temp |= (pipe_bpc << 11);
2140 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2141 I915_READ(fdi_rx_reg);
2142
2143 udelay(100);
2144
2145 /* still set train pattern 1 */
2146 temp = I915_READ(fdi_tx_reg);
2147 temp &= ~FDI_LINK_TRAIN_NONE;
2148 temp |= FDI_LINK_TRAIN_PATTERN_1;
2149 I915_WRITE(fdi_tx_reg, temp);
2150 POSTING_READ(fdi_tx_reg);
2151
2152 temp = I915_READ(fdi_rx_reg);
2153 if (HAS_PCH_CPT(dev)) {
2154 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2155 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2156 } else {
2157 temp &= ~FDI_LINK_TRAIN_NONE;
2158 temp |= FDI_LINK_TRAIN_PATTERN_1;
2159 }
2160 I915_WRITE(fdi_rx_reg, temp);
2161 POSTING_READ(fdi_rx_reg);
2162
2163 udelay(100);
2164
2165 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2166 temp = I915_READ(PCH_LVDS);
2167 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2168 I915_READ(PCH_LVDS);
2169 udelay(100);
2170 }
2171
2172 /* disable PCH transcoder */
2173 temp = I915_READ(transconf_reg);
2174 if ((temp & TRANS_ENABLE) != 0) {
2175 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2176
2177 /* wait for PCH transcoder off, transcoder state */
2178 if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1))
2179 DRM_ERROR("failed to disable transcoder\n");
2180 }
2181
2182 temp = I915_READ(transconf_reg);
2183 /* BPC in transcoder is consistent with that in pipeconf */
2184 temp &= ~PIPE_BPC_MASK;
2185 temp |= pipe_bpc;
2186 I915_WRITE(transconf_reg, temp);
2187 I915_READ(transconf_reg);
2188 udelay(100);
2189
2190 if (HAS_PCH_CPT(dev)) {
2191 /* disable TRANS_DP_CTL */
2192 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2193 int reg;
2194
2195 reg = I915_READ(trans_dp_ctl);
2196 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2197 I915_WRITE(trans_dp_ctl, reg);
2198 POSTING_READ(trans_dp_ctl);
2199
2200 /* disable DPLL_SEL */
2201 temp = I915_READ(PCH_DPLL_SEL);
2202 if (trans_dpll_sel == 0)
2203 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2204 else
2205 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2206 I915_WRITE(PCH_DPLL_SEL, temp);
2207 I915_READ(PCH_DPLL_SEL);
2208
2209 }
2210
2211 /* disable PCH DPLL */
2212 temp = I915_READ(pch_dpll_reg);
2213 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2214 I915_READ(pch_dpll_reg);
2215
2216 /* Switch from PCDclk to Rawclk */
2217 temp = I915_READ(fdi_rx_reg);
2218 temp &= ~FDI_SEL_PCDCLK;
2219 I915_WRITE(fdi_rx_reg, temp);
2220 I915_READ(fdi_rx_reg);
2221
2222 /* Disable CPU FDI TX PLL */
2223 temp = I915_READ(fdi_tx_reg);
2224 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2225 I915_READ(fdi_tx_reg);
2226 udelay(100);
2227
2228 temp = I915_READ(fdi_rx_reg);
2229 temp &= ~FDI_RX_PLL_ENABLE;
2230 I915_WRITE(fdi_rx_reg, temp);
2231 I915_READ(fdi_rx_reg);
2232
2233 /* Wait for the clocks to turn off. */
2234 udelay(100);
2235 break;
2236 }
2237 }
2238
2239 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2240 {
2241 struct intel_overlay *overlay;
2242 int ret;
2243
2244 if (!enable && intel_crtc->overlay) {
2245 overlay = intel_crtc->overlay;
2246 mutex_lock(&overlay->dev->struct_mutex);
2247 for (;;) {
2248 ret = intel_overlay_switch_off(overlay);
2249 if (ret == 0)
2250 break;
2251
2252 ret = intel_overlay_recover_from_interrupt(overlay, 0);
2253 if (ret != 0) {
2254 /* overlay doesn't react anymore. Usually
2255 * results in a black screen and an unkillable
2256 * X server. */
2257 BUG();
2258 overlay->hw_wedged = HW_WEDGED;
2259 break;
2260 }
2261 }
2262 mutex_unlock(&overlay->dev->struct_mutex);
2263 }
2264 /* Let userspace switch the overlay on again. In most cases userspace
2265 * has to recompute where to put it anyway. */
2266
2267 return;
2268 }
2269
2270 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2271 {
2272 struct drm_device *dev = crtc->dev;
2273 struct drm_i915_private *dev_priv = dev->dev_private;
2274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2275 int pipe = intel_crtc->pipe;
2276 int plane = intel_crtc->plane;
2277 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2278 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2279 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2280 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2281 u32 temp;
2282
2283 /* XXX: When our outputs are all unaware of DPMS modes other than off
2284 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2285 */
2286 switch (mode) {
2287 case DRM_MODE_DPMS_ON:
2288 case DRM_MODE_DPMS_STANDBY:
2289 case DRM_MODE_DPMS_SUSPEND:
2290 /* Enable the DPLL */
2291 temp = I915_READ(dpll_reg);
2292 if ((temp & DPLL_VCO_ENABLE) == 0) {
2293 I915_WRITE(dpll_reg, temp);
2294 I915_READ(dpll_reg);
2295 /* Wait for the clocks to stabilize. */
2296 udelay(150);
2297 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2298 I915_READ(dpll_reg);
2299 /* Wait for the clocks to stabilize. */
2300 udelay(150);
2301 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2302 I915_READ(dpll_reg);
2303 /* Wait for the clocks to stabilize. */
2304 udelay(150);
2305 }
2306
2307 /* Enable the pipe */
2308 temp = I915_READ(pipeconf_reg);
2309 if ((temp & PIPEACONF_ENABLE) == 0)
2310 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2311
2312 /* Enable the plane */
2313 temp = I915_READ(dspcntr_reg);
2314 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2315 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2316 /* Flush the plane changes */
2317 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2318 }
2319
2320 intel_crtc_load_lut(crtc);
2321
2322 if ((IS_I965G(dev) || plane == 0))
2323 intel_update_fbc(crtc, &crtc->mode);
2324
2325 /* Give the overlay scaler a chance to enable if it's on this pipe */
2326 intel_crtc_dpms_overlay(intel_crtc, true);
2327 break;
2328 case DRM_MODE_DPMS_OFF:
2329 /* Give the overlay scaler a chance to disable if it's on this pipe */
2330 intel_crtc_dpms_overlay(intel_crtc, false);
2331 drm_vblank_off(dev, pipe);
2332
2333 if (dev_priv->cfb_plane == plane &&
2334 dev_priv->display.disable_fbc)
2335 dev_priv->display.disable_fbc(dev);
2336
2337 /* Disable display plane */
2338 temp = I915_READ(dspcntr_reg);
2339 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2340 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2341 /* Flush the plane changes */
2342 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2343 I915_READ(dspbase_reg);
2344 }
2345
2346 if (!IS_I9XX(dev)) {
2347 /* Wait for vblank for the disable to take effect */
2348 intel_wait_for_vblank(dev);
2349 }
2350
2351 /* Don't disable pipe A or pipe A PLLs if needed */
2352 if (pipeconf_reg == PIPEACONF &&
2353 (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2354 goto skip_pipe_off;
2355
2356 /* Next, disable display pipes */
2357 temp = I915_READ(pipeconf_reg);
2358 if ((temp & PIPEACONF_ENABLE) != 0) {
2359 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2360 I915_READ(pipeconf_reg);
2361 }
2362
2363 /* Wait for vblank for the disable to take effect. */
2364 intel_wait_for_vblank(dev);
2365
2366 temp = I915_READ(dpll_reg);
2367 if ((temp & DPLL_VCO_ENABLE) != 0) {
2368 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2369 I915_READ(dpll_reg);
2370 }
2371 skip_pipe_off:
2372 /* Wait for the clocks to turn off. */
2373 udelay(150);
2374 break;
2375 }
2376 }
2377
2378 /**
2379 * Sets the power management mode of the pipe and plane.
2380 */
2381 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2382 {
2383 struct drm_device *dev = crtc->dev;
2384 struct drm_i915_private *dev_priv = dev->dev_private;
2385 struct drm_i915_master_private *master_priv;
2386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2387 int pipe = intel_crtc->pipe;
2388 bool enabled;
2389
2390 intel_crtc->dpms_mode = mode;
2391 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2392
2393 /* When switching on the display, ensure that SR is disabled
2394 * with multiple pipes prior to enabling to new pipe.
2395 *
2396 * When switching off the display, make sure the cursor is
2397 * properly hidden prior to disabling the pipe.
2398 */
2399 if (mode == DRM_MODE_DPMS_ON)
2400 intel_update_watermarks(dev);
2401 else
2402 intel_crtc_update_cursor(crtc);
2403
2404 dev_priv->display.dpms(crtc, mode);
2405
2406 if (mode == DRM_MODE_DPMS_ON)
2407 intel_crtc_update_cursor(crtc);
2408 else
2409 intel_update_watermarks(dev);
2410
2411 if (!dev->primary->master)
2412 return;
2413
2414 master_priv = dev->primary->master->driver_priv;
2415 if (!master_priv->sarea_priv)
2416 return;
2417
2418 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2419
2420 switch (pipe) {
2421 case 0:
2422 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2423 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2424 break;
2425 case 1:
2426 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2427 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2428 break;
2429 default:
2430 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2431 break;
2432 }
2433 }
2434
2435 static void intel_crtc_prepare (struct drm_crtc *crtc)
2436 {
2437 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2438 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2439 }
2440
2441 static void intel_crtc_commit (struct drm_crtc *crtc)
2442 {
2443 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2444 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2445 }
2446
2447 void intel_encoder_prepare (struct drm_encoder *encoder)
2448 {
2449 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2450 /* lvds has its own version of prepare see intel_lvds_prepare */
2451 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2452 }
2453
2454 void intel_encoder_commit (struct drm_encoder *encoder)
2455 {
2456 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2457 /* lvds has its own version of commit see intel_lvds_commit */
2458 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2459 }
2460
2461 void intel_encoder_destroy(struct drm_encoder *encoder)
2462 {
2463 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2464
2465 if (intel_encoder->ddc_bus)
2466 intel_i2c_destroy(intel_encoder->ddc_bus);
2467
2468 if (intel_encoder->i2c_bus)
2469 intel_i2c_destroy(intel_encoder->i2c_bus);
2470
2471 drm_encoder_cleanup(encoder);
2472 kfree(intel_encoder);
2473 }
2474
2475 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2476 struct drm_display_mode *mode,
2477 struct drm_display_mode *adjusted_mode)
2478 {
2479 struct drm_device *dev = crtc->dev;
2480 if (HAS_PCH_SPLIT(dev)) {
2481 /* FDI link clock is fixed at 2.7G */
2482 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2483 return false;
2484 }
2485 return true;
2486 }
2487
2488 static int i945_get_display_clock_speed(struct drm_device *dev)
2489 {
2490 return 400000;
2491 }
2492
2493 static int i915_get_display_clock_speed(struct drm_device *dev)
2494 {
2495 return 333000;
2496 }
2497
2498 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2499 {
2500 return 200000;
2501 }
2502
2503 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2504 {
2505 u16 gcfgc = 0;
2506
2507 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2508
2509 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2510 return 133000;
2511 else {
2512 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2513 case GC_DISPLAY_CLOCK_333_MHZ:
2514 return 333000;
2515 default:
2516 case GC_DISPLAY_CLOCK_190_200_MHZ:
2517 return 190000;
2518 }
2519 }
2520 }
2521
2522 static int i865_get_display_clock_speed(struct drm_device *dev)
2523 {
2524 return 266000;
2525 }
2526
2527 static int i855_get_display_clock_speed(struct drm_device *dev)
2528 {
2529 u16 hpllcc = 0;
2530 /* Assume that the hardware is in the high speed state. This
2531 * should be the default.
2532 */
2533 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2534 case GC_CLOCK_133_200:
2535 case GC_CLOCK_100_200:
2536 return 200000;
2537 case GC_CLOCK_166_250:
2538 return 250000;
2539 case GC_CLOCK_100_133:
2540 return 133000;
2541 }
2542
2543 /* Shouldn't happen */
2544 return 0;
2545 }
2546
2547 static int i830_get_display_clock_speed(struct drm_device *dev)
2548 {
2549 return 133000;
2550 }
2551
2552 /**
2553 * Return the pipe currently connected to the panel fitter,
2554 * or -1 if the panel fitter is not present or not in use
2555 */
2556 int intel_panel_fitter_pipe (struct drm_device *dev)
2557 {
2558 struct drm_i915_private *dev_priv = dev->dev_private;
2559 u32 pfit_control;
2560
2561 /* i830 doesn't have a panel fitter */
2562 if (IS_I830(dev))
2563 return -1;
2564
2565 pfit_control = I915_READ(PFIT_CONTROL);
2566
2567 /* See if the panel fitter is in use */
2568 if ((pfit_control & PFIT_ENABLE) == 0)
2569 return -1;
2570
2571 /* 965 can place panel fitter on either pipe */
2572 if (IS_I965G(dev))
2573 return (pfit_control >> 29) & 0x3;
2574
2575 /* older chips can only use pipe 1 */
2576 return 1;
2577 }
2578
2579 struct fdi_m_n {
2580 u32 tu;
2581 u32 gmch_m;
2582 u32 gmch_n;
2583 u32 link_m;
2584 u32 link_n;
2585 };
2586
2587 static void
2588 fdi_reduce_ratio(u32 *num, u32 *den)
2589 {
2590 while (*num > 0xffffff || *den > 0xffffff) {
2591 *num >>= 1;
2592 *den >>= 1;
2593 }
2594 }
2595
2596 #define DATA_N 0x800000
2597 #define LINK_N 0x80000
2598
2599 static void
2600 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2601 int link_clock, struct fdi_m_n *m_n)
2602 {
2603 u64 temp;
2604
2605 m_n->tu = 64; /* default size */
2606
2607 temp = (u64) DATA_N * pixel_clock;
2608 temp = div_u64(temp, link_clock);
2609 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2610 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2611 m_n->gmch_n = DATA_N;
2612 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2613
2614 temp = (u64) LINK_N * pixel_clock;
2615 m_n->link_m = div_u64(temp, link_clock);
2616 m_n->link_n = LINK_N;
2617 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2618 }
2619
2620
2621 struct intel_watermark_params {
2622 unsigned long fifo_size;
2623 unsigned long max_wm;
2624 unsigned long default_wm;
2625 unsigned long guard_size;
2626 unsigned long cacheline_size;
2627 };
2628
2629 /* Pineview has different values for various configs */
2630 static struct intel_watermark_params pineview_display_wm = {
2631 PINEVIEW_DISPLAY_FIFO,
2632 PINEVIEW_MAX_WM,
2633 PINEVIEW_DFT_WM,
2634 PINEVIEW_GUARD_WM,
2635 PINEVIEW_FIFO_LINE_SIZE
2636 };
2637 static struct intel_watermark_params pineview_display_hplloff_wm = {
2638 PINEVIEW_DISPLAY_FIFO,
2639 PINEVIEW_MAX_WM,
2640 PINEVIEW_DFT_HPLLOFF_WM,
2641 PINEVIEW_GUARD_WM,
2642 PINEVIEW_FIFO_LINE_SIZE
2643 };
2644 static struct intel_watermark_params pineview_cursor_wm = {
2645 PINEVIEW_CURSOR_FIFO,
2646 PINEVIEW_CURSOR_MAX_WM,
2647 PINEVIEW_CURSOR_DFT_WM,
2648 PINEVIEW_CURSOR_GUARD_WM,
2649 PINEVIEW_FIFO_LINE_SIZE,
2650 };
2651 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2652 PINEVIEW_CURSOR_FIFO,
2653 PINEVIEW_CURSOR_MAX_WM,
2654 PINEVIEW_CURSOR_DFT_WM,
2655 PINEVIEW_CURSOR_GUARD_WM,
2656 PINEVIEW_FIFO_LINE_SIZE
2657 };
2658 static struct intel_watermark_params g4x_wm_info = {
2659 G4X_FIFO_SIZE,
2660 G4X_MAX_WM,
2661 G4X_MAX_WM,
2662 2,
2663 G4X_FIFO_LINE_SIZE,
2664 };
2665 static struct intel_watermark_params g4x_cursor_wm_info = {
2666 I965_CURSOR_FIFO,
2667 I965_CURSOR_MAX_WM,
2668 I965_CURSOR_DFT_WM,
2669 2,
2670 G4X_FIFO_LINE_SIZE,
2671 };
2672 static struct intel_watermark_params i965_cursor_wm_info = {
2673 I965_CURSOR_FIFO,
2674 I965_CURSOR_MAX_WM,
2675 I965_CURSOR_DFT_WM,
2676 2,
2677 I915_FIFO_LINE_SIZE,
2678 };
2679 static struct intel_watermark_params i945_wm_info = {
2680 I945_FIFO_SIZE,
2681 I915_MAX_WM,
2682 1,
2683 2,
2684 I915_FIFO_LINE_SIZE
2685 };
2686 static struct intel_watermark_params i915_wm_info = {
2687 I915_FIFO_SIZE,
2688 I915_MAX_WM,
2689 1,
2690 2,
2691 I915_FIFO_LINE_SIZE
2692 };
2693 static struct intel_watermark_params i855_wm_info = {
2694 I855GM_FIFO_SIZE,
2695 I915_MAX_WM,
2696 1,
2697 2,
2698 I830_FIFO_LINE_SIZE
2699 };
2700 static struct intel_watermark_params i830_wm_info = {
2701 I830_FIFO_SIZE,
2702 I915_MAX_WM,
2703 1,
2704 2,
2705 I830_FIFO_LINE_SIZE
2706 };
2707
2708 static struct intel_watermark_params ironlake_display_wm_info = {
2709 ILK_DISPLAY_FIFO,
2710 ILK_DISPLAY_MAXWM,
2711 ILK_DISPLAY_DFTWM,
2712 2,
2713 ILK_FIFO_LINE_SIZE
2714 };
2715
2716 static struct intel_watermark_params ironlake_cursor_wm_info = {
2717 ILK_CURSOR_FIFO,
2718 ILK_CURSOR_MAXWM,
2719 ILK_CURSOR_DFTWM,
2720 2,
2721 ILK_FIFO_LINE_SIZE
2722 };
2723
2724 static struct intel_watermark_params ironlake_display_srwm_info = {
2725 ILK_DISPLAY_SR_FIFO,
2726 ILK_DISPLAY_MAX_SRWM,
2727 ILK_DISPLAY_DFT_SRWM,
2728 2,
2729 ILK_FIFO_LINE_SIZE
2730 };
2731
2732 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2733 ILK_CURSOR_SR_FIFO,
2734 ILK_CURSOR_MAX_SRWM,
2735 ILK_CURSOR_DFT_SRWM,
2736 2,
2737 ILK_FIFO_LINE_SIZE
2738 };
2739
2740 /**
2741 * intel_calculate_wm - calculate watermark level
2742 * @clock_in_khz: pixel clock
2743 * @wm: chip FIFO params
2744 * @pixel_size: display pixel size
2745 * @latency_ns: memory latency for the platform
2746 *
2747 * Calculate the watermark level (the level at which the display plane will
2748 * start fetching from memory again). Each chip has a different display
2749 * FIFO size and allocation, so the caller needs to figure that out and pass
2750 * in the correct intel_watermark_params structure.
2751 *
2752 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2753 * on the pixel size. When it reaches the watermark level, it'll start
2754 * fetching FIFO line sized based chunks from memory until the FIFO fills
2755 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2756 * will occur, and a display engine hang could result.
2757 */
2758 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2759 struct intel_watermark_params *wm,
2760 int pixel_size,
2761 unsigned long latency_ns)
2762 {
2763 long entries_required, wm_size;
2764
2765 /*
2766 * Note: we need to make sure we don't overflow for various clock &
2767 * latency values.
2768 * clocks go from a few thousand to several hundred thousand.
2769 * latency is usually a few thousand
2770 */
2771 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2772 1000;
2773 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2774
2775 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2776
2777 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2778
2779 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2780
2781 /* Don't promote wm_size to unsigned... */
2782 if (wm_size > (long)wm->max_wm)
2783 wm_size = wm->max_wm;
2784 if (wm_size <= 0) {
2785 wm_size = wm->default_wm;
2786 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2787 " entries required = %ld, available = %lu.\n",
2788 entries_required + wm->guard_size,
2789 wm->fifo_size);
2790 }
2791
2792 return wm_size;
2793 }
2794
2795 struct cxsr_latency {
2796 int is_desktop;
2797 int is_ddr3;
2798 unsigned long fsb_freq;
2799 unsigned long mem_freq;
2800 unsigned long display_sr;
2801 unsigned long display_hpll_disable;
2802 unsigned long cursor_sr;
2803 unsigned long cursor_hpll_disable;
2804 };
2805
2806 static const struct cxsr_latency cxsr_latency_table[] = {
2807 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2808 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2809 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2810 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2811 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2812
2813 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2814 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2815 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2816 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2817 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2818
2819 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2820 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2821 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2822 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2823 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2824
2825 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2826 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2827 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2828 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2829 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2830
2831 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2832 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2833 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2834 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2835 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2836
2837 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2838 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2839 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2840 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2841 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2842 };
2843
2844 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2845 int is_ddr3,
2846 int fsb,
2847 int mem)
2848 {
2849 const struct cxsr_latency *latency;
2850 int i;
2851
2852 if (fsb == 0 || mem == 0)
2853 return NULL;
2854
2855 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2856 latency = &cxsr_latency_table[i];
2857 if (is_desktop == latency->is_desktop &&
2858 is_ddr3 == latency->is_ddr3 &&
2859 fsb == latency->fsb_freq && mem == latency->mem_freq)
2860 return latency;
2861 }
2862
2863 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2864
2865 return NULL;
2866 }
2867
2868 static void pineview_disable_cxsr(struct drm_device *dev)
2869 {
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2871
2872 /* deactivate cxsr */
2873 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2874 }
2875
2876 /*
2877 * Latency for FIFO fetches is dependent on several factors:
2878 * - memory configuration (speed, channels)
2879 * - chipset
2880 * - current MCH state
2881 * It can be fairly high in some situations, so here we assume a fairly
2882 * pessimal value. It's a tradeoff between extra memory fetches (if we
2883 * set this value too high, the FIFO will fetch frequently to stay full)
2884 * and power consumption (set it too low to save power and we might see
2885 * FIFO underruns and display "flicker").
2886 *
2887 * A value of 5us seems to be a good balance; safe for very low end
2888 * platforms but not overly aggressive on lower latency configs.
2889 */
2890 static const int latency_ns = 5000;
2891
2892 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2893 {
2894 struct drm_i915_private *dev_priv = dev->dev_private;
2895 uint32_t dsparb = I915_READ(DSPARB);
2896 int size;
2897
2898 size = dsparb & 0x7f;
2899 if (plane)
2900 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2901
2902 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2903 plane ? "B" : "A", size);
2904
2905 return size;
2906 }
2907
2908 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2909 {
2910 struct drm_i915_private *dev_priv = dev->dev_private;
2911 uint32_t dsparb = I915_READ(DSPARB);
2912 int size;
2913
2914 size = dsparb & 0x1ff;
2915 if (plane)
2916 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2917 size >>= 1; /* Convert to cachelines */
2918
2919 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2920 plane ? "B" : "A", size);
2921
2922 return size;
2923 }
2924
2925 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2926 {
2927 struct drm_i915_private *dev_priv = dev->dev_private;
2928 uint32_t dsparb = I915_READ(DSPARB);
2929 int size;
2930
2931 size = dsparb & 0x7f;
2932 size >>= 2; /* Convert to cachelines */
2933
2934 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2935 plane ? "B" : "A",
2936 size);
2937
2938 return size;
2939 }
2940
2941 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2942 {
2943 struct drm_i915_private *dev_priv = dev->dev_private;
2944 uint32_t dsparb = I915_READ(DSPARB);
2945 int size;
2946
2947 size = dsparb & 0x7f;
2948 size >>= 1; /* Convert to cachelines */
2949
2950 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2951 plane ? "B" : "A", size);
2952
2953 return size;
2954 }
2955
2956 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2957 int planeb_clock, int sr_hdisplay, int unused,
2958 int pixel_size)
2959 {
2960 struct drm_i915_private *dev_priv = dev->dev_private;
2961 const struct cxsr_latency *latency;
2962 u32 reg;
2963 unsigned long wm;
2964 int sr_clock;
2965
2966 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2967 dev_priv->fsb_freq, dev_priv->mem_freq);
2968 if (!latency) {
2969 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2970 pineview_disable_cxsr(dev);
2971 return;
2972 }
2973
2974 if (!planea_clock || !planeb_clock) {
2975 sr_clock = planea_clock ? planea_clock : planeb_clock;
2976
2977 /* Display SR */
2978 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2979 pixel_size, latency->display_sr);
2980 reg = I915_READ(DSPFW1);
2981 reg &= ~DSPFW_SR_MASK;
2982 reg |= wm << DSPFW_SR_SHIFT;
2983 I915_WRITE(DSPFW1, reg);
2984 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2985
2986 /* cursor SR */
2987 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2988 pixel_size, latency->cursor_sr);
2989 reg = I915_READ(DSPFW3);
2990 reg &= ~DSPFW_CURSOR_SR_MASK;
2991 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2992 I915_WRITE(DSPFW3, reg);
2993
2994 /* Display HPLL off SR */
2995 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2996 pixel_size, latency->display_hpll_disable);
2997 reg = I915_READ(DSPFW3);
2998 reg &= ~DSPFW_HPLL_SR_MASK;
2999 reg |= wm & DSPFW_HPLL_SR_MASK;
3000 I915_WRITE(DSPFW3, reg);
3001
3002 /* cursor HPLL off SR */
3003 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3004 pixel_size, latency->cursor_hpll_disable);
3005 reg = I915_READ(DSPFW3);
3006 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3007 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3008 I915_WRITE(DSPFW3, reg);
3009 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3010
3011 /* activate cxsr */
3012 I915_WRITE(DSPFW3,
3013 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3014 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3015 } else {
3016 pineview_disable_cxsr(dev);
3017 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3018 }
3019 }
3020
3021 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3022 int planeb_clock, int sr_hdisplay, int sr_htotal,
3023 int pixel_size)
3024 {
3025 struct drm_i915_private *dev_priv = dev->dev_private;
3026 int total_size, cacheline_size;
3027 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3028 struct intel_watermark_params planea_params, planeb_params;
3029 unsigned long line_time_us;
3030 int sr_clock, sr_entries = 0, entries_required;
3031
3032 /* Create copies of the base settings for each pipe */
3033 planea_params = planeb_params = g4x_wm_info;
3034
3035 /* Grab a couple of global values before we overwrite them */
3036 total_size = planea_params.fifo_size;
3037 cacheline_size = planea_params.cacheline_size;
3038
3039 /*
3040 * Note: we need to make sure we don't overflow for various clock &
3041 * latency values.
3042 * clocks go from a few thousand to several hundred thousand.
3043 * latency is usually a few thousand
3044 */
3045 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3046 1000;
3047 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3048 planea_wm = entries_required + planea_params.guard_size;
3049
3050 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3051 1000;
3052 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3053 planeb_wm = entries_required + planeb_params.guard_size;
3054
3055 cursora_wm = cursorb_wm = 16;
3056 cursor_sr = 32;
3057
3058 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3059
3060 /* Calc sr entries for one plane configs */
3061 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3062 /* self-refresh has much higher latency */
3063 static const int sr_latency_ns = 12000;
3064
3065 sr_clock = planea_clock ? planea_clock : planeb_clock;
3066 line_time_us = ((sr_htotal * 1000) / sr_clock);
3067
3068 /* Use ns/us then divide to preserve precision */
3069 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3070 pixel_size * sr_hdisplay;
3071 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3072
3073 entries_required = (((sr_latency_ns / line_time_us) +
3074 1000) / 1000) * pixel_size * 64;
3075 entries_required = DIV_ROUND_UP(entries_required,
3076 g4x_cursor_wm_info.cacheline_size);
3077 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3078
3079 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3080 cursor_sr = g4x_cursor_wm_info.max_wm;
3081 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3082 "cursor %d\n", sr_entries, cursor_sr);
3083
3084 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3085 } else {
3086 /* Turn off self refresh if both pipes are enabled */
3087 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3088 & ~FW_BLC_SELF_EN);
3089 }
3090
3091 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3092 planea_wm, planeb_wm, sr_entries);
3093
3094 planea_wm &= 0x3f;
3095 planeb_wm &= 0x3f;
3096
3097 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3098 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3099 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3100 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3101 (cursora_wm << DSPFW_CURSORA_SHIFT));
3102 /* HPLL off in SR has some issues on G4x... disable it */
3103 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3104 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3105 }
3106
3107 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3108 int planeb_clock, int sr_hdisplay, int sr_htotal,
3109 int pixel_size)
3110 {
3111 struct drm_i915_private *dev_priv = dev->dev_private;
3112 unsigned long line_time_us;
3113 int sr_clock, sr_entries, srwm = 1;
3114 int cursor_sr = 16;
3115
3116 /* Calc sr entries for one plane configs */
3117 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3118 /* self-refresh has much higher latency */
3119 static const int sr_latency_ns = 12000;
3120
3121 sr_clock = planea_clock ? planea_clock : planeb_clock;
3122 line_time_us = ((sr_htotal * 1000) / sr_clock);
3123
3124 /* Use ns/us then divide to preserve precision */
3125 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3126 pixel_size * sr_hdisplay;
3127 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3128 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3129 srwm = I965_FIFO_SIZE - sr_entries;
3130 if (srwm < 0)
3131 srwm = 1;
3132 srwm &= 0x1ff;
3133
3134 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3135 pixel_size * 64;
3136 sr_entries = DIV_ROUND_UP(sr_entries,
3137 i965_cursor_wm_info.cacheline_size);
3138 cursor_sr = i965_cursor_wm_info.fifo_size -
3139 (sr_entries + i965_cursor_wm_info.guard_size);
3140
3141 if (cursor_sr > i965_cursor_wm_info.max_wm)
3142 cursor_sr = i965_cursor_wm_info.max_wm;
3143
3144 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3145 "cursor %d\n", srwm, cursor_sr);
3146
3147 if (IS_I965GM(dev))
3148 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3149 } else {
3150 /* Turn off self refresh if both pipes are enabled */
3151 if (IS_I965GM(dev))
3152 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3153 & ~FW_BLC_SELF_EN);
3154 }
3155
3156 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3157 srwm);
3158
3159 /* 965 has limitations... */
3160 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3161 (8 << 0));
3162 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3163 /* update cursor SR watermark */
3164 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3165 }
3166
3167 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3168 int planeb_clock, int sr_hdisplay, int sr_htotal,
3169 int pixel_size)
3170 {
3171 struct drm_i915_private *dev_priv = dev->dev_private;
3172 uint32_t fwater_lo;
3173 uint32_t fwater_hi;
3174 int total_size, cacheline_size, cwm, srwm = 1;
3175 int planea_wm, planeb_wm;
3176 struct intel_watermark_params planea_params, planeb_params;
3177 unsigned long line_time_us;
3178 int sr_clock, sr_entries = 0;
3179
3180 /* Create copies of the base settings for each pipe */
3181 if (IS_I965GM(dev) || IS_I945GM(dev))
3182 planea_params = planeb_params = i945_wm_info;
3183 else if (IS_I9XX(dev))
3184 planea_params = planeb_params = i915_wm_info;
3185 else
3186 planea_params = planeb_params = i855_wm_info;
3187
3188 /* Grab a couple of global values before we overwrite them */
3189 total_size = planea_params.fifo_size;
3190 cacheline_size = planea_params.cacheline_size;
3191
3192 /* Update per-plane FIFO sizes */
3193 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3194 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3195
3196 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3197 pixel_size, latency_ns);
3198 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3199 pixel_size, latency_ns);
3200 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3201
3202 /*
3203 * Overlay gets an aggressive default since video jitter is bad.
3204 */
3205 cwm = 2;
3206
3207 /* Calc sr entries for one plane configs */
3208 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3209 (!planea_clock || !planeb_clock)) {
3210 /* self-refresh has much higher latency */
3211 static const int sr_latency_ns = 6000;
3212
3213 sr_clock = planea_clock ? planea_clock : planeb_clock;
3214 line_time_us = ((sr_htotal * 1000) / sr_clock);
3215
3216 /* Use ns/us then divide to preserve precision */
3217 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3218 pixel_size * sr_hdisplay;
3219 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3220 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3221 srwm = total_size - sr_entries;
3222 if (srwm < 0)
3223 srwm = 1;
3224
3225 if (IS_I945G(dev) || IS_I945GM(dev))
3226 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3227 else if (IS_I915GM(dev)) {
3228 /* 915M has a smaller SRWM field */
3229 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3230 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3231 }
3232 } else {
3233 /* Turn off self refresh if both pipes are enabled */
3234 if (IS_I945G(dev) || IS_I945GM(dev)) {
3235 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3236 & ~FW_BLC_SELF_EN);
3237 } else if (IS_I915GM(dev)) {
3238 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3239 }
3240 }
3241
3242 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3243 planea_wm, planeb_wm, cwm, srwm);
3244
3245 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3246 fwater_hi = (cwm & 0x1f);
3247
3248 /* Set request length to 8 cachelines per fetch */
3249 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3250 fwater_hi = fwater_hi | (1 << 8);
3251
3252 I915_WRITE(FW_BLC, fwater_lo);
3253 I915_WRITE(FW_BLC2, fwater_hi);
3254 }
3255
3256 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3257 int unused2, int unused3, int pixel_size)
3258 {
3259 struct drm_i915_private *dev_priv = dev->dev_private;
3260 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3261 int planea_wm;
3262
3263 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3264
3265 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3266 pixel_size, latency_ns);
3267 fwater_lo |= (3<<8) | planea_wm;
3268
3269 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3270
3271 I915_WRITE(FW_BLC, fwater_lo);
3272 }
3273
3274 #define ILK_LP0_PLANE_LATENCY 700
3275 #define ILK_LP0_CURSOR_LATENCY 1300
3276
3277 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3278 int planeb_clock, int sr_hdisplay, int sr_htotal,
3279 int pixel_size)
3280 {
3281 struct drm_i915_private *dev_priv = dev->dev_private;
3282 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3283 int sr_wm, cursor_wm;
3284 unsigned long line_time_us;
3285 int sr_clock, entries_required;
3286 u32 reg_value;
3287 int line_count;
3288 int planea_htotal = 0, planeb_htotal = 0;
3289 struct drm_crtc *crtc;
3290
3291 /* Need htotal for all active display plane */
3292 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3294 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3295 if (intel_crtc->plane == 0)
3296 planea_htotal = crtc->mode.htotal;
3297 else
3298 planeb_htotal = crtc->mode.htotal;
3299 }
3300 }
3301
3302 /* Calculate and update the watermark for plane A */
3303 if (planea_clock) {
3304 entries_required = ((planea_clock / 1000) * pixel_size *
3305 ILK_LP0_PLANE_LATENCY) / 1000;
3306 entries_required = DIV_ROUND_UP(entries_required,
3307 ironlake_display_wm_info.cacheline_size);
3308 planea_wm = entries_required +
3309 ironlake_display_wm_info.guard_size;
3310
3311 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3312 planea_wm = ironlake_display_wm_info.max_wm;
3313
3314 /* Use the large buffer method to calculate cursor watermark */
3315 line_time_us = (planea_htotal * 1000) / planea_clock;
3316
3317 /* Use ns/us then divide to preserve precision */
3318 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3319
3320 /* calculate the cursor watermark for cursor A */
3321 entries_required = line_count * 64 * pixel_size;
3322 entries_required = DIV_ROUND_UP(entries_required,
3323 ironlake_cursor_wm_info.cacheline_size);
3324 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3325 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3326 cursora_wm = ironlake_cursor_wm_info.max_wm;
3327
3328 reg_value = I915_READ(WM0_PIPEA_ILK);
3329 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3330 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3331 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3332 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3333 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3334 "cursor: %d\n", planea_wm, cursora_wm);
3335 }
3336 /* Calculate and update the watermark for plane B */
3337 if (planeb_clock) {
3338 entries_required = ((planeb_clock / 1000) * pixel_size *
3339 ILK_LP0_PLANE_LATENCY) / 1000;
3340 entries_required = DIV_ROUND_UP(entries_required,
3341 ironlake_display_wm_info.cacheline_size);
3342 planeb_wm = entries_required +
3343 ironlake_display_wm_info.guard_size;
3344
3345 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3346 planeb_wm = ironlake_display_wm_info.max_wm;
3347
3348 /* Use the large buffer method to calculate cursor watermark */
3349 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3350
3351 /* Use ns/us then divide to preserve precision */
3352 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3353
3354 /* calculate the cursor watermark for cursor B */
3355 entries_required = line_count * 64 * pixel_size;
3356 entries_required = DIV_ROUND_UP(entries_required,
3357 ironlake_cursor_wm_info.cacheline_size);
3358 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3359 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3360 cursorb_wm = ironlake_cursor_wm_info.max_wm;
3361
3362 reg_value = I915_READ(WM0_PIPEB_ILK);
3363 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3364 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3365 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3366 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3367 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3368 "cursor: %d\n", planeb_wm, cursorb_wm);
3369 }
3370
3371 /*
3372 * Calculate and update the self-refresh watermark only when one
3373 * display plane is used.
3374 */
3375 if (!planea_clock || !planeb_clock) {
3376
3377 /* Read the self-refresh latency. The unit is 0.5us */
3378 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3379
3380 sr_clock = planea_clock ? planea_clock : planeb_clock;
3381 line_time_us = ((sr_htotal * 1000) / sr_clock);
3382
3383 /* Use ns/us then divide to preserve precision */
3384 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3385 / 1000;
3386
3387 /* calculate the self-refresh watermark for display plane */
3388 entries_required = line_count * sr_hdisplay * pixel_size;
3389 entries_required = DIV_ROUND_UP(entries_required,
3390 ironlake_display_srwm_info.cacheline_size);
3391 sr_wm = entries_required +
3392 ironlake_display_srwm_info.guard_size;
3393
3394 /* calculate the self-refresh watermark for display cursor */
3395 entries_required = line_count * pixel_size * 64;
3396 entries_required = DIV_ROUND_UP(entries_required,
3397 ironlake_cursor_srwm_info.cacheline_size);
3398 cursor_wm = entries_required +
3399 ironlake_cursor_srwm_info.guard_size;
3400
3401 /* configure watermark and enable self-refresh */
3402 reg_value = I915_READ(WM1_LP_ILK);
3403 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3404 WM1_LP_CURSOR_MASK);
3405 reg_value |= WM1_LP_SR_EN |
3406 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3407 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3408
3409 I915_WRITE(WM1_LP_ILK, reg_value);
3410 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3411 "cursor %d\n", sr_wm, cursor_wm);
3412
3413 } else {
3414 /* Turn off self refresh if both pipes are enabled */
3415 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3416 }
3417 }
3418 /**
3419 * intel_update_watermarks - update FIFO watermark values based on current modes
3420 *
3421 * Calculate watermark values for the various WM regs based on current mode
3422 * and plane configuration.
3423 *
3424 * There are several cases to deal with here:
3425 * - normal (i.e. non-self-refresh)
3426 * - self-refresh (SR) mode
3427 * - lines are large relative to FIFO size (buffer can hold up to 2)
3428 * - lines are small relative to FIFO size (buffer can hold more than 2
3429 * lines), so need to account for TLB latency
3430 *
3431 * The normal calculation is:
3432 * watermark = dotclock * bytes per pixel * latency
3433 * where latency is platform & configuration dependent (we assume pessimal
3434 * values here).
3435 *
3436 * The SR calculation is:
3437 * watermark = (trunc(latency/line time)+1) * surface width *
3438 * bytes per pixel
3439 * where
3440 * line time = htotal / dotclock
3441 * surface width = hdisplay for normal plane and 64 for cursor
3442 * and latency is assumed to be high, as above.
3443 *
3444 * The final value programmed to the register should always be rounded up,
3445 * and include an extra 2 entries to account for clock crossings.
3446 *
3447 * We don't use the sprite, so we can ignore that. And on Crestline we have
3448 * to set the non-SR watermarks to 8.
3449 */
3450 static void intel_update_watermarks(struct drm_device *dev)
3451 {
3452 struct drm_i915_private *dev_priv = dev->dev_private;
3453 struct drm_crtc *crtc;
3454 int sr_hdisplay = 0;
3455 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3456 int enabled = 0, pixel_size = 0;
3457 int sr_htotal = 0;
3458
3459 if (!dev_priv->display.update_wm)
3460 return;
3461
3462 /* Get the clock config from both planes */
3463 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3465 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3466 enabled++;
3467 if (intel_crtc->plane == 0) {
3468 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3469 intel_crtc->pipe, crtc->mode.clock);
3470 planea_clock = crtc->mode.clock;
3471 } else {
3472 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3473 intel_crtc->pipe, crtc->mode.clock);
3474 planeb_clock = crtc->mode.clock;
3475 }
3476 sr_hdisplay = crtc->mode.hdisplay;
3477 sr_clock = crtc->mode.clock;
3478 sr_htotal = crtc->mode.htotal;
3479 if (crtc->fb)
3480 pixel_size = crtc->fb->bits_per_pixel / 8;
3481 else
3482 pixel_size = 4; /* by default */
3483 }
3484 }
3485
3486 if (enabled <= 0)
3487 return;
3488
3489 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3490 sr_hdisplay, sr_htotal, pixel_size);
3491 }
3492
3493 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3494 struct drm_display_mode *mode,
3495 struct drm_display_mode *adjusted_mode,
3496 int x, int y,
3497 struct drm_framebuffer *old_fb)
3498 {
3499 struct drm_device *dev = crtc->dev;
3500 struct drm_i915_private *dev_priv = dev->dev_private;
3501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3502 int pipe = intel_crtc->pipe;
3503 int plane = intel_crtc->plane;
3504 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3505 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3506 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3507 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3508 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3509 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3510 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3511 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3512 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3513 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3514 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3515 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3516 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3517 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3518 int refclk, num_connectors = 0;
3519 intel_clock_t clock, reduced_clock;
3520 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3521 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3522 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3523 bool is_edp = false;
3524 struct drm_mode_config *mode_config = &dev->mode_config;
3525 struct drm_encoder *encoder;
3526 struct intel_encoder *intel_encoder = NULL;
3527 const intel_limit_t *limit;
3528 int ret;
3529 struct fdi_m_n m_n = {0};
3530 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3531 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3532 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3533 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3534 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3535 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3536 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3537 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3538 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3539 int lvds_reg = LVDS;
3540 u32 temp;
3541 int sdvo_pixel_multiply;
3542 int target_clock;
3543
3544 drm_vblank_pre_modeset(dev, pipe);
3545
3546 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3547
3548 if (!encoder || encoder->crtc != crtc)
3549 continue;
3550
3551 intel_encoder = enc_to_intel_encoder(encoder);
3552
3553 switch (intel_encoder->type) {
3554 case INTEL_OUTPUT_LVDS:
3555 is_lvds = true;
3556 break;
3557 case INTEL_OUTPUT_SDVO:
3558 case INTEL_OUTPUT_HDMI:
3559 is_sdvo = true;
3560 if (intel_encoder->needs_tv_clock)
3561 is_tv = true;
3562 break;
3563 case INTEL_OUTPUT_DVO:
3564 is_dvo = true;
3565 break;
3566 case INTEL_OUTPUT_TVOUT:
3567 is_tv = true;
3568 break;
3569 case INTEL_OUTPUT_ANALOG:
3570 is_crt = true;
3571 break;
3572 case INTEL_OUTPUT_DISPLAYPORT:
3573 is_dp = true;
3574 break;
3575 case INTEL_OUTPUT_EDP:
3576 is_edp = true;
3577 break;
3578 }
3579
3580 num_connectors++;
3581 }
3582
3583 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3584 refclk = dev_priv->lvds_ssc_freq * 1000;
3585 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3586 refclk / 1000);
3587 } else if (IS_I9XX(dev)) {
3588 refclk = 96000;
3589 if (HAS_PCH_SPLIT(dev))
3590 refclk = 120000; /* 120Mhz refclk */
3591 } else {
3592 refclk = 48000;
3593 }
3594
3595
3596 /*
3597 * Returns a set of divisors for the desired target clock with the given
3598 * refclk, or FALSE. The returned values represent the clock equation:
3599 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3600 */
3601 limit = intel_limit(crtc);
3602 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3603 if (!ok) {
3604 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3605 drm_vblank_post_modeset(dev, pipe);
3606 return -EINVAL;
3607 }
3608
3609 /* Ensure that the cursor is valid for the new mode before changing... */
3610 intel_crtc_update_cursor(crtc);
3611
3612 if (is_lvds && dev_priv->lvds_downclock_avail) {
3613 has_reduced_clock = limit->find_pll(limit, crtc,
3614 dev_priv->lvds_downclock,
3615 refclk,
3616 &reduced_clock);
3617 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3618 /*
3619 * If the different P is found, it means that we can't
3620 * switch the display clock by using the FP0/FP1.
3621 * In such case we will disable the LVDS downclock
3622 * feature.
3623 */
3624 DRM_DEBUG_KMS("Different P is found for "
3625 "LVDS clock/downclock\n");
3626 has_reduced_clock = 0;
3627 }
3628 }
3629 /* SDVO TV has fixed PLL values depend on its clock range,
3630 this mirrors vbios setting. */
3631 if (is_sdvo && is_tv) {
3632 if (adjusted_mode->clock >= 100000
3633 && adjusted_mode->clock < 140500) {
3634 clock.p1 = 2;
3635 clock.p2 = 10;
3636 clock.n = 3;
3637 clock.m1 = 16;
3638 clock.m2 = 8;
3639 } else if (adjusted_mode->clock >= 140500
3640 && adjusted_mode->clock <= 200000) {
3641 clock.p1 = 1;
3642 clock.p2 = 10;
3643 clock.n = 6;
3644 clock.m1 = 12;
3645 clock.m2 = 8;
3646 }
3647 }
3648
3649 /* FDI link */
3650 if (HAS_PCH_SPLIT(dev)) {
3651 int lane = 0, link_bw, bpp;
3652 /* eDP doesn't require FDI link, so just set DP M/N
3653 according to current link config */
3654 if (is_edp) {
3655 target_clock = mode->clock;
3656 intel_edp_link_config(intel_encoder,
3657 &lane, &link_bw);
3658 } else {
3659 /* DP over FDI requires target mode clock
3660 instead of link clock */
3661 if (is_dp)
3662 target_clock = mode->clock;
3663 else
3664 target_clock = adjusted_mode->clock;
3665 link_bw = 270000;
3666 }
3667
3668 /* determine panel color depth */
3669 temp = I915_READ(pipeconf_reg);
3670 temp &= ~PIPE_BPC_MASK;
3671 if (is_lvds) {
3672 int lvds_reg = I915_READ(PCH_LVDS);
3673 /* the BPC will be 6 if it is 18-bit LVDS panel */
3674 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3675 temp |= PIPE_8BPC;
3676 else
3677 temp |= PIPE_6BPC;
3678 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
3679 switch (dev_priv->edp_bpp/3) {
3680 case 8:
3681 temp |= PIPE_8BPC;
3682 break;
3683 case 10:
3684 temp |= PIPE_10BPC;
3685 break;
3686 case 6:
3687 temp |= PIPE_6BPC;
3688 break;
3689 case 12:
3690 temp |= PIPE_12BPC;
3691 break;
3692 }
3693 } else
3694 temp |= PIPE_8BPC;
3695 I915_WRITE(pipeconf_reg, temp);
3696 I915_READ(pipeconf_reg);
3697
3698 switch (temp & PIPE_BPC_MASK) {
3699 case PIPE_8BPC:
3700 bpp = 24;
3701 break;
3702 case PIPE_10BPC:
3703 bpp = 30;
3704 break;
3705 case PIPE_6BPC:
3706 bpp = 18;
3707 break;
3708 case PIPE_12BPC:
3709 bpp = 36;
3710 break;
3711 default:
3712 DRM_ERROR("unknown pipe bpc value\n");
3713 bpp = 24;
3714 }
3715
3716 if (!lane) {
3717 /*
3718 * Account for spread spectrum to avoid
3719 * oversubscribing the link. Max center spread
3720 * is 2.5%; use 5% for safety's sake.
3721 */
3722 u32 bps = target_clock * bpp * 21 / 20;
3723 lane = bps / (link_bw * 8) + 1;
3724 }
3725
3726 intel_crtc->fdi_lanes = lane;
3727
3728 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3729 }
3730
3731 /* Ironlake: try to setup display ref clock before DPLL
3732 * enabling. This is only under driver's control after
3733 * PCH B stepping, previous chipset stepping should be
3734 * ignoring this setting.
3735 */
3736 if (HAS_PCH_SPLIT(dev)) {
3737 temp = I915_READ(PCH_DREF_CONTROL);
3738 /* Always enable nonspread source */
3739 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3740 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3741 I915_WRITE(PCH_DREF_CONTROL, temp);
3742 POSTING_READ(PCH_DREF_CONTROL);
3743
3744 temp &= ~DREF_SSC_SOURCE_MASK;
3745 temp |= DREF_SSC_SOURCE_ENABLE;
3746 I915_WRITE(PCH_DREF_CONTROL, temp);
3747 POSTING_READ(PCH_DREF_CONTROL);
3748
3749 udelay(200);
3750
3751 if (is_edp) {
3752 if (dev_priv->lvds_use_ssc) {
3753 temp |= DREF_SSC1_ENABLE;
3754 I915_WRITE(PCH_DREF_CONTROL, temp);
3755 POSTING_READ(PCH_DREF_CONTROL);
3756
3757 udelay(200);
3758
3759 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3760 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3761 I915_WRITE(PCH_DREF_CONTROL, temp);
3762 POSTING_READ(PCH_DREF_CONTROL);
3763 } else {
3764 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3765 I915_WRITE(PCH_DREF_CONTROL, temp);
3766 POSTING_READ(PCH_DREF_CONTROL);
3767 }
3768 }
3769 }
3770
3771 if (IS_PINEVIEW(dev)) {
3772 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3773 if (has_reduced_clock)
3774 fp2 = (1 << reduced_clock.n) << 16 |
3775 reduced_clock.m1 << 8 | reduced_clock.m2;
3776 } else {
3777 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3778 if (has_reduced_clock)
3779 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3780 reduced_clock.m2;
3781 }
3782
3783 if (!HAS_PCH_SPLIT(dev))
3784 dpll = DPLL_VGA_MODE_DIS;
3785
3786 if (IS_I9XX(dev)) {
3787 if (is_lvds)
3788 dpll |= DPLLB_MODE_LVDS;
3789 else
3790 dpll |= DPLLB_MODE_DAC_SERIAL;
3791 if (is_sdvo) {
3792 dpll |= DPLL_DVO_HIGH_SPEED;
3793 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3794 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3795 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3796 else if (HAS_PCH_SPLIT(dev))
3797 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3798 }
3799 if (is_dp)
3800 dpll |= DPLL_DVO_HIGH_SPEED;
3801
3802 /* compute bitmask from p1 value */
3803 if (IS_PINEVIEW(dev))
3804 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3805 else {
3806 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3807 /* also FPA1 */
3808 if (HAS_PCH_SPLIT(dev))
3809 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3810 if (IS_G4X(dev) && has_reduced_clock)
3811 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3812 }
3813 switch (clock.p2) {
3814 case 5:
3815 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3816 break;
3817 case 7:
3818 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3819 break;
3820 case 10:
3821 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3822 break;
3823 case 14:
3824 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3825 break;
3826 }
3827 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3828 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3829 } else {
3830 if (is_lvds) {
3831 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3832 } else {
3833 if (clock.p1 == 2)
3834 dpll |= PLL_P1_DIVIDE_BY_TWO;
3835 else
3836 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3837 if (clock.p2 == 4)
3838 dpll |= PLL_P2_DIVIDE_BY_4;
3839 }
3840 }
3841
3842 if (is_sdvo && is_tv)
3843 dpll |= PLL_REF_INPUT_TVCLKINBC;
3844 else if (is_tv)
3845 /* XXX: just matching BIOS for now */
3846 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3847 dpll |= 3;
3848 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3849 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3850 else
3851 dpll |= PLL_REF_INPUT_DREFCLK;
3852
3853 /* setup pipeconf */
3854 pipeconf = I915_READ(pipeconf_reg);
3855
3856 /* Set up the display plane register */
3857 dspcntr = DISPPLANE_GAMMA_ENABLE;
3858
3859 /* Ironlake's plane is forced to pipe, bit 24 is to
3860 enable color space conversion */
3861 if (!HAS_PCH_SPLIT(dev)) {
3862 if (pipe == 0)
3863 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3864 else
3865 dspcntr |= DISPPLANE_SEL_PIPE_B;
3866 }
3867
3868 if (pipe == 0 && !IS_I965G(dev)) {
3869 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3870 * core speed.
3871 *
3872 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3873 * pipe == 0 check?
3874 */
3875 if (mode->clock >
3876 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3877 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3878 else
3879 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3880 }
3881
3882 dspcntr |= DISPLAY_PLANE_ENABLE;
3883 pipeconf |= PIPEACONF_ENABLE;
3884 dpll |= DPLL_VCO_ENABLE;
3885
3886
3887 /* Disable the panel fitter if it was on our pipe */
3888 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3889 I915_WRITE(PFIT_CONTROL, 0);
3890
3891 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3892 drm_mode_debug_printmodeline(mode);
3893
3894 /* assign to Ironlake registers */
3895 if (HAS_PCH_SPLIT(dev)) {
3896 fp_reg = pch_fp_reg;
3897 dpll_reg = pch_dpll_reg;
3898 }
3899
3900 if (!is_edp) {
3901 I915_WRITE(fp_reg, fp);
3902 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3903 I915_READ(dpll_reg);
3904 udelay(150);
3905 }
3906
3907 /* enable transcoder DPLL */
3908 if (HAS_PCH_CPT(dev)) {
3909 temp = I915_READ(PCH_DPLL_SEL);
3910 if (trans_dpll_sel == 0)
3911 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3912 else
3913 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3914 I915_WRITE(PCH_DPLL_SEL, temp);
3915 I915_READ(PCH_DPLL_SEL);
3916 udelay(150);
3917 }
3918
3919 if (HAS_PCH_SPLIT(dev)) {
3920 pipeconf &= ~PIPE_ENABLE_DITHER;
3921 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3922 }
3923
3924 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3925 * This is an exception to the general rule that mode_set doesn't turn
3926 * things on.
3927 */
3928 if (is_lvds) {
3929 u32 lvds;
3930
3931 if (HAS_PCH_SPLIT(dev))
3932 lvds_reg = PCH_LVDS;
3933
3934 lvds = I915_READ(lvds_reg);
3935 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3936 if (pipe == 1) {
3937 if (HAS_PCH_CPT(dev))
3938 lvds |= PORT_TRANS_B_SEL_CPT;
3939 else
3940 lvds |= LVDS_PIPEB_SELECT;
3941 } else {
3942 if (HAS_PCH_CPT(dev))
3943 lvds &= ~PORT_TRANS_SEL_MASK;
3944 else
3945 lvds &= ~LVDS_PIPEB_SELECT;
3946 }
3947 /* set the corresponsding LVDS_BORDER bit */
3948 lvds |= dev_priv->lvds_border_bits;
3949 /* Set the B0-B3 data pairs corresponding to whether we're going to
3950 * set the DPLLs for dual-channel mode or not.
3951 */
3952 if (clock.p2 == 7)
3953 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3954 else
3955 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3956
3957 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3958 * appropriately here, but we need to look more thoroughly into how
3959 * panels behave in the two modes.
3960 */
3961 /* set the dithering flag */
3962 if (IS_I965G(dev)) {
3963 if (dev_priv->lvds_dither) {
3964 if (HAS_PCH_SPLIT(dev)) {
3965 pipeconf |= PIPE_ENABLE_DITHER;
3966 pipeconf |= PIPE_DITHER_TYPE_ST01;
3967 } else
3968 lvds |= LVDS_ENABLE_DITHER;
3969 } else {
3970 if (!HAS_PCH_SPLIT(dev)) {
3971 lvds &= ~LVDS_ENABLE_DITHER;
3972 }
3973 }
3974 }
3975 I915_WRITE(lvds_reg, lvds);
3976 I915_READ(lvds_reg);
3977 }
3978 if (is_dp)
3979 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3980 else if (HAS_PCH_SPLIT(dev)) {
3981 /* For non-DP output, clear any trans DP clock recovery setting.*/
3982 if (pipe == 0) {
3983 I915_WRITE(TRANSA_DATA_M1, 0);
3984 I915_WRITE(TRANSA_DATA_N1, 0);
3985 I915_WRITE(TRANSA_DP_LINK_M1, 0);
3986 I915_WRITE(TRANSA_DP_LINK_N1, 0);
3987 } else {
3988 I915_WRITE(TRANSB_DATA_M1, 0);
3989 I915_WRITE(TRANSB_DATA_N1, 0);
3990 I915_WRITE(TRANSB_DP_LINK_M1, 0);
3991 I915_WRITE(TRANSB_DP_LINK_N1, 0);
3992 }
3993 }
3994
3995 if (!is_edp) {
3996 I915_WRITE(fp_reg, fp);
3997 I915_WRITE(dpll_reg, dpll);
3998 I915_READ(dpll_reg);
3999 /* Wait for the clocks to stabilize. */
4000 udelay(150);
4001
4002 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4003 if (is_sdvo) {
4004 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
4005 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4006 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
4007 } else
4008 I915_WRITE(dpll_md_reg, 0);
4009 } else {
4010 /* write it again -- the BIOS does, after all */
4011 I915_WRITE(dpll_reg, dpll);
4012 }
4013 I915_READ(dpll_reg);
4014 /* Wait for the clocks to stabilize. */
4015 udelay(150);
4016 }
4017
4018 if (is_lvds && has_reduced_clock && i915_powersave) {
4019 I915_WRITE(fp_reg + 4, fp2);
4020 intel_crtc->lowfreq_avail = true;
4021 if (HAS_PIPE_CXSR(dev)) {
4022 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4023 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4024 }
4025 } else {
4026 I915_WRITE(fp_reg + 4, fp);
4027 intel_crtc->lowfreq_avail = false;
4028 if (HAS_PIPE_CXSR(dev)) {
4029 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4030 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4031 }
4032 }
4033
4034 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4035 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4036 /* the chip adds 2 halflines automatically */
4037 adjusted_mode->crtc_vdisplay -= 1;
4038 adjusted_mode->crtc_vtotal -= 1;
4039 adjusted_mode->crtc_vblank_start -= 1;
4040 adjusted_mode->crtc_vblank_end -= 1;
4041 adjusted_mode->crtc_vsync_end -= 1;
4042 adjusted_mode->crtc_vsync_start -= 1;
4043 } else
4044 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4045
4046 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4047 ((adjusted_mode->crtc_htotal - 1) << 16));
4048 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4049 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4050 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4051 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4052 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4053 ((adjusted_mode->crtc_vtotal - 1) << 16));
4054 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4055 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4056 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4057 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4058 /* pipesrc and dspsize control the size that is scaled from, which should
4059 * always be the user's requested size.
4060 */
4061 if (!HAS_PCH_SPLIT(dev)) {
4062 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4063 (mode->hdisplay - 1));
4064 I915_WRITE(dsppos_reg, 0);
4065 }
4066 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4067
4068 if (HAS_PCH_SPLIT(dev)) {
4069 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4070 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4071 I915_WRITE(link_m1_reg, m_n.link_m);
4072 I915_WRITE(link_n1_reg, m_n.link_n);
4073
4074 if (is_edp) {
4075 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4076 } else {
4077 /* enable FDI RX PLL too */
4078 temp = I915_READ(fdi_rx_reg);
4079 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4080 I915_READ(fdi_rx_reg);
4081 udelay(200);
4082
4083 /* enable FDI TX PLL too */
4084 temp = I915_READ(fdi_tx_reg);
4085 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4086 I915_READ(fdi_tx_reg);
4087
4088 /* enable FDI RX PCDCLK */
4089 temp = I915_READ(fdi_rx_reg);
4090 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4091 I915_READ(fdi_rx_reg);
4092 udelay(200);
4093 }
4094 }
4095
4096 I915_WRITE(pipeconf_reg, pipeconf);
4097 I915_READ(pipeconf_reg);
4098
4099 intel_wait_for_vblank(dev);
4100
4101 if (IS_IRONLAKE(dev)) {
4102 /* enable address swizzle for tiling buffer */
4103 temp = I915_READ(DISP_ARB_CTL);
4104 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4105 }
4106
4107 I915_WRITE(dspcntr_reg, dspcntr);
4108
4109 /* Flush the plane changes */
4110 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4111
4112 intel_update_watermarks(dev);
4113
4114 drm_vblank_post_modeset(dev, pipe);
4115
4116 return ret;
4117 }
4118
4119 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4120 void intel_crtc_load_lut(struct drm_crtc *crtc)
4121 {
4122 struct drm_device *dev = crtc->dev;
4123 struct drm_i915_private *dev_priv = dev->dev_private;
4124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4125 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4126 int i;
4127
4128 /* The clocks have to be on to load the palette. */
4129 if (!crtc->enabled)
4130 return;
4131
4132 /* use legacy palette for Ironlake */
4133 if (HAS_PCH_SPLIT(dev))
4134 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4135 LGC_PALETTE_B;
4136
4137 for (i = 0; i < 256; i++) {
4138 I915_WRITE(palreg + 4 * i,
4139 (intel_crtc->lut_r[i] << 16) |
4140 (intel_crtc->lut_g[i] << 8) |
4141 intel_crtc->lut_b[i]);
4142 }
4143 }
4144
4145 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4146 {
4147 struct drm_device *dev = crtc->dev;
4148 struct drm_i915_private *dev_priv = dev->dev_private;
4149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4150 bool visible = base != 0;
4151 u32 cntl;
4152
4153 if (intel_crtc->cursor_visible == visible)
4154 return;
4155
4156 cntl = I915_READ(CURACNTR);
4157 if (visible) {
4158 /* On these chipsets we can only modify the base whilst
4159 * the cursor is disabled.
4160 */
4161 I915_WRITE(CURABASE, base);
4162
4163 cntl &= ~(CURSOR_FORMAT_MASK);
4164 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4165 cntl |= CURSOR_ENABLE |
4166 CURSOR_GAMMA_ENABLE |
4167 CURSOR_FORMAT_ARGB;
4168 } else
4169 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4170 I915_WRITE(CURACNTR, cntl);
4171
4172 intel_crtc->cursor_visible = visible;
4173 }
4174
4175 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4176 {
4177 struct drm_device *dev = crtc->dev;
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4180 int pipe = intel_crtc->pipe;
4181 bool visible = base != 0;
4182
4183 if (intel_crtc->cursor_visible != visible) {
4184 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4185 if (base) {
4186 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4187 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4188 cntl |= pipe << 28; /* Connect to correct pipe */
4189 } else {
4190 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4191 cntl |= CURSOR_MODE_DISABLE;
4192 }
4193 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4194
4195 intel_crtc->cursor_visible = visible;
4196 }
4197 /* and commit changes on next vblank */
4198 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4199 }
4200
4201 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4202 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4203 {
4204 struct drm_device *dev = crtc->dev;
4205 struct drm_i915_private *dev_priv = dev->dev_private;
4206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4207 int pipe = intel_crtc->pipe;
4208 int x = intel_crtc->cursor_x;
4209 int y = intel_crtc->cursor_y;
4210 u32 base, pos;
4211 bool visible;
4212
4213 pos = 0;
4214
4215 if (intel_crtc->cursor_on && crtc->fb) {
4216 base = intel_crtc->cursor_addr;
4217 if (x > (int) crtc->fb->width)
4218 base = 0;
4219
4220 if (y > (int) crtc->fb->height)
4221 base = 0;
4222 } else
4223 base = 0;
4224
4225 if (x < 0) {
4226 if (x + intel_crtc->cursor_width < 0)
4227 base = 0;
4228
4229 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4230 x = -x;
4231 }
4232 pos |= x << CURSOR_X_SHIFT;
4233
4234 if (y < 0) {
4235 if (y + intel_crtc->cursor_height < 0)
4236 base = 0;
4237
4238 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4239 y = -y;
4240 }
4241 pos |= y << CURSOR_Y_SHIFT;
4242
4243 visible = base != 0;
4244 if (!visible && !intel_crtc->cursor_visible)
4245 return;
4246
4247 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4248 if (IS_845G(dev) || IS_I865G(dev))
4249 i845_update_cursor(crtc, base);
4250 else
4251 i9xx_update_cursor(crtc, base);
4252
4253 if (visible)
4254 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4255 }
4256
4257 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4258 struct drm_file *file_priv,
4259 uint32_t handle,
4260 uint32_t width, uint32_t height)
4261 {
4262 struct drm_device *dev = crtc->dev;
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4265 struct drm_gem_object *bo;
4266 struct drm_i915_gem_object *obj_priv;
4267 uint32_t addr;
4268 int ret;
4269
4270 DRM_DEBUG_KMS("\n");
4271
4272 /* if we want to turn off the cursor ignore width and height */
4273 if (!handle) {
4274 DRM_DEBUG_KMS("cursor off\n");
4275 addr = 0;
4276 bo = NULL;
4277 mutex_lock(&dev->struct_mutex);
4278 goto finish;
4279 }
4280
4281 /* Currently we only support 64x64 cursors */
4282 if (width != 64 || height != 64) {
4283 DRM_ERROR("we currently only support 64x64 cursors\n");
4284 return -EINVAL;
4285 }
4286
4287 bo = drm_gem_object_lookup(dev, file_priv, handle);
4288 if (!bo)
4289 return -ENOENT;
4290
4291 obj_priv = to_intel_bo(bo);
4292
4293 if (bo->size < width * height * 4) {
4294 DRM_ERROR("buffer is to small\n");
4295 ret = -ENOMEM;
4296 goto fail;
4297 }
4298
4299 /* we only need to pin inside GTT if cursor is non-phy */
4300 mutex_lock(&dev->struct_mutex);
4301 if (!dev_priv->info->cursor_needs_physical) {
4302 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4303 if (ret) {
4304 DRM_ERROR("failed to pin cursor bo\n");
4305 goto fail_locked;
4306 }
4307
4308 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4309 if (ret) {
4310 DRM_ERROR("failed to move cursor bo into the GTT\n");
4311 goto fail_unpin;
4312 }
4313
4314 addr = obj_priv->gtt_offset;
4315 } else {
4316 int align = IS_I830(dev) ? 16 * 1024 : 256;
4317 ret = i915_gem_attach_phys_object(dev, bo,
4318 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4319 align);
4320 if (ret) {
4321 DRM_ERROR("failed to attach phys object\n");
4322 goto fail_locked;
4323 }
4324 addr = obj_priv->phys_obj->handle->busaddr;
4325 }
4326
4327 if (!IS_I9XX(dev))
4328 I915_WRITE(CURSIZE, (height << 12) | width);
4329
4330 finish:
4331 if (intel_crtc->cursor_bo) {
4332 if (dev_priv->info->cursor_needs_physical) {
4333 if (intel_crtc->cursor_bo != bo)
4334 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4335 } else
4336 i915_gem_object_unpin(intel_crtc->cursor_bo);
4337 drm_gem_object_unreference(intel_crtc->cursor_bo);
4338 }
4339
4340 mutex_unlock(&dev->struct_mutex);
4341
4342 intel_crtc->cursor_addr = addr;
4343 intel_crtc->cursor_bo = bo;
4344 intel_crtc->cursor_width = width;
4345 intel_crtc->cursor_height = height;
4346
4347 intel_crtc_update_cursor(crtc);
4348
4349 return 0;
4350 fail_unpin:
4351 i915_gem_object_unpin(bo);
4352 fail_locked:
4353 mutex_unlock(&dev->struct_mutex);
4354 fail:
4355 drm_gem_object_unreference_unlocked(bo);
4356 return ret;
4357 }
4358
4359 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4360 {
4361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4362
4363 intel_crtc->cursor_x = x;
4364 intel_crtc->cursor_y = y;
4365
4366 intel_crtc_update_cursor(crtc);
4367
4368 return 0;
4369 }
4370
4371 /** Sets the color ramps on behalf of RandR */
4372 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4373 u16 blue, int regno)
4374 {
4375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4376
4377 intel_crtc->lut_r[regno] = red >> 8;
4378 intel_crtc->lut_g[regno] = green >> 8;
4379 intel_crtc->lut_b[regno] = blue >> 8;
4380 }
4381
4382 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4383 u16 *blue, int regno)
4384 {
4385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4386
4387 *red = intel_crtc->lut_r[regno] << 8;
4388 *green = intel_crtc->lut_g[regno] << 8;
4389 *blue = intel_crtc->lut_b[regno] << 8;
4390 }
4391
4392 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4393 u16 *blue, uint32_t size)
4394 {
4395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4396 int i;
4397
4398 if (size != 256)
4399 return;
4400
4401 for (i = 0; i < 256; i++) {
4402 intel_crtc->lut_r[i] = red[i] >> 8;
4403 intel_crtc->lut_g[i] = green[i] >> 8;
4404 intel_crtc->lut_b[i] = blue[i] >> 8;
4405 }
4406
4407 intel_crtc_load_lut(crtc);
4408 }
4409
4410 /**
4411 * Get a pipe with a simple mode set on it for doing load-based monitor
4412 * detection.
4413 *
4414 * It will be up to the load-detect code to adjust the pipe as appropriate for
4415 * its requirements. The pipe will be connected to no other encoders.
4416 *
4417 * Currently this code will only succeed if there is a pipe with no encoders
4418 * configured for it. In the future, it could choose to temporarily disable
4419 * some outputs to free up a pipe for its use.
4420 *
4421 * \return crtc, or NULL if no pipes are available.
4422 */
4423
4424 /* VESA 640x480x72Hz mode to set on the pipe */
4425 static struct drm_display_mode load_detect_mode = {
4426 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4427 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4428 };
4429
4430 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4431 struct drm_connector *connector,
4432 struct drm_display_mode *mode,
4433 int *dpms_mode)
4434 {
4435 struct intel_crtc *intel_crtc;
4436 struct drm_crtc *possible_crtc;
4437 struct drm_crtc *supported_crtc =NULL;
4438 struct drm_encoder *encoder = &intel_encoder->enc;
4439 struct drm_crtc *crtc = NULL;
4440 struct drm_device *dev = encoder->dev;
4441 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4442 struct drm_crtc_helper_funcs *crtc_funcs;
4443 int i = -1;
4444
4445 /*
4446 * Algorithm gets a little messy:
4447 * - if the connector already has an assigned crtc, use it (but make
4448 * sure it's on first)
4449 * - try to find the first unused crtc that can drive this connector,
4450 * and use that if we find one
4451 * - if there are no unused crtcs available, try to use the first
4452 * one we found that supports the connector
4453 */
4454
4455 /* See if we already have a CRTC for this connector */
4456 if (encoder->crtc) {
4457 crtc = encoder->crtc;
4458 /* Make sure the crtc and connector are running */
4459 intel_crtc = to_intel_crtc(crtc);
4460 *dpms_mode = intel_crtc->dpms_mode;
4461 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4462 crtc_funcs = crtc->helper_private;
4463 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4464 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4465 }
4466 return crtc;
4467 }
4468
4469 /* Find an unused one (if possible) */
4470 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4471 i++;
4472 if (!(encoder->possible_crtcs & (1 << i)))
4473 continue;
4474 if (!possible_crtc->enabled) {
4475 crtc = possible_crtc;
4476 break;
4477 }
4478 if (!supported_crtc)
4479 supported_crtc = possible_crtc;
4480 }
4481
4482 /*
4483 * If we didn't find an unused CRTC, don't use any.
4484 */
4485 if (!crtc) {
4486 return NULL;
4487 }
4488
4489 encoder->crtc = crtc;
4490 connector->encoder = encoder;
4491 intel_encoder->load_detect_temp = true;
4492
4493 intel_crtc = to_intel_crtc(crtc);
4494 *dpms_mode = intel_crtc->dpms_mode;
4495
4496 if (!crtc->enabled) {
4497 if (!mode)
4498 mode = &load_detect_mode;
4499 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4500 } else {
4501 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4502 crtc_funcs = crtc->helper_private;
4503 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4504 }
4505
4506 /* Add this connector to the crtc */
4507 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4508 encoder_funcs->commit(encoder);
4509 }
4510 /* let the connector get through one full cycle before testing */
4511 intel_wait_for_vblank(dev);
4512
4513 return crtc;
4514 }
4515
4516 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4517 struct drm_connector *connector, int dpms_mode)
4518 {
4519 struct drm_encoder *encoder = &intel_encoder->enc;
4520 struct drm_device *dev = encoder->dev;
4521 struct drm_crtc *crtc = encoder->crtc;
4522 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4523 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4524
4525 if (intel_encoder->load_detect_temp) {
4526 encoder->crtc = NULL;
4527 connector->encoder = NULL;
4528 intel_encoder->load_detect_temp = false;
4529 crtc->enabled = drm_helper_crtc_in_use(crtc);
4530 drm_helper_disable_unused_functions(dev);
4531 }
4532
4533 /* Switch crtc and encoder back off if necessary */
4534 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4535 if (encoder->crtc == crtc)
4536 encoder_funcs->dpms(encoder, dpms_mode);
4537 crtc_funcs->dpms(crtc, dpms_mode);
4538 }
4539 }
4540
4541 /* Returns the clock of the currently programmed mode of the given pipe. */
4542 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4543 {
4544 struct drm_i915_private *dev_priv = dev->dev_private;
4545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4546 int pipe = intel_crtc->pipe;
4547 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4548 u32 fp;
4549 intel_clock_t clock;
4550
4551 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4552 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4553 else
4554 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4555
4556 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4557 if (IS_PINEVIEW(dev)) {
4558 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4559 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4560 } else {
4561 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4562 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4563 }
4564
4565 if (IS_I9XX(dev)) {
4566 if (IS_PINEVIEW(dev))
4567 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4568 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4569 else
4570 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4571 DPLL_FPA01_P1_POST_DIV_SHIFT);
4572
4573 switch (dpll & DPLL_MODE_MASK) {
4574 case DPLLB_MODE_DAC_SERIAL:
4575 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4576 5 : 10;
4577 break;
4578 case DPLLB_MODE_LVDS:
4579 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4580 7 : 14;
4581 break;
4582 default:
4583 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4584 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4585 return 0;
4586 }
4587
4588 /* XXX: Handle the 100Mhz refclk */
4589 intel_clock(dev, 96000, &clock);
4590 } else {
4591 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4592
4593 if (is_lvds) {
4594 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4595 DPLL_FPA01_P1_POST_DIV_SHIFT);
4596 clock.p2 = 14;
4597
4598 if ((dpll & PLL_REF_INPUT_MASK) ==
4599 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4600 /* XXX: might not be 66MHz */
4601 intel_clock(dev, 66000, &clock);
4602 } else
4603 intel_clock(dev, 48000, &clock);
4604 } else {
4605 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4606 clock.p1 = 2;
4607 else {
4608 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4609 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4610 }
4611 if (dpll & PLL_P2_DIVIDE_BY_4)
4612 clock.p2 = 4;
4613 else
4614 clock.p2 = 2;
4615
4616 intel_clock(dev, 48000, &clock);
4617 }
4618 }
4619
4620 /* XXX: It would be nice to validate the clocks, but we can't reuse
4621 * i830PllIsValid() because it relies on the xf86_config connector
4622 * configuration being accurate, which it isn't necessarily.
4623 */
4624
4625 return clock.dot;
4626 }
4627
4628 /** Returns the currently programmed mode of the given pipe. */
4629 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4630 struct drm_crtc *crtc)
4631 {
4632 struct drm_i915_private *dev_priv = dev->dev_private;
4633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4634 int pipe = intel_crtc->pipe;
4635 struct drm_display_mode *mode;
4636 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4637 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4638 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4639 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4640
4641 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4642 if (!mode)
4643 return NULL;
4644
4645 mode->clock = intel_crtc_clock_get(dev, crtc);
4646 mode->hdisplay = (htot & 0xffff) + 1;
4647 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4648 mode->hsync_start = (hsync & 0xffff) + 1;
4649 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4650 mode->vdisplay = (vtot & 0xffff) + 1;
4651 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4652 mode->vsync_start = (vsync & 0xffff) + 1;
4653 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4654
4655 drm_mode_set_name(mode);
4656 drm_mode_set_crtcinfo(mode, 0);
4657
4658 return mode;
4659 }
4660
4661 #define GPU_IDLE_TIMEOUT 500 /* ms */
4662
4663 /* When this timer fires, we've been idle for awhile */
4664 static void intel_gpu_idle_timer(unsigned long arg)
4665 {
4666 struct drm_device *dev = (struct drm_device *)arg;
4667 drm_i915_private_t *dev_priv = dev->dev_private;
4668
4669 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4670
4671 dev_priv->busy = false;
4672
4673 queue_work(dev_priv->wq, &dev_priv->idle_work);
4674 }
4675
4676 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4677
4678 static void intel_crtc_idle_timer(unsigned long arg)
4679 {
4680 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4681 struct drm_crtc *crtc = &intel_crtc->base;
4682 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4683
4684 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4685
4686 intel_crtc->busy = false;
4687
4688 queue_work(dev_priv->wq, &dev_priv->idle_work);
4689 }
4690
4691 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4692 {
4693 struct drm_device *dev = crtc->dev;
4694 drm_i915_private_t *dev_priv = dev->dev_private;
4695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4696 int pipe = intel_crtc->pipe;
4697 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4698 int dpll = I915_READ(dpll_reg);
4699
4700 if (HAS_PCH_SPLIT(dev))
4701 return;
4702
4703 if (!dev_priv->lvds_downclock_avail)
4704 return;
4705
4706 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4707 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4708
4709 /* Unlock panel regs */
4710 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4711 PANEL_UNLOCK_REGS);
4712
4713 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4714 I915_WRITE(dpll_reg, dpll);
4715 dpll = I915_READ(dpll_reg);
4716 intel_wait_for_vblank(dev);
4717 dpll = I915_READ(dpll_reg);
4718 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4719 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4720
4721 /* ...and lock them again */
4722 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4723 }
4724
4725 /* Schedule downclock */
4726 if (schedule)
4727 mod_timer(&intel_crtc->idle_timer, jiffies +
4728 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4729 }
4730
4731 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4732 {
4733 struct drm_device *dev = crtc->dev;
4734 drm_i915_private_t *dev_priv = dev->dev_private;
4735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4736 int pipe = intel_crtc->pipe;
4737 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4738 int dpll = I915_READ(dpll_reg);
4739
4740 if (HAS_PCH_SPLIT(dev))
4741 return;
4742
4743 if (!dev_priv->lvds_downclock_avail)
4744 return;
4745
4746 /*
4747 * Since this is called by a timer, we should never get here in
4748 * the manual case.
4749 */
4750 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4751 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4752
4753 /* Unlock panel regs */
4754 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4755 PANEL_UNLOCK_REGS);
4756
4757 dpll |= DISPLAY_RATE_SELECT_FPA1;
4758 I915_WRITE(dpll_reg, dpll);
4759 dpll = I915_READ(dpll_reg);
4760 intel_wait_for_vblank(dev);
4761 dpll = I915_READ(dpll_reg);
4762 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4763 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4764
4765 /* ...and lock them again */
4766 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4767 }
4768
4769 }
4770
4771 /**
4772 * intel_idle_update - adjust clocks for idleness
4773 * @work: work struct
4774 *
4775 * Either the GPU or display (or both) went idle. Check the busy status
4776 * here and adjust the CRTC and GPU clocks as necessary.
4777 */
4778 static void intel_idle_update(struct work_struct *work)
4779 {
4780 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4781 idle_work);
4782 struct drm_device *dev = dev_priv->dev;
4783 struct drm_crtc *crtc;
4784 struct intel_crtc *intel_crtc;
4785 int enabled = 0;
4786
4787 if (!i915_powersave)
4788 return;
4789
4790 mutex_lock(&dev->struct_mutex);
4791
4792 i915_update_gfx_val(dev_priv);
4793
4794 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4795 /* Skip inactive CRTCs */
4796 if (!crtc->fb)
4797 continue;
4798
4799 enabled++;
4800 intel_crtc = to_intel_crtc(crtc);
4801 if (!intel_crtc->busy)
4802 intel_decrease_pllclock(crtc);
4803 }
4804
4805 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4806 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4807 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4808 }
4809
4810 mutex_unlock(&dev->struct_mutex);
4811 }
4812
4813 /**
4814 * intel_mark_busy - mark the GPU and possibly the display busy
4815 * @dev: drm device
4816 * @obj: object we're operating on
4817 *
4818 * Callers can use this function to indicate that the GPU is busy processing
4819 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4820 * buffer), we'll also mark the display as busy, so we know to increase its
4821 * clock frequency.
4822 */
4823 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4824 {
4825 drm_i915_private_t *dev_priv = dev->dev_private;
4826 struct drm_crtc *crtc = NULL;
4827 struct intel_framebuffer *intel_fb;
4828 struct intel_crtc *intel_crtc;
4829
4830 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4831 return;
4832
4833 if (!dev_priv->busy) {
4834 if (IS_I945G(dev) || IS_I945GM(dev)) {
4835 u32 fw_blc_self;
4836
4837 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4838 fw_blc_self = I915_READ(FW_BLC_SELF);
4839 fw_blc_self &= ~FW_BLC_SELF_EN;
4840 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4841 }
4842 dev_priv->busy = true;
4843 } else
4844 mod_timer(&dev_priv->idle_timer, jiffies +
4845 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4846
4847 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4848 if (!crtc->fb)
4849 continue;
4850
4851 intel_crtc = to_intel_crtc(crtc);
4852 intel_fb = to_intel_framebuffer(crtc->fb);
4853 if (intel_fb->obj == obj) {
4854 if (!intel_crtc->busy) {
4855 if (IS_I945G(dev) || IS_I945GM(dev)) {
4856 u32 fw_blc_self;
4857
4858 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4859 fw_blc_self = I915_READ(FW_BLC_SELF);
4860 fw_blc_self &= ~FW_BLC_SELF_EN;
4861 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4862 }
4863 /* Non-busy -> busy, upclock */
4864 intel_increase_pllclock(crtc, true);
4865 intel_crtc->busy = true;
4866 } else {
4867 /* Busy -> busy, put off timer */
4868 mod_timer(&intel_crtc->idle_timer, jiffies +
4869 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4870 }
4871 }
4872 }
4873 }
4874
4875 static void intel_crtc_destroy(struct drm_crtc *crtc)
4876 {
4877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4878
4879 drm_crtc_cleanup(crtc);
4880 kfree(intel_crtc);
4881 }
4882
4883 struct intel_unpin_work {
4884 struct work_struct work;
4885 struct drm_device *dev;
4886 struct drm_gem_object *old_fb_obj;
4887 struct drm_gem_object *pending_flip_obj;
4888 struct drm_pending_vblank_event *event;
4889 int pending;
4890 };
4891
4892 static void intel_unpin_work_fn(struct work_struct *__work)
4893 {
4894 struct intel_unpin_work *work =
4895 container_of(__work, struct intel_unpin_work, work);
4896
4897 mutex_lock(&work->dev->struct_mutex);
4898 i915_gem_object_unpin(work->old_fb_obj);
4899 drm_gem_object_unreference(work->pending_flip_obj);
4900 drm_gem_object_unreference(work->old_fb_obj);
4901 mutex_unlock(&work->dev->struct_mutex);
4902 kfree(work);
4903 }
4904
4905 static void do_intel_finish_page_flip(struct drm_device *dev,
4906 struct drm_crtc *crtc)
4907 {
4908 drm_i915_private_t *dev_priv = dev->dev_private;
4909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4910 struct intel_unpin_work *work;
4911 struct drm_i915_gem_object *obj_priv;
4912 struct drm_pending_vblank_event *e;
4913 struct timeval now;
4914 unsigned long flags;
4915
4916 /* Ignore early vblank irqs */
4917 if (intel_crtc == NULL)
4918 return;
4919
4920 spin_lock_irqsave(&dev->event_lock, flags);
4921 work = intel_crtc->unpin_work;
4922 if (work == NULL || !work->pending) {
4923 spin_unlock_irqrestore(&dev->event_lock, flags);
4924 return;
4925 }
4926
4927 intel_crtc->unpin_work = NULL;
4928 drm_vblank_put(dev, intel_crtc->pipe);
4929
4930 if (work->event) {
4931 e = work->event;
4932 do_gettimeofday(&now);
4933 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4934 e->event.tv_sec = now.tv_sec;
4935 e->event.tv_usec = now.tv_usec;
4936 list_add_tail(&e->base.link,
4937 &e->base.file_priv->event_list);
4938 wake_up_interruptible(&e->base.file_priv->event_wait);
4939 }
4940
4941 spin_unlock_irqrestore(&dev->event_lock, flags);
4942
4943 obj_priv = to_intel_bo(work->pending_flip_obj);
4944
4945 /* Initial scanout buffer will have a 0 pending flip count */
4946 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4947 atomic_dec_and_test(&obj_priv->pending_flip))
4948 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4949 schedule_work(&work->work);
4950
4951 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4952 }
4953
4954 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4955 {
4956 drm_i915_private_t *dev_priv = dev->dev_private;
4957 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4958
4959 do_intel_finish_page_flip(dev, crtc);
4960 }
4961
4962 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4963 {
4964 drm_i915_private_t *dev_priv = dev->dev_private;
4965 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4966
4967 do_intel_finish_page_flip(dev, crtc);
4968 }
4969
4970 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4971 {
4972 drm_i915_private_t *dev_priv = dev->dev_private;
4973 struct intel_crtc *intel_crtc =
4974 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4975 unsigned long flags;
4976
4977 spin_lock_irqsave(&dev->event_lock, flags);
4978 if (intel_crtc->unpin_work) {
4979 intel_crtc->unpin_work->pending = 1;
4980 } else {
4981 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4982 }
4983 spin_unlock_irqrestore(&dev->event_lock, flags);
4984 }
4985
4986 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4987 struct drm_framebuffer *fb,
4988 struct drm_pending_vblank_event *event)
4989 {
4990 struct drm_device *dev = crtc->dev;
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992 struct intel_framebuffer *intel_fb;
4993 struct drm_i915_gem_object *obj_priv;
4994 struct drm_gem_object *obj;
4995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4996 struct intel_unpin_work *work;
4997 unsigned long flags, offset;
4998 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4999 int ret, pipesrc;
5000 u32 flip_mask;
5001
5002 work = kzalloc(sizeof *work, GFP_KERNEL);
5003 if (work == NULL)
5004 return -ENOMEM;
5005
5006 work->event = event;
5007 work->dev = crtc->dev;
5008 intel_fb = to_intel_framebuffer(crtc->fb);
5009 work->old_fb_obj = intel_fb->obj;
5010 INIT_WORK(&work->work, intel_unpin_work_fn);
5011
5012 /* We borrow the event spin lock for protecting unpin_work */
5013 spin_lock_irqsave(&dev->event_lock, flags);
5014 if (intel_crtc->unpin_work) {
5015 spin_unlock_irqrestore(&dev->event_lock, flags);
5016 kfree(work);
5017
5018 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5019 return -EBUSY;
5020 }
5021 intel_crtc->unpin_work = work;
5022 spin_unlock_irqrestore(&dev->event_lock, flags);
5023
5024 intel_fb = to_intel_framebuffer(fb);
5025 obj = intel_fb->obj;
5026
5027 mutex_lock(&dev->struct_mutex);
5028 ret = intel_pin_and_fence_fb_obj(dev, obj);
5029 if (ret)
5030 goto cleanup_work;
5031
5032 /* Reference the objects for the scheduled work. */
5033 drm_gem_object_reference(work->old_fb_obj);
5034 drm_gem_object_reference(obj);
5035
5036 crtc->fb = fb;
5037 ret = i915_gem_object_flush_write_domain(obj);
5038 if (ret)
5039 goto cleanup_objs;
5040
5041 ret = drm_vblank_get(dev, intel_crtc->pipe);
5042 if (ret)
5043 goto cleanup_objs;
5044
5045 obj_priv = to_intel_bo(obj);
5046 atomic_inc(&obj_priv->pending_flip);
5047 work->pending_flip_obj = obj;
5048
5049 if (intel_crtc->plane)
5050 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5051 else
5052 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5053
5054 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5055 BEGIN_LP_RING(2);
5056 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5057 OUT_RING(0);
5058 ADVANCE_LP_RING();
5059 }
5060
5061 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5062 offset = obj_priv->gtt_offset;
5063 offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5064
5065 BEGIN_LP_RING(4);
5066 if (IS_I965G(dev)) {
5067 OUT_RING(MI_DISPLAY_FLIP |
5068 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5069 OUT_RING(fb->pitch);
5070 OUT_RING(offset | obj_priv->tiling_mode);
5071 pipesrc = I915_READ(pipesrc_reg);
5072 OUT_RING(pipesrc & 0x0fff0fff);
5073 } else if (IS_GEN3(dev)) {
5074 OUT_RING(MI_DISPLAY_FLIP_I915 |
5075 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5076 OUT_RING(fb->pitch);
5077 OUT_RING(offset);
5078 OUT_RING(MI_NOOP);
5079 } else {
5080 OUT_RING(MI_DISPLAY_FLIP |
5081 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5082 OUT_RING(fb->pitch);
5083 OUT_RING(offset);
5084 OUT_RING(MI_NOOP);
5085 }
5086 ADVANCE_LP_RING();
5087
5088 mutex_unlock(&dev->struct_mutex);
5089
5090 trace_i915_flip_request(intel_crtc->plane, obj);
5091
5092 return 0;
5093
5094 cleanup_objs:
5095 drm_gem_object_unreference(work->old_fb_obj);
5096 drm_gem_object_unreference(obj);
5097 cleanup_work:
5098 mutex_unlock(&dev->struct_mutex);
5099
5100 spin_lock_irqsave(&dev->event_lock, flags);
5101 intel_crtc->unpin_work = NULL;
5102 spin_unlock_irqrestore(&dev->event_lock, flags);
5103
5104 kfree(work);
5105
5106 return ret;
5107 }
5108
5109 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5110 .dpms = intel_crtc_dpms,
5111 .mode_fixup = intel_crtc_mode_fixup,
5112 .mode_set = intel_crtc_mode_set,
5113 .mode_set_base = intel_pipe_set_base,
5114 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5115 .prepare = intel_crtc_prepare,
5116 .commit = intel_crtc_commit,
5117 .load_lut = intel_crtc_load_lut,
5118 };
5119
5120 static const struct drm_crtc_funcs intel_crtc_funcs = {
5121 .cursor_set = intel_crtc_cursor_set,
5122 .cursor_move = intel_crtc_cursor_move,
5123 .gamma_set = intel_crtc_gamma_set,
5124 .set_config = drm_crtc_helper_set_config,
5125 .destroy = intel_crtc_destroy,
5126 .page_flip = intel_crtc_page_flip,
5127 };
5128
5129
5130 static void intel_crtc_init(struct drm_device *dev, int pipe)
5131 {
5132 drm_i915_private_t *dev_priv = dev->dev_private;
5133 struct intel_crtc *intel_crtc;
5134 int i;
5135
5136 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5137 if (intel_crtc == NULL)
5138 return;
5139
5140 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5141
5142 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5143 intel_crtc->pipe = pipe;
5144 intel_crtc->plane = pipe;
5145 for (i = 0; i < 256; i++) {
5146 intel_crtc->lut_r[i] = i;
5147 intel_crtc->lut_g[i] = i;
5148 intel_crtc->lut_b[i] = i;
5149 }
5150
5151 /* Swap pipes & planes for FBC on pre-965 */
5152 intel_crtc->pipe = pipe;
5153 intel_crtc->plane = pipe;
5154 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5155 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5156 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5157 }
5158
5159 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5160 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5161 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5162 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5163
5164 intel_crtc->cursor_addr = 0;
5165 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5166 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5167
5168 intel_crtc->busy = false;
5169
5170 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5171 (unsigned long)intel_crtc);
5172 }
5173
5174 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5175 struct drm_file *file_priv)
5176 {
5177 drm_i915_private_t *dev_priv = dev->dev_private;
5178 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5179 struct drm_mode_object *drmmode_obj;
5180 struct intel_crtc *crtc;
5181
5182 if (!dev_priv) {
5183 DRM_ERROR("called with no initialization\n");
5184 return -EINVAL;
5185 }
5186
5187 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5188 DRM_MODE_OBJECT_CRTC);
5189
5190 if (!drmmode_obj) {
5191 DRM_ERROR("no such CRTC id\n");
5192 return -EINVAL;
5193 }
5194
5195 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5196 pipe_from_crtc_id->pipe = crtc->pipe;
5197
5198 return 0;
5199 }
5200
5201 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5202 {
5203 struct drm_crtc *crtc = NULL;
5204
5205 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5207 if (intel_crtc->pipe == pipe)
5208 break;
5209 }
5210 return crtc;
5211 }
5212
5213 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5214 {
5215 int index_mask = 0;
5216 struct drm_encoder *encoder;
5217 int entry = 0;
5218
5219 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5220 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5221 if (type_mask & intel_encoder->clone_mask)
5222 index_mask |= (1 << entry);
5223 entry++;
5224 }
5225 return index_mask;
5226 }
5227
5228
5229 static void intel_setup_outputs(struct drm_device *dev)
5230 {
5231 struct drm_i915_private *dev_priv = dev->dev_private;
5232 struct drm_encoder *encoder;
5233 bool dpd_is_edp = false;
5234
5235 if (IS_MOBILE(dev) && !IS_I830(dev))
5236 intel_lvds_init(dev);
5237
5238 if (HAS_PCH_SPLIT(dev)) {
5239 dpd_is_edp = intel_dpd_is_edp(dev);
5240
5241 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5242 intel_dp_init(dev, DP_A);
5243
5244 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5245 intel_dp_init(dev, PCH_DP_D);
5246 }
5247
5248 intel_crt_init(dev);
5249
5250 if (HAS_PCH_SPLIT(dev)) {
5251 int found;
5252
5253 if (I915_READ(HDMIB) & PORT_DETECTED) {
5254 /* PCH SDVOB multiplex with HDMIB */
5255 found = intel_sdvo_init(dev, PCH_SDVOB);
5256 if (!found)
5257 intel_hdmi_init(dev, HDMIB);
5258 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5259 intel_dp_init(dev, PCH_DP_B);
5260 }
5261
5262 if (I915_READ(HDMIC) & PORT_DETECTED)
5263 intel_hdmi_init(dev, HDMIC);
5264
5265 if (I915_READ(HDMID) & PORT_DETECTED)
5266 intel_hdmi_init(dev, HDMID);
5267
5268 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5269 intel_dp_init(dev, PCH_DP_C);
5270
5271 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5272 intel_dp_init(dev, PCH_DP_D);
5273
5274 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5275 bool found = false;
5276
5277 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5278 DRM_DEBUG_KMS("probing SDVOB\n");
5279 found = intel_sdvo_init(dev, SDVOB);
5280 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5281 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5282 intel_hdmi_init(dev, SDVOB);
5283 }
5284
5285 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5286 DRM_DEBUG_KMS("probing DP_B\n");
5287 intel_dp_init(dev, DP_B);
5288 }
5289 }
5290
5291 /* Before G4X SDVOC doesn't have its own detect register */
5292
5293 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5294 DRM_DEBUG_KMS("probing SDVOC\n");
5295 found = intel_sdvo_init(dev, SDVOC);
5296 }
5297
5298 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5299
5300 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5301 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5302 intel_hdmi_init(dev, SDVOC);
5303 }
5304 if (SUPPORTS_INTEGRATED_DP(dev)) {
5305 DRM_DEBUG_KMS("probing DP_C\n");
5306 intel_dp_init(dev, DP_C);
5307 }
5308 }
5309
5310 if (SUPPORTS_INTEGRATED_DP(dev) &&
5311 (I915_READ(DP_D) & DP_DETECTED)) {
5312 DRM_DEBUG_KMS("probing DP_D\n");
5313 intel_dp_init(dev, DP_D);
5314 }
5315 } else if (IS_GEN2(dev))
5316 intel_dvo_init(dev);
5317
5318 if (SUPPORTS_TV(dev))
5319 intel_tv_init(dev);
5320
5321 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5322 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5323
5324 encoder->possible_crtcs = intel_encoder->crtc_mask;
5325 encoder->possible_clones = intel_encoder_clones(dev,
5326 intel_encoder->clone_mask);
5327 }
5328 }
5329
5330 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5331 {
5332 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5333
5334 drm_framebuffer_cleanup(fb);
5335 drm_gem_object_unreference_unlocked(intel_fb->obj);
5336
5337 kfree(intel_fb);
5338 }
5339
5340 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5341 struct drm_file *file_priv,
5342 unsigned int *handle)
5343 {
5344 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5345 struct drm_gem_object *object = intel_fb->obj;
5346
5347 return drm_gem_handle_create(file_priv, object, handle);
5348 }
5349
5350 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5351 .destroy = intel_user_framebuffer_destroy,
5352 .create_handle = intel_user_framebuffer_create_handle,
5353 };
5354
5355 int intel_framebuffer_init(struct drm_device *dev,
5356 struct intel_framebuffer *intel_fb,
5357 struct drm_mode_fb_cmd *mode_cmd,
5358 struct drm_gem_object *obj)
5359 {
5360 int ret;
5361
5362 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5363 if (ret) {
5364 DRM_ERROR("framebuffer init failed %d\n", ret);
5365 return ret;
5366 }
5367
5368 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5369 intel_fb->obj = obj;
5370 return 0;
5371 }
5372
5373 static struct drm_framebuffer *
5374 intel_user_framebuffer_create(struct drm_device *dev,
5375 struct drm_file *filp,
5376 struct drm_mode_fb_cmd *mode_cmd)
5377 {
5378 struct drm_gem_object *obj;
5379 struct intel_framebuffer *intel_fb;
5380 int ret;
5381
5382 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5383 if (!obj)
5384 return NULL;
5385
5386 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5387 if (!intel_fb)
5388 return NULL;
5389
5390 ret = intel_framebuffer_init(dev, intel_fb,
5391 mode_cmd, obj);
5392 if (ret) {
5393 drm_gem_object_unreference_unlocked(obj);
5394 kfree(intel_fb);
5395 return NULL;
5396 }
5397
5398 return &intel_fb->base;
5399 }
5400
5401 static const struct drm_mode_config_funcs intel_mode_funcs = {
5402 .fb_create = intel_user_framebuffer_create,
5403 .output_poll_changed = intel_fb_output_poll_changed,
5404 };
5405
5406 static struct drm_gem_object *
5407 intel_alloc_context_page(struct drm_device *dev)
5408 {
5409 struct drm_gem_object *ctx;
5410 int ret;
5411
5412 ctx = i915_gem_alloc_object(dev, 4096);
5413 if (!ctx) {
5414 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5415 return NULL;
5416 }
5417
5418 mutex_lock(&dev->struct_mutex);
5419 ret = i915_gem_object_pin(ctx, 4096);
5420 if (ret) {
5421 DRM_ERROR("failed to pin power context: %d\n", ret);
5422 goto err_unref;
5423 }
5424
5425 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5426 if (ret) {
5427 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5428 goto err_unpin;
5429 }
5430 mutex_unlock(&dev->struct_mutex);
5431
5432 return ctx;
5433
5434 err_unpin:
5435 i915_gem_object_unpin(ctx);
5436 err_unref:
5437 drm_gem_object_unreference(ctx);
5438 mutex_unlock(&dev->struct_mutex);
5439 return NULL;
5440 }
5441
5442 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5443 {
5444 struct drm_i915_private *dev_priv = dev->dev_private;
5445 u16 rgvswctl;
5446
5447 rgvswctl = I915_READ16(MEMSWCTL);
5448 if (rgvswctl & MEMCTL_CMD_STS) {
5449 DRM_DEBUG("gpu busy, RCS change rejected\n");
5450 return false; /* still busy with another command */
5451 }
5452
5453 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5454 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5455 I915_WRITE16(MEMSWCTL, rgvswctl);
5456 POSTING_READ16(MEMSWCTL);
5457
5458 rgvswctl |= MEMCTL_CMD_STS;
5459 I915_WRITE16(MEMSWCTL, rgvswctl);
5460
5461 return true;
5462 }
5463
5464 void ironlake_enable_drps(struct drm_device *dev)
5465 {
5466 struct drm_i915_private *dev_priv = dev->dev_private;
5467 u32 rgvmodectl = I915_READ(MEMMODECTL);
5468 u8 fmax, fmin, fstart, vstart;
5469
5470 /* 100ms RC evaluation intervals */
5471 I915_WRITE(RCUPEI, 100000);
5472 I915_WRITE(RCDNEI, 100000);
5473
5474 /* Set max/min thresholds to 90ms and 80ms respectively */
5475 I915_WRITE(RCBMAXAVG, 90000);
5476 I915_WRITE(RCBMINAVG, 80000);
5477
5478 I915_WRITE(MEMIHYST, 1);
5479
5480 /* Set up min, max, and cur for interrupt handling */
5481 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5482 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5483 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5484 MEMMODE_FSTART_SHIFT;
5485 fstart = fmax;
5486
5487 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5488 PXVFREQ_PX_SHIFT;
5489
5490 dev_priv->fmax = fstart; /* IPS callback will increase this */
5491 dev_priv->fstart = fstart;
5492
5493 dev_priv->max_delay = fmax;
5494 dev_priv->min_delay = fmin;
5495 dev_priv->cur_delay = fstart;
5496
5497 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5498 fstart);
5499
5500 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5501
5502 /*
5503 * Interrupts will be enabled in ironlake_irq_postinstall
5504 */
5505
5506 I915_WRITE(VIDSTART, vstart);
5507 POSTING_READ(VIDSTART);
5508
5509 rgvmodectl |= MEMMODE_SWMODE_EN;
5510 I915_WRITE(MEMMODECTL, rgvmodectl);
5511
5512 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0))
5513 DRM_ERROR("stuck trying to change perf mode\n");
5514 msleep(1);
5515
5516 ironlake_set_drps(dev, fstart);
5517
5518 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5519 I915_READ(0x112e0);
5520 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5521 dev_priv->last_count2 = I915_READ(0x112f4);
5522 getrawmonotonic(&dev_priv->last_time2);
5523 }
5524
5525 void ironlake_disable_drps(struct drm_device *dev)
5526 {
5527 struct drm_i915_private *dev_priv = dev->dev_private;
5528 u16 rgvswctl = I915_READ16(MEMSWCTL);
5529
5530 /* Ack interrupts, disable EFC interrupt */
5531 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5532 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5533 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5534 I915_WRITE(DEIIR, DE_PCU_EVENT);
5535 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5536
5537 /* Go back to the starting frequency */
5538 ironlake_set_drps(dev, dev_priv->fstart);
5539 msleep(1);
5540 rgvswctl |= MEMCTL_CMD_STS;
5541 I915_WRITE(MEMSWCTL, rgvswctl);
5542 msleep(1);
5543
5544 }
5545
5546 static unsigned long intel_pxfreq(u32 vidfreq)
5547 {
5548 unsigned long freq;
5549 int div = (vidfreq & 0x3f0000) >> 16;
5550 int post = (vidfreq & 0x3000) >> 12;
5551 int pre = (vidfreq & 0x7);
5552
5553 if (!pre)
5554 return 0;
5555
5556 freq = ((div * 133333) / ((1<<post) * pre));
5557
5558 return freq;
5559 }
5560
5561 void intel_init_emon(struct drm_device *dev)
5562 {
5563 struct drm_i915_private *dev_priv = dev->dev_private;
5564 u32 lcfuse;
5565 u8 pxw[16];
5566 int i;
5567
5568 /* Disable to program */
5569 I915_WRITE(ECR, 0);
5570 POSTING_READ(ECR);
5571
5572 /* Program energy weights for various events */
5573 I915_WRITE(SDEW, 0x15040d00);
5574 I915_WRITE(CSIEW0, 0x007f0000);
5575 I915_WRITE(CSIEW1, 0x1e220004);
5576 I915_WRITE(CSIEW2, 0x04000004);
5577
5578 for (i = 0; i < 5; i++)
5579 I915_WRITE(PEW + (i * 4), 0);
5580 for (i = 0; i < 3; i++)
5581 I915_WRITE(DEW + (i * 4), 0);
5582
5583 /* Program P-state weights to account for frequency power adjustment */
5584 for (i = 0; i < 16; i++) {
5585 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5586 unsigned long freq = intel_pxfreq(pxvidfreq);
5587 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5588 PXVFREQ_PX_SHIFT;
5589 unsigned long val;
5590
5591 val = vid * vid;
5592 val *= (freq / 1000);
5593 val *= 255;
5594 val /= (127*127*900);
5595 if (val > 0xff)
5596 DRM_ERROR("bad pxval: %ld\n", val);
5597 pxw[i] = val;
5598 }
5599 /* Render standby states get 0 weight */
5600 pxw[14] = 0;
5601 pxw[15] = 0;
5602
5603 for (i = 0; i < 4; i++) {
5604 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5605 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5606 I915_WRITE(PXW + (i * 4), val);
5607 }
5608
5609 /* Adjust magic regs to magic values (more experimental results) */
5610 I915_WRITE(OGW0, 0);
5611 I915_WRITE(OGW1, 0);
5612 I915_WRITE(EG0, 0x00007f00);
5613 I915_WRITE(EG1, 0x0000000e);
5614 I915_WRITE(EG2, 0x000e0000);
5615 I915_WRITE(EG3, 0x68000300);
5616 I915_WRITE(EG4, 0x42000000);
5617 I915_WRITE(EG5, 0x00140031);
5618 I915_WRITE(EG6, 0);
5619 I915_WRITE(EG7, 0);
5620
5621 for (i = 0; i < 8; i++)
5622 I915_WRITE(PXWL + (i * 4), 0);
5623
5624 /* Enable PMON + select events */
5625 I915_WRITE(ECR, 0x80000019);
5626
5627 lcfuse = I915_READ(LCFUSE02);
5628
5629 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5630 }
5631
5632 void intel_init_clock_gating(struct drm_device *dev)
5633 {
5634 struct drm_i915_private *dev_priv = dev->dev_private;
5635
5636 /*
5637 * Disable clock gating reported to work incorrectly according to the
5638 * specs, but enable as much else as we can.
5639 */
5640 if (HAS_PCH_SPLIT(dev)) {
5641 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5642
5643 if (IS_IRONLAKE(dev)) {
5644 /* Required for FBC */
5645 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5646 /* Required for CxSR */
5647 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5648
5649 I915_WRITE(PCH_3DCGDIS0,
5650 MARIUNIT_CLOCK_GATE_DISABLE |
5651 SVSMUNIT_CLOCK_GATE_DISABLE);
5652 }
5653
5654 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5655
5656 /*
5657 * According to the spec the following bits should be set in
5658 * order to enable memory self-refresh
5659 * The bit 22/21 of 0x42004
5660 * The bit 5 of 0x42020
5661 * The bit 15 of 0x45000
5662 */
5663 if (IS_IRONLAKE(dev)) {
5664 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5665 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5666 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5667 I915_WRITE(ILK_DSPCLK_GATE,
5668 (I915_READ(ILK_DSPCLK_GATE) |
5669 ILK_DPARB_CLK_GATE));
5670 I915_WRITE(DISP_ARB_CTL,
5671 (I915_READ(DISP_ARB_CTL) |
5672 DISP_FBC_WM_DIS));
5673 }
5674 /*
5675 * Based on the document from hardware guys the following bits
5676 * should be set unconditionally in order to enable FBC.
5677 * The bit 22 of 0x42000
5678 * The bit 22 of 0x42004
5679 * The bit 7,8,9 of 0x42020.
5680 */
5681 if (IS_IRONLAKE_M(dev)) {
5682 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5683 I915_READ(ILK_DISPLAY_CHICKEN1) |
5684 ILK_FBCQ_DIS);
5685 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5686 I915_READ(ILK_DISPLAY_CHICKEN2) |
5687 ILK_DPARB_GATE);
5688 I915_WRITE(ILK_DSPCLK_GATE,
5689 I915_READ(ILK_DSPCLK_GATE) |
5690 ILK_DPFC_DIS1 |
5691 ILK_DPFC_DIS2 |
5692 ILK_CLK_FBC);
5693 }
5694 if (IS_GEN6(dev))
5695 return;
5696 } else if (IS_G4X(dev)) {
5697 uint32_t dspclk_gate;
5698 I915_WRITE(RENCLK_GATE_D1, 0);
5699 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5700 GS_UNIT_CLOCK_GATE_DISABLE |
5701 CL_UNIT_CLOCK_GATE_DISABLE);
5702 I915_WRITE(RAMCLK_GATE_D, 0);
5703 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5704 OVRUNIT_CLOCK_GATE_DISABLE |
5705 OVCUNIT_CLOCK_GATE_DISABLE;
5706 if (IS_GM45(dev))
5707 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5708 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5709 } else if (IS_I965GM(dev)) {
5710 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5711 I915_WRITE(RENCLK_GATE_D2, 0);
5712 I915_WRITE(DSPCLK_GATE_D, 0);
5713 I915_WRITE(RAMCLK_GATE_D, 0);
5714 I915_WRITE16(DEUC, 0);
5715 } else if (IS_I965G(dev)) {
5716 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5717 I965_RCC_CLOCK_GATE_DISABLE |
5718 I965_RCPB_CLOCK_GATE_DISABLE |
5719 I965_ISC_CLOCK_GATE_DISABLE |
5720 I965_FBC_CLOCK_GATE_DISABLE);
5721 I915_WRITE(RENCLK_GATE_D2, 0);
5722 } else if (IS_I9XX(dev)) {
5723 u32 dstate = I915_READ(D_STATE);
5724
5725 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5726 DSTATE_DOT_CLOCK_GATING;
5727 I915_WRITE(D_STATE, dstate);
5728 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5729 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5730 } else if (IS_I830(dev)) {
5731 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5732 }
5733
5734 /*
5735 * GPU can automatically power down the render unit if given a page
5736 * to save state.
5737 */
5738 if (IS_IRONLAKE_M(dev)) {
5739 if (dev_priv->renderctx == NULL)
5740 dev_priv->renderctx = intel_alloc_context_page(dev);
5741 if (dev_priv->renderctx) {
5742 struct drm_i915_gem_object *obj_priv;
5743 obj_priv = to_intel_bo(dev_priv->renderctx);
5744 if (obj_priv) {
5745 BEGIN_LP_RING(4);
5746 OUT_RING(MI_SET_CONTEXT);
5747 OUT_RING(obj_priv->gtt_offset |
5748 MI_MM_SPACE_GTT |
5749 MI_SAVE_EXT_STATE_EN |
5750 MI_RESTORE_EXT_STATE_EN |
5751 MI_RESTORE_INHIBIT);
5752 OUT_RING(MI_NOOP);
5753 OUT_RING(MI_FLUSH);
5754 ADVANCE_LP_RING();
5755 }
5756 } else {
5757 DRM_DEBUG_KMS("Failed to allocate render context."
5758 "Disable RC6\n");
5759 return;
5760 }
5761 }
5762
5763 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5764 struct drm_i915_gem_object *obj_priv = NULL;
5765
5766 if (dev_priv->pwrctx) {
5767 obj_priv = to_intel_bo(dev_priv->pwrctx);
5768 } else {
5769 struct drm_gem_object *pwrctx;
5770
5771 pwrctx = intel_alloc_context_page(dev);
5772 if (pwrctx) {
5773 dev_priv->pwrctx = pwrctx;
5774 obj_priv = to_intel_bo(pwrctx);
5775 }
5776 }
5777
5778 if (obj_priv) {
5779 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5780 I915_WRITE(MCHBAR_RENDER_STANDBY,
5781 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5782 }
5783 }
5784 }
5785
5786 /* Set up chip specific display functions */
5787 static void intel_init_display(struct drm_device *dev)
5788 {
5789 struct drm_i915_private *dev_priv = dev->dev_private;
5790
5791 /* We always want a DPMS function */
5792 if (HAS_PCH_SPLIT(dev))
5793 dev_priv->display.dpms = ironlake_crtc_dpms;
5794 else
5795 dev_priv->display.dpms = i9xx_crtc_dpms;
5796
5797 if (I915_HAS_FBC(dev)) {
5798 if (IS_IRONLAKE_M(dev)) {
5799 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5800 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5801 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5802 } else if (IS_GM45(dev)) {
5803 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5804 dev_priv->display.enable_fbc = g4x_enable_fbc;
5805 dev_priv->display.disable_fbc = g4x_disable_fbc;
5806 } else if (IS_I965GM(dev)) {
5807 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5808 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5809 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5810 }
5811 /* 855GM needs testing */
5812 }
5813
5814 /* Returns the core display clock speed */
5815 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5816 dev_priv->display.get_display_clock_speed =
5817 i945_get_display_clock_speed;
5818 else if (IS_I915G(dev))
5819 dev_priv->display.get_display_clock_speed =
5820 i915_get_display_clock_speed;
5821 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5822 dev_priv->display.get_display_clock_speed =
5823 i9xx_misc_get_display_clock_speed;
5824 else if (IS_I915GM(dev))
5825 dev_priv->display.get_display_clock_speed =
5826 i915gm_get_display_clock_speed;
5827 else if (IS_I865G(dev))
5828 dev_priv->display.get_display_clock_speed =
5829 i865_get_display_clock_speed;
5830 else if (IS_I85X(dev))
5831 dev_priv->display.get_display_clock_speed =
5832 i855_get_display_clock_speed;
5833 else /* 852, 830 */
5834 dev_priv->display.get_display_clock_speed =
5835 i830_get_display_clock_speed;
5836
5837 /* For FIFO watermark updates */
5838 if (HAS_PCH_SPLIT(dev)) {
5839 if (IS_IRONLAKE(dev)) {
5840 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5841 dev_priv->display.update_wm = ironlake_update_wm;
5842 else {
5843 DRM_DEBUG_KMS("Failed to get proper latency. "
5844 "Disable CxSR\n");
5845 dev_priv->display.update_wm = NULL;
5846 }
5847 } else
5848 dev_priv->display.update_wm = NULL;
5849 } else if (IS_PINEVIEW(dev)) {
5850 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5851 dev_priv->is_ddr3,
5852 dev_priv->fsb_freq,
5853 dev_priv->mem_freq)) {
5854 DRM_INFO("failed to find known CxSR latency "
5855 "(found ddr%s fsb freq %d, mem freq %d), "
5856 "disabling CxSR\n",
5857 (dev_priv->is_ddr3 == 1) ? "3": "2",
5858 dev_priv->fsb_freq, dev_priv->mem_freq);
5859 /* Disable CxSR and never update its watermark again */
5860 pineview_disable_cxsr(dev);
5861 dev_priv->display.update_wm = NULL;
5862 } else
5863 dev_priv->display.update_wm = pineview_update_wm;
5864 } else if (IS_G4X(dev))
5865 dev_priv->display.update_wm = g4x_update_wm;
5866 else if (IS_I965G(dev))
5867 dev_priv->display.update_wm = i965_update_wm;
5868 else if (IS_I9XX(dev)) {
5869 dev_priv->display.update_wm = i9xx_update_wm;
5870 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5871 } else if (IS_I85X(dev)) {
5872 dev_priv->display.update_wm = i9xx_update_wm;
5873 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5874 } else {
5875 dev_priv->display.update_wm = i830_update_wm;
5876 if (IS_845G(dev))
5877 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5878 else
5879 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5880 }
5881 }
5882
5883 /*
5884 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5885 * resume, or other times. This quirk makes sure that's the case for
5886 * affected systems.
5887 */
5888 static void quirk_pipea_force (struct drm_device *dev)
5889 {
5890 struct drm_i915_private *dev_priv = dev->dev_private;
5891
5892 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5893 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5894 }
5895
5896 struct intel_quirk {
5897 int device;
5898 int subsystem_vendor;
5899 int subsystem_device;
5900 void (*hook)(struct drm_device *dev);
5901 };
5902
5903 struct intel_quirk intel_quirks[] = {
5904 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5905 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5906 /* HP Mini needs pipe A force quirk (LP: #322104) */
5907 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5908
5909 /* Thinkpad R31 needs pipe A force quirk */
5910 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5911 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5912 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5913
5914 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5915 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
5916 /* ThinkPad X40 needs pipe A force quirk */
5917
5918 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5919 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5920
5921 /* 855 & before need to leave pipe A & dpll A up */
5922 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5923 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5924 };
5925
5926 static void intel_init_quirks(struct drm_device *dev)
5927 {
5928 struct pci_dev *d = dev->pdev;
5929 int i;
5930
5931 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5932 struct intel_quirk *q = &intel_quirks[i];
5933
5934 if (d->device == q->device &&
5935 (d->subsystem_vendor == q->subsystem_vendor ||
5936 q->subsystem_vendor == PCI_ANY_ID) &&
5937 (d->subsystem_device == q->subsystem_device ||
5938 q->subsystem_device == PCI_ANY_ID))
5939 q->hook(dev);
5940 }
5941 }
5942
5943 /* Disable the VGA plane that we never use */
5944 static void i915_disable_vga(struct drm_device *dev)
5945 {
5946 struct drm_i915_private *dev_priv = dev->dev_private;
5947 u8 sr1;
5948 u32 vga_reg;
5949
5950 if (HAS_PCH_SPLIT(dev))
5951 vga_reg = CPU_VGACNTRL;
5952 else
5953 vga_reg = VGACNTRL;
5954
5955 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5956 outb(1, VGA_SR_INDEX);
5957 sr1 = inb(VGA_SR_DATA);
5958 outb(sr1 | 1<<5, VGA_SR_DATA);
5959 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5960 udelay(300);
5961
5962 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
5963 POSTING_READ(vga_reg);
5964 }
5965
5966 void intel_modeset_init(struct drm_device *dev)
5967 {
5968 struct drm_i915_private *dev_priv = dev->dev_private;
5969 int i;
5970
5971 drm_mode_config_init(dev);
5972
5973 dev->mode_config.min_width = 0;
5974 dev->mode_config.min_height = 0;
5975
5976 dev->mode_config.funcs = (void *)&intel_mode_funcs;
5977
5978 intel_init_quirks(dev);
5979
5980 intel_init_display(dev);
5981
5982 if (IS_I965G(dev)) {
5983 dev->mode_config.max_width = 8192;
5984 dev->mode_config.max_height = 8192;
5985 } else if (IS_I9XX(dev)) {
5986 dev->mode_config.max_width = 4096;
5987 dev->mode_config.max_height = 4096;
5988 } else {
5989 dev->mode_config.max_width = 2048;
5990 dev->mode_config.max_height = 2048;
5991 }
5992
5993 /* set memory base */
5994 if (IS_I9XX(dev))
5995 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5996 else
5997 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5998
5999 if (IS_MOBILE(dev) || IS_I9XX(dev))
6000 dev_priv->num_pipe = 2;
6001 else
6002 dev_priv->num_pipe = 1;
6003 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6004 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6005
6006 for (i = 0; i < dev_priv->num_pipe; i++) {
6007 intel_crtc_init(dev, i);
6008 }
6009
6010 intel_setup_outputs(dev);
6011
6012 intel_init_clock_gating(dev);
6013
6014 /* Just disable it once at startup */
6015 i915_disable_vga(dev);
6016
6017 if (IS_IRONLAKE_M(dev)) {
6018 ironlake_enable_drps(dev);
6019 intel_init_emon(dev);
6020 }
6021
6022 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6023 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6024 (unsigned long)dev);
6025
6026 intel_setup_overlay(dev);
6027 }
6028
6029 void intel_modeset_cleanup(struct drm_device *dev)
6030 {
6031 struct drm_i915_private *dev_priv = dev->dev_private;
6032 struct drm_crtc *crtc;
6033 struct intel_crtc *intel_crtc;
6034
6035 mutex_lock(&dev->struct_mutex);
6036
6037 drm_kms_helper_poll_fini(dev);
6038 intel_fbdev_fini(dev);
6039
6040 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6041 /* Skip inactive CRTCs */
6042 if (!crtc->fb)
6043 continue;
6044
6045 intel_crtc = to_intel_crtc(crtc);
6046 intel_increase_pllclock(crtc, false);
6047 del_timer_sync(&intel_crtc->idle_timer);
6048 }
6049
6050 del_timer_sync(&dev_priv->idle_timer);
6051
6052 if (dev_priv->display.disable_fbc)
6053 dev_priv->display.disable_fbc(dev);
6054
6055 if (dev_priv->renderctx) {
6056 struct drm_i915_gem_object *obj_priv;
6057
6058 obj_priv = to_intel_bo(dev_priv->renderctx);
6059 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6060 I915_READ(CCID);
6061 i915_gem_object_unpin(dev_priv->renderctx);
6062 drm_gem_object_unreference(dev_priv->renderctx);
6063 }
6064
6065 if (dev_priv->pwrctx) {
6066 struct drm_i915_gem_object *obj_priv;
6067
6068 obj_priv = to_intel_bo(dev_priv->pwrctx);
6069 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6070 I915_READ(PWRCTXA);
6071 i915_gem_object_unpin(dev_priv->pwrctx);
6072 drm_gem_object_unreference(dev_priv->pwrctx);
6073 }
6074
6075 if (IS_IRONLAKE_M(dev))
6076 ironlake_disable_drps(dev);
6077
6078 mutex_unlock(&dev->struct_mutex);
6079
6080 drm_mode_config_cleanup(dev);
6081 }
6082
6083
6084 /*
6085 * Return which encoder is currently attached for connector.
6086 */
6087 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6088 {
6089 struct drm_mode_object *obj;
6090 struct drm_encoder *encoder;
6091 int i;
6092
6093 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6094 if (connector->encoder_ids[i] == 0)
6095 break;
6096
6097 obj = drm_mode_object_find(connector->dev,
6098 connector->encoder_ids[i],
6099 DRM_MODE_OBJECT_ENCODER);
6100 if (!obj)
6101 continue;
6102
6103 encoder = obj_to_encoder(obj);
6104 return encoder;
6105 }
6106 return NULL;
6107 }
6108
6109 /*
6110 * set vga decode state - true == enable VGA decode
6111 */
6112 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6113 {
6114 struct drm_i915_private *dev_priv = dev->dev_private;
6115 u16 gmch_ctrl;
6116
6117 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6118 if (state)
6119 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6120 else
6121 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6122 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6123 return 0;
6124 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree