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davinci: add mdio platform devices
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-davinci / devices-da8xx.c
blob9039221649d4d9587cf27c465e0b8786cc2d90a7
1 /*
2 * DA8XX/OMAP L1XX platform device data
3 *
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/serial_8250.h>
17
18 #include <mach/cputype.h>
19 #include <mach/common.h>
20 #include <mach/time.h>
21 #include <mach/da8xx.h>
22 #include <mach/cpuidle.h>
23
24 #include "clock.h"
25
26 #define DA8XX_TPCC_BASE 0x01c00000
27 #define DA850_MMCSD1_BASE 0x01e1b000
28 #define DA850_TPCC1_BASE 0x01e30000
29 #define DA8XX_TPTC0_BASE 0x01c08000
30 #define DA8XX_TPTC1_BASE 0x01c08400
31 #define DA850_TPTC2_BASE 0x01e38000
32 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
33 #define DA8XX_I2C0_BASE 0x01c22000
34 #define DA8XX_RTC_BASE 0x01C23000
35 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
36 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
37 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
38 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
39 #define DA8XX_GPIO_BASE 0x01e26000
40 #define DA8XX_I2C1_BASE 0x01e28000
41
42 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
43 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
44 #define DA8XX_EMAC_RAM_OFFSET 0x0000
45 #define DA8XX_MDIO_REG_OFFSET 0x4000
46 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
47
48 void __iomem *da8xx_syscfg0_base;
49 void __iomem *da8xx_syscfg1_base;
50
51 static struct plat_serial8250_port da8xx_serial_pdata[] = {
52 {
53 .mapbase = DA8XX_UART0_BASE,
54 .irq = IRQ_DA8XX_UARTINT0,
55 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
56 UPF_IOREMAP,
57 .iotype = UPIO_MEM,
58 .regshift = 2,
59 },
60 {
61 .mapbase = DA8XX_UART1_BASE,
62 .irq = IRQ_DA8XX_UARTINT1,
63 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
64 UPF_IOREMAP,
65 .iotype = UPIO_MEM,
66 .regshift = 2,
67 },
68 {
69 .mapbase = DA8XX_UART2_BASE,
70 .irq = IRQ_DA8XX_UARTINT2,
71 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
72 UPF_IOREMAP,
73 .iotype = UPIO_MEM,
74 .regshift = 2,
75 },
76 {
77 .flags = 0,
78 },
79 };
80
81 struct platform_device da8xx_serial_device = {
82 .name = "serial8250",
83 .id = PLAT8250_DEV_PLATFORM,
84 .dev = {
85 .platform_data = da8xx_serial_pdata,
86 },
87 };
88
89 static const s8 da8xx_queue_tc_mapping[][2] = {
90 /* {event queue no, TC no} */
91 {0, 0},
92 {1, 1},
93 {-1, -1}
94 };
95
96 static const s8 da8xx_queue_priority_mapping[][2] = {
97 /* {event queue no, Priority} */
98 {0, 3},
99 {1, 7},
100 {-1, -1}
101 };
102
103 static const s8 da850_queue_tc_mapping[][2] = {
104 /* {event queue no, TC no} */
105 {0, 0},
106 {-1, -1}
107 };
108
109 static const s8 da850_queue_priority_mapping[][2] = {
110 /* {event queue no, Priority} */
111 {0, 3},
112 {-1, -1}
113 };
114
115 static struct edma_soc_info da830_edma_cc0_info = {
116 .n_channel = 32,
117 .n_region = 4,
118 .n_slot = 128,
119 .n_tc = 2,
120 .n_cc = 1,
121 .queue_tc_mapping = da8xx_queue_tc_mapping,
122 .queue_priority_mapping = da8xx_queue_priority_mapping,
123 };
124
125 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
126 &da830_edma_cc0_info,
127 };
128
129 static struct edma_soc_info da850_edma_cc_info[] = {
130 {
131 .n_channel = 32,
132 .n_region = 4,
133 .n_slot = 128,
134 .n_tc = 2,
135 .n_cc = 1,
136 .queue_tc_mapping = da8xx_queue_tc_mapping,
137 .queue_priority_mapping = da8xx_queue_priority_mapping,
138 },
139 {
140 .n_channel = 32,
141 .n_region = 4,
142 .n_slot = 128,
143 .n_tc = 1,
144 .n_cc = 1,
145 .queue_tc_mapping = da850_queue_tc_mapping,
146 .queue_priority_mapping = da850_queue_priority_mapping,
147 },
148 };
149
150 static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
151 &da850_edma_cc_info[0],
152 &da850_edma_cc_info[1],
153 };
154
155 static struct resource da830_edma_resources[] = {
156 {
157 .name = "edma_cc0",
158 .start = DA8XX_TPCC_BASE,
159 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
160 .flags = IORESOURCE_MEM,
161 },
162 {
163 .name = "edma_tc0",
164 .start = DA8XX_TPTC0_BASE,
165 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
166 .flags = IORESOURCE_MEM,
167 },
168 {
169 .name = "edma_tc1",
170 .start = DA8XX_TPTC1_BASE,
171 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
172 .flags = IORESOURCE_MEM,
173 },
174 {
175 .name = "edma0",
176 .start = IRQ_DA8XX_CCINT0,
177 .flags = IORESOURCE_IRQ,
178 },
179 {
180 .name = "edma0_err",
181 .start = IRQ_DA8XX_CCERRINT,
182 .flags = IORESOURCE_IRQ,
183 },
184 };
185
186 static struct resource da850_edma_resources[] = {
187 {
188 .name = "edma_cc0",
189 .start = DA8XX_TPCC_BASE,
190 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
191 .flags = IORESOURCE_MEM,
192 },
193 {
194 .name = "edma_tc0",
195 .start = DA8XX_TPTC0_BASE,
196 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
197 .flags = IORESOURCE_MEM,
198 },
199 {
200 .name = "edma_tc1",
201 .start = DA8XX_TPTC1_BASE,
202 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
203 .flags = IORESOURCE_MEM,
204 },
205 {
206 .name = "edma_cc1",
207 .start = DA850_TPCC1_BASE,
208 .end = DA850_TPCC1_BASE + SZ_32K - 1,
209 .flags = IORESOURCE_MEM,
210 },
211 {
212 .name = "edma_tc2",
213 .start = DA850_TPTC2_BASE,
214 .end = DA850_TPTC2_BASE + SZ_1K - 1,
215 .flags = IORESOURCE_MEM,
216 },
217 {
218 .name = "edma0",
219 .start = IRQ_DA8XX_CCINT0,
220 .flags = IORESOURCE_IRQ,
221 },
222 {
223 .name = "edma0_err",
224 .start = IRQ_DA8XX_CCERRINT,
225 .flags = IORESOURCE_IRQ,
226 },
227 {
228 .name = "edma1",
229 .start = IRQ_DA850_CCINT1,
230 .flags = IORESOURCE_IRQ,
231 },
232 {
233 .name = "edma1_err",
234 .start = IRQ_DA850_CCERRINT1,
235 .flags = IORESOURCE_IRQ,
236 },
237 };
238
239 static struct platform_device da830_edma_device = {
240 .name = "edma",
241 .id = -1,
242 .dev = {
243 .platform_data = da830_edma_info,
244 },
245 .num_resources = ARRAY_SIZE(da830_edma_resources),
246 .resource = da830_edma_resources,
247 };
248
249 static struct platform_device da850_edma_device = {
250 .name = "edma",
251 .id = -1,
252 .dev = {
253 .platform_data = da850_edma_info,
254 },
255 .num_resources = ARRAY_SIZE(da850_edma_resources),
256 .resource = da850_edma_resources,
257 };
258
259 int __init da830_register_edma(struct edma_rsv_info *rsv)
260 {
261 da830_edma_cc0_info.rsv = rsv;
262
263 return platform_device_register(&da830_edma_device);
264 }
265
266 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
267 {
268 if (rsv) {
269 da850_edma_cc_info[0].rsv = rsv[0];
270 da850_edma_cc_info[1].rsv = rsv[1];
271 }
272
273 return platform_device_register(&da850_edma_device);
274 }
275
276 static struct resource da8xx_i2c_resources0[] = {
277 {
278 .start = DA8XX_I2C0_BASE,
279 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
280 .flags = IORESOURCE_MEM,
281 },
282 {
283 .start = IRQ_DA8XX_I2CINT0,
284 .end = IRQ_DA8XX_I2CINT0,
285 .flags = IORESOURCE_IRQ,
286 },
287 };
288
289 static struct platform_device da8xx_i2c_device0 = {
290 .name = "i2c_davinci",
291 .id = 1,
292 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
293 .resource = da8xx_i2c_resources0,
294 };
295
296 static struct resource da8xx_i2c_resources1[] = {
297 {
298 .start = DA8XX_I2C1_BASE,
299 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
300 .flags = IORESOURCE_MEM,
301 },
302 {
303 .start = IRQ_DA8XX_I2CINT1,
304 .end = IRQ_DA8XX_I2CINT1,
305 .flags = IORESOURCE_IRQ,
306 },
307 };
308
309 static struct platform_device da8xx_i2c_device1 = {
310 .name = "i2c_davinci",
311 .id = 2,
312 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
313 .resource = da8xx_i2c_resources1,
314 };
315
316 int __init da8xx_register_i2c(int instance,
317 struct davinci_i2c_platform_data *pdata)
318 {
319 struct platform_device *pdev;
320
321 if (instance == 0)
322 pdev = &da8xx_i2c_device0;
323 else if (instance == 1)
324 pdev = &da8xx_i2c_device1;
325 else
326 return -EINVAL;
327
328 pdev->dev.platform_data = pdata;
329 return platform_device_register(pdev);
330 }
331
332 static struct resource da8xx_watchdog_resources[] = {
333 {
334 .start = DA8XX_WDOG_BASE,
335 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
336 .flags = IORESOURCE_MEM,
337 },
338 };
339
340 struct platform_device da8xx_wdt_device = {
341 .name = "watchdog",
342 .id = -1,
343 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
344 .resource = da8xx_watchdog_resources,
345 };
346
347 int __init da8xx_register_watchdog(void)
348 {
349 return platform_device_register(&da8xx_wdt_device);
350 }
351
352 static struct resource da8xx_emac_resources[] = {
353 {
354 .start = DA8XX_EMAC_CPPI_PORT_BASE,
355 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
356 .flags = IORESOURCE_MEM,
357 },
358 {
359 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
360 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
361 .flags = IORESOURCE_IRQ,
362 },
363 {
364 .start = IRQ_DA8XX_C0_RX_PULSE,
365 .end = IRQ_DA8XX_C0_RX_PULSE,
366 .flags = IORESOURCE_IRQ,
367 },
368 {
369 .start = IRQ_DA8XX_C0_TX_PULSE,
370 .end = IRQ_DA8XX_C0_TX_PULSE,
371 .flags = IORESOURCE_IRQ,
372 },
373 {
374 .start = IRQ_DA8XX_C0_MISC_PULSE,
375 .end = IRQ_DA8XX_C0_MISC_PULSE,
376 .flags = IORESOURCE_IRQ,
377 },
378 };
379
380 struct emac_platform_data da8xx_emac_pdata = {
381 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
382 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
383 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
384 .mdio_reg_offset = DA8XX_MDIO_REG_OFFSET,
385 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
386 .version = EMAC_VERSION_2,
387 };
388
389 static struct platform_device da8xx_emac_device = {
390 .name = "davinci_emac",
391 .id = 1,
392 .dev = {
393 .platform_data = &da8xx_emac_pdata,
394 },
395 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
396 .resource = da8xx_emac_resources,
397 };
398
399 static struct resource da8xx_mdio_resources[] = {
400 {
401 .start = DA8XX_EMAC_MDIO_BASE,
402 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
403 .flags = IORESOURCE_MEM,
404 },
405 };
406
407 static struct platform_device da8xx_mdio_device = {
408 .name = "davinci_mdio",
409 .id = 0,
410 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
411 .resource = da8xx_mdio_resources,
412 };
413
414 int __init da8xx_register_emac(void)
415 {
416 int ret;
417
418 ret = platform_device_register(&da8xx_mdio_device);
419 if (ret < 0)
420 return ret;
421 ret = platform_device_register(&da8xx_emac_device);
422 if (ret < 0)
423 return ret;
424 ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev),
425 NULL, &da8xx_emac_device.dev);
426 return ret;
427 }
428
429 static struct resource da830_mcasp1_resources[] = {
430 {
431 .name = "mcasp1",
432 .start = DAVINCI_DA830_MCASP1_REG_BASE,
433 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
434 .flags = IORESOURCE_MEM,
435 },
436 /* TX event */
437 {
438 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
439 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
440 .flags = IORESOURCE_DMA,
441 },
442 /* RX event */
443 {
444 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
445 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
446 .flags = IORESOURCE_DMA,
447 },
448 };
449
450 static struct platform_device da830_mcasp1_device = {
451 .name = "davinci-mcasp",
452 .id = 1,
453 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
454 .resource = da830_mcasp1_resources,
455 };
456
457 static struct resource da850_mcasp_resources[] = {
458 {
459 .name = "mcasp",
460 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
461 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
462 .flags = IORESOURCE_MEM,
463 },
464 /* TX event */
465 {
466 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
467 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
468 .flags = IORESOURCE_DMA,
469 },
470 /* RX event */
471 {
472 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
473 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
474 .flags = IORESOURCE_DMA,
475 },
476 };
477
478 static struct platform_device da850_mcasp_device = {
479 .name = "davinci-mcasp",
480 .id = 0,
481 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
482 .resource = da850_mcasp_resources,
483 };
484
485 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
486 {
487 /* DA830/OMAP-L137 has 3 instances of McASP */
488 if (cpu_is_davinci_da830() && id == 1) {
489 da830_mcasp1_device.dev.platform_data = pdata;
490 platform_device_register(&da830_mcasp1_device);
491 } else if (cpu_is_davinci_da850()) {
492 da850_mcasp_device.dev.platform_data = pdata;
493 platform_device_register(&da850_mcasp_device);
494 }
495 }
496
497 static const struct display_panel disp_panel = {
498 QVGA,
499 16,
500 16,
501 COLOR_ACTIVE,
502 };
503
504 static struct lcd_ctrl_config lcd_cfg = {
505 &disp_panel,
506 .ac_bias = 255,
507 .ac_bias_intrpt = 0,
508 .dma_burst_sz = 16,
509 .bpp = 16,
510 .fdd = 255,
511 .tft_alt_mode = 0,
512 .stn_565_mode = 0,
513 .mono_8bit_mode = 0,
514 .invert_line_clock = 1,
515 .invert_frm_clock = 1,
516 .sync_edge = 0,
517 .sync_ctrl = 1,
518 .raster_order = 0,
519 };
520
521 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
522 .manu_name = "sharp",
523 .controller_data = &lcd_cfg,
524 .type = "Sharp_LCD035Q3DG01",
525 };
526
527 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
528 .manu_name = "sharp",
529 .controller_data = &lcd_cfg,
530 .type = "Sharp_LK043T1DG01",
531 };
532
533 static struct resource da8xx_lcdc_resources[] = {
534 [0] = { /* registers */
535 .start = DA8XX_LCD_CNTRL_BASE,
536 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
537 .flags = IORESOURCE_MEM,
538 },
539 [1] = { /* interrupt */
540 .start = IRQ_DA8XX_LCDINT,
541 .end = IRQ_DA8XX_LCDINT,
542 .flags = IORESOURCE_IRQ,
543 },
544 };
545
546 static struct platform_device da8xx_lcdc_device = {
547 .name = "da8xx_lcdc",
548 .id = 0,
549 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
550 .resource = da8xx_lcdc_resources,
551 };
552
553 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
554 {
555 da8xx_lcdc_device.dev.platform_data = pdata;
556 return platform_device_register(&da8xx_lcdc_device);
557 }
558
559 static struct resource da8xx_mmcsd0_resources[] = {
560 { /* registers */
561 .start = DA8XX_MMCSD0_BASE,
562 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
563 .flags = IORESOURCE_MEM,
564 },
565 { /* interrupt */
566 .start = IRQ_DA8XX_MMCSDINT0,
567 .end = IRQ_DA8XX_MMCSDINT0,
568 .flags = IORESOURCE_IRQ,
569 },
570 { /* DMA RX */
571 .start = EDMA_CTLR_CHAN(0, 16),
572 .end = EDMA_CTLR_CHAN(0, 16),
573 .flags = IORESOURCE_DMA,
574 },
575 { /* DMA TX */
576 .start = EDMA_CTLR_CHAN(0, 17),
577 .end = EDMA_CTLR_CHAN(0, 17),
578 .flags = IORESOURCE_DMA,
579 },
580 };
581
582 static struct platform_device da8xx_mmcsd0_device = {
583 .name = "davinci_mmc",
584 .id = 0,
585 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
586 .resource = da8xx_mmcsd0_resources,
587 };
588
589 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
590 {
591 da8xx_mmcsd0_device.dev.platform_data = config;
592 return platform_device_register(&da8xx_mmcsd0_device);
593 }
594
595 #ifdef CONFIG_ARCH_DAVINCI_DA850
596 static struct resource da850_mmcsd1_resources[] = {
597 { /* registers */
598 .start = DA850_MMCSD1_BASE,
599 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
600 .flags = IORESOURCE_MEM,
601 },
602 { /* interrupt */
603 .start = IRQ_DA850_MMCSDINT0_1,
604 .end = IRQ_DA850_MMCSDINT0_1,
605 .flags = IORESOURCE_IRQ,
606 },
607 { /* DMA RX */
608 .start = EDMA_CTLR_CHAN(1, 28),
609 .end = EDMA_CTLR_CHAN(1, 28),
610 .flags = IORESOURCE_DMA,
611 },
612 { /* DMA TX */
613 .start = EDMA_CTLR_CHAN(1, 29),
614 .end = EDMA_CTLR_CHAN(1, 29),
615 .flags = IORESOURCE_DMA,
616 },
617 };
618
619 static struct platform_device da850_mmcsd1_device = {
620 .name = "davinci_mmc",
621 .id = 1,
622 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
623 .resource = da850_mmcsd1_resources,
624 };
625
626 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
627 {
628 da850_mmcsd1_device.dev.platform_data = config;
629 return platform_device_register(&da850_mmcsd1_device);
630 }
631 #endif
632
633 static struct resource da8xx_rtc_resources[] = {
634 {
635 .start = DA8XX_RTC_BASE,
636 .end = DA8XX_RTC_BASE + SZ_4K - 1,
637 .flags = IORESOURCE_MEM,
638 },
639 { /* timer irq */
640 .start = IRQ_DA8XX_RTC,
641 .end = IRQ_DA8XX_RTC,
642 .flags = IORESOURCE_IRQ,
643 },
644 { /* alarm irq */
645 .start = IRQ_DA8XX_RTC,
646 .end = IRQ_DA8XX_RTC,
647 .flags = IORESOURCE_IRQ,
648 },
649 };
650
651 static struct platform_device da8xx_rtc_device = {
652 .name = "omap_rtc",
653 .id = -1,
654 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
655 .resource = da8xx_rtc_resources,
656 };
657
658 int da8xx_register_rtc(void)
659 {
660 int ret;
661 void __iomem *base;
662
663 base = ioremap(DA8XX_RTC_BASE, SZ_4K);
664 if (WARN_ON(!base))
665 return -ENOMEM;
666
667 /* Unlock the rtc's registers */
668 __raw_writel(0x83e70b13, base + 0x6c);
669 __raw_writel(0x95a4f1e0, base + 0x70);
670
671 iounmap(base);
672
673 ret = platform_device_register(&da8xx_rtc_device);
674 if (!ret)
675 /* Atleast on DA850, RTC is a wakeup source */
676 device_init_wakeup(&da8xx_rtc_device.dev, true);
677
678 return ret;
679 }
680
681 static void __iomem *da8xx_ddr2_ctlr_base;
682 void __iomem * __init da8xx_get_mem_ctlr(void)
683 {
684 if (da8xx_ddr2_ctlr_base)
685 return da8xx_ddr2_ctlr_base;
686
687 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
688 if (!da8xx_ddr2_ctlr_base)
689 pr_warning("%s: Unable to map DDR2 controller", __func__);
690
691 return da8xx_ddr2_ctlr_base;
692 }
693
694 static struct resource da8xx_cpuidle_resources[] = {
695 {
696 .start = DA8XX_DDR2_CTL_BASE,
697 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
698 .flags = IORESOURCE_MEM,
699 },
700 };
701
702 /* DA8XX devices support DDR2 power down */
703 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
704 .ddr2_pdown = 1,
705 };
706
707
708 static struct platform_device da8xx_cpuidle_device = {
709 .name = "cpuidle-davinci",
710 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
711 .resource = da8xx_cpuidle_resources,
712 .dev = {
713 .platform_data = &da8xx_cpuidle_pdata,
714 },
715 };
716
717 int __init da8xx_register_cpuidle(void)
718 {
719 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
720
721 return platform_device_register(&da8xx_cpuidle_device);
722 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree