[SPARC64]: Add missing IDs for newer cpus.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / sparc64 / kernel / cpu.c
blob77ef5df4e5a7c7bb40b8b5f0ff96036083fd9078
1 /* cpu.c: Dinky routines to look for the kind of Sparc cpu
2 * we are on.
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 */
7 #include <linux/config.h>
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/sched.h>
11 #include <linux/smp.h>
12 #include <asm/asi.h>
13 #include <asm/system.h>
14 #include <asm/fpumacro.h>
15 #include <asm/cpudata.h>
17 DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
19 struct cpu_iu_info {
20 short manuf;
21 short impl;
22 char* cpu_name; /* should be enough I hope... */
25 struct cpu_fp_info {
26 short manuf;
27 short impl;
28 char fpu_vers;
29 char* fp_name;
32 struct cpu_fp_info linux_sparc_fpu[] = {
33 { 0x17, 0x10, 0, "UltraSparc I integrated FPU"},
34 { 0x22, 0x10, 0, "UltraSparc I integrated FPU"},
35 { 0x17, 0x11, 0, "UltraSparc II integrated FPU"},
36 { 0x17, 0x12, 0, "UltraSparc IIi integrated FPU"},
37 { 0x17, 0x13, 0, "UltraSparc IIe integrated FPU"},
38 { 0x3e, 0x14, 0, "UltraSparc III integrated FPU"},
39 { 0x3e, 0x15, 0, "UltraSparc III+ integrated FPU"},
40 { 0x3e, 0x16, 0, "UltraSparc IIIi integrated FPU"},
41 { 0x3e, 0x18, 0, "UltraSparc IV integrated FPU"},
42 { 0x3e, 0x19, 0, "UltraSparc IV+ integrated FPU"},
43 { 0x3e, 0x22, 0, "UltraSparc IIIi+ integrated FPU"},
46 #define NSPARCFPU (sizeof(linux_sparc_fpu)/sizeof(struct cpu_fp_info))
48 struct cpu_iu_info linux_sparc_chips[] = {
49 { 0x17, 0x10, "TI UltraSparc I (SpitFire)"},
50 { 0x22, 0x10, "TI UltraSparc I (SpitFire)"},
51 { 0x17, 0x11, "TI UltraSparc II (BlackBird)"},
52 { 0x17, 0x12, "TI UltraSparc IIi (Sabre)"},
53 { 0x17, 0x13, "TI UltraSparc IIe (Hummingbird)"},
54 { 0x3e, 0x14, "TI UltraSparc III (Cheetah)"},
55 { 0x3e, 0x15, "TI UltraSparc III+ (Cheetah+)"},
56 { 0x3e, 0x16, "TI UltraSparc IIIi (Jalapeno)"},
57 { 0x3e, 0x18, "TI UltraSparc IV (Jaguar)"},
58 { 0x3e, 0x19, "TI UltraSparc IV+ (Panther)"},
59 { 0x3e, 0x22, "TI UltraSparc IIIi+ (Serrano)"},
62 #define NSPARCCHIPS (sizeof(linux_sparc_chips)/sizeof(struct cpu_iu_info))
64 char *sparc_cpu_type = "cpu-oops";
65 char *sparc_fpu_type = "fpu-oops";
67 unsigned int fsr_storage;
69 void __init cpu_probe(void)
71 unsigned long ver, fpu_vers, manuf, impl, fprs;
72 int i;
74 fprs = fprs_read();
75 fprs_write(FPRS_FEF);
76 __asm__ __volatile__ ("rdpr %%ver, %0; stx %%fsr, [%1]"
77 : "=&r" (ver)
78 : "r" (&fpu_vers));
79 fprs_write(fprs);
81 manuf = ((ver >> 48) & 0xffff);
82 impl = ((ver >> 32) & 0xffff);
84 fpu_vers = ((fpu_vers >> 17) & 0x7);
86 retry:
87 for (i = 0; i < NSPARCCHIPS; i++) {
88 if (linux_sparc_chips[i].manuf == manuf) {
89 if (linux_sparc_chips[i].impl == impl) {
90 sparc_cpu_type =
91 linux_sparc_chips[i].cpu_name;
92 break;
97 if (i == NSPARCCHIPS) {
98 /* Maybe it is a cheetah+ derivative, report it as cheetah+
99 * in that case until we learn the real names.
101 if (manuf == 0x3e &&
102 impl > 0x15) {
103 impl = 0x15;
104 goto retry;
105 } else {
106 printk("DEBUG: manuf[%lx] impl[%lx]\n",
107 manuf, impl);
109 sparc_cpu_type = "Unknown CPU";
112 for (i = 0; i < NSPARCFPU; i++) {
113 if (linux_sparc_fpu[i].manuf == manuf &&
114 linux_sparc_fpu[i].impl == impl) {
115 if (linux_sparc_fpu[i].fpu_vers == fpu_vers) {
116 sparc_fpu_type =
117 linux_sparc_fpu[i].fp_name;
118 break;
123 if (i == NSPARCFPU) {
124 printk("DEBUG: manuf[%lx] impl[%lx] fsr.vers[%lx]\n",
125 manuf, impl, fpu_vers);
126 sparc_fpu_type = "Unknown FPU";