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rtl8180: use cached queue mapping for skb in rtl8180_tx
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / davinci_emac.c
blob32960b9b02ae0ba96b539d88cddda617125e8da0
1 /*
2 * DaVinci Ethernet Medium Access Controller
3 *
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
5 *
6 * Copyright (C) 2009 Texas Instruments.
7 *
8 * ---------------------------------------------------------------------------
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
24 * History:
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
29 * PHY layer usage
30 */
31
32 /** Pending Items in this driver:
33 * 1. Use Linux cache infrastcture for DMA'ed memory (dma_xxx functions)
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/string.h>
40 #include <linux/timer.h>
41 #include <linux/errno.h>
42 #include <linux/in.h>
43 #include <linux/ioport.h>
44 #include <linux/slab.h>
45 #include <linux/mm.h>
46 #include <linux/interrupt.h>
47 #include <linux/init.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/skbuff.h>
51 #include <linux/ethtool.h>
52 #include <linux/highmem.h>
53 #include <linux/proc_fs.h>
54 #include <linux/ctype.h>
55 #include <linux/version.h>
56 #include <linux/spinlock.h>
57 #include <linux/dma-mapping.h>
58 #include <linux/clk.h>
59 #include <linux/platform_device.h>
60 #include <linux/semaphore.h>
61 #include <linux/phy.h>
62 #include <linux/bitops.h>
63 #include <linux/io.h>
64 #include <linux/uaccess.h>
65 #include <linux/davinci_emac.h>
66
67 #include <asm/irq.h>
68 #include <asm/page.h>
69
70 static int debug_level;
71 module_param(debug_level, int, 0);
72 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
73
74 /* Netif debug messages possible */
75 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
76 NETIF_MSG_PROBE | \
77 NETIF_MSG_LINK | \
78 NETIF_MSG_TIMER | \
79 NETIF_MSG_IFDOWN | \
80 NETIF_MSG_IFUP | \
81 NETIF_MSG_RX_ERR | \
82 NETIF_MSG_TX_ERR | \
83 NETIF_MSG_TX_QUEUED | \
84 NETIF_MSG_INTR | \
85 NETIF_MSG_TX_DONE | \
86 NETIF_MSG_RX_STATUS | \
87 NETIF_MSG_PKTDATA | \
88 NETIF_MSG_HW | \
89 NETIF_MSG_WOL)
90
91 /* version info */
92 #define EMAC_MAJOR_VERSION 6
93 #define EMAC_MINOR_VERSION 1
94 #define EMAC_MODULE_VERSION "6.1"
95 MODULE_VERSION(EMAC_MODULE_VERSION);
96 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
97
98 /* Configuration items */
99 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */
100 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
101 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
102 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
103 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
104 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
105 #define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */
106 #define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */
107 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
108 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
109 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
110 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
111
112 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
113 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
114
115 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
116 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
117 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
118 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
119 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
120 #define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */
121 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
122 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
123 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
124
125 /* Buffer descriptor parameters */
126 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
127 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
128
129 /* EMAC register related defines */
130 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
131 #define EMAC_NUM_MULTICAST_BITS (64)
132 #define EMAC_TEARDOWN_VALUE (0xFFFFFFFC)
133 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
134 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
135 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
136 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
137 #define EMAC_INT_MASK_CLEAR (0xFF)
138
139 /* RX MBP register bit positions */
140 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
141 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
142 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
143 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
144 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
145 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
146 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
147 #define EMAC_RXMBP_PROMCH_SHIFT (16)
148 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
149 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
150 #define EMAC_RXMBP_BROADCH_SHIFT (8)
151 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
152 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
153 #define EMAC_RXMBP_MULTICH_SHIFT (0)
154 #define EMAC_RXMBP_MULTICH_MASK (0x7)
155 #define EMAC_RXMBP_CHMASK (0x7)
156
157 /* EMAC register definitions/bit maps used */
158 # define EMAC_MBP_RXPROMISC (0x00200000)
159 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
160 # define EMAC_MBP_RXBCAST (0x00002000)
161 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
162 # define EMAC_MBP_RXMCAST (0x00000020)
163 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
164
165 /* EMAC mac_control register */
166 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
167 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
168 #define EMAC_MACCONTROL_GMIIEN BIT(5)
169 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
170 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
171 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
172
173 /* GIGABIT MODE related bits */
174 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
175 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
176
177 /* EMAC mac_status register */
178 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
179 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
180 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
181 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
182 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
183 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
184 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
185 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
186
187 /* EMAC RX register masks */
188 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
189 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
190
191 /* MAC_IN_VECTOR (0x180) register bit fields */
192 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
193 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
194 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
195 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
196
197 /** NOTE:: For DM646x the IN_VECTOR has changed */
198 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
199 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
200 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
201 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
202
203 /* CPPI bit positions */
204 #define EMAC_CPPI_SOP_BIT BIT(31)
205 #define EMAC_CPPI_EOP_BIT BIT(30)
206 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
207 #define EMAC_CPPI_EOQ_BIT BIT(28)
208 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
209 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
210 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
211 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
212 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
213
214 /* Max hardware defines */
215 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
216 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
217
218 /* EMAC Peripheral Device Register Memory Layout structure */
219 #define EMAC_TXIDVER 0x0
220 #define EMAC_TXCONTROL 0x4
221 #define EMAC_TXTEARDOWN 0x8
222 #define EMAC_RXIDVER 0x10
223 #define EMAC_RXCONTROL 0x14
224 #define EMAC_RXTEARDOWN 0x18
225 #define EMAC_TXINTSTATRAW 0x80
226 #define EMAC_TXINTSTATMASKED 0x84
227 #define EMAC_TXINTMASKSET 0x88
228 #define EMAC_TXINTMASKCLEAR 0x8C
229 #define EMAC_MACINVECTOR 0x90
230
231 #define EMAC_DM646X_MACEOIVECTOR 0x94
232
233 #define EMAC_RXINTSTATRAW 0xA0
234 #define EMAC_RXINTSTATMASKED 0xA4
235 #define EMAC_RXINTMASKSET 0xA8
236 #define EMAC_RXINTMASKCLEAR 0xAC
237 #define EMAC_MACINTSTATRAW 0xB0
238 #define EMAC_MACINTSTATMASKED 0xB4
239 #define EMAC_MACINTMASKSET 0xB8
240 #define EMAC_MACINTMASKCLEAR 0xBC
241
242 #define EMAC_RXMBPENABLE 0x100
243 #define EMAC_RXUNICASTSET 0x104
244 #define EMAC_RXUNICASTCLEAR 0x108
245 #define EMAC_RXMAXLEN 0x10C
246 #define EMAC_RXBUFFEROFFSET 0x110
247 #define EMAC_RXFILTERLOWTHRESH 0x114
248
249 #define EMAC_MACCONTROL 0x160
250 #define EMAC_MACSTATUS 0x164
251 #define EMAC_EMCONTROL 0x168
252 #define EMAC_FIFOCONTROL 0x16C
253 #define EMAC_MACCONFIG 0x170
254 #define EMAC_SOFTRESET 0x174
255 #define EMAC_MACSRCADDRLO 0x1D0
256 #define EMAC_MACSRCADDRHI 0x1D4
257 #define EMAC_MACHASH1 0x1D8
258 #define EMAC_MACHASH2 0x1DC
259 #define EMAC_MACADDRLO 0x500
260 #define EMAC_MACADDRHI 0x504
261 #define EMAC_MACINDEX 0x508
262
263 /* EMAC HDP and Completion registors */
264 #define EMAC_TXHDP(ch) (0x600 + (ch * 4))
265 #define EMAC_RXHDP(ch) (0x620 + (ch * 4))
266 #define EMAC_TXCP(ch) (0x640 + (ch * 4))
267 #define EMAC_RXCP(ch) (0x660 + (ch * 4))
268
269 /* EMAC statistics registers */
270 #define EMAC_RXGOODFRAMES 0x200
271 #define EMAC_RXBCASTFRAMES 0x204
272 #define EMAC_RXMCASTFRAMES 0x208
273 #define EMAC_RXPAUSEFRAMES 0x20C
274 #define EMAC_RXCRCERRORS 0x210
275 #define EMAC_RXALIGNCODEERRORS 0x214
276 #define EMAC_RXOVERSIZED 0x218
277 #define EMAC_RXJABBER 0x21C
278 #define EMAC_RXUNDERSIZED 0x220
279 #define EMAC_RXFRAGMENTS 0x224
280 #define EMAC_RXFILTERED 0x228
281 #define EMAC_RXQOSFILTERED 0x22C
282 #define EMAC_RXOCTETS 0x230
283 #define EMAC_TXGOODFRAMES 0x234
284 #define EMAC_TXBCASTFRAMES 0x238
285 #define EMAC_TXMCASTFRAMES 0x23C
286 #define EMAC_TXPAUSEFRAMES 0x240
287 #define EMAC_TXDEFERRED 0x244
288 #define EMAC_TXCOLLISION 0x248
289 #define EMAC_TXSINGLECOLL 0x24C
290 #define EMAC_TXMULTICOLL 0x250
291 #define EMAC_TXEXCESSIVECOLL 0x254
292 #define EMAC_TXLATECOLL 0x258
293 #define EMAC_TXUNDERRUN 0x25C
294 #define EMAC_TXCARRIERSENSE 0x260
295 #define EMAC_TXOCTETS 0x264
296 #define EMAC_NETOCTETS 0x280
297 #define EMAC_RXSOFOVERRUNS 0x284
298 #define EMAC_RXMOFOVERRUNS 0x288
299 #define EMAC_RXDMAOVERRUNS 0x28C
300
301 /* EMAC DM644x control registers */
302 #define EMAC_CTRL_EWCTL (0x4)
303 #define EMAC_CTRL_EWINTTCNT (0x8)
304
305 /* EMAC MDIO related */
306 /* Mask & Control defines */
307 #define MDIO_CONTROL_CLKDIV (0xFF)
308 #define MDIO_CONTROL_ENABLE BIT(30)
309 #define MDIO_USERACCESS_GO BIT(31)
310 #define MDIO_USERACCESS_WRITE BIT(30)
311 #define MDIO_USERACCESS_READ (0)
312 #define MDIO_USERACCESS_REGADR (0x1F << 21)
313 #define MDIO_USERACCESS_PHYADR (0x1F << 16)
314 #define MDIO_USERACCESS_DATA (0xFFFF)
315 #define MDIO_USERPHYSEL_LINKSEL BIT(7)
316 #define MDIO_VER_MODID (0xFFFF << 16)
317 #define MDIO_VER_REVMAJ (0xFF << 8)
318 #define MDIO_VER_REVMIN (0xFF)
319
320 #define MDIO_USERACCESS(inst) (0x80 + (inst * 8))
321 #define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8))
322 #define MDIO_CONTROL (0x04)
323
324 /* EMAC DM646X control module registers */
325 #define EMAC_DM646X_CMRXINTEN (0x14)
326 #define EMAC_DM646X_CMTXINTEN (0x18)
327
328 /* EMAC EOI codes for C0 */
329 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
330 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
331
332 /* EMAC Stats Clear Mask */
333 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
334
335 /** net_buf_obj: EMAC network bufferdata structure
336 *
337 * EMAC network buffer data structure
338 */
339 struct emac_netbufobj {
340 void *buf_token;
341 char *data_ptr;
342 int length;
343 };
344
345 /** net_pkt_obj: EMAC network packet data structure
346 *
347 * EMAC network packet data structure - supports buffer list (for future)
348 */
349 struct emac_netpktobj {
350 void *pkt_token; /* data token may hold tx/rx chan id */
351 struct emac_netbufobj *buf_list; /* array of network buffer objects */
352 int num_bufs;
353 int pkt_length;
354 };
355
356 /** emac_tx_bd: EMAC TX Buffer descriptor data structure
357 *
358 * EMAC TX Buffer descriptor data structure
359 */
360 struct emac_tx_bd {
361 int h_next;
362 int buff_ptr;
363 int off_b_len;
364 int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
365 struct emac_tx_bd __iomem *next;
366 void *buf_token;
367 };
368
369 /** emac_txch: EMAC TX Channel data structure
370 *
371 * EMAC TX Channel data structure
372 */
373 struct emac_txch {
374 /* Config related */
375 u32 num_bd;
376 u32 service_max;
377
378 /* CPPI specific */
379 u32 alloc_size;
380 void __iomem *bd_mem;
381 struct emac_tx_bd __iomem *bd_pool_head;
382 struct emac_tx_bd __iomem *active_queue_head;
383 struct emac_tx_bd __iomem *active_queue_tail;
384 struct emac_tx_bd __iomem *last_hw_bdprocessed;
385 u32 queue_active;
386 u32 teardown_pending;
387 u32 *tx_complete;
388
389 /** statistics */
390 u32 proc_count; /* TX: # of times emac_tx_bdproc is called */
391 u32 mis_queued_packets;
392 u32 queue_reinit;
393 u32 end_of_queue_add;
394 u32 out_of_tx_bd;
395 u32 no_active_pkts; /* IRQ when there were no packets to process */
396 u32 active_queue_count;
397 };
398
399 /** emac_rx_bd: EMAC RX Buffer descriptor data structure
400 *
401 * EMAC RX Buffer descriptor data structure
402 */
403 struct emac_rx_bd {
404 int h_next;
405 int buff_ptr;
406 int off_b_len;
407 int mode;
408 struct emac_rx_bd __iomem *next;
409 void *data_ptr;
410 void *buf_token;
411 };
412
413 /** emac_rxch: EMAC RX Channel data structure
414 *
415 * EMAC RX Channel data structure
416 */
417 struct emac_rxch {
418 /* configuration info */
419 u32 num_bd;
420 u32 service_max;
421 u32 buf_size;
422 char mac_addr[6];
423
424 /** CPPI specific */
425 u32 alloc_size;
426 void __iomem *bd_mem;
427 struct emac_rx_bd __iomem *bd_pool_head;
428 struct emac_rx_bd __iomem *active_queue_head;
429 struct emac_rx_bd __iomem *active_queue_tail;
430 u32 queue_active;
431 u32 teardown_pending;
432
433 /* packet and buffer objects */
434 struct emac_netpktobj pkt_queue;
435 struct emac_netbufobj buf_queue;
436
437 /** statistics */
438 u32 proc_count; /* number of times emac_rx_bdproc is called */
439 u32 processed_bd;
440 u32 recycled_bd;
441 u32 out_of_rx_bd;
442 u32 out_of_rx_buffers;
443 u32 queue_reinit;
444 u32 end_of_queue_add;
445 u32 end_of_queue;
446 u32 mis_queued_packets;
447 };
448
449 /* emac_priv: EMAC private data structure
450 *
451 * EMAC adapter private data structure
452 */
453 struct emac_priv {
454 u32 msg_enable;
455 struct net_device *ndev;
456 struct platform_device *pdev;
457 struct napi_struct napi;
458 char mac_addr[6];
459 spinlock_t tx_lock;
460 spinlock_t rx_lock;
461 void __iomem *remap_addr;
462 u32 emac_base_phys;
463 void __iomem *emac_base;
464 void __iomem *ctrl_base;
465 void __iomem *emac_ctrl_ram;
466 u32 ctrl_ram_size;
467 u32 hw_ram_addr;
468 struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
469 struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
470 u32 link; /* 1=link on, 0=link off */
471 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
472 u32 duplex; /* Link duplex: 0=Half, 1=Full */
473 u32 rx_buf_size;
474 u32 isr_count;
475 u8 rmii_en;
476 u8 version;
477 struct net_device_stats net_dev_stats;
478 u32 mac_hash1;
479 u32 mac_hash2;
480 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
481 u32 rx_addr_type;
482 /* periodic timer required for MDIO polling */
483 struct timer_list periodic_timer;
484 u32 periodic_ticks;
485 u32 timer_active;
486 u32 phy_mask;
487 /* mii_bus,phy members */
488 struct mii_bus *mii_bus;
489 struct phy_device *phydev;
490 spinlock_t lock;
491 /*platform specific members*/
492 void (*int_enable) (void);
493 void (*int_disable) (void);
494 };
495
496 /* clock frequency for EMAC */
497 static struct clk *emac_clk;
498 static unsigned long emac_bus_frequency;
499 static unsigned long mdio_max_freq;
500
501 #define emac_virt_to_phys(addr, priv) \
502 (((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \
503 + priv->hw_ram_addr)
504
505 /* Cache macros - Packet buffers would be from skb pool which is cached */
506 #define EMAC_VIRT_NOCACHE(addr) (addr)
507 #define EMAC_CACHE_INVALIDATE(addr, size) \
508 dma_cache_maint((void *)addr, size, DMA_FROM_DEVICE)
509 #define EMAC_CACHE_WRITEBACK(addr, size) \
510 dma_cache_maint((void *)addr, size, DMA_TO_DEVICE)
511 #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \
512 dma_cache_maint((void *)addr, size, DMA_BIDIRECTIONAL)
513
514 /* DM644x does not have BD's in cached memory - so no cache functions */
515 #define BD_CACHE_INVALIDATE(addr, size)
516 #define BD_CACHE_WRITEBACK(addr, size)
517 #define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
518
519 /* EMAC TX Host Error description strings */
520 static char *emac_txhost_errcodes[16] = {
521 "No error", "SOP error", "Ownership bit not set in SOP buffer",
522 "Zero Next Buffer Descriptor Pointer Without EOP",
523 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
524 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
525 "Reserved", "Reserved", "Reserved", "Reserved"
526 };
527
528 /* EMAC RX Host Error description strings */
529 static char *emac_rxhost_errcodes[16] = {
530 "No error", "Reserved", "Ownership bit not set in input buffer",
531 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
532 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
533 "Reserved", "Reserved", "Reserved", "Reserved"
534 };
535
536 /* Helper macros */
537 #define emac_read(reg) ioread32(priv->emac_base + (reg))
538 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
539
540 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
541 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
542
543 #define emac_mdio_read(reg) ioread32(bus->priv + (reg))
544 #define emac_mdio_write(reg, val) iowrite32(val, (bus->priv + (reg)))
545
546 /**
547 * emac_dump_regs: Dump important EMAC registers to debug terminal
548 * @priv: The DaVinci EMAC private adapter structure
549 *
550 * Executes ethtool set cmd & sets phy mode
551 *
552 */
553 static void emac_dump_regs(struct emac_priv *priv)
554 {
555 struct device *emac_dev = &priv->ndev->dev;
556
557 /* Print important registers in EMAC */
558 dev_info(emac_dev, "EMAC Basic registers\n");
559 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
560 emac_ctrl_read(EMAC_CTRL_EWCTL),
561 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
562 dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n",
563 emac_read(EMAC_TXIDVER),
564 ((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"),
565 emac_read(EMAC_RXIDVER),
566 ((emac_read(EMAC_RXCONTROL)) ? "enabled" : "disabled"));
567 dev_info(emac_dev, "EMAC: TXIntRaw:%08X, TxIntMasked: %08X, "\
568 "TxIntMasSet: %08X\n", emac_read(EMAC_TXINTSTATRAW),
569 emac_read(EMAC_TXINTSTATMASKED), emac_read(EMAC_TXINTMASKSET));
570 dev_info(emac_dev, "EMAC: RXIntRaw:%08X, RxIntMasked: %08X, "\
571 "RxIntMasSet: %08X\n", emac_read(EMAC_RXINTSTATRAW),
572 emac_read(EMAC_RXINTSTATMASKED), emac_read(EMAC_RXINTMASKSET));
573 dev_info(emac_dev, "EMAC: MacIntRaw:%08X, MacIntMasked: %08X, "\
574 "MacInVector=%08X\n", emac_read(EMAC_MACINTSTATRAW),
575 emac_read(EMAC_MACINTSTATMASKED), emac_read(EMAC_MACINVECTOR));
576 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
577 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
578 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
579 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
580 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
581 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
582 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
583 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
584 dev_info(emac_dev, "EMAC: TXHDP[0]:%08X, RXHDP[0]: %08X\n",
585 emac_read(EMAC_TXHDP(0)), emac_read(EMAC_RXHDP(0)));
586 dev_info(emac_dev, "EMAC Statistics\n");
587 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
588 emac_read(EMAC_RXGOODFRAMES));
589 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
590 emac_read(EMAC_RXBCASTFRAMES));
591 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
592 emac_read(EMAC_RXMCASTFRAMES));
593 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
594 emac_read(EMAC_RXPAUSEFRAMES));
595 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
596 emac_read(EMAC_RXCRCERRORS));
597 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
598 emac_read(EMAC_RXALIGNCODEERRORS));
599 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
600 emac_read(EMAC_RXOVERSIZED));
601 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
602 emac_read(EMAC_RXJABBER));
603 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
604 emac_read(EMAC_RXUNDERSIZED));
605 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
606 emac_read(EMAC_RXFRAGMENTS));
607 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
608 emac_read(EMAC_RXFILTERED));
609 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
610 emac_read(EMAC_RXQOSFILTERED));
611 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
612 emac_read(EMAC_RXOCTETS));
613 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
614 emac_read(EMAC_TXGOODFRAMES));
615 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
616 emac_read(EMAC_TXBCASTFRAMES));
617 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
618 emac_read(EMAC_TXMCASTFRAMES));
619 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
620 emac_read(EMAC_TXPAUSEFRAMES));
621 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
622 emac_read(EMAC_TXDEFERRED));
623 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
624 emac_read(EMAC_TXCOLLISION));
625 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
626 emac_read(EMAC_TXSINGLECOLL));
627 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
628 emac_read(EMAC_TXMULTICOLL));
629 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
630 emac_read(EMAC_TXEXCESSIVECOLL));
631 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
632 emac_read(EMAC_TXLATECOLL));
633 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
634 emac_read(EMAC_TXUNDERRUN));
635 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
636 emac_read(EMAC_TXCARRIERSENSE));
637 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
638 emac_read(EMAC_TXOCTETS));
639 dev_info(emac_dev, "EMAC: net_octets:%d\n",
640 emac_read(EMAC_NETOCTETS));
641 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
642 emac_read(EMAC_RXSOFOVERRUNS));
643 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
644 emac_read(EMAC_RXMOFOVERRUNS));
645 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
646 emac_read(EMAC_RXDMAOVERRUNS));
647 }
648
649 /*************************************************************************
650 * EMAC MDIO/Phy Functionality
651 *************************************************************************/
652 /**
653 * emac_get_drvinfo: Get EMAC driver information
654 * @ndev: The DaVinci EMAC network adapter
655 * @info: ethtool info structure containing name and version
656 *
657 * Returns EMAC driver information (name and version)
658 *
659 */
660 static void emac_get_drvinfo(struct net_device *ndev,
661 struct ethtool_drvinfo *info)
662 {
663 strcpy(info->driver, emac_version_string);
664 strcpy(info->version, EMAC_MODULE_VERSION);
665 }
666
667 /**
668 * emac_get_settings: Get EMAC settings
669 * @ndev: The DaVinci EMAC network adapter
670 * @ecmd: ethtool command
671 *
672 * Executes ethool get command
673 *
674 */
675 static int emac_get_settings(struct net_device *ndev,
676 struct ethtool_cmd *ecmd)
677 {
678 struct emac_priv *priv = netdev_priv(ndev);
679 if (priv->phy_mask)
680 return phy_ethtool_gset(priv->phydev, ecmd);
681 else
682 return -EOPNOTSUPP;
683
684 }
685
686 /**
687 * emac_set_settings: Set EMAC settings
688 * @ndev: The DaVinci EMAC network adapter
689 * @ecmd: ethtool command
690 *
691 * Executes ethool set command
692 *
693 */
694 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
695 {
696 struct emac_priv *priv = netdev_priv(ndev);
697 if (priv->phy_mask)
698 return phy_ethtool_sset(priv->phydev, ecmd);
699 else
700 return -EOPNOTSUPP;
701
702 }
703
704 /**
705 * ethtool_ops: DaVinci EMAC Ethtool structure
706 *
707 * Ethtool support for EMAC adapter
708 *
709 */
710 static const struct ethtool_ops ethtool_ops = {
711 .get_drvinfo = emac_get_drvinfo,
712 .get_settings = emac_get_settings,
713 .set_settings = emac_set_settings,
714 .get_link = ethtool_op_get_link,
715 };
716
717 /**
718 * emac_update_phystatus: Update Phy status
719 * @priv: The DaVinci EMAC private adapter structure
720 *
721 * Updates phy status and takes action for network queue if required
722 * based upon link status
723 *
724 */
725 static void emac_update_phystatus(struct emac_priv *priv)
726 {
727 u32 mac_control;
728 u32 new_duplex;
729 u32 cur_duplex;
730 struct net_device *ndev = priv->ndev;
731
732 mac_control = emac_read(EMAC_MACCONTROL);
733 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
734 DUPLEX_FULL : DUPLEX_HALF;
735 if (priv->phy_mask)
736 new_duplex = priv->phydev->duplex;
737 else
738 new_duplex = DUPLEX_FULL;
739
740 /* We get called only if link has changed (speed/duplex/status) */
741 if ((priv->link) && (new_duplex != cur_duplex)) {
742 priv->duplex = new_duplex;
743 if (DUPLEX_FULL == priv->duplex)
744 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
745 else
746 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
747 }
748
749 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
750 mac_control = emac_read(EMAC_MACCONTROL);
751 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
752 EMAC_DM646X_MACCONTORL_GIGFORCE);
753 } else {
754 /* Clear the GIG bit and GIGFORCE bit */
755 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
756 EMAC_DM646X_MACCONTORL_GIG);
757
758 if (priv->rmii_en && (priv->speed == SPEED_100))
759 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
760 else
761 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
762 }
763
764 /* Update mac_control if changed */
765 emac_write(EMAC_MACCONTROL, mac_control);
766
767 if (priv->link) {
768 /* link ON */
769 if (!netif_carrier_ok(ndev))
770 netif_carrier_on(ndev);
771 /* reactivate the transmit queue if it is stopped */
772 if (netif_running(ndev) && netif_queue_stopped(ndev))
773 netif_wake_queue(ndev);
774 } else {
775 /* link OFF */
776 if (netif_carrier_ok(ndev))
777 netif_carrier_off(ndev);
778 if (!netif_queue_stopped(ndev))
779 netif_stop_queue(ndev);
780 }
781 }
782
783 /**
784 * hash_get: Calculate hash value from mac address
785 * @addr: mac address to delete from hash table
786 *
787 * Calculates hash value from mac address
788 *
789 */
790 static u32 hash_get(u8 *addr)
791 {
792 u32 hash;
793 u8 tmpval;
794 int cnt;
795 hash = 0;
796
797 for (cnt = 0; cnt < 2; cnt++) {
798 tmpval = *addr++;
799 hash ^= (tmpval >> 2) ^ (tmpval << 4);
800 tmpval = *addr++;
801 hash ^= (tmpval >> 4) ^ (tmpval << 2);
802 tmpval = *addr++;
803 hash ^= (tmpval >> 6) ^ (tmpval);
804 }
805
806 return hash & 0x3F;
807 }
808
809 /**
810 * hash_add: Hash function to add mac addr from hash table
811 * @priv: The DaVinci EMAC private adapter structure
812 * mac_addr: mac address to delete from hash table
813 *
814 * Adds mac address to the internal hash table
815 *
816 */
817 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
818 {
819 struct device *emac_dev = &priv->ndev->dev;
820 u32 rc = 0;
821 u32 hash_bit;
822 u32 hash_value = hash_get(mac_addr);
823
824 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
825 if (netif_msg_drv(priv)) {
826 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
827 "Hash %08x, should not be greater than %08x",
828 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
829 }
830 return -1;
831 }
832
833 /* set the hash bit only if not previously set */
834 if (priv->multicast_hash_cnt[hash_value] == 0) {
835 rc = 1; /* hash value changed */
836 if (hash_value < 32) {
837 hash_bit = BIT(hash_value);
838 priv->mac_hash1 |= hash_bit;
839 } else {
840 hash_bit = BIT((hash_value - 32));
841 priv->mac_hash2 |= hash_bit;
842 }
843 }
844
845 /* incr counter for num of mcast addr's mapped to "this" hash bit */
846 ++priv->multicast_hash_cnt[hash_value];
847
848 return rc;
849 }
850
851 /**
852 * hash_del: Hash function to delete mac addr from hash table
853 * @priv: The DaVinci EMAC private adapter structure
854 * mac_addr: mac address to delete from hash table
855 *
856 * Removes mac address from the internal hash table
857 *
858 */
859 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
860 {
861 u32 hash_value;
862 u32 hash_bit;
863
864 hash_value = hash_get(mac_addr);
865 if (priv->multicast_hash_cnt[hash_value] > 0) {
866 /* dec cntr for num of mcast addr's mapped to this hash bit */
867 --priv->multicast_hash_cnt[hash_value];
868 }
869
870 /* if counter still > 0, at least one multicast address refers
871 * to this hash bit. so return 0 */
872 if (priv->multicast_hash_cnt[hash_value] > 0)
873 return 0;
874
875 if (hash_value < 32) {
876 hash_bit = BIT(hash_value);
877 priv->mac_hash1 &= ~hash_bit;
878 } else {
879 hash_bit = BIT((hash_value - 32));
880 priv->mac_hash2 &= ~hash_bit;
881 }
882
883 /* return 1 to indicate change in mac_hash registers reqd */
884 return 1;
885 }
886
887 /* EMAC multicast operation */
888 #define EMAC_MULTICAST_ADD 0
889 #define EMAC_MULTICAST_DEL 1
890 #define EMAC_ALL_MULTI_SET 2
891 #define EMAC_ALL_MULTI_CLR 3
892
893 /**
894 * emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
895 * @priv: The DaVinci EMAC private adapter structure
896 * @action: multicast operation to perform
897 * mac_addr: mac address to set
898 *
899 * Set multicast addresses in EMAC adapter - internal function
900 *
901 */
902 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
903 {
904 struct device *emac_dev = &priv->ndev->dev;
905 int update = -1;
906
907 switch (action) {
908 case EMAC_MULTICAST_ADD:
909 update = hash_add(priv, mac_addr);
910 break;
911 case EMAC_MULTICAST_DEL:
912 update = hash_del(priv, mac_addr);
913 break;
914 case EMAC_ALL_MULTI_SET:
915 update = 1;
916 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
917 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
918 break;
919 case EMAC_ALL_MULTI_CLR:
920 update = 1;
921 priv->mac_hash1 = 0;
922 priv->mac_hash2 = 0;
923 memset(&(priv->multicast_hash_cnt[0]), 0,
924 sizeof(priv->multicast_hash_cnt[0]) *
925 EMAC_NUM_MULTICAST_BITS);
926 break;
927 default:
928 if (netif_msg_drv(priv))
929 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
930 ": bad operation %d", action);
931 break;
932 }
933
934 /* write to the hardware only if the register status chances */
935 if (update > 0) {
936 emac_write(EMAC_MACHASH1, priv->mac_hash1);
937 emac_write(EMAC_MACHASH2, priv->mac_hash2);
938 }
939 }
940
941 /**
942 * emac_dev_mcast_set: Set multicast address in the EMAC adapter
943 * @ndev: The DaVinci EMAC network adapter
944 *
945 * Set multicast addresses in EMAC adapter
946 *
947 */
948 static void emac_dev_mcast_set(struct net_device *ndev)
949 {
950 u32 mbp_enable;
951 struct emac_priv *priv = netdev_priv(ndev);
952
953 mbp_enable = emac_read(EMAC_RXMBPENABLE);
954 if (ndev->flags & IFF_PROMISC) {
955 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
956 mbp_enable |= (EMAC_MBP_RXPROMISC);
957 } else {
958 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
959 if ((ndev->flags & IFF_ALLMULTI) ||
960 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
961 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
962 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
963 }
964 if (!netdev_mc_empty(ndev)) {
965 struct dev_mc_list *mc_ptr;
966 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
967 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
968 /* program multicast address list into EMAC hardware */
969 netdev_for_each_mc_addr(mc_ptr, ndev) {
970 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
971 (u8 *) mc_ptr->dmi_addr);
972 }
973 } else {
974 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
975 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
976 }
977 }
978 /* Set mbp config register */
979 emac_write(EMAC_RXMBPENABLE, mbp_enable);
980 }
981
982 /*************************************************************************
983 * EMAC Hardware manipulation
984 *************************************************************************/
985
986 /**
987 * emac_int_disable: Disable EMAC module interrupt (from adapter)
988 * @priv: The DaVinci EMAC private adapter structure
989 *
990 * Disable EMAC interrupt on the adapter
991 *
992 */
993 static void emac_int_disable(struct emac_priv *priv)
994 {
995 if (priv->version == EMAC_VERSION_2) {
996 unsigned long flags;
997
998 local_irq_save(flags);
999
1000 /* Program C0_Int_En to zero to turn off
1001 * interrupts to the CPU */
1002 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
1003 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
1004 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
1005 if (priv->int_disable)
1006 priv->int_disable();
1007
1008 local_irq_restore(flags);
1009
1010 } else {
1011 /* Set DM644x control registers for interrupt control */
1012 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
1013 }
1014 }
1015
1016 /**
1017 * emac_int_enable: Enable EMAC module interrupt (from adapter)
1018 * @priv: The DaVinci EMAC private adapter structure
1019 *
1020 * Enable EMAC interrupt on the adapter
1021 *
1022 */
1023 static void emac_int_enable(struct emac_priv *priv)
1024 {
1025 if (priv->version == EMAC_VERSION_2) {
1026 if (priv->int_enable)
1027 priv->int_enable();
1028
1029 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
1030 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
1031
1032 /* In addition to turning on interrupt Enable, we need
1033 * ack by writing appropriate values to the EOI
1034 * register */
1035
1036 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
1037
1038 /* ack rxen only then a new pulse will be generated */
1039 emac_write(EMAC_DM646X_MACEOIVECTOR,
1040 EMAC_DM646X_MAC_EOI_C0_RXEN);
1041
1042 /* ack txen- only then a new pulse will be generated */
1043 emac_write(EMAC_DM646X_MACEOIVECTOR,
1044 EMAC_DM646X_MAC_EOI_C0_TXEN);
1045
1046 } else {
1047 /* Set DM644x control registers for interrupt control */
1048 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
1049 }
1050 }
1051
1052 /**
1053 * emac_irq: EMAC interrupt handler
1054 * @irq: interrupt number
1055 * @dev_id: EMAC network adapter data structure ptr
1056 *
1057 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
1058 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
1059 *
1060 * Returns interrupt handled condition
1061 */
1062 static irqreturn_t emac_irq(int irq, void *dev_id)
1063 {
1064 struct net_device *ndev = (struct net_device *)dev_id;
1065 struct emac_priv *priv = netdev_priv(ndev);
1066
1067 ++priv->isr_count;
1068 if (likely(netif_running(priv->ndev))) {
1069 emac_int_disable(priv);
1070 napi_schedule(&priv->napi);
1071 } else {
1072 /* we are closing down, so dont process anything */
1073 }
1074 return IRQ_HANDLED;
1075 }
1076
1077 /** EMAC on-chip buffer descriptor memory
1078 *
1079 * WARNING: Please note that the on chip memory is used for both TX and RX
1080 * buffer descriptor queues and is equally divided between TX and RX desc's
1081 * If the number of TX or RX descriptors change this memory pointers need
1082 * to be adjusted. If external memory is allocated then these pointers can
1083 * pointer to the memory
1084 *
1085 */
1086 #define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram)
1087 #define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \
1088 (((priv)->ctrl_ram_size) >> 1))
1089
1090 /**
1091 * emac_init_txch: TX channel initialization
1092 * @priv: The DaVinci EMAC private adapter structure
1093 * @ch: RX channel number
1094 *
1095 * Called during device init to setup a TX channel (allocate buffer desc
1096 * create free pool and keep ready for transmission
1097 *
1098 * Returns success(0) or mem alloc failures error code
1099 */
1100 static int emac_init_txch(struct emac_priv *priv, u32 ch)
1101 {
1102 struct device *emac_dev = &priv->ndev->dev;
1103 u32 cnt, bd_size;
1104 void __iomem *mem;
1105 struct emac_tx_bd __iomem *curr_bd;
1106 struct emac_txch *txch = NULL;
1107
1108 txch = kzalloc(sizeof(struct emac_txch), GFP_KERNEL);
1109 if (NULL == txch) {
1110 dev_err(emac_dev, "DaVinci EMAC: TX Ch mem alloc failed");
1111 return -ENOMEM;
1112 }
1113 priv->txch[ch] = txch;
1114 txch->service_max = EMAC_DEF_TX_MAX_SERVICE;
1115 txch->active_queue_head = NULL;
1116 txch->active_queue_tail = NULL;
1117 txch->queue_active = 0;
1118 txch->teardown_pending = 0;
1119
1120 /* allocate memory for TX CPPI channel on a 4 byte boundry */
1121 txch->tx_complete = kzalloc(txch->service_max * sizeof(u32),
1122 GFP_KERNEL);
1123 if (NULL == txch->tx_complete) {
1124 dev_err(emac_dev, "DaVinci EMAC: Tx service mem alloc failed");
1125 kfree(txch);
1126 return -ENOMEM;
1127 }
1128
1129 /* allocate buffer descriptor pool align every BD on four word
1130 * boundry for future requirements */
1131 bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF;
1132 txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1133 txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF);
1134
1135 /* alloc TX BD memory */
1136 txch->bd_mem = EMAC_TX_BD_MEM(priv);
1137 __memzero((void __force *)txch->bd_mem, txch->alloc_size);
1138
1139 /* initialize the BD linked list */
1140 mem = (void __force __iomem *)
1141 (((u32 __force) txch->bd_mem + 0xF) & ~0xF);
1142 txch->bd_pool_head = NULL;
1143 for (cnt = 0; cnt < txch->num_bd; cnt++) {
1144 curr_bd = mem + (cnt * bd_size);
1145 curr_bd->next = txch->bd_pool_head;
1146 txch->bd_pool_head = curr_bd;
1147 }
1148
1149 /* reset statistics counters */
1150 txch->out_of_tx_bd = 0;
1151 txch->no_active_pkts = 0;
1152 txch->active_queue_count = 0;
1153
1154 return 0;
1155 }
1156
1157 /**
1158 * emac_cleanup_txch: Book-keep function to clean TX channel resources
1159 * @priv: The DaVinci EMAC private adapter structure
1160 * @ch: TX channel number
1161 *
1162 * Called to clean up TX channel resources
1163 *
1164 */
1165 static void emac_cleanup_txch(struct emac_priv *priv, u32 ch)
1166 {
1167 struct emac_txch *txch = priv->txch[ch];
1168
1169 if (txch) {
1170 if (txch->bd_mem)
1171 txch->bd_mem = NULL;
1172 kfree(txch->tx_complete);
1173 kfree(txch);
1174 priv->txch[ch] = NULL;
1175 }
1176 }
1177
1178 /**
1179 * emac_net_tx_complete: TX packet completion function
1180 * @priv: The DaVinci EMAC private adapter structure
1181 * @net_data_tokens: packet token - skb pointer
1182 * @num_tokens: number of skb's to free
1183 * @ch: TX channel number
1184 *
1185 * Frees the skb once packet is transmitted
1186 *
1187 */
1188 static int emac_net_tx_complete(struct emac_priv *priv,
1189 void **net_data_tokens,
1190 int num_tokens, u32 ch)
1191 {
1192 u32 cnt;
1193
1194 if (unlikely(num_tokens && netif_queue_stopped(priv->ndev)))
1195 netif_start_queue(priv->ndev);
1196 for (cnt = 0; cnt < num_tokens; cnt++) {
1197 struct sk_buff *skb = (struct sk_buff *)net_data_tokens[cnt];
1198 if (skb == NULL)
1199 continue;
1200 priv->net_dev_stats.tx_packets++;
1201 priv->net_dev_stats.tx_bytes += skb->len;
1202 dev_kfree_skb_any(skb);
1203 }
1204 return 0;
1205 }
1206
1207 /**
1208 * emac_txch_teardown: TX channel teardown
1209 * @priv: The DaVinci EMAC private adapter structure
1210 * @ch: TX channel number
1211 *
1212 * Called to teardown TX channel
1213 *
1214 */
1215 static void emac_txch_teardown(struct emac_priv *priv, u32 ch)
1216 {
1217 struct device *emac_dev = &priv->ndev->dev;
1218 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1219 struct emac_txch *txch = priv->txch[ch];
1220 struct emac_tx_bd __iomem *curr_bd;
1221
1222 while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1223 EMAC_TEARDOWN_VALUE) {
1224 /* wait till tx teardown complete */
1225 cpu_relax(); /* TODO: check if this helps ... */
1226 --teardown_cnt;
1227 if (0 == teardown_cnt) {
1228 dev_err(emac_dev, "EMAC: TX teardown aborted\n");
1229 break;
1230 }
1231 }
1232 emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE);
1233
1234 /* process sent packets and return skb's to upper layer */
1235 if (1 == txch->queue_active) {
1236 curr_bd = txch->active_queue_head;
1237 while (curr_bd != NULL) {
1238 emac_net_tx_complete(priv, (void __force *)
1239 &curr_bd->buf_token, 1, ch);
1240 if (curr_bd != txch->active_queue_tail)
1241 curr_bd = curr_bd->next;
1242 else
1243 break;
1244 }
1245 txch->bd_pool_head = txch->active_queue_head;
1246 txch->active_queue_head =
1247 txch->active_queue_tail = NULL;
1248 }
1249 }
1250
1251 /**
1252 * emac_stop_txch: Stop TX channel operation
1253 * @priv: The DaVinci EMAC private adapter structure
1254 * @ch: TX channel number
1255 *
1256 * Called to stop TX channel operation
1257 *
1258 */
1259 static void emac_stop_txch(struct emac_priv *priv, u32 ch)
1260 {
1261 struct emac_txch *txch = priv->txch[ch];
1262
1263 if (txch) {
1264 txch->teardown_pending = 1;
1265 emac_write(EMAC_TXTEARDOWN, 0);
1266 emac_txch_teardown(priv, ch);
1267 txch->teardown_pending = 0;
1268 emac_write(EMAC_TXINTMASKCLEAR, BIT(ch));
1269 }
1270 }
1271
1272 /**
1273 * emac_tx_bdproc: TX buffer descriptor (packet) processing
1274 * @priv: The DaVinci EMAC private adapter structure
1275 * @ch: TX channel number to process buffer descriptors for
1276 * @budget: number of packets allowed to process
1277 * @pending: indication to caller that packets are pending to process
1278 *
1279 * Processes TX buffer descriptors after packets are transmitted - checks
1280 * ownership bit on the TX * descriptor and requeues it to free pool & frees
1281 * the SKB buffer. Only "budget" number of packets are processed and
1282 * indication of pending packets provided to the caller
1283 *
1284 * Returns number of packets processed
1285 */
1286 static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1287 {
1288 struct device *emac_dev = &priv->ndev->dev;
1289 unsigned long flags;
1290 u32 frame_status;
1291 u32 pkts_processed = 0;
1292 u32 tx_complete_cnt = 0;
1293 struct emac_tx_bd __iomem *curr_bd;
1294 struct emac_txch *txch = priv->txch[ch];
1295 u32 *tx_complete_ptr = txch->tx_complete;
1296
1297 if (unlikely(1 == txch->teardown_pending)) {
1298 if (netif_msg_tx_err(priv) && net_ratelimit()) {
1299 dev_err(emac_dev, "DaVinci EMAC:emac_tx_bdproc: "\
1300 "teardown pending\n");
1301 }
1302 return 0; /* dont handle any pkt completions */
1303 }
1304
1305 ++txch->proc_count;
1306 spin_lock_irqsave(&priv->tx_lock, flags);
1307 curr_bd = txch->active_queue_head;
1308 if (NULL == curr_bd) {
1309 emac_write(EMAC_TXCP(ch),
1310 emac_virt_to_phys(txch->last_hw_bdprocessed, priv));
1311 txch->no_active_pkts++;
1312 spin_unlock_irqrestore(&priv->tx_lock, flags);
1313 return 0;
1314 }
1315 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1316 frame_status = curr_bd->mode;
1317 while ((curr_bd) &&
1318 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1319 (pkts_processed < budget)) {
1320 emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd, priv));
1321 txch->active_queue_head = curr_bd->next;
1322 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1323 if (curr_bd->next) { /* misqueued packet */
1324 emac_write(EMAC_TXHDP(ch), curr_bd->h_next);
1325 ++txch->mis_queued_packets;
1326 } else {
1327 txch->queue_active = 0; /* end of queue */
1328 }
1329 }
1330 *tx_complete_ptr = (u32) curr_bd->buf_token;
1331 ++tx_complete_ptr;
1332 ++tx_complete_cnt;
1333 curr_bd->next = txch->bd_pool_head;
1334 txch->bd_pool_head = curr_bd;
1335 --txch->active_queue_count;
1336 pkts_processed++;
1337 txch->last_hw_bdprocessed = curr_bd;
1338 curr_bd = txch->active_queue_head;
1339 if (curr_bd) {
1340 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1341 frame_status = curr_bd->mode;
1342 }
1343 } /* end of pkt processing loop */
1344
1345 emac_net_tx_complete(priv,
1346 (void *)&txch->tx_complete[0],
1347 tx_complete_cnt, ch);
1348 spin_unlock_irqrestore(&priv->tx_lock, flags);
1349 return pkts_processed;
1350 }
1351
1352 #define EMAC_ERR_TX_OUT_OF_BD -1
1353
1354 /**
1355 * emac_send: EMAC Transmit function (internal)
1356 * @priv: The DaVinci EMAC private adapter structure
1357 * @pkt: packet pointer (contains skb ptr)
1358 * @ch: TX channel number
1359 *
1360 * Called by the transmit function to queue the packet in EMAC hardware queue
1361 *
1362 * Returns success(0) or error code (typically out of desc's)
1363 */
1364 static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1365 {
1366 unsigned long flags;
1367 struct emac_tx_bd __iomem *curr_bd;
1368 struct emac_txch *txch;
1369 struct emac_netbufobj *buf_list;
1370
1371 txch = priv->txch[ch];
1372 buf_list = pkt->buf_list; /* get handle to the buffer array */
1373
1374 /* check packet size and pad if short */
1375 if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) {
1376 buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length);
1377 pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE;
1378 }
1379
1380 spin_lock_irqsave(&priv->tx_lock, flags);
1381 curr_bd = txch->bd_pool_head;
1382 if (curr_bd == NULL) {
1383 txch->out_of_tx_bd++;
1384 spin_unlock_irqrestore(&priv->tx_lock, flags);
1385 return EMAC_ERR_TX_OUT_OF_BD;
1386 }
1387
1388 txch->bd_pool_head = curr_bd->next;
1389 curr_bd->buf_token = buf_list->buf_token;
1390 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1391 curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr);
1392 curr_bd->off_b_len = buf_list->length;
1393 curr_bd->h_next = 0;
1394 curr_bd->next = NULL;
1395 curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT |
1396 EMAC_CPPI_EOP_BIT | pkt->pkt_length);
1397
1398 /* flush the packet from cache if write back cache is present */
1399 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1400
1401 /* send the packet */
1402 if (txch->active_queue_head == NULL) {
1403 txch->active_queue_head = curr_bd;
1404 txch->active_queue_tail = curr_bd;
1405 if (1 != txch->queue_active) {
1406 emac_write(EMAC_TXHDP(ch),
1407 emac_virt_to_phys(curr_bd, priv));
1408 txch->queue_active = 1;
1409 }
1410 ++txch->queue_reinit;
1411 } else {
1412 register struct emac_tx_bd __iomem *tail_bd;
1413 register u32 frame_status;
1414
1415 tail_bd = txch->active_queue_tail;
1416 tail_bd->next = curr_bd;
1417 txch->active_queue_tail = curr_bd;
1418 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1419 tail_bd->h_next = (int)emac_virt_to_phys(curr_bd, priv);
1420 frame_status = tail_bd->mode;
1421 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1422 emac_write(EMAC_TXHDP(ch),
1423 emac_virt_to_phys(curr_bd, priv));
1424 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1425 tail_bd->mode = frame_status;
1426 ++txch->end_of_queue_add;
1427 }
1428 }
1429 txch->active_queue_count++;
1430 spin_unlock_irqrestore(&priv->tx_lock, flags);
1431 return 0;
1432 }
1433
1434 /**
1435 * emac_dev_xmit: EMAC Transmit function
1436 * @skb: SKB pointer
1437 * @ndev: The DaVinci EMAC network adapter
1438 *
1439 * Called by the system to transmit a packet - we queue the packet in
1440 * EMAC hardware transmit queue
1441 *
1442 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1443 */
1444 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1445 {
1446 struct device *emac_dev = &ndev->dev;
1447 int ret_code;
1448 struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */
1449 struct emac_netpktobj tx_packet; /* packet object */
1450 struct emac_priv *priv = netdev_priv(ndev);
1451
1452 /* If no link, return */
1453 if (unlikely(!priv->link)) {
1454 if (netif_msg_tx_err(priv) && net_ratelimit())
1455 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1456 return NETDEV_TX_BUSY;
1457 }
1458
1459 /* Build the buffer and packet objects - Since only single fragment is
1460 * supported, need not set length and token in both packet & object.
1461 * Doing so for completeness sake & to show that this needs to be done
1462 * in multifragment case
1463 */
1464 tx_packet.buf_list = &tx_buf;
1465 tx_packet.num_bufs = 1; /* only single fragment supported */
1466 tx_packet.pkt_length = skb->len;
1467 tx_packet.pkt_token = (void *)skb;
1468 tx_buf.length = skb->len;
1469 tx_buf.buf_token = (void *)skb;
1470 tx_buf.data_ptr = skb->data;
1471 EMAC_CACHE_WRITEBACK((unsigned long)skb->data, skb->len);
1472 ndev->trans_start = jiffies;
1473 ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
1474 if (unlikely(ret_code != 0)) {
1475 if (ret_code == EMAC_ERR_TX_OUT_OF_BD) {
1476 if (netif_msg_tx_err(priv) && net_ratelimit())
1477 dev_err(emac_dev, "DaVinci EMAC: xmit() fatal"\
1478 " err. Out of TX BD's");
1479 netif_stop_queue(priv->ndev);
1480 }
1481 priv->net_dev_stats.tx_dropped++;
1482 return NETDEV_TX_BUSY;
1483 }
1484
1485 return NETDEV_TX_OK;
1486 }
1487
1488 /**
1489 * emac_dev_tx_timeout: EMAC Transmit timeout function
1490 * @ndev: The DaVinci EMAC network adapter
1491 *
1492 * Called when system detects that a skb timeout period has expired
1493 * potentially due to a fault in the adapter in not being able to send
1494 * it out on the wire. We teardown the TX channel assuming a hardware
1495 * error and re-initialize the TX channel for hardware operation
1496 *
1497 */
1498 static void emac_dev_tx_timeout(struct net_device *ndev)
1499 {
1500 struct emac_priv *priv = netdev_priv(ndev);
1501 struct device *emac_dev = &ndev->dev;
1502
1503 if (netif_msg_tx_err(priv))
1504 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1505
1506 priv->net_dev_stats.tx_errors++;
1507 emac_int_disable(priv);
1508 emac_stop_txch(priv, EMAC_DEF_TX_CH);
1509 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
1510 emac_init_txch(priv, EMAC_DEF_TX_CH);
1511 emac_write(EMAC_TXHDP(0), 0);
1512 emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH));
1513 emac_int_enable(priv);
1514 }
1515
1516 /**
1517 * emac_net_alloc_rx_buf: Allocate a skb for RX
1518 * @priv: The DaVinci EMAC private adapter structure
1519 * @buf_size: size of SKB data buffer to allocate
1520 * @data_token: data token returned (skb handle for storing in buffer desc)
1521 * @ch: RX channel number
1522 *
1523 * Called during RX channel setup - allocates skb buffer of required size
1524 * and provides the skb handle and allocated buffer data pointer to caller
1525 *
1526 * Returns skb data pointer or 0 on failure to alloc skb
1527 */
1528 static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size,
1529 void **data_token, u32 ch)
1530 {
1531 struct net_device *ndev = priv->ndev;
1532 struct device *emac_dev = &ndev->dev;
1533 struct sk_buff *p_skb;
1534
1535 p_skb = dev_alloc_skb(buf_size);
1536 if (unlikely(NULL == p_skb)) {
1537 if (netif_msg_rx_err(priv) && net_ratelimit())
1538 dev_err(emac_dev, "DaVinci EMAC: failed to alloc skb");
1539 return NULL;
1540 }
1541
1542 /* set device pointer in skb and reserve space for extra bytes */
1543 p_skb->dev = ndev;
1544 skb_reserve(p_skb, NET_IP_ALIGN);
1545 *data_token = (void *) p_skb;
1546 EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p_skb->data, buf_size);
1547 return p_skb->data;
1548 }
1549
1550 /**
1551 * emac_init_rxch: RX channel initialization
1552 * @priv: The DaVinci EMAC private adapter structure
1553 * @ch: RX channel number
1554 * @param: mac address for RX channel
1555 *
1556 * Called during device init to setup a RX channel (allocate buffers and
1557 * buffer descriptors, create queue and keep ready for reception
1558 *
1559 * Returns success(0) or mem alloc failures error code
1560 */
1561 static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param)
1562 {
1563 struct device *emac_dev = &priv->ndev->dev;
1564 u32 cnt, bd_size;
1565 void __iomem *mem;
1566 struct emac_rx_bd __iomem *curr_bd;
1567 struct emac_rxch *rxch = NULL;
1568
1569 rxch = kzalloc(sizeof(struct emac_rxch), GFP_KERNEL);
1570 if (NULL == rxch) {
1571 dev_err(emac_dev, "DaVinci EMAC: RX Ch mem alloc failed");
1572 return -ENOMEM;
1573 }
1574 priv->rxch[ch] = rxch;
1575 rxch->buf_size = priv->rx_buf_size;
1576 rxch->service_max = EMAC_DEF_RX_MAX_SERVICE;
1577 rxch->queue_active = 0;
1578 rxch->teardown_pending = 0;
1579
1580 /* save mac address */
1581 for (cnt = 0; cnt < 6; cnt++)
1582 rxch->mac_addr[cnt] = param[cnt];
1583
1584 /* allocate buffer descriptor pool align every BD on four word
1585 * boundry for future requirements */
1586 bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF;
1587 rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1588 rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF);
1589 rxch->bd_mem = EMAC_RX_BD_MEM(priv);
1590 __memzero((void __force *)rxch->bd_mem, rxch->alloc_size);
1591 rxch->pkt_queue.buf_list = &rxch->buf_queue;
1592
1593 /* allocate RX buffer and initialize the BD linked list */
1594 mem = (void __force __iomem *)
1595 (((u32 __force) rxch->bd_mem + 0xF) & ~0xF);
1596 rxch->active_queue_head = NULL;
1597 rxch->active_queue_tail = mem;
1598 for (cnt = 0; cnt < rxch->num_bd; cnt++) {
1599 curr_bd = mem + (cnt * bd_size);
1600 /* for future use the last parameter contains the BD ptr */
1601 curr_bd->data_ptr = emac_net_alloc_rx_buf(priv,
1602 rxch->buf_size,
1603 (void __force **)&curr_bd->buf_token,
1604 EMAC_DEF_RX_CH);
1605 if (curr_bd->data_ptr == NULL) {
1606 dev_err(emac_dev, "DaVinci EMAC: RX buf mem alloc " \
1607 "failed for ch %d\n", ch);
1608 kfree(rxch);
1609 return -ENOMEM;
1610 }
1611
1612 /* populate the hardware descriptor */
1613 curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head,
1614 priv);
1615 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1616 curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr);
1617 curr_bd->off_b_len = rxch->buf_size;
1618 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1619
1620 /* write back to hardware memory */
1621 BD_CACHE_WRITEBACK_INVALIDATE((u32) curr_bd,
1622 EMAC_BD_LENGTH_FOR_CACHE);
1623 curr_bd->next = rxch->active_queue_head;
1624 rxch->active_queue_head = curr_bd;
1625 }
1626
1627 /* At this point rxCppi->activeQueueHead points to the first
1628 RX BD ready to be given to RX HDP and rxch->active_queue_tail
1629 points to the last RX BD
1630 */
1631 return 0;
1632 }
1633
1634 /**
1635 * emac_rxch_teardown: RX channel teardown
1636 * @priv: The DaVinci EMAC private adapter structure
1637 * @ch: RX channel number
1638 *
1639 * Called during device stop to teardown RX channel
1640 *
1641 */
1642 static void emac_rxch_teardown(struct emac_priv *priv, u32 ch)
1643 {
1644 struct device *emac_dev = &priv->ndev->dev;
1645 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1646
1647 while ((emac_read(EMAC_RXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1648 EMAC_TEARDOWN_VALUE) {
1649 /* wait till tx teardown complete */
1650 cpu_relax(); /* TODO: check if this helps ... */
1651 --teardown_cnt;
1652 if (0 == teardown_cnt) {
1653 dev_err(emac_dev, "EMAC: RX teardown aborted\n");
1654 break;
1655 }
1656 }
1657 emac_write(EMAC_RXCP(ch), EMAC_TEARDOWN_VALUE);
1658 }
1659
1660 /**
1661 * emac_stop_rxch: Stop RX channel operation
1662 * @priv: The DaVinci EMAC private adapter structure
1663 * @ch: RX channel number
1664 *
1665 * Called during device stop to stop RX channel operation
1666 *
1667 */
1668 static void emac_stop_rxch(struct emac_priv *priv, u32 ch)
1669 {
1670 struct emac_rxch *rxch = priv->rxch[ch];
1671
1672 if (rxch) {
1673 rxch->teardown_pending = 1;
1674 emac_write(EMAC_RXTEARDOWN, ch);
1675 /* wait for teardown complete */
1676 emac_rxch_teardown(priv, ch);
1677 rxch->teardown_pending = 0;
1678 emac_write(EMAC_RXINTMASKCLEAR, BIT(ch));
1679 }
1680 }
1681
1682 /**
1683 * emac_cleanup_rxch: Book-keep function to clean RX channel resources
1684 * @priv: The DaVinci EMAC private adapter structure
1685 * @ch: RX channel number
1686 *
1687 * Called during device stop to clean up RX channel resources
1688 *
1689 */
1690 static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch)
1691 {
1692 struct emac_rxch *rxch = priv->rxch[ch];
1693 struct emac_rx_bd __iomem *curr_bd;
1694
1695 if (rxch) {
1696 /* free the receive buffers previously allocated */
1697 curr_bd = rxch->active_queue_head;
1698 while (curr_bd) {
1699 if (curr_bd->buf_token) {
1700 dev_kfree_skb_any((struct sk_buff *)\
1701 curr_bd->buf_token);
1702 }
1703 curr_bd = curr_bd->next;
1704 }
1705 if (rxch->bd_mem)
1706 rxch->bd_mem = NULL;
1707 kfree(rxch);
1708 priv->rxch[ch] = NULL;
1709 }
1710 }
1711
1712 /**
1713 * emac_set_type0addr: Set EMAC Type0 mac address
1714 * @priv: The DaVinci EMAC private adapter structure
1715 * @ch: RX channel number
1716 * @mac_addr: MAC address to set in device
1717 *
1718 * Called internally to set Type0 mac address of the adapter (Device)
1719 *
1720 * Returns success (0) or appropriate error code (none as of now)
1721 */
1722 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1723 {
1724 u32 val;
1725 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1726 emac_write(EMAC_MACSRCADDRLO, val);
1727
1728 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1729 (mac_addr[1] << 8) | (mac_addr[0]));
1730 emac_write(EMAC_MACSRCADDRHI, val);
1731 val = emac_read(EMAC_RXUNICASTSET);
1732 val |= BIT(ch);
1733 emac_write(EMAC_RXUNICASTSET, val);
1734 val = emac_read(EMAC_RXUNICASTCLEAR);
1735 val &= ~BIT(ch);
1736 emac_write(EMAC_RXUNICASTCLEAR, val);
1737 }
1738
1739 /**
1740 * emac_set_type1addr: Set EMAC Type1 mac address
1741 * @priv: The DaVinci EMAC private adapter structure
1742 * @ch: RX channel number
1743 * @mac_addr: MAC address to set in device
1744 *
1745 * Called internally to set Type1 mac address of the adapter (Device)
1746 *
1747 * Returns success (0) or appropriate error code (none as of now)
1748 */
1749 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1750 {
1751 u32 val;
1752 emac_write(EMAC_MACINDEX, ch);
1753 val = ((mac_addr[5] << 8) | mac_addr[4]);
1754 emac_write(EMAC_MACADDRLO, val);
1755 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1756 (mac_addr[1] << 8) | (mac_addr[0]));
1757 emac_write(EMAC_MACADDRHI, val);
1758 emac_set_type0addr(priv, ch, mac_addr);
1759 }
1760
1761 /**
1762 * emac_set_type2addr: Set EMAC Type2 mac address
1763 * @priv: The DaVinci EMAC private adapter structure
1764 * @ch: RX channel number
1765 * @mac_addr: MAC address to set in device
1766 * @index: index into RX address entries
1767 * @match: match parameter for RX address matching logic
1768 *
1769 * Called internally to set Type2 mac address of the adapter (Device)
1770 *
1771 * Returns success (0) or appropriate error code (none as of now)
1772 */
1773 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1774 char *mac_addr, int index, int match)
1775 {
1776 u32 val;
1777 emac_write(EMAC_MACINDEX, index);
1778 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1779 (mac_addr[1] << 8) | (mac_addr[0]));
1780 emac_write(EMAC_MACADDRHI, val);
1781 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1782 (match << 19) | BIT(20));
1783 emac_write(EMAC_MACADDRLO, val);
1784 emac_set_type0addr(priv, ch, mac_addr);
1785 }
1786
1787 /**
1788 * emac_setmac: Set mac address in the adapter (internal function)
1789 * @priv: The DaVinci EMAC private adapter structure
1790 * @ch: RX channel number
1791 * @mac_addr: MAC address to set in device
1792 *
1793 * Called internally to set the mac address of the adapter (Device)
1794 *
1795 * Returns success (0) or appropriate error code (none as of now)
1796 */
1797 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1798 {
1799 struct device *emac_dev = &priv->ndev->dev;
1800
1801 if (priv->rx_addr_type == 0) {
1802 emac_set_type0addr(priv, ch, mac_addr);
1803 } else if (priv->rx_addr_type == 1) {
1804 u32 cnt;
1805 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1806 emac_set_type1addr(priv, ch, mac_addr);
1807 } else if (priv->rx_addr_type == 2) {
1808 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1809 emac_set_type0addr(priv, ch, mac_addr);
1810 } else {
1811 if (netif_msg_drv(priv))
1812 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1813 }
1814 }
1815
1816 /**
1817 * emac_dev_setmac_addr: Set mac address in the adapter
1818 * @ndev: The DaVinci EMAC network adapter
1819 * @addr: MAC address to set in device
1820 *
1821 * Called by the system to set the mac address of the adapter (Device)
1822 *
1823 * Returns success (0) or appropriate error code (none as of now)
1824 */
1825 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1826 {
1827 struct emac_priv *priv = netdev_priv(ndev);
1828 struct emac_rxch *rxch = priv->rxch[EMAC_DEF_RX_CH];
1829 struct device *emac_dev = &priv->ndev->dev;
1830 struct sockaddr *sa = addr;
1831
1832 if (!is_valid_ether_addr(sa->sa_data))
1833 return -EINVAL;
1834
1835 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1836 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1837 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1838
1839 /* If the interface is down - rxch is NULL. */
1840 /* MAC address is configured only after the interface is enabled. */
1841 if (netif_running(ndev)) {
1842 memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len);
1843 emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr);
1844 }
1845
1846 if (netif_msg_drv(priv))
1847 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1848 priv->mac_addr);
1849
1850 return 0;
1851 }
1852
1853 /**
1854 * emac_addbd_to_rx_queue: Recycle RX buffer descriptor
1855 * @priv: The DaVinci EMAC private adapter structure
1856 * @ch: RX channel number to process buffer descriptors for
1857 * @curr_bd: current buffer descriptor
1858 * @buffer: buffer pointer for descriptor
1859 * @buf_token: buffer token (stores skb information)
1860 *
1861 * Prepares the recycled buffer descriptor and addes it to hardware
1862 * receive queue - if queue empty this descriptor becomes the head
1863 * else addes the descriptor to end of queue
1864 *
1865 */
1866 static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1867 struct emac_rx_bd __iomem *curr_bd,
1868 char *buffer, void *buf_token)
1869 {
1870 struct emac_rxch *rxch = priv->rxch[ch];
1871
1872 /* populate the hardware descriptor */
1873 curr_bd->h_next = 0;
1874 /* FIXME buff_ptr = dma_map_single(... buffer ...) */
1875 curr_bd->buff_ptr = virt_to_phys(buffer);
1876 curr_bd->off_b_len = rxch->buf_size;
1877 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1878 curr_bd->next = NULL;
1879 curr_bd->data_ptr = buffer;
1880 curr_bd->buf_token = buf_token;
1881
1882 /* write back */
1883 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1884 if (rxch->active_queue_head == NULL) {
1885 rxch->active_queue_head = curr_bd;
1886 rxch->active_queue_tail = curr_bd;
1887 if (0 != rxch->queue_active) {
1888 emac_write(EMAC_RXHDP(ch),
1889 emac_virt_to_phys(rxch->active_queue_head, priv));
1890 rxch->queue_active = 1;
1891 }
1892 } else {
1893 struct emac_rx_bd __iomem *tail_bd;
1894 u32 frame_status;
1895
1896 tail_bd = rxch->active_queue_tail;
1897 rxch->active_queue_tail = curr_bd;
1898 tail_bd->next = curr_bd;
1899 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1900 tail_bd->h_next = emac_virt_to_phys(curr_bd, priv);
1901 frame_status = tail_bd->mode;
1902 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1903 emac_write(EMAC_RXHDP(ch),
1904 emac_virt_to_phys(curr_bd, priv));
1905 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1906 tail_bd->mode = frame_status;
1907 ++rxch->end_of_queue_add;
1908 }
1909 }
1910 ++rxch->recycled_bd;
1911 }
1912
1913 /**
1914 * emac_net_rx_cb: Prepares packet and sends to upper layer
1915 * @priv: The DaVinci EMAC private adapter structure
1916 * @net_pkt_list: Network packet list (received packets)
1917 *
1918 * Invalidates packet buffer memory and sends the received packet to upper
1919 * layer
1920 *
1921 * Returns success or appropriate error code (none as of now)
1922 */
1923 static int emac_net_rx_cb(struct emac_priv *priv,
1924 struct emac_netpktobj *net_pkt_list)
1925 {
1926 struct sk_buff *p_skb;
1927 p_skb = (struct sk_buff *)net_pkt_list->pkt_token;
1928 /* set length of packet */
1929 skb_put(p_skb, net_pkt_list->pkt_length);
1930 EMAC_CACHE_INVALIDATE((unsigned long)p_skb->data, p_skb->len);
1931 p_skb->protocol = eth_type_trans(p_skb, priv->ndev);
1932 netif_receive_skb(p_skb);
1933 priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length;
1934 priv->net_dev_stats.rx_packets++;
1935 return 0;
1936 }
1937
1938 /**
1939 * emac_rx_bdproc: RX buffer descriptor (packet) processing
1940 * @priv: The DaVinci EMAC private adapter structure
1941 * @ch: RX channel number to process buffer descriptors for
1942 * @budget: number of packets allowed to process
1943 * @pending: indication to caller that packets are pending to process
1944 *
1945 * Processes RX buffer descriptors - checks ownership bit on the RX buffer
1946 * descriptor, sends the receive packet to upper layer, allocates a new SKB
1947 * and recycles the buffer descriptor (requeues it in hardware RX queue).
1948 * Only "budget" number of packets are processed and indication of pending
1949 * packets provided to the caller.
1950 *
1951 * Returns number of packets processed (and indication of pending packets)
1952 */
1953 static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1954 {
1955 unsigned long flags;
1956 u32 frame_status;
1957 u32 pkts_processed = 0;
1958 char *new_buffer;
1959 struct emac_rx_bd __iomem *curr_bd;
1960 struct emac_rx_bd __iomem *last_bd;
1961 struct emac_netpktobj *curr_pkt, pkt_obj;
1962 struct emac_netbufobj buf_obj;
1963 struct emac_netbufobj *rx_buf_obj;
1964 void *new_buf_token;
1965 struct emac_rxch *rxch = priv->rxch[ch];
1966
1967 if (unlikely(1 == rxch->teardown_pending))
1968 return 0;
1969 ++rxch->proc_count;
1970 spin_lock_irqsave(&priv->rx_lock, flags);
1971 pkt_obj.buf_list = &buf_obj;
1972 curr_pkt = &pkt_obj;
1973 curr_bd = rxch->active_queue_head;
1974 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1975 frame_status = curr_bd->mode;
1976
1977 while ((curr_bd) &&
1978 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1979 (pkts_processed < budget)) {
1980
1981 new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size,
1982 &new_buf_token, EMAC_DEF_RX_CH);
1983 if (unlikely(NULL == new_buffer)) {
1984 ++rxch->out_of_rx_buffers;
1985 goto end_emac_rx_bdproc;
1986 }
1987
1988 /* populate received packet data structure */
1989 rx_buf_obj = &curr_pkt->buf_list[0];
1990 rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
1991 rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
1992 rx_buf_obj->buf_token = curr_bd->buf_token;
1993 curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
1994 curr_pkt->num_bufs = 1;
1995 curr_pkt->pkt_length =
1996 (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
1997 emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd, priv));
1998 ++rxch->processed_bd;
1999 last_bd = curr_bd;
2000 curr_bd = last_bd->next;
2001 rxch->active_queue_head = curr_bd;
2002
2003 /* check if end of RX queue ? */
2004 if (frame_status & EMAC_CPPI_EOQ_BIT) {
2005 if (curr_bd) {
2006 ++rxch->mis_queued_packets;
2007 emac_write(EMAC_RXHDP(ch),
2008 emac_virt_to_phys(curr_bd, priv));
2009 } else {
2010 ++rxch->end_of_queue;
2011 rxch->queue_active = 0;
2012 }
2013 }
2014
2015 /* recycle BD */
2016 emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer,
2017 new_buf_token);
2018
2019 /* return the packet to the user - BD ptr passed in
2020 * last parameter for potential *future* use */
2021 spin_unlock_irqrestore(&priv->rx_lock, flags);
2022 emac_net_rx_cb(priv, curr_pkt);
2023 spin_lock_irqsave(&priv->rx_lock, flags);
2024 curr_bd = rxch->active_queue_head;
2025 if (curr_bd) {
2026 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2027 frame_status = curr_bd->mode;
2028 }
2029 ++pkts_processed;
2030 }
2031
2032 end_emac_rx_bdproc:
2033 spin_unlock_irqrestore(&priv->rx_lock, flags);
2034 return pkts_processed;
2035 }
2036
2037 /**
2038 * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
2039 * @priv: The DaVinci EMAC private adapter structure
2040 *
2041 * Enables EMAC hardware for packet processing - enables PHY, enables RX
2042 * for packet reception and enables device interrupts and then NAPI
2043 *
2044 * Returns success (0) or appropriate error code (none right now)
2045 */
2046 static int emac_hw_enable(struct emac_priv *priv)
2047 {
2048 u32 ch, val, mbp_enable, mac_control;
2049
2050 /* Soft reset */
2051 emac_write(EMAC_SOFTRESET, 1);
2052 while (emac_read(EMAC_SOFTRESET))
2053 cpu_relax();
2054
2055 /* Disable interrupt & Set pacing for more interrupts initially */
2056 emac_int_disable(priv);
2057
2058 /* Full duplex enable bit set when auto negotiation happens */
2059 mac_control =
2060 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
2061 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
2062 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
2063 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
2064 emac_write(EMAC_MACCONTROL, mac_control);
2065
2066 mbp_enable =
2067 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
2068 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
2069 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
2070 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
2071 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
2072 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
2073 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
2074 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
2075 EMAC_RXMBP_PROMCH_SHIFT) |
2076 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
2077 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
2078 EMAC_RXMBP_BROADCH_SHIFT) |
2079 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
2080 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
2081 EMAC_RXMBP_MULTICH_SHIFT));
2082 emac_write(EMAC_RXMBPENABLE, mbp_enable);
2083 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
2084 EMAC_RX_MAX_LEN_MASK));
2085 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
2086 EMAC_RX_BUFFER_OFFSET_MASK));
2087 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
2088 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
2089 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
2090
2091 val = emac_read(EMAC_TXCONTROL);
2092 val |= EMAC_TX_CONTROL_TX_ENABLE_VAL;
2093 emac_write(EMAC_TXCONTROL, val);
2094 val = emac_read(EMAC_RXCONTROL);
2095 val |= EMAC_RX_CONTROL_RX_ENABLE_VAL;
2096 emac_write(EMAC_RXCONTROL, val);
2097 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
2098
2099 for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) {
2100 emac_write(EMAC_TXHDP(ch), 0);
2101 emac_write(EMAC_TXINTMASKSET, BIT(ch));
2102 }
2103 for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) {
2104 struct emac_rxch *rxch = priv->rxch[ch];
2105 emac_setmac(priv, ch, rxch->mac_addr);
2106 emac_write(EMAC_RXINTMASKSET, BIT(ch));
2107 rxch->queue_active = 1;
2108 emac_write(EMAC_RXHDP(ch),
2109 emac_virt_to_phys(rxch->active_queue_head, priv));
2110 }
2111
2112 /* Enable MII */
2113 val = emac_read(EMAC_MACCONTROL);
2114 val |= (EMAC_MACCONTROL_GMIIEN);
2115 emac_write(EMAC_MACCONTROL, val);
2116
2117 /* Enable NAPI and interrupts */
2118 napi_enable(&priv->napi);
2119 emac_int_enable(priv);
2120 return 0;
2121
2122 }
2123
2124 /**
2125 * emac_poll: EMAC NAPI Poll function
2126 * @ndev: The DaVinci EMAC network adapter
2127 * @budget: Number of receive packets to process (as told by NAPI layer)
2128 *
2129 * NAPI Poll function implemented to process packets as per budget. We check
2130 * the type of interrupt on the device and accordingly call the TX or RX
2131 * packet processing functions. We follow the budget for RX processing and
2132 * also put a cap on number of TX pkts processed through config param. The
2133 * NAPI schedule function is called if more packets pending.
2134 *
2135 * Returns number of packets received (in most cases; else TX pkts - rarely)
2136 */
2137 static int emac_poll(struct napi_struct *napi, int budget)
2138 {
2139 unsigned int mask;
2140 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
2141 struct net_device *ndev = priv->ndev;
2142 struct device *emac_dev = &ndev->dev;
2143 u32 status = 0;
2144 u32 num_pkts = 0;
2145
2146 /* Check interrupt vectors and call packet processing */
2147 status = emac_read(EMAC_MACINVECTOR);
2148
2149 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
2150
2151 if (priv->version == EMAC_VERSION_2)
2152 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
2153
2154 if (status & mask) {
2155 num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
2156 EMAC_DEF_TX_MAX_SERVICE);
2157 } /* TX processing */
2158
2159 if (num_pkts)
2160 return budget;
2161
2162 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
2163
2164 if (priv->version == EMAC_VERSION_2)
2165 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
2166
2167 if (status & mask) {
2168 num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget);
2169 } /* RX processing */
2170
2171 if (num_pkts < budget) {
2172 napi_complete(napi);
2173 emac_int_enable(priv);
2174 }
2175
2176 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
2177 if (priv->version == EMAC_VERSION_2)
2178 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
2179
2180 if (unlikely(status & mask)) {
2181 u32 ch, cause;
2182 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
2183 netif_stop_queue(ndev);
2184 napi_disable(&priv->napi);
2185
2186 status = emac_read(EMAC_MACSTATUS);
2187 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
2188 EMAC_MACSTATUS_TXERRCODE_SHIFT);
2189 if (cause) {
2190 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
2191 EMAC_MACSTATUS_TXERRCH_SHIFT);
2192 if (net_ratelimit()) {
2193 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
2194 &emac_txhost_errcodes[cause][0], ch);
2195 }
2196 }
2197 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
2198 EMAC_MACSTATUS_RXERRCODE_SHIFT);
2199 if (cause) {
2200 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
2201 EMAC_MACSTATUS_RXERRCH_SHIFT);
2202 if (netif_msg_hw(priv) && net_ratelimit())
2203 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
2204 &emac_rxhost_errcodes[cause][0], ch);
2205 }
2206 } /* Host error processing */
2207
2208 return num_pkts;
2209 }
2210
2211 #ifdef CONFIG_NET_POLL_CONTROLLER
2212 /**
2213 * emac_poll_controller: EMAC Poll controller function
2214 * @ndev: The DaVinci EMAC network adapter
2215 *
2216 * Polled functionality used by netconsole and others in non interrupt mode
2217 *
2218 */
2219 void emac_poll_controller(struct net_device *ndev)
2220 {
2221 struct emac_priv *priv = netdev_priv(ndev);
2222
2223 emac_int_disable(priv);
2224 emac_irq(ndev->irq, ndev);
2225 emac_int_enable(priv);
2226 }
2227 #endif
2228
2229 /* PHY/MII bus related */
2230
2231 /* Wait until mdio is ready for next command */
2232 #define MDIO_WAIT_FOR_USER_ACCESS\
2233 while ((emac_mdio_read((MDIO_USERACCESS(0))) &\
2234 MDIO_USERACCESS_GO) != 0)
2235
2236 static int emac_mii_read(struct mii_bus *bus, int phy_id, int phy_reg)
2237 {
2238 unsigned int phy_data = 0;
2239 unsigned int phy_control;
2240
2241 /* Wait until mdio is ready for next command */
2242 MDIO_WAIT_FOR_USER_ACCESS;
2243
2244 phy_control = (MDIO_USERACCESS_GO |
2245 MDIO_USERACCESS_READ |
2246 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2247 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2248 (phy_data & MDIO_USERACCESS_DATA));
2249 emac_mdio_write(MDIO_USERACCESS(0), phy_control);
2250
2251 /* Wait until mdio is ready for next command */
2252 MDIO_WAIT_FOR_USER_ACCESS;
2253
2254 return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA;
2255
2256 }
2257
2258 static int emac_mii_write(struct mii_bus *bus, int phy_id,
2259 int phy_reg, u16 phy_data)
2260 {
2261
2262 unsigned int control;
2263
2264 /* until mdio is ready for next command */
2265 MDIO_WAIT_FOR_USER_ACCESS;
2266
2267 control = (MDIO_USERACCESS_GO |
2268 MDIO_USERACCESS_WRITE |
2269 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2270 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2271 (phy_data & MDIO_USERACCESS_DATA));
2272 emac_mdio_write(MDIO_USERACCESS(0), control);
2273
2274 return 0;
2275 }
2276
2277 static int emac_mii_reset(struct mii_bus *bus)
2278 {
2279 unsigned int clk_div;
2280 int mdio_bus_freq = emac_bus_frequency;
2281
2282 if (mdio_max_freq && mdio_bus_freq)
2283 clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
2284 else
2285 clk_div = 0xFF;
2286
2287 clk_div &= MDIO_CONTROL_CLKDIV;
2288
2289 /* Set enable and clock divider in MDIOControl */
2290 emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE));
2291
2292 return 0;
2293
2294 }
2295
2296 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, PHY_POLL };
2297
2298 /* emac_driver: EMAC MII bus structure */
2299
2300 static struct mii_bus *emac_mii;
2301
2302 static void emac_adjust_link(struct net_device *ndev)
2303 {
2304 struct emac_priv *priv = netdev_priv(ndev);
2305 struct phy_device *phydev = priv->phydev;
2306 unsigned long flags;
2307 int new_state = 0;
2308
2309 spin_lock_irqsave(&priv->lock, flags);
2310
2311 if (phydev->link) {
2312 /* check the mode of operation - full/half duplex */
2313 if (phydev->duplex != priv->duplex) {
2314 new_state = 1;
2315 priv->duplex = phydev->duplex;
2316 }
2317 if (phydev->speed != priv->speed) {
2318 new_state = 1;
2319 priv->speed = phydev->speed;
2320 }
2321 if (!priv->link) {
2322 new_state = 1;
2323 priv->link = 1;
2324 }
2325
2326 } else if (priv->link) {
2327 new_state = 1;
2328 priv->link = 0;
2329 priv->speed = 0;
2330 priv->duplex = ~0;
2331 }
2332 if (new_state) {
2333 emac_update_phystatus(priv);
2334 phy_print_status(priv->phydev);
2335 }
2336
2337 spin_unlock_irqrestore(&priv->lock, flags);
2338 }
2339
2340 /*************************************************************************
2341 * Linux Driver Model
2342 *************************************************************************/
2343
2344 /**
2345 * emac_devioctl: EMAC adapter ioctl
2346 * @ndev: The DaVinci EMAC network adapter
2347 * @ifrq: request parameter
2348 * @cmd: command parameter
2349 *
2350 * EMAC driver ioctl function
2351 *
2352 * Returns success(0) or appropriate error code
2353 */
2354 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
2355 {
2356 dev_warn(&ndev->dev, "DaVinci EMAC: ioctl not supported\n");
2357
2358 if (!(netif_running(ndev)))
2359 return -EINVAL;
2360
2361 /* TODO: Add phy read and write and private statistics get feature */
2362
2363 return -EOPNOTSUPP;
2364 }
2365
2366 /**
2367 * emac_dev_open: EMAC device open
2368 * @ndev: The DaVinci EMAC network adapter
2369 *
2370 * Called when system wants to start the interface. We init TX/RX channels
2371 * and enable the hardware for packet reception/transmission and start the
2372 * network queue.
2373 *
2374 * Returns 0 for a successful open, or appropriate error code
2375 */
2376 static int emac_dev_open(struct net_device *ndev)
2377 {
2378 struct device *emac_dev = &ndev->dev;
2379 u32 rc, cnt, ch;
2380 int phy_addr;
2381 struct resource *res;
2382 int q, m;
2383 int i = 0;
2384 int k = 0;
2385 struct emac_priv *priv = netdev_priv(ndev);
2386
2387 netif_carrier_off(ndev);
2388 for (cnt = 0; cnt < ETH_ALEN; cnt++)
2389 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
2390
2391 /* Configuration items */
2392 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
2393
2394 /* Clear basic hardware */
2395 for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) {
2396 emac_write(EMAC_TXHDP(ch), 0);
2397 emac_write(EMAC_RXHDP(ch), 0);
2398 emac_write(EMAC_RXHDP(ch), 0);
2399 emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2400 emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2401 }
2402 priv->mac_hash1 = 0;
2403 priv->mac_hash2 = 0;
2404 emac_write(EMAC_MACHASH1, 0);
2405 emac_write(EMAC_MACHASH2, 0);
2406
2407 /* multi ch not supported - open 1 TX, 1RX ch by default */
2408 rc = emac_init_txch(priv, EMAC_DEF_TX_CH);
2409 if (0 != rc) {
2410 dev_err(emac_dev, "DaVinci EMAC: emac_init_txch() failed");
2411 return rc;
2412 }
2413 rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr);
2414 if (0 != rc) {
2415 dev_err(emac_dev, "DaVinci EMAC: emac_init_rxch() failed");
2416 return rc;
2417 }
2418
2419 /* Request IRQ */
2420
2421 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2422 for (i = res->start; i <= res->end; i++) {
2423 if (request_irq(i, emac_irq, IRQF_DISABLED,
2424 ndev->name, ndev))
2425 goto rollback;
2426 }
2427 k++;
2428 }
2429
2430 /* Start/Enable EMAC hardware */
2431 emac_hw_enable(priv);
2432
2433 /* find the first phy */
2434 priv->phydev = NULL;
2435 if (priv->phy_mask) {
2436 emac_mii_reset(priv->mii_bus);
2437 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
2438 if (priv->mii_bus->phy_map[phy_addr]) {
2439 priv->phydev = priv->mii_bus->phy_map[phy_addr];
2440 break;
2441 }
2442 }
2443
2444 if (!priv->phydev) {
2445 printk(KERN_ERR "%s: no PHY found\n", ndev->name);
2446 return -1;
2447 }
2448
2449 priv->phydev = phy_connect(ndev, dev_name(&priv->phydev->dev),
2450 &emac_adjust_link, 0, PHY_INTERFACE_MODE_MII);
2451
2452 if (IS_ERR(priv->phydev)) {
2453 printk(KERN_ERR "%s: Could not attach to PHY\n",
2454 ndev->name);
2455 return PTR_ERR(priv->phydev);
2456 }
2457
2458 priv->link = 0;
2459 priv->speed = 0;
2460 priv->duplex = ~0;
2461
2462 printk(KERN_INFO "%s: attached PHY driver [%s] "
2463 "(mii_bus:phy_addr=%s, id=%x)\n", ndev->name,
2464 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
2465 priv->phydev->phy_id);
2466 } else{
2467 /* No PHY , fix the link, speed and duplex settings */
2468 priv->link = 1;
2469 priv->speed = SPEED_100;
2470 priv->duplex = DUPLEX_FULL;
2471 emac_update_phystatus(priv);
2472 }
2473
2474 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
2475 emac_dump_regs(priv);
2476
2477 if (netif_msg_drv(priv))
2478 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
2479
2480 if (priv->phy_mask)
2481 phy_start(priv->phydev);
2482
2483 return 0;
2484
2485 rollback:
2486
2487 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
2488
2489 for (q = k; k >= 0; k--) {
2490 for (m = i; m >= res->start; m--)
2491 free_irq(m, ndev);
2492 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
2493 m = res->end;
2494 }
2495 return -EBUSY;
2496 }
2497
2498 /**
2499 * emac_dev_stop: EMAC device stop
2500 * @ndev: The DaVinci EMAC network adapter
2501 *
2502 * Called when system wants to stop or down the interface. We stop the network
2503 * queue, disable interrupts and cleanup TX/RX channels.
2504 *
2505 * We return the statistics in net_device_stats structure pulled from emac
2506 */
2507 static int emac_dev_stop(struct net_device *ndev)
2508 {
2509 struct resource *res;
2510 int i = 0;
2511 int irq_num;
2512 struct emac_priv *priv = netdev_priv(ndev);
2513 struct device *emac_dev = &ndev->dev;
2514
2515 /* inform the upper layers. */
2516 netif_stop_queue(ndev);
2517 napi_disable(&priv->napi);
2518
2519 netif_carrier_off(ndev);
2520 emac_int_disable(priv);
2521 emac_stop_txch(priv, EMAC_DEF_TX_CH);
2522 emac_stop_rxch(priv, EMAC_DEF_RX_CH);
2523 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
2524 emac_cleanup_rxch(priv, EMAC_DEF_RX_CH);
2525 emac_write(EMAC_SOFTRESET, 1);
2526
2527 if (priv->phydev)
2528 phy_disconnect(priv->phydev);
2529
2530 /* Free IRQ */
2531 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
2532 for (irq_num = res->start; irq_num <= res->end; irq_num++)
2533 free_irq(irq_num, priv->ndev);
2534 i++;
2535 }
2536
2537 if (netif_msg_drv(priv))
2538 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
2539
2540 return 0;
2541 }
2542
2543 /**
2544 * emac_dev_getnetstats: EMAC get statistics function
2545 * @ndev: The DaVinci EMAC network adapter
2546 *
2547 * Called when system wants to get statistics from the device.
2548 *
2549 * We return the statistics in net_device_stats structure pulled from emac
2550 */
2551 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
2552 {
2553 struct emac_priv *priv = netdev_priv(ndev);
2554 u32 mac_control;
2555 u32 stats_clear_mask;
2556
2557 /* update emac hardware stats and reset the registers*/
2558
2559 mac_control = emac_read(EMAC_MACCONTROL);
2560
2561 if (mac_control & EMAC_MACCONTROL_GMIIEN)
2562 stats_clear_mask = EMAC_STATS_CLR_MASK;
2563 else
2564 stats_clear_mask = 0;
2565
2566 priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
2567 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
2568
2569 priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) +
2570 emac_read(EMAC_TXSINGLECOLL) +
2571 emac_read(EMAC_TXMULTICOLL));
2572 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
2573 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
2574 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
2575
2576 priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
2577 emac_read(EMAC_RXJABBER) +
2578 emac_read(EMAC_RXUNDERSIZED));
2579 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
2580 emac_write(EMAC_RXJABBER, stats_clear_mask);
2581 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
2582
2583 priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
2584 emac_read(EMAC_RXMOFOVERRUNS));
2585 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
2586 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
2587
2588 priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
2589 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
2590
2591 priv->net_dev_stats.tx_carrier_errors +=
2592 emac_read(EMAC_TXCARRIERSENSE);
2593 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
2594
2595 priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
2596 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
2597
2598 return &priv->net_dev_stats;
2599 }
2600
2601 static const struct net_device_ops emac_netdev_ops = {
2602 .ndo_open = emac_dev_open,
2603 .ndo_stop = emac_dev_stop,
2604 .ndo_start_xmit = emac_dev_xmit,
2605 .ndo_set_multicast_list = emac_dev_mcast_set,
2606 .ndo_set_mac_address = emac_dev_setmac_addr,
2607 .ndo_do_ioctl = emac_devioctl,
2608 .ndo_tx_timeout = emac_dev_tx_timeout,
2609 .ndo_get_stats = emac_dev_getnetstats,
2610 #ifdef CONFIG_NET_POLL_CONTROLLER
2611 .ndo_poll_controller = emac_poll_controller,
2612 #endif
2613 };
2614
2615 /**
2616 * davinci_emac_probe: EMAC device probe
2617 * @pdev: The DaVinci EMAC device that we are removing
2618 *
2619 * Called when probing for emac devicesr. We get details of instances and
2620 * resource information from platform init and register a network device
2621 * and allocate resources necessary for driver to perform
2622 */
2623 static int __devinit davinci_emac_probe(struct platform_device *pdev)
2624 {
2625 int rc = 0;
2626 struct resource *res;
2627 struct net_device *ndev;
2628 struct emac_priv *priv;
2629 unsigned long size;
2630 struct emac_platform_data *pdata;
2631 struct device *emac_dev;
2632
2633 /* obtain emac clock from kernel */
2634 emac_clk = clk_get(&pdev->dev, NULL);
2635 if (IS_ERR(emac_clk)) {
2636 printk(KERN_ERR "DaVinci EMAC: Failed to get EMAC clock\n");
2637 return -EBUSY;
2638 }
2639 emac_bus_frequency = clk_get_rate(emac_clk);
2640 /* TODO: Probe PHY here if possible */
2641
2642 ndev = alloc_etherdev(sizeof(struct emac_priv));
2643 if (!ndev) {
2644 printk(KERN_ERR "DaVinci EMAC: Error allocating net_device\n");
2645 clk_put(emac_clk);
2646 return -ENOMEM;
2647 }
2648
2649 platform_set_drvdata(pdev, ndev);
2650 priv = netdev_priv(ndev);
2651 priv->pdev = pdev;
2652 priv->ndev = ndev;
2653 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
2654
2655 spin_lock_init(&priv->tx_lock);
2656 spin_lock_init(&priv->rx_lock);
2657 spin_lock_init(&priv->lock);
2658
2659 pdata = pdev->dev.platform_data;
2660 if (!pdata) {
2661 printk(KERN_ERR "DaVinci EMAC: No platfrom data\n");
2662 return -ENODEV;
2663 }
2664
2665 /* MAC addr and PHY mask , RMII enable info from platform_data */
2666 memcpy(priv->mac_addr, pdata->mac_addr, 6);
2667 priv->phy_mask = pdata->phy_mask;
2668 priv->rmii_en = pdata->rmii_en;
2669 priv->version = pdata->version;
2670 priv->int_enable = pdata->interrupt_enable;
2671 priv->int_disable = pdata->interrupt_disable;
2672
2673 emac_dev = &ndev->dev;
2674 /* Get EMAC platform data */
2675 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2676 if (!res) {
2677 dev_err(emac_dev, "DaVinci EMAC: Error getting res\n");
2678 rc = -ENOENT;
2679 goto probe_quit;
2680 }
2681
2682 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
2683 size = res->end - res->start + 1;
2684 if (!request_mem_region(res->start, size, ndev->name)) {
2685 dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() for regs\n");
2686 rc = -ENXIO;
2687 goto probe_quit;
2688 }
2689
2690 priv->remap_addr = ioremap(res->start, size);
2691 if (!priv->remap_addr) {
2692 dev_err(emac_dev, "Unable to map IO\n");
2693 rc = -ENOMEM;
2694 release_mem_region(res->start, size);
2695 goto probe_quit;
2696 }
2697 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
2698 ndev->base_addr = (unsigned long)priv->remap_addr;
2699
2700 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
2701 priv->ctrl_ram_size = pdata->ctrl_ram_size;
2702 priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
2703
2704 if (pdata->hw_ram_addr)
2705 priv->hw_ram_addr = pdata->hw_ram_addr;
2706 else
2707 priv->hw_ram_addr = (u32 __force)res->start +
2708 pdata->ctrl_ram_offset;
2709
2710 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2711 if (!res) {
2712 dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n");
2713 rc = -ENOENT;
2714 goto no_irq_res;
2715 }
2716 ndev->irq = res->start;
2717
2718 if (!is_valid_ether_addr(priv->mac_addr)) {
2719 /* Use random MAC if none passed */
2720 random_ether_addr(priv->mac_addr);
2721 printk(KERN_WARNING "%s: using random MAC addr: %pM\n",
2722 __func__, priv->mac_addr);
2723 }
2724
2725 ndev->netdev_ops = &emac_netdev_ops;
2726 SET_ETHTOOL_OPS(ndev, &ethtool_ops);
2727 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
2728
2729 clk_enable(emac_clk);
2730
2731 /* register the network device */
2732 SET_NETDEV_DEV(ndev, &pdev->dev);
2733 rc = register_netdev(ndev);
2734 if (rc) {
2735 dev_err(emac_dev, "DaVinci EMAC: Error in register_netdev\n");
2736 rc = -ENODEV;
2737 goto netdev_reg_err;
2738 }
2739
2740
2741 /* MII/Phy intialisation, mdio bus registration */
2742 emac_mii = mdiobus_alloc();
2743 if (emac_mii == NULL) {
2744 dev_err(emac_dev, "DaVinci EMAC: Error allocating mii_bus\n");
2745 rc = -ENOMEM;
2746 goto mdio_alloc_err;
2747 }
2748
2749 priv->mii_bus = emac_mii;
2750 emac_mii->name = "emac-mii",
2751 emac_mii->read = emac_mii_read,
2752 emac_mii->write = emac_mii_write,
2753 emac_mii->reset = emac_mii_reset,
2754 emac_mii->irq = mii_irqs,
2755 emac_mii->phy_mask = ~(priv->phy_mask);
2756 emac_mii->parent = &pdev->dev;
2757 emac_mii->priv = priv->remap_addr + pdata->mdio_reg_offset;
2758 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", priv->pdev->id);
2759 mdio_max_freq = pdata->mdio_max_freq;
2760 emac_mii->reset(emac_mii);
2761
2762 /* Register the MII bus */
2763 rc = mdiobus_register(emac_mii);
2764 if (rc)
2765 goto mdiobus_quit;
2766
2767 if (netif_msg_probe(priv)) {
2768 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
2769 "(regs: %p, irq: %d)\n",
2770 (void *)priv->emac_base_phys, ndev->irq);
2771 }
2772 return 0;
2773
2774 mdiobus_quit:
2775 mdiobus_free(emac_mii);
2776
2777 netdev_reg_err:
2778 mdio_alloc_err:
2779 clk_disable(emac_clk);
2780 no_irq_res:
2781 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2782 release_mem_region(res->start, res->end - res->start + 1);
2783 iounmap(priv->remap_addr);
2784
2785 probe_quit:
2786 clk_put(emac_clk);
2787 free_netdev(ndev);
2788 return rc;
2789 }
2790
2791 /**
2792 * davinci_emac_remove: EMAC device remove
2793 * @pdev: The DaVinci EMAC device that we are removing
2794 *
2795 * Called when removing the device driver. We disable clock usage and release
2796 * the resources taken up by the driver and unregister network device
2797 */
2798 static int __devexit davinci_emac_remove(struct platform_device *pdev)
2799 {
2800 struct resource *res;
2801 struct net_device *ndev = platform_get_drvdata(pdev);
2802 struct emac_priv *priv = netdev_priv(ndev);
2803
2804 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2805
2806 platform_set_drvdata(pdev, NULL);
2807 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2808 mdiobus_unregister(priv->mii_bus);
2809 mdiobus_free(priv->mii_bus);
2810
2811 release_mem_region(res->start, res->end - res->start + 1);
2812
2813 unregister_netdev(ndev);
2814 free_netdev(ndev);
2815 iounmap(priv->remap_addr);
2816
2817 clk_disable(emac_clk);
2818 clk_put(emac_clk);
2819
2820 return 0;
2821 }
2822
2823 static
2824 int davinci_emac_suspend(struct platform_device *pdev, pm_message_t state)
2825 {
2826 struct net_device *dev = platform_get_drvdata(pdev);
2827
2828 if (netif_running(dev))
2829 emac_dev_stop(dev);
2830
2831 clk_disable(emac_clk);
2832
2833 return 0;
2834 }
2835
2836 static int davinci_emac_resume(struct platform_device *pdev)
2837 {
2838 struct net_device *dev = platform_get_drvdata(pdev);
2839
2840 clk_enable(emac_clk);
2841
2842 if (netif_running(dev))
2843 emac_dev_open(dev);
2844
2845 return 0;
2846 }
2847
2848 /**
2849 * davinci_emac_driver: EMAC platform driver structure
2850 */
2851 static struct platform_driver davinci_emac_driver = {
2852 .driver = {
2853 .name = "davinci_emac",
2854 .owner = THIS_MODULE,
2855 },
2856 .probe = davinci_emac_probe,
2857 .remove = __devexit_p(davinci_emac_remove),
2858 .suspend = davinci_emac_suspend,
2859 .resume = davinci_emac_resume,
2860 };
2861
2862 /**
2863 * davinci_emac_init: EMAC driver module init
2864 *
2865 * Called when initializing the driver. We register the driver with
2866 * the platform.
2867 */
2868 static int __init davinci_emac_init(void)
2869 {
2870 return platform_driver_register(&davinci_emac_driver);
2871 }
2872 late_initcall(davinci_emac_init);
2873
2874 /**
2875 * davinci_emac_exit: EMAC driver module exit
2876 *
2877 * Called when exiting the driver completely. We unregister the driver with
2878 * the platform and exit
2879 */
2880 static void __exit davinci_emac_exit(void)
2881 {
2882 platform_driver_unregister(&davinci_emac_driver);
2883 }
2884 module_exit(davinci_emac_exit);
2885
2886 MODULE_LICENSE("GPL");
2887 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2888 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2889 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree