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rtl8180: use cached queue mapping for skb in rtl8180_tx
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / cnic.c
blob9781942992e9a77c460cd339592716c0372899b7
1 /* cnic.c: Broadcom CNIC core network driver.
2 *
3 * Copyright (c) 2006-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
10 * Modified and maintained by: Michael Chan <mchan@broadcom.com>
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/module.h>
16
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/list.h>
20 #include <linux/slab.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/netdevice.h>
24 #include <linux/uio_driver.h>
25 #include <linux/in.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/delay.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
31 #define BCM_VLAN 1
32 #endif
33 #include <net/ip.h>
34 #include <net/tcp.h>
35 #include <net/route.h>
36 #include <net/ipv6.h>
37 #include <net/ip6_route.h>
38 #include <net/ip6_checksum.h>
39 #include <scsi/iscsi_if.h>
40
41 #include "cnic_if.h"
42 #include "bnx2.h"
43 #include "bnx2x_reg.h"
44 #include "bnx2x_fw_defs.h"
45 #include "bnx2x_hsi.h"
46 #include "../scsi/bnx2i/57xx_iscsi_constants.h"
47 #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
48 #include "cnic.h"
49 #include "cnic_defs.h"
50
51 #define DRV_MODULE_NAME "cnic"
52
53 static char version[] __devinitdata =
54 "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
55
56 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
57 "Chen (zongxi@broadcom.com");
58 MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
59 MODULE_LICENSE("GPL");
60 MODULE_VERSION(CNIC_MODULE_VERSION);
61
62 static LIST_HEAD(cnic_dev_list);
63 static DEFINE_RWLOCK(cnic_dev_lock);
64 static DEFINE_MUTEX(cnic_lock);
65
66 static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
67
68 static int cnic_service_bnx2(void *, void *);
69 static int cnic_service_bnx2x(void *, void *);
70 static int cnic_ctl(void *, struct cnic_ctl_info *);
71
72 static struct cnic_ops cnic_bnx2_ops = {
73 .cnic_owner = THIS_MODULE,
74 .cnic_handler = cnic_service_bnx2,
75 .cnic_ctl = cnic_ctl,
76 };
77
78 static struct cnic_ops cnic_bnx2x_ops = {
79 .cnic_owner = THIS_MODULE,
80 .cnic_handler = cnic_service_bnx2x,
81 .cnic_ctl = cnic_ctl,
82 };
83
84 static void cnic_shutdown_rings(struct cnic_dev *);
85 static void cnic_init_rings(struct cnic_dev *);
86 static int cnic_cm_set_pg(struct cnic_sock *);
87
88 static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
89 {
90 struct cnic_dev *dev = uinfo->priv;
91 struct cnic_local *cp = dev->cnic_priv;
92
93 if (!capable(CAP_NET_ADMIN))
94 return -EPERM;
95
96 if (cp->uio_dev != -1)
97 return -EBUSY;
98
99 rtnl_lock();
100 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
101 rtnl_unlock();
102 return -ENODEV;
103 }
104
105 cp->uio_dev = iminor(inode);
106
107 cnic_init_rings(dev);
108 rtnl_unlock();
109
110 return 0;
111 }
112
113 static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
114 {
115 struct cnic_dev *dev = uinfo->priv;
116 struct cnic_local *cp = dev->cnic_priv;
117
118 cnic_shutdown_rings(dev);
119
120 cp->uio_dev = -1;
121 return 0;
122 }
123
124 static inline void cnic_hold(struct cnic_dev *dev)
125 {
126 atomic_inc(&dev->ref_count);
127 }
128
129 static inline void cnic_put(struct cnic_dev *dev)
130 {
131 atomic_dec(&dev->ref_count);
132 }
133
134 static inline void csk_hold(struct cnic_sock *csk)
135 {
136 atomic_inc(&csk->ref_count);
137 }
138
139 static inline void csk_put(struct cnic_sock *csk)
140 {
141 atomic_dec(&csk->ref_count);
142 }
143
144 static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
145 {
146 struct cnic_dev *cdev;
147
148 read_lock(&cnic_dev_lock);
149 list_for_each_entry(cdev, &cnic_dev_list, list) {
150 if (netdev == cdev->netdev) {
151 cnic_hold(cdev);
152 read_unlock(&cnic_dev_lock);
153 return cdev;
154 }
155 }
156 read_unlock(&cnic_dev_lock);
157 return NULL;
158 }
159
160 static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
161 {
162 atomic_inc(&ulp_ops->ref_count);
163 }
164
165 static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
166 {
167 atomic_dec(&ulp_ops->ref_count);
168 }
169
170 static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
171 {
172 struct cnic_local *cp = dev->cnic_priv;
173 struct cnic_eth_dev *ethdev = cp->ethdev;
174 struct drv_ctl_info info;
175 struct drv_ctl_io *io = &info.data.io;
176
177 info.cmd = DRV_CTL_CTX_WR_CMD;
178 io->cid_addr = cid_addr;
179 io->offset = off;
180 io->data = val;
181 ethdev->drv_ctl(dev->netdev, &info);
182 }
183
184 static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
185 {
186 struct cnic_local *cp = dev->cnic_priv;
187 struct cnic_eth_dev *ethdev = cp->ethdev;
188 struct drv_ctl_info info;
189 struct drv_ctl_io *io = &info.data.io;
190
191 info.cmd = DRV_CTL_CTXTBL_WR_CMD;
192 io->offset = off;
193 io->dma_addr = addr;
194 ethdev->drv_ctl(dev->netdev, &info);
195 }
196
197 static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
198 {
199 struct cnic_local *cp = dev->cnic_priv;
200 struct cnic_eth_dev *ethdev = cp->ethdev;
201 struct drv_ctl_info info;
202 struct drv_ctl_l2_ring *ring = &info.data.ring;
203
204 if (start)
205 info.cmd = DRV_CTL_START_L2_CMD;
206 else
207 info.cmd = DRV_CTL_STOP_L2_CMD;
208
209 ring->cid = cid;
210 ring->client_id = cl_id;
211 ethdev->drv_ctl(dev->netdev, &info);
212 }
213
214 static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
215 {
216 struct cnic_local *cp = dev->cnic_priv;
217 struct cnic_eth_dev *ethdev = cp->ethdev;
218 struct drv_ctl_info info;
219 struct drv_ctl_io *io = &info.data.io;
220
221 info.cmd = DRV_CTL_IO_WR_CMD;
222 io->offset = off;
223 io->data = val;
224 ethdev->drv_ctl(dev->netdev, &info);
225 }
226
227 static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
228 {
229 struct cnic_local *cp = dev->cnic_priv;
230 struct cnic_eth_dev *ethdev = cp->ethdev;
231 struct drv_ctl_info info;
232 struct drv_ctl_io *io = &info.data.io;
233
234 info.cmd = DRV_CTL_IO_RD_CMD;
235 io->offset = off;
236 ethdev->drv_ctl(dev->netdev, &info);
237 return io->data;
238 }
239
240 static int cnic_in_use(struct cnic_sock *csk)
241 {
242 return test_bit(SK_F_INUSE, &csk->flags);
243 }
244
245 static void cnic_kwq_completion(struct cnic_dev *dev, u32 count)
246 {
247 struct cnic_local *cp = dev->cnic_priv;
248 struct cnic_eth_dev *ethdev = cp->ethdev;
249 struct drv_ctl_info info;
250
251 info.cmd = DRV_CTL_COMPLETION_CMD;
252 info.data.comp.comp_count = count;
253 ethdev->drv_ctl(dev->netdev, &info);
254 }
255
256 static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
257 {
258 u32 i;
259
260 for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
261 if (cp->ctx_tbl[i].cid == cid) {
262 *l5_cid = i;
263 return 0;
264 }
265 }
266 return -EINVAL;
267 }
268
269 static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
270 struct cnic_sock *csk)
271 {
272 struct iscsi_path path_req;
273 char *buf = NULL;
274 u16 len = 0;
275 u32 msg_type = ISCSI_KEVENT_IF_DOWN;
276 struct cnic_ulp_ops *ulp_ops;
277
278 if (cp->uio_dev == -1)
279 return -ENODEV;
280
281 if (csk) {
282 len = sizeof(path_req);
283 buf = (char *) &path_req;
284 memset(&path_req, 0, len);
285
286 msg_type = ISCSI_KEVENT_PATH_REQ;
287 path_req.handle = (u64) csk->l5_cid;
288 if (test_bit(SK_F_IPV6, &csk->flags)) {
289 memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
290 sizeof(struct in6_addr));
291 path_req.ip_addr_len = 16;
292 } else {
293 memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
294 sizeof(struct in_addr));
295 path_req.ip_addr_len = 4;
296 }
297 path_req.vlan_id = csk->vlan_id;
298 path_req.pmtu = csk->mtu;
299 }
300
301 rcu_read_lock();
302 ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
303 if (ulp_ops)
304 ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
305 rcu_read_unlock();
306 return 0;
307 }
308
309 static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
310 char *buf, u16 len)
311 {
312 int rc = -EINVAL;
313
314 switch (msg_type) {
315 case ISCSI_UEVENT_PATH_UPDATE: {
316 struct cnic_local *cp;
317 u32 l5_cid;
318 struct cnic_sock *csk;
319 struct iscsi_path *path_resp;
320
321 if (len < sizeof(*path_resp))
322 break;
323
324 path_resp = (struct iscsi_path *) buf;
325 cp = dev->cnic_priv;
326 l5_cid = (u32) path_resp->handle;
327 if (l5_cid >= MAX_CM_SK_TBL_SZ)
328 break;
329
330 rcu_read_lock();
331 if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
332 rc = -ENODEV;
333 rcu_read_unlock();
334 break;
335 }
336 csk = &cp->csk_tbl[l5_cid];
337 csk_hold(csk);
338 if (cnic_in_use(csk)) {
339 memcpy(csk->ha, path_resp->mac_addr, 6);
340 if (test_bit(SK_F_IPV6, &csk->flags))
341 memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
342 sizeof(struct in6_addr));
343 else
344 memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
345 sizeof(struct in_addr));
346 if (is_valid_ether_addr(csk->ha))
347 cnic_cm_set_pg(csk);
348 }
349 csk_put(csk);
350 rcu_read_unlock();
351 rc = 0;
352 }
353 }
354
355 return rc;
356 }
357
358 static int cnic_offld_prep(struct cnic_sock *csk)
359 {
360 if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
361 return 0;
362
363 if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
364 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
365 return 0;
366 }
367
368 return 1;
369 }
370
371 static int cnic_close_prep(struct cnic_sock *csk)
372 {
373 clear_bit(SK_F_CONNECT_START, &csk->flags);
374 smp_mb__after_clear_bit();
375
376 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
377 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
378 msleep(1);
379
380 return 1;
381 }
382 return 0;
383 }
384
385 static int cnic_abort_prep(struct cnic_sock *csk)
386 {
387 clear_bit(SK_F_CONNECT_START, &csk->flags);
388 smp_mb__after_clear_bit();
389
390 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
391 msleep(1);
392
393 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
394 csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
395 return 1;
396 }
397
398 return 0;
399 }
400
401 static void cnic_uio_stop(void)
402 {
403 struct cnic_dev *dev;
404
405 read_lock(&cnic_dev_lock);
406 list_for_each_entry(dev, &cnic_dev_list, list) {
407 struct cnic_local *cp = dev->cnic_priv;
408
409 if (cp->cnic_uinfo)
410 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
411 }
412 read_unlock(&cnic_dev_lock);
413 }
414
415 int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
416 {
417 struct cnic_dev *dev;
418
419 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
420 pr_err("%s: Bad type %d\n", __func__, ulp_type);
421 return -EINVAL;
422 }
423 mutex_lock(&cnic_lock);
424 if (cnic_ulp_tbl[ulp_type]) {
425 pr_err("%s: Type %d has already been registered\n",
426 __func__, ulp_type);
427 mutex_unlock(&cnic_lock);
428 return -EBUSY;
429 }
430
431 read_lock(&cnic_dev_lock);
432 list_for_each_entry(dev, &cnic_dev_list, list) {
433 struct cnic_local *cp = dev->cnic_priv;
434
435 clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
436 }
437 read_unlock(&cnic_dev_lock);
438
439 atomic_set(&ulp_ops->ref_count, 0);
440 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
441 mutex_unlock(&cnic_lock);
442
443 /* Prevent race conditions with netdev_event */
444 rtnl_lock();
445 read_lock(&cnic_dev_lock);
446 list_for_each_entry(dev, &cnic_dev_list, list) {
447 struct cnic_local *cp = dev->cnic_priv;
448
449 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
450 ulp_ops->cnic_init(dev);
451 }
452 read_unlock(&cnic_dev_lock);
453 rtnl_unlock();
454
455 return 0;
456 }
457
458 int cnic_unregister_driver(int ulp_type)
459 {
460 struct cnic_dev *dev;
461 struct cnic_ulp_ops *ulp_ops;
462 int i = 0;
463
464 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
465 pr_err("%s: Bad type %d\n", __func__, ulp_type);
466 return -EINVAL;
467 }
468 mutex_lock(&cnic_lock);
469 ulp_ops = cnic_ulp_tbl[ulp_type];
470 if (!ulp_ops) {
471 pr_err("%s: Type %d has not been registered\n",
472 __func__, ulp_type);
473 goto out_unlock;
474 }
475 read_lock(&cnic_dev_lock);
476 list_for_each_entry(dev, &cnic_dev_list, list) {
477 struct cnic_local *cp = dev->cnic_priv;
478
479 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
480 pr_err("%s: Type %d still has devices registered\n",
481 __func__, ulp_type);
482 read_unlock(&cnic_dev_lock);
483 goto out_unlock;
484 }
485 }
486 read_unlock(&cnic_dev_lock);
487
488 if (ulp_type == CNIC_ULP_ISCSI)
489 cnic_uio_stop();
490
491 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
492
493 mutex_unlock(&cnic_lock);
494 synchronize_rcu();
495 while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
496 msleep(100);
497 i++;
498 }
499
500 if (atomic_read(&ulp_ops->ref_count) != 0)
501 netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
502 return 0;
503
504 out_unlock:
505 mutex_unlock(&cnic_lock);
506 return -EINVAL;
507 }
508
509 static int cnic_start_hw(struct cnic_dev *);
510 static void cnic_stop_hw(struct cnic_dev *);
511
512 static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
513 void *ulp_ctx)
514 {
515 struct cnic_local *cp = dev->cnic_priv;
516 struct cnic_ulp_ops *ulp_ops;
517
518 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
519 pr_err("%s: Bad type %d\n", __func__, ulp_type);
520 return -EINVAL;
521 }
522 mutex_lock(&cnic_lock);
523 if (cnic_ulp_tbl[ulp_type] == NULL) {
524 pr_err("%s: Driver with type %d has not been registered\n",
525 __func__, ulp_type);
526 mutex_unlock(&cnic_lock);
527 return -EAGAIN;
528 }
529 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
530 pr_err("%s: Type %d has already been registered to this device\n",
531 __func__, ulp_type);
532 mutex_unlock(&cnic_lock);
533 return -EBUSY;
534 }
535
536 clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
537 cp->ulp_handle[ulp_type] = ulp_ctx;
538 ulp_ops = cnic_ulp_tbl[ulp_type];
539 rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
540 cnic_hold(dev);
541
542 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
543 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
544 ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
545
546 mutex_unlock(&cnic_lock);
547
548 return 0;
549
550 }
551 EXPORT_SYMBOL(cnic_register_driver);
552
553 static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
554 {
555 struct cnic_local *cp = dev->cnic_priv;
556 int i = 0;
557
558 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
559 pr_err("%s: Bad type %d\n", __func__, ulp_type);
560 return -EINVAL;
561 }
562 mutex_lock(&cnic_lock);
563 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
564 rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
565 cnic_put(dev);
566 } else {
567 pr_err("%s: device not registered to this ulp type %d\n",
568 __func__, ulp_type);
569 mutex_unlock(&cnic_lock);
570 return -EINVAL;
571 }
572 mutex_unlock(&cnic_lock);
573
574 synchronize_rcu();
575
576 while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
577 i < 20) {
578 msleep(100);
579 i++;
580 }
581 if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
582 netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
583
584 return 0;
585 }
586 EXPORT_SYMBOL(cnic_unregister_driver);
587
588 static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
589 {
590 id_tbl->start = start_id;
591 id_tbl->max = size;
592 id_tbl->next = 0;
593 spin_lock_init(&id_tbl->lock);
594 id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
595 if (!id_tbl->table)
596 return -ENOMEM;
597
598 return 0;
599 }
600
601 static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
602 {
603 kfree(id_tbl->table);
604 id_tbl->table = NULL;
605 }
606
607 static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
608 {
609 int ret = -1;
610
611 id -= id_tbl->start;
612 if (id >= id_tbl->max)
613 return ret;
614
615 spin_lock(&id_tbl->lock);
616 if (!test_bit(id, id_tbl->table)) {
617 set_bit(id, id_tbl->table);
618 ret = 0;
619 }
620 spin_unlock(&id_tbl->lock);
621 return ret;
622 }
623
624 /* Returns -1 if not successful */
625 static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
626 {
627 u32 id;
628
629 spin_lock(&id_tbl->lock);
630 id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
631 if (id >= id_tbl->max) {
632 id = -1;
633 if (id_tbl->next != 0) {
634 id = find_first_zero_bit(id_tbl->table, id_tbl->next);
635 if (id >= id_tbl->next)
636 id = -1;
637 }
638 }
639
640 if (id < id_tbl->max) {
641 set_bit(id, id_tbl->table);
642 id_tbl->next = (id + 1) & (id_tbl->max - 1);
643 id += id_tbl->start;
644 }
645
646 spin_unlock(&id_tbl->lock);
647
648 return id;
649 }
650
651 static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
652 {
653 if (id == -1)
654 return;
655
656 id -= id_tbl->start;
657 if (id >= id_tbl->max)
658 return;
659
660 clear_bit(id, id_tbl->table);
661 }
662
663 static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
664 {
665 int i;
666
667 if (!dma->pg_arr)
668 return;
669
670 for (i = 0; i < dma->num_pages; i++) {
671 if (dma->pg_arr[i]) {
672 dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
673 dma->pg_arr[i], dma->pg_map_arr[i]);
674 dma->pg_arr[i] = NULL;
675 }
676 }
677 if (dma->pgtbl) {
678 dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
679 dma->pgtbl, dma->pgtbl_map);
680 dma->pgtbl = NULL;
681 }
682 kfree(dma->pg_arr);
683 dma->pg_arr = NULL;
684 dma->num_pages = 0;
685 }
686
687 static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
688 {
689 int i;
690 u32 *page_table = dma->pgtbl;
691
692 for (i = 0; i < dma->num_pages; i++) {
693 /* Each entry needs to be in big endian format. */
694 *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
695 page_table++;
696 *page_table = (u32) dma->pg_map_arr[i];
697 page_table++;
698 }
699 }
700
701 static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
702 {
703 int i;
704 u32 *page_table = dma->pgtbl;
705
706 for (i = 0; i < dma->num_pages; i++) {
707 /* Each entry needs to be in little endian format. */
708 *page_table = dma->pg_map_arr[i] & 0xffffffff;
709 page_table++;
710 *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
711 page_table++;
712 }
713 }
714
715 static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
716 int pages, int use_pg_tbl)
717 {
718 int i, size;
719 struct cnic_local *cp = dev->cnic_priv;
720
721 size = pages * (sizeof(void *) + sizeof(dma_addr_t));
722 dma->pg_arr = kzalloc(size, GFP_ATOMIC);
723 if (dma->pg_arr == NULL)
724 return -ENOMEM;
725
726 dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
727 dma->num_pages = pages;
728
729 for (i = 0; i < pages; i++) {
730 dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
731 BCM_PAGE_SIZE,
732 &dma->pg_map_arr[i],
733 GFP_ATOMIC);
734 if (dma->pg_arr[i] == NULL)
735 goto error;
736 }
737 if (!use_pg_tbl)
738 return 0;
739
740 dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
741 ~(BCM_PAGE_SIZE - 1);
742 dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
743 &dma->pgtbl_map, GFP_ATOMIC);
744 if (dma->pgtbl == NULL)
745 goto error;
746
747 cp->setup_pgtbl(dev, dma);
748
749 return 0;
750
751 error:
752 cnic_free_dma(dev, dma);
753 return -ENOMEM;
754 }
755
756 static void cnic_free_context(struct cnic_dev *dev)
757 {
758 struct cnic_local *cp = dev->cnic_priv;
759 int i;
760
761 for (i = 0; i < cp->ctx_blks; i++) {
762 if (cp->ctx_arr[i].ctx) {
763 dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
764 cp->ctx_arr[i].ctx,
765 cp->ctx_arr[i].mapping);
766 cp->ctx_arr[i].ctx = NULL;
767 }
768 }
769 }
770
771 static void cnic_free_resc(struct cnic_dev *dev)
772 {
773 struct cnic_local *cp = dev->cnic_priv;
774 int i = 0;
775
776 if (cp->cnic_uinfo) {
777 while (cp->uio_dev != -1 && i < 15) {
778 msleep(100);
779 i++;
780 }
781 uio_unregister_device(cp->cnic_uinfo);
782 kfree(cp->cnic_uinfo);
783 cp->cnic_uinfo = NULL;
784 }
785
786 if (cp->l2_buf) {
787 dma_free_coherent(&dev->pcidev->dev, cp->l2_buf_size,
788 cp->l2_buf, cp->l2_buf_map);
789 cp->l2_buf = NULL;
790 }
791
792 if (cp->l2_ring) {
793 dma_free_coherent(&dev->pcidev->dev, cp->l2_ring_size,
794 cp->l2_ring, cp->l2_ring_map);
795 cp->l2_ring = NULL;
796 }
797
798 cnic_free_context(dev);
799 kfree(cp->ctx_arr);
800 cp->ctx_arr = NULL;
801 cp->ctx_blks = 0;
802
803 cnic_free_dma(dev, &cp->gbl_buf_info);
804 cnic_free_dma(dev, &cp->conn_buf_info);
805 cnic_free_dma(dev, &cp->kwq_info);
806 cnic_free_dma(dev, &cp->kwq_16_data_info);
807 cnic_free_dma(dev, &cp->kcq_info);
808 kfree(cp->iscsi_tbl);
809 cp->iscsi_tbl = NULL;
810 kfree(cp->ctx_tbl);
811 cp->ctx_tbl = NULL;
812
813 cnic_free_id_tbl(&cp->cid_tbl);
814 }
815
816 static int cnic_alloc_context(struct cnic_dev *dev)
817 {
818 struct cnic_local *cp = dev->cnic_priv;
819
820 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
821 int i, k, arr_size;
822
823 cp->ctx_blk_size = BCM_PAGE_SIZE;
824 cp->cids_per_blk = BCM_PAGE_SIZE / 128;
825 arr_size = BNX2_MAX_CID / cp->cids_per_blk *
826 sizeof(struct cnic_ctx);
827 cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
828 if (cp->ctx_arr == NULL)
829 return -ENOMEM;
830
831 k = 0;
832 for (i = 0; i < 2; i++) {
833 u32 j, reg, off, lo, hi;
834
835 if (i == 0)
836 off = BNX2_PG_CTX_MAP;
837 else
838 off = BNX2_ISCSI_CTX_MAP;
839
840 reg = cnic_reg_rd_ind(dev, off);
841 lo = reg >> 16;
842 hi = reg & 0xffff;
843 for (j = lo; j < hi; j += cp->cids_per_blk, k++)
844 cp->ctx_arr[k].cid = j;
845 }
846
847 cp->ctx_blks = k;
848 if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
849 cp->ctx_blks = 0;
850 return -ENOMEM;
851 }
852
853 for (i = 0; i < cp->ctx_blks; i++) {
854 cp->ctx_arr[i].ctx =
855 dma_alloc_coherent(&dev->pcidev->dev,
856 BCM_PAGE_SIZE,
857 &cp->ctx_arr[i].mapping,
858 GFP_KERNEL);
859 if (cp->ctx_arr[i].ctx == NULL)
860 return -ENOMEM;
861 }
862 }
863 return 0;
864 }
865
866 static int cnic_alloc_l2_rings(struct cnic_dev *dev, int pages)
867 {
868 struct cnic_local *cp = dev->cnic_priv;
869
870 cp->l2_ring_size = pages * BCM_PAGE_SIZE;
871 cp->l2_ring = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_ring_size,
872 &cp->l2_ring_map,
873 GFP_KERNEL | __GFP_COMP);
874 if (!cp->l2_ring)
875 return -ENOMEM;
876
877 cp->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
878 cp->l2_buf_size = PAGE_ALIGN(cp->l2_buf_size);
879 cp->l2_buf = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_buf_size,
880 &cp->l2_buf_map,
881 GFP_KERNEL | __GFP_COMP);
882 if (!cp->l2_buf)
883 return -ENOMEM;
884
885 return 0;
886 }
887
888 static int cnic_alloc_uio(struct cnic_dev *dev) {
889 struct cnic_local *cp = dev->cnic_priv;
890 struct uio_info *uinfo;
891 int ret;
892
893 uinfo = kzalloc(sizeof(*uinfo), GFP_ATOMIC);
894 if (!uinfo)
895 return -ENOMEM;
896
897 uinfo->mem[0].addr = dev->netdev->base_addr;
898 uinfo->mem[0].internal_addr = dev->regview;
899 uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
900 uinfo->mem[0].memtype = UIO_MEM_PHYS;
901
902 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
903 uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
904 PAGE_MASK;
905 if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
906 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
907 else
908 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
909
910 uinfo->name = "bnx2_cnic";
911 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
912 uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
913 PAGE_MASK;
914 uinfo->mem[1].size = sizeof(struct host_def_status_block);
915
916 uinfo->name = "bnx2x_cnic";
917 }
918
919 uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
920
921 uinfo->mem[2].addr = (unsigned long) cp->l2_ring;
922 uinfo->mem[2].size = cp->l2_ring_size;
923 uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
924
925 uinfo->mem[3].addr = (unsigned long) cp->l2_buf;
926 uinfo->mem[3].size = cp->l2_buf_size;
927 uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
928
929 uinfo->version = CNIC_MODULE_VERSION;
930 uinfo->irq = UIO_IRQ_CUSTOM;
931
932 uinfo->open = cnic_uio_open;
933 uinfo->release = cnic_uio_close;
934
935 uinfo->priv = dev;
936
937 ret = uio_register_device(&dev->pcidev->dev, uinfo);
938 if (ret) {
939 kfree(uinfo);
940 return ret;
941 }
942
943 cp->cnic_uinfo = uinfo;
944 return 0;
945 }
946
947 static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
948 {
949 struct cnic_local *cp = dev->cnic_priv;
950 int ret;
951
952 ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
953 if (ret)
954 goto error;
955 cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
956
957 ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 1);
958 if (ret)
959 goto error;
960 cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr;
961
962 ret = cnic_alloc_context(dev);
963 if (ret)
964 goto error;
965
966 ret = cnic_alloc_l2_rings(dev, 2);
967 if (ret)
968 goto error;
969
970 ret = cnic_alloc_uio(dev);
971 if (ret)
972 goto error;
973
974 return 0;
975
976 error:
977 cnic_free_resc(dev);
978 return ret;
979 }
980
981 static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
982 {
983 struct cnic_local *cp = dev->cnic_priv;
984 struct cnic_eth_dev *ethdev = cp->ethdev;
985 int ctx_blk_size = cp->ethdev->ctx_blk_size;
986 int total_mem, blks, i, cid_space;
987
988 if (BNX2X_ISCSI_START_CID < ethdev->starting_cid)
989 return -EINVAL;
990
991 cid_space = MAX_ISCSI_TBL_SZ +
992 (BNX2X_ISCSI_START_CID - ethdev->starting_cid);
993
994 total_mem = BNX2X_CONTEXT_MEM_SIZE * cid_space;
995 blks = total_mem / ctx_blk_size;
996 if (total_mem % ctx_blk_size)
997 blks++;
998
999 if (blks > cp->ethdev->ctx_tbl_len)
1000 return -ENOMEM;
1001
1002 cp->ctx_arr = kzalloc(blks * sizeof(struct cnic_ctx), GFP_KERNEL);
1003 if (cp->ctx_arr == NULL)
1004 return -ENOMEM;
1005
1006 cp->ctx_blks = blks;
1007 cp->ctx_blk_size = ctx_blk_size;
1008 if (BNX2X_CHIP_IS_E1H(cp->chip_id))
1009 cp->ctx_align = 0;
1010 else
1011 cp->ctx_align = ctx_blk_size;
1012
1013 cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
1014
1015 for (i = 0; i < blks; i++) {
1016 cp->ctx_arr[i].ctx =
1017 dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
1018 &cp->ctx_arr[i].mapping,
1019 GFP_KERNEL);
1020 if (cp->ctx_arr[i].ctx == NULL)
1021 return -ENOMEM;
1022
1023 if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
1024 if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
1025 cnic_free_context(dev);
1026 cp->ctx_blk_size += cp->ctx_align;
1027 i = -1;
1028 continue;
1029 }
1030 }
1031 }
1032 return 0;
1033 }
1034
1035 static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
1036 {
1037 struct cnic_local *cp = dev->cnic_priv;
1038 int i, j, n, ret, pages;
1039 struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
1040
1041 cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
1042 GFP_KERNEL);
1043 if (!cp->iscsi_tbl)
1044 goto error;
1045
1046 cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
1047 MAX_CNIC_L5_CONTEXT, GFP_KERNEL);
1048 if (!cp->ctx_tbl)
1049 goto error;
1050
1051 for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
1052 cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
1053 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
1054 }
1055
1056 pages = PAGE_ALIGN(MAX_CNIC_L5_CONTEXT * CNIC_KWQ16_DATA_SIZE) /
1057 PAGE_SIZE;
1058
1059 ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
1060 if (ret)
1061 return -ENOMEM;
1062
1063 n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
1064 for (i = 0, j = 0; i < MAX_ISCSI_TBL_SZ; i++) {
1065 long off = CNIC_KWQ16_DATA_SIZE * (i % n);
1066
1067 cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
1068 cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
1069 off;
1070
1071 if ((i % n) == (n - 1))
1072 j++;
1073 }
1074
1075 ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 0);
1076 if (ret)
1077 goto error;
1078 cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr;
1079
1080 for (i = 0; i < KCQ_PAGE_CNT; i++) {
1081 struct bnx2x_bd_chain_next *next =
1082 (struct bnx2x_bd_chain_next *)
1083 &cp->kcq[i][MAX_KCQE_CNT];
1084 int j = i + 1;
1085
1086 if (j >= KCQ_PAGE_CNT)
1087 j = 0;
1088 next->addr_hi = (u64) cp->kcq_info.pg_map_arr[j] >> 32;
1089 next->addr_lo = cp->kcq_info.pg_map_arr[j] & 0xffffffff;
1090 }
1091
1092 pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
1093 BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
1094 ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
1095 if (ret)
1096 goto error;
1097
1098 pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
1099 ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
1100 if (ret)
1101 goto error;
1102
1103 ret = cnic_alloc_bnx2x_context(dev);
1104 if (ret)
1105 goto error;
1106
1107 cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
1108
1109 memset(cp->status_blk.bnx2x, 0, sizeof(*cp->status_blk.bnx2x));
1110
1111 cp->l2_rx_ring_size = 15;
1112
1113 ret = cnic_alloc_l2_rings(dev, 4);
1114 if (ret)
1115 goto error;
1116
1117 ret = cnic_alloc_uio(dev);
1118 if (ret)
1119 goto error;
1120
1121 return 0;
1122
1123 error:
1124 cnic_free_resc(dev);
1125 return -ENOMEM;
1126 }
1127
1128 static inline u32 cnic_kwq_avail(struct cnic_local *cp)
1129 {
1130 return cp->max_kwq_idx -
1131 ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
1132 }
1133
1134 static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
1135 u32 num_wqes)
1136 {
1137 struct cnic_local *cp = dev->cnic_priv;
1138 struct kwqe *prod_qe;
1139 u16 prod, sw_prod, i;
1140
1141 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
1142 return -EAGAIN; /* bnx2 is down */
1143
1144 spin_lock_bh(&cp->cnic_ulp_lock);
1145 if (num_wqes > cnic_kwq_avail(cp) &&
1146 !(cp->cnic_local_flags & CNIC_LCL_FL_KWQ_INIT)) {
1147 spin_unlock_bh(&cp->cnic_ulp_lock);
1148 return -EAGAIN;
1149 }
1150
1151 cp->cnic_local_flags &= ~CNIC_LCL_FL_KWQ_INIT;
1152
1153 prod = cp->kwq_prod_idx;
1154 sw_prod = prod & MAX_KWQ_IDX;
1155 for (i = 0; i < num_wqes; i++) {
1156 prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
1157 memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
1158 prod++;
1159 sw_prod = prod & MAX_KWQ_IDX;
1160 }
1161 cp->kwq_prod_idx = prod;
1162
1163 CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
1164
1165 spin_unlock_bh(&cp->cnic_ulp_lock);
1166 return 0;
1167 }
1168
1169 static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
1170 union l5cm_specific_data *l5_data)
1171 {
1172 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1173 dma_addr_t map;
1174
1175 map = ctx->kwqe_data_mapping;
1176 l5_data->phy_address.lo = (u64) map & 0xffffffff;
1177 l5_data->phy_address.hi = (u64) map >> 32;
1178 return ctx->kwqe_data;
1179 }
1180
1181 static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
1182 u32 type, union l5cm_specific_data *l5_data)
1183 {
1184 struct cnic_local *cp = dev->cnic_priv;
1185 struct l5cm_spe kwqe;
1186 struct kwqe_16 *kwq[1];
1187 int ret;
1188
1189 kwqe.hdr.conn_and_cmd_data =
1190 cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
1191 BNX2X_HW_CID(cid, cp->func)));
1192 kwqe.hdr.type = cpu_to_le16(type);
1193 kwqe.hdr.reserved = 0;
1194 kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
1195 kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
1196
1197 kwq[0] = (struct kwqe_16 *) &kwqe;
1198
1199 spin_lock_bh(&cp->cnic_ulp_lock);
1200 ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
1201 spin_unlock_bh(&cp->cnic_ulp_lock);
1202
1203 if (ret == 1)
1204 return 0;
1205
1206 return -EBUSY;
1207 }
1208
1209 static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
1210 struct kcqe *cqes[], u32 num_cqes)
1211 {
1212 struct cnic_local *cp = dev->cnic_priv;
1213 struct cnic_ulp_ops *ulp_ops;
1214
1215 rcu_read_lock();
1216 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
1217 if (likely(ulp_ops)) {
1218 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
1219 cqes, num_cqes);
1220 }
1221 rcu_read_unlock();
1222 }
1223
1224 static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
1225 {
1226 struct cnic_local *cp = dev->cnic_priv;
1227 struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
1228 int func = cp->func, pages;
1229 int hq_bds;
1230
1231 cp->num_iscsi_tasks = req1->num_tasks_per_conn;
1232 cp->num_ccells = req1->num_ccells_per_conn;
1233 cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
1234 cp->num_iscsi_tasks;
1235 cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
1236 BNX2X_ISCSI_R2TQE_SIZE;
1237 cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
1238 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1239 hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
1240 cp->num_cqs = req1->num_cqs;
1241
1242 if (!dev->max_iscsi_conn)
1243 return 0;
1244
1245 /* init Tstorm RAM */
1246 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(func),
1247 req1->rq_num_wqes);
1248 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
1249 PAGE_SIZE);
1250 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1251 TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
1252 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1253 TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
1254 req1->num_tasks_per_conn);
1255
1256 /* init Ustorm RAM */
1257 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1258 USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(func),
1259 req1->rq_buffer_size);
1260 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(func),
1261 PAGE_SIZE);
1262 CNIC_WR8(dev, BAR_USTRORM_INTMEM +
1263 USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
1264 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1265 USTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
1266 req1->num_tasks_per_conn);
1267 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(func),
1268 req1->rq_num_wqes);
1269 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(func),
1270 req1->cq_num_wqes);
1271 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(func),
1272 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1273
1274 /* init Xstorm RAM */
1275 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
1276 PAGE_SIZE);
1277 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1278 XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
1279 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1280 XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
1281 req1->num_tasks_per_conn);
1282 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(func),
1283 hq_bds);
1284 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(func),
1285 req1->num_tasks_per_conn);
1286 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(func),
1287 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1288
1289 /* init Cstorm RAM */
1290 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
1291 PAGE_SIZE);
1292 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
1293 CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
1294 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1295 CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
1296 req1->num_tasks_per_conn);
1297 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(func),
1298 req1->cq_num_wqes);
1299 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(func),
1300 hq_bds);
1301
1302 return 0;
1303 }
1304
1305 static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
1306 {
1307 struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
1308 struct cnic_local *cp = dev->cnic_priv;
1309 int func = cp->func;
1310 struct iscsi_kcqe kcqe;
1311 struct kcqe *cqes[1];
1312
1313 memset(&kcqe, 0, sizeof(kcqe));
1314 if (!dev->max_iscsi_conn) {
1315 kcqe.completion_status =
1316 ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
1317 goto done;
1318 }
1319
1320 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1321 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]);
1322 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1323 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4,
1324 req2->error_bit_map[1]);
1325
1326 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1327 USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn);
1328 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1329 USTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]);
1330 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1331 USTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4,
1332 req2->error_bit_map[1]);
1333
1334 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1335 CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn);
1336
1337 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1338
1339 done:
1340 kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
1341 cqes[0] = (struct kcqe *) &kcqe;
1342 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1343
1344 return 0;
1345 }
1346
1347 static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1348 {
1349 struct cnic_local *cp = dev->cnic_priv;
1350 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1351
1352 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
1353 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1354
1355 cnic_free_dma(dev, &iscsi->hq_info);
1356 cnic_free_dma(dev, &iscsi->r2tq_info);
1357 cnic_free_dma(dev, &iscsi->task_array_info);
1358 }
1359 cnic_free_id(&cp->cid_tbl, ctx->cid);
1360 ctx->cid = 0;
1361 }
1362
1363 static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1364 {
1365 u32 cid;
1366 int ret, pages;
1367 struct cnic_local *cp = dev->cnic_priv;
1368 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1369 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1370
1371 cid = cnic_alloc_new_id(&cp->cid_tbl);
1372 if (cid == -1) {
1373 ret = -ENOMEM;
1374 goto error;
1375 }
1376
1377 ctx->cid = cid;
1378 pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
1379
1380 ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
1381 if (ret)
1382 goto error;
1383
1384 pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
1385 ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
1386 if (ret)
1387 goto error;
1388
1389 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1390 ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
1391 if (ret)
1392 goto error;
1393
1394 return 0;
1395
1396 error:
1397 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1398 return ret;
1399 }
1400
1401 static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
1402 struct regpair *ctx_addr)
1403 {
1404 struct cnic_local *cp = dev->cnic_priv;
1405 struct cnic_eth_dev *ethdev = cp->ethdev;
1406 int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
1407 int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
1408 unsigned long align_off = 0;
1409 dma_addr_t ctx_map;
1410 void *ctx;
1411
1412 if (cp->ctx_align) {
1413 unsigned long mask = cp->ctx_align - 1;
1414
1415 if (cp->ctx_arr[blk].mapping & mask)
1416 align_off = cp->ctx_align -
1417 (cp->ctx_arr[blk].mapping & mask);
1418 }
1419 ctx_map = cp->ctx_arr[blk].mapping + align_off +
1420 (off * BNX2X_CONTEXT_MEM_SIZE);
1421 ctx = cp->ctx_arr[blk].ctx + align_off +
1422 (off * BNX2X_CONTEXT_MEM_SIZE);
1423 if (init)
1424 memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
1425
1426 ctx_addr->lo = ctx_map & 0xffffffff;
1427 ctx_addr->hi = (u64) ctx_map >> 32;
1428 return ctx;
1429 }
1430
1431 static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
1432 u32 num)
1433 {
1434 struct cnic_local *cp = dev->cnic_priv;
1435 struct iscsi_kwqe_conn_offload1 *req1 =
1436 (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1437 struct iscsi_kwqe_conn_offload2 *req2 =
1438 (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1439 struct iscsi_kwqe_conn_offload3 *req3;
1440 struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
1441 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1442 u32 cid = ctx->cid;
1443 u32 hw_cid = BNX2X_HW_CID(cid, cp->func);
1444 struct iscsi_context *ictx;
1445 struct regpair context_addr;
1446 int i, j, n = 2, n_max;
1447
1448 ctx->ctx_flags = 0;
1449 if (!req2->num_additional_wqes)
1450 return -EINVAL;
1451
1452 n_max = req2->num_additional_wqes + 2;
1453
1454 ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
1455 if (ictx == NULL)
1456 return -ENOMEM;
1457
1458 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1459
1460 ictx->xstorm_ag_context.hq_prod = 1;
1461
1462 ictx->xstorm_st_context.iscsi.first_burst_length =
1463 ISCSI_DEF_FIRST_BURST_LEN;
1464 ictx->xstorm_st_context.iscsi.max_send_pdu_length =
1465 ISCSI_DEF_MAX_RECV_SEG_LEN;
1466 ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
1467 req1->sq_page_table_addr_lo;
1468 ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
1469 req1->sq_page_table_addr_hi;
1470 ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
1471 ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
1472 ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
1473 iscsi->hq_info.pgtbl_map & 0xffffffff;
1474 ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
1475 (u64) iscsi->hq_info.pgtbl_map >> 32;
1476 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
1477 iscsi->hq_info.pgtbl[0];
1478 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
1479 iscsi->hq_info.pgtbl[1];
1480 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
1481 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1482 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
1483 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1484 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
1485 iscsi->r2tq_info.pgtbl[0];
1486 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
1487 iscsi->r2tq_info.pgtbl[1];
1488 ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
1489 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1490 ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
1491 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1492 ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
1493 BNX2X_ISCSI_PBL_NOT_CACHED;
1494 ictx->xstorm_st_context.iscsi.flags.flags |=
1495 XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
1496 ictx->xstorm_st_context.iscsi.flags.flags |=
1497 XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
1498
1499 ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
1500 /* TSTORM requires the base address of RQ DB & not PTE */
1501 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
1502 req2->rq_page_table_addr_lo & PAGE_MASK;
1503 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
1504 req2->rq_page_table_addr_hi;
1505 ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
1506 ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
1507 ictx->tstorm_st_context.tcp.flags2 |=
1508 TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
1509
1510 ictx->timers_context.flags |= ISCSI_TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
1511
1512 ictx->ustorm_st_context.ring.rq.pbl_base.lo =
1513 req2->rq_page_table_addr_lo;
1514 ictx->ustorm_st_context.ring.rq.pbl_base.hi =
1515 req2->rq_page_table_addr_hi;
1516 ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
1517 ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
1518 ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
1519 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1520 ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
1521 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1522 ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
1523 iscsi->r2tq_info.pgtbl[0];
1524 ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
1525 iscsi->r2tq_info.pgtbl[1];
1526 ictx->ustorm_st_context.ring.cq_pbl_base.lo =
1527 req1->cq_page_table_addr_lo;
1528 ictx->ustorm_st_context.ring.cq_pbl_base.hi =
1529 req1->cq_page_table_addr_hi;
1530 ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
1531 ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
1532 ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
1533 ictx->ustorm_st_context.task_pbe_cache_index =
1534 BNX2X_ISCSI_PBL_NOT_CACHED;
1535 ictx->ustorm_st_context.task_pdu_cache_index =
1536 BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
1537
1538 for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
1539 if (j == 3) {
1540 if (n >= n_max)
1541 break;
1542 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1543 j = 0;
1544 }
1545 ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
1546 ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
1547 req3->qp_first_pte[j].hi;
1548 ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
1549 req3->qp_first_pte[j].lo;
1550 }
1551
1552 ictx->ustorm_st_context.task_pbl_base.lo =
1553 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1554 ictx->ustorm_st_context.task_pbl_base.hi =
1555 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1556 ictx->ustorm_st_context.tce_phy_addr.lo =
1557 iscsi->task_array_info.pgtbl[0];
1558 ictx->ustorm_st_context.tce_phy_addr.hi =
1559 iscsi->task_array_info.pgtbl[1];
1560 ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1561 ictx->ustorm_st_context.num_cqs = cp->num_cqs;
1562 ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
1563 ictx->ustorm_st_context.negotiated_rx_and_flags |=
1564 ISCSI_DEF_MAX_BURST_LEN;
1565 ictx->ustorm_st_context.negotiated_rx |=
1566 ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
1567 USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
1568
1569 ictx->cstorm_st_context.hq_pbl_base.lo =
1570 iscsi->hq_info.pgtbl_map & 0xffffffff;
1571 ictx->cstorm_st_context.hq_pbl_base.hi =
1572 (u64) iscsi->hq_info.pgtbl_map >> 32;
1573 ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
1574 ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
1575 ictx->cstorm_st_context.task_pbl_base.lo =
1576 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1577 ictx->cstorm_st_context.task_pbl_base.hi =
1578 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1579 /* CSTORM and USTORM initialization is different, CSTORM requires
1580 * CQ DB base & not PTE addr */
1581 ictx->cstorm_st_context.cq_db_base.lo =
1582 req1->cq_page_table_addr_lo & PAGE_MASK;
1583 ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
1584 ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1585 ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
1586 for (i = 0; i < cp->num_cqs; i++) {
1587 ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
1588 ISCSI_INITIAL_SN;
1589 ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
1590 ISCSI_INITIAL_SN;
1591 }
1592
1593 ictx->xstorm_ag_context.cdu_reserved =
1594 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
1595 ISCSI_CONNECTION_TYPE);
1596 ictx->ustorm_ag_context.cdu_usage =
1597 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
1598 ISCSI_CONNECTION_TYPE);
1599 return 0;
1600
1601 }
1602
1603 static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
1604 u32 num, int *work)
1605 {
1606 struct iscsi_kwqe_conn_offload1 *req1;
1607 struct iscsi_kwqe_conn_offload2 *req2;
1608 struct cnic_local *cp = dev->cnic_priv;
1609 struct iscsi_kcqe kcqe;
1610 struct kcqe *cqes[1];
1611 u32 l5_cid;
1612 int ret;
1613
1614 if (num < 2) {
1615 *work = num;
1616 return -EINVAL;
1617 }
1618
1619 req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1620 req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1621 if ((num - 2) < req2->num_additional_wqes) {
1622 *work = num;
1623 return -EINVAL;
1624 }
1625 *work = 2 + req2->num_additional_wqes;;
1626
1627 l5_cid = req1->iscsi_conn_id;
1628 if (l5_cid >= MAX_ISCSI_TBL_SZ)
1629 return -EINVAL;
1630
1631 memset(&kcqe, 0, sizeof(kcqe));
1632 kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
1633 kcqe.iscsi_conn_id = l5_cid;
1634 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
1635
1636 if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
1637 atomic_dec(&cp->iscsi_conn);
1638 ret = 0;
1639 goto done;
1640 }
1641 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
1642 if (ret) {
1643 atomic_dec(&cp->iscsi_conn);
1644 ret = 0;
1645 goto done;
1646 }
1647 ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
1648 if (ret < 0) {
1649 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1650 atomic_dec(&cp->iscsi_conn);
1651 goto done;
1652 }
1653
1654 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1655 kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp->ctx_tbl[l5_cid].cid,
1656 cp->func);
1657
1658 done:
1659 cqes[0] = (struct kcqe *) &kcqe;
1660 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1661 return ret;
1662 }
1663
1664
1665 static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
1666 {
1667 struct cnic_local *cp = dev->cnic_priv;
1668 struct iscsi_kwqe_conn_update *req =
1669 (struct iscsi_kwqe_conn_update *) kwqe;
1670 void *data;
1671 union l5cm_specific_data l5_data;
1672 u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
1673 int ret;
1674
1675 if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
1676 return -EINVAL;
1677
1678 data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1679 if (!data)
1680 return -ENOMEM;
1681
1682 memcpy(data, kwqe, sizeof(struct kwqe));
1683
1684 ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
1685 req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
1686 return ret;
1687 }
1688
1689 static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
1690 {
1691 struct cnic_local *cp = dev->cnic_priv;
1692 struct iscsi_kwqe_conn_destroy *req =
1693 (struct iscsi_kwqe_conn_destroy *) kwqe;
1694 union l5cm_specific_data l5_data;
1695 u32 l5_cid = req->reserved0;
1696 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1697 int ret = 0;
1698 struct iscsi_kcqe kcqe;
1699 struct kcqe *cqes[1];
1700
1701 if (!(ctx->ctx_flags & CTX_FL_OFFLD_START))
1702 goto skip_cfc_delete;
1703
1704 while (!time_after(jiffies, ctx->timestamp + (2 * HZ)))
1705 msleep(250);
1706
1707 init_waitqueue_head(&ctx->waitq);
1708 ctx->wait_cond = 0;
1709 memset(&l5_data, 0, sizeof(l5_data));
1710 ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CFC_DEL,
1711 req->context_id,
1712 ETH_CONNECTION_TYPE |
1713 (1 << SPE_HDR_COMMON_RAMROD_SHIFT),
1714 &l5_data);
1715 if (ret == 0)
1716 wait_event(ctx->waitq, ctx->wait_cond);
1717
1718 skip_cfc_delete:
1719 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1720
1721 atomic_dec(&cp->iscsi_conn);
1722
1723 memset(&kcqe, 0, sizeof(kcqe));
1724 kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
1725 kcqe.iscsi_conn_id = l5_cid;
1726 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1727 kcqe.iscsi_conn_context_id = req->context_id;
1728
1729 cqes[0] = (struct kcqe *) &kcqe;
1730 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1731
1732 return ret;
1733 }
1734
1735 static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
1736 struct l4_kwq_connect_req1 *kwqe1,
1737 struct l4_kwq_connect_req3 *kwqe3,
1738 struct l5cm_active_conn_buffer *conn_buf)
1739 {
1740 struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
1741 struct l5cm_xstorm_conn_buffer *xstorm_buf =
1742 &conn_buf->xstorm_conn_buffer;
1743 struct l5cm_tstorm_conn_buffer *tstorm_buf =
1744 &conn_buf->tstorm_conn_buffer;
1745 struct regpair context_addr;
1746 u32 cid = BNX2X_SW_CID(kwqe1->cid);
1747 struct in6_addr src_ip, dst_ip;
1748 int i;
1749 u32 *addrp;
1750
1751 addrp = (u32 *) &conn_addr->local_ip_addr;
1752 for (i = 0; i < 4; i++, addrp++)
1753 src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1754
1755 addrp = (u32 *) &conn_addr->remote_ip_addr;
1756 for (i = 0; i < 4; i++, addrp++)
1757 dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1758
1759 cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
1760
1761 xstorm_buf->context_addr.hi = context_addr.hi;
1762 xstorm_buf->context_addr.lo = context_addr.lo;
1763 xstorm_buf->mss = 0xffff;
1764 xstorm_buf->rcv_buf = kwqe3->rcv_buf;
1765 if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
1766 xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
1767 xstorm_buf->pseudo_header_checksum =
1768 swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
1769
1770 if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
1771 tstorm_buf->params |=
1772 L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
1773 if (kwqe3->ka_timeout) {
1774 tstorm_buf->ka_enable = 1;
1775 tstorm_buf->ka_timeout = kwqe3->ka_timeout;
1776 tstorm_buf->ka_interval = kwqe3->ka_interval;
1777 tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
1778 }
1779 tstorm_buf->rcv_buf = kwqe3->rcv_buf;
1780 tstorm_buf->snd_buf = kwqe3->snd_buf;
1781 tstorm_buf->max_rt_time = 0xffffffff;
1782 }
1783
1784 static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
1785 {
1786 struct cnic_local *cp = dev->cnic_priv;
1787 int func = CNIC_FUNC(cp);
1788 u8 *mac = dev->mac_addr;
1789
1790 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1791 XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(func), mac[0]);
1792 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1793 XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(func), mac[1]);
1794 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1795 XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(func), mac[2]);
1796 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1797 XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(func), mac[3]);
1798 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1799 XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(func), mac[4]);
1800 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1801 XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(func), mac[5]);
1802
1803 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1804 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func), mac[5]);
1805 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1806 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func) + 1,
1807 mac[4]);
1808 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1809 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func), mac[3]);
1810 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1811 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 1,
1812 mac[2]);
1813 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1814 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 2,
1815 mac[1]);
1816 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1817 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 3,
1818 mac[0]);
1819 }
1820
1821 static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
1822 {
1823 struct cnic_local *cp = dev->cnic_priv;
1824 u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
1825 u16 tstorm_flags = 0;
1826
1827 if (tcp_ts) {
1828 xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1829 tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1830 }
1831
1832 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1833 XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), xstorm_flags);
1834
1835 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1836 TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), tstorm_flags);
1837 }
1838
1839 static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
1840 u32 num, int *work)
1841 {
1842 struct cnic_local *cp = dev->cnic_priv;
1843 struct l4_kwq_connect_req1 *kwqe1 =
1844 (struct l4_kwq_connect_req1 *) wqes[0];
1845 struct l4_kwq_connect_req3 *kwqe3;
1846 struct l5cm_active_conn_buffer *conn_buf;
1847 struct l5cm_conn_addr_params *conn_addr;
1848 union l5cm_specific_data l5_data;
1849 u32 l5_cid = kwqe1->pg_cid;
1850 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
1851 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1852 int ret;
1853
1854 if (num < 2) {
1855 *work = num;
1856 return -EINVAL;
1857 }
1858
1859 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
1860 *work = 3;
1861 else
1862 *work = 2;
1863
1864 if (num < *work) {
1865 *work = num;
1866 return -EINVAL;
1867 }
1868
1869 if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
1870 netdev_err(dev->netdev, "conn_buf size too big\n");
1871 return -ENOMEM;
1872 }
1873 conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1874 if (!conn_buf)
1875 return -ENOMEM;
1876
1877 memset(conn_buf, 0, sizeof(*conn_buf));
1878
1879 conn_addr = &conn_buf->conn_addr_buf;
1880 conn_addr->remote_addr_0 = csk->ha[0];
1881 conn_addr->remote_addr_1 = csk->ha[1];
1882 conn_addr->remote_addr_2 = csk->ha[2];
1883 conn_addr->remote_addr_3 = csk->ha[3];
1884 conn_addr->remote_addr_4 = csk->ha[4];
1885 conn_addr->remote_addr_5 = csk->ha[5];
1886
1887 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
1888 struct l4_kwq_connect_req2 *kwqe2 =
1889 (struct l4_kwq_connect_req2 *) wqes[1];
1890
1891 conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
1892 conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
1893 conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
1894
1895 conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
1896 conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
1897 conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
1898 conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
1899 }
1900 kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
1901
1902 conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
1903 conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
1904 conn_addr->local_tcp_port = kwqe1->src_port;
1905 conn_addr->remote_tcp_port = kwqe1->dst_port;
1906
1907 conn_addr->pmtu = kwqe3->pmtu;
1908 cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
1909
1910 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1911 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->func), csk->vlan_id);
1912
1913 cnic_bnx2x_set_tcp_timestamp(dev,
1914 kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
1915
1916 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
1917 kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
1918 if (!ret)
1919 ctx->ctx_flags |= CTX_FL_OFFLD_START;
1920
1921 return ret;
1922 }
1923
1924 static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
1925 {
1926 struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
1927 union l5cm_specific_data l5_data;
1928 int ret;
1929
1930 memset(&l5_data, 0, sizeof(l5_data));
1931 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
1932 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
1933 return ret;
1934 }
1935
1936 static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
1937 {
1938 struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
1939 union l5cm_specific_data l5_data;
1940 int ret;
1941
1942 memset(&l5_data, 0, sizeof(l5_data));
1943 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
1944 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
1945 return ret;
1946 }
1947 static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
1948 {
1949 struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
1950 struct l4_kcq kcqe;
1951 struct kcqe *cqes[1];
1952
1953 memset(&kcqe, 0, sizeof(kcqe));
1954 kcqe.pg_host_opaque = req->host_opaque;
1955 kcqe.pg_cid = req->host_opaque;
1956 kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
1957 cqes[0] = (struct kcqe *) &kcqe;
1958 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
1959 return 0;
1960 }
1961
1962 static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
1963 {
1964 struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
1965 struct l4_kcq kcqe;
1966 struct kcqe *cqes[1];
1967
1968 memset(&kcqe, 0, sizeof(kcqe));
1969 kcqe.pg_host_opaque = req->pg_host_opaque;
1970 kcqe.pg_cid = req->pg_cid;
1971 kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
1972 cqes[0] = (struct kcqe *) &kcqe;
1973 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
1974 return 0;
1975 }
1976
1977 static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
1978 u32 num_wqes)
1979 {
1980 int i, work, ret;
1981 u32 opcode;
1982 struct kwqe *kwqe;
1983
1984 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
1985 return -EAGAIN; /* bnx2 is down */
1986
1987 for (i = 0; i < num_wqes; ) {
1988 kwqe = wqes[i];
1989 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
1990 work = 1;
1991
1992 switch (opcode) {
1993 case ISCSI_KWQE_OPCODE_INIT1:
1994 ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
1995 break;
1996 case ISCSI_KWQE_OPCODE_INIT2:
1997 ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
1998 break;
1999 case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
2000 ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
2001 num_wqes - i, &work);
2002 break;
2003 case ISCSI_KWQE_OPCODE_UPDATE_CONN:
2004 ret = cnic_bnx2x_iscsi_update(dev, kwqe);
2005 break;
2006 case ISCSI_KWQE_OPCODE_DESTROY_CONN:
2007 ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
2008 break;
2009 case L4_KWQE_OPCODE_VALUE_CONNECT1:
2010 ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
2011 &work);
2012 break;
2013 case L4_KWQE_OPCODE_VALUE_CLOSE:
2014 ret = cnic_bnx2x_close(dev, kwqe);
2015 break;
2016 case L4_KWQE_OPCODE_VALUE_RESET:
2017 ret = cnic_bnx2x_reset(dev, kwqe);
2018 break;
2019 case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
2020 ret = cnic_bnx2x_offload_pg(dev, kwqe);
2021 break;
2022 case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
2023 ret = cnic_bnx2x_update_pg(dev, kwqe);
2024 break;
2025 case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
2026 ret = 0;
2027 break;
2028 default:
2029 ret = 0;
2030 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2031 opcode);
2032 break;
2033 }
2034 if (ret < 0)
2035 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2036 opcode);
2037 i += work;
2038 }
2039 return 0;
2040 }
2041
2042 static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2043 {
2044 struct cnic_local *cp = dev->cnic_priv;
2045 int i, j;
2046
2047 i = 0;
2048 j = 1;
2049 while (num_cqes) {
2050 struct cnic_ulp_ops *ulp_ops;
2051 int ulp_type;
2052 u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
2053 u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
2054
2055 if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
2056 cnic_kwq_completion(dev, 1);
2057
2058 while (j < num_cqes) {
2059 u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
2060
2061 if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
2062 break;
2063
2064 if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
2065 cnic_kwq_completion(dev, 1);
2066 j++;
2067 }
2068
2069 if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
2070 ulp_type = CNIC_ULP_RDMA;
2071 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
2072 ulp_type = CNIC_ULP_ISCSI;
2073 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
2074 ulp_type = CNIC_ULP_L4;
2075 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
2076 goto end;
2077 else {
2078 netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
2079 kcqe_op_flag);
2080 goto end;
2081 }
2082
2083 rcu_read_lock();
2084 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
2085 if (likely(ulp_ops)) {
2086 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
2087 cp->completed_kcq + i, j);
2088 }
2089 rcu_read_unlock();
2090 end:
2091 num_cqes -= j;
2092 i += j;
2093 j = 1;
2094 }
2095 return;
2096 }
2097
2098 static u16 cnic_bnx2_next_idx(u16 idx)
2099 {
2100 return idx + 1;
2101 }
2102
2103 static u16 cnic_bnx2_hw_idx(u16 idx)
2104 {
2105 return idx;
2106 }
2107
2108 static u16 cnic_bnx2x_next_idx(u16 idx)
2109 {
2110 idx++;
2111 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2112 idx++;
2113
2114 return idx;
2115 }
2116
2117 static u16 cnic_bnx2x_hw_idx(u16 idx)
2118 {
2119 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2120 idx++;
2121 return idx;
2122 }
2123
2124 static int cnic_get_kcqes(struct cnic_dev *dev, u16 hw_prod, u16 *sw_prod)
2125 {
2126 struct cnic_local *cp = dev->cnic_priv;
2127 u16 i, ri, last;
2128 struct kcqe *kcqe;
2129 int kcqe_cnt = 0, last_cnt = 0;
2130
2131 i = ri = last = *sw_prod;
2132 ri &= MAX_KCQ_IDX;
2133
2134 while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
2135 kcqe = &cp->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
2136 cp->completed_kcq[kcqe_cnt++] = kcqe;
2137 i = cp->next_idx(i);
2138 ri = i & MAX_KCQ_IDX;
2139 if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
2140 last_cnt = kcqe_cnt;
2141 last = i;
2142 }
2143 }
2144
2145 *sw_prod = last;
2146 return last_cnt;
2147 }
2148
2149 static void cnic_chk_pkt_rings(struct cnic_local *cp)
2150 {
2151 u16 rx_cons = *cp->rx_cons_ptr;
2152 u16 tx_cons = *cp->tx_cons_ptr;
2153
2154 if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
2155 cp->tx_cons = tx_cons;
2156 cp->rx_cons = rx_cons;
2157
2158 uio_event_notify(cp->cnic_uinfo);
2159 }
2160 }
2161
2162 static int cnic_service_bnx2(void *data, void *status_blk)
2163 {
2164 struct cnic_dev *dev = data;
2165 struct status_block *sblk = status_blk;
2166 struct cnic_local *cp = dev->cnic_priv;
2167 u32 status_idx = sblk->status_idx;
2168 u16 hw_prod, sw_prod;
2169 int kcqe_cnt;
2170
2171 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2172 return status_idx;
2173
2174 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2175
2176 hw_prod = sblk->status_completion_producer_index;
2177 sw_prod = cp->kcq_prod_idx;
2178 while (sw_prod != hw_prod) {
2179 kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
2180 if (kcqe_cnt == 0)
2181 goto done;
2182
2183 service_kcqes(dev, kcqe_cnt);
2184
2185 /* Tell compiler that status_blk fields can change. */
2186 barrier();
2187 if (status_idx != sblk->status_idx) {
2188 status_idx = sblk->status_idx;
2189 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2190 hw_prod = sblk->status_completion_producer_index;
2191 } else
2192 break;
2193 }
2194
2195 done:
2196 CNIC_WR16(dev, cp->kcq_io_addr, sw_prod);
2197
2198 cp->kcq_prod_idx = sw_prod;
2199
2200 cnic_chk_pkt_rings(cp);
2201 return status_idx;
2202 }
2203
2204 static void cnic_service_bnx2_msix(unsigned long data)
2205 {
2206 struct cnic_dev *dev = (struct cnic_dev *) data;
2207 struct cnic_local *cp = dev->cnic_priv;
2208 struct status_block_msix *status_blk = cp->status_blk.bnx2;
2209 u32 status_idx = status_blk->status_idx;
2210 u16 hw_prod, sw_prod;
2211 int kcqe_cnt;
2212
2213 cp->kwq_con_idx = status_blk->status_cmd_consumer_index;
2214
2215 hw_prod = status_blk->status_completion_producer_index;
2216 sw_prod = cp->kcq_prod_idx;
2217 while (sw_prod != hw_prod) {
2218 kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
2219 if (kcqe_cnt == 0)
2220 goto done;
2221
2222 service_kcqes(dev, kcqe_cnt);
2223
2224 /* Tell compiler that status_blk fields can change. */
2225 barrier();
2226 if (status_idx != status_blk->status_idx) {
2227 status_idx = status_blk->status_idx;
2228 cp->kwq_con_idx = status_blk->status_cmd_consumer_index;
2229 hw_prod = status_blk->status_completion_producer_index;
2230 } else
2231 break;
2232 }
2233
2234 done:
2235 CNIC_WR16(dev, cp->kcq_io_addr, sw_prod);
2236 cp->kcq_prod_idx = sw_prod;
2237
2238 cnic_chk_pkt_rings(cp);
2239
2240 cp->last_status_idx = status_idx;
2241 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
2242 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
2243 }
2244
2245 static irqreturn_t cnic_irq(int irq, void *dev_instance)
2246 {
2247 struct cnic_dev *dev = dev_instance;
2248 struct cnic_local *cp = dev->cnic_priv;
2249 u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX;
2250
2251 if (cp->ack_int)
2252 cp->ack_int(dev);
2253
2254 prefetch(cp->status_blk.gen);
2255 prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
2256
2257 if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2258 tasklet_schedule(&cp->cnic_irq_task);
2259
2260 return IRQ_HANDLED;
2261 }
2262
2263 static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
2264 u16 index, u8 op, u8 update)
2265 {
2266 struct cnic_local *cp = dev->cnic_priv;
2267 u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
2268 COMMAND_REG_INT_ACK);
2269 struct igu_ack_register igu_ack;
2270
2271 igu_ack.status_block_index = index;
2272 igu_ack.sb_id_and_flags =
2273 ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2274 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2275 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2276 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2277
2278 CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
2279 }
2280
2281 static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
2282 {
2283 struct cnic_local *cp = dev->cnic_priv;
2284
2285 cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID, 0,
2286 IGU_INT_DISABLE, 0);
2287 }
2288
2289 static void cnic_service_bnx2x_bh(unsigned long data)
2290 {
2291 struct cnic_dev *dev = (struct cnic_dev *) data;
2292 struct cnic_local *cp = dev->cnic_priv;
2293 u16 hw_prod, sw_prod;
2294 struct cstorm_status_block_c *sblk =
2295 &cp->status_blk.bnx2x->c_status_block;
2296 u32 status_idx = sblk->status_block_index;
2297 int kcqe_cnt;
2298
2299 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2300 return;
2301
2302 hw_prod = sblk->index_values[HC_INDEX_C_ISCSI_EQ_CONS];
2303 hw_prod = cp->hw_idx(hw_prod);
2304 sw_prod = cp->kcq_prod_idx;
2305 while (sw_prod != hw_prod) {
2306 kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
2307 if (kcqe_cnt == 0)
2308 goto done;
2309
2310 service_kcqes(dev, kcqe_cnt);
2311
2312 /* Tell compiler that sblk fields can change. */
2313 barrier();
2314 if (status_idx == sblk->status_block_index)
2315 break;
2316
2317 status_idx = sblk->status_block_index;
2318 hw_prod = sblk->index_values[HC_INDEX_C_ISCSI_EQ_CONS];
2319 hw_prod = cp->hw_idx(hw_prod);
2320 }
2321
2322 done:
2323 CNIC_WR16(dev, cp->kcq_io_addr, sw_prod + MAX_KCQ_IDX);
2324 cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID,
2325 status_idx, IGU_INT_ENABLE, 1);
2326
2327 cp->kcq_prod_idx = sw_prod;
2328 return;
2329 }
2330
2331 static int cnic_service_bnx2x(void *data, void *status_blk)
2332 {
2333 struct cnic_dev *dev = data;
2334 struct cnic_local *cp = dev->cnic_priv;
2335 u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX;
2336
2337 prefetch(cp->status_blk.bnx2x);
2338 prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
2339
2340 if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2341 tasklet_schedule(&cp->cnic_irq_task);
2342
2343 cnic_chk_pkt_rings(cp);
2344
2345 return 0;
2346 }
2347
2348 static void cnic_ulp_stop(struct cnic_dev *dev)
2349 {
2350 struct cnic_local *cp = dev->cnic_priv;
2351 int if_type;
2352
2353 if (cp->cnic_uinfo)
2354 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
2355
2356 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
2357 struct cnic_ulp_ops *ulp_ops;
2358
2359 mutex_lock(&cnic_lock);
2360 ulp_ops = cp->ulp_ops[if_type];
2361 if (!ulp_ops) {
2362 mutex_unlock(&cnic_lock);
2363 continue;
2364 }
2365 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2366 mutex_unlock(&cnic_lock);
2367
2368 if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2369 ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
2370
2371 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2372 }
2373 }
2374
2375 static void cnic_ulp_start(struct cnic_dev *dev)
2376 {
2377 struct cnic_local *cp = dev->cnic_priv;
2378 int if_type;
2379
2380 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
2381 struct cnic_ulp_ops *ulp_ops;
2382
2383 mutex_lock(&cnic_lock);
2384 ulp_ops = cp->ulp_ops[if_type];
2385 if (!ulp_ops || !ulp_ops->cnic_start) {
2386 mutex_unlock(&cnic_lock);
2387 continue;
2388 }
2389 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2390 mutex_unlock(&cnic_lock);
2391
2392 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2393 ulp_ops->cnic_start(cp->ulp_handle[if_type]);
2394
2395 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2396 }
2397 }
2398
2399 static int cnic_ctl(void *data, struct cnic_ctl_info *info)
2400 {
2401 struct cnic_dev *dev = data;
2402
2403 switch (info->cmd) {
2404 case CNIC_CTL_STOP_CMD:
2405 cnic_hold(dev);
2406
2407 cnic_ulp_stop(dev);
2408 cnic_stop_hw(dev);
2409
2410 cnic_put(dev);
2411 break;
2412 case CNIC_CTL_START_CMD:
2413 cnic_hold(dev);
2414
2415 if (!cnic_start_hw(dev))
2416 cnic_ulp_start(dev);
2417
2418 cnic_put(dev);
2419 break;
2420 case CNIC_CTL_COMPLETION_CMD: {
2421 u32 cid = BNX2X_SW_CID(info->data.comp.cid);
2422 u32 l5_cid;
2423 struct cnic_local *cp = dev->cnic_priv;
2424
2425 if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
2426 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
2427
2428 ctx->wait_cond = 1;
2429 wake_up(&ctx->waitq);
2430 }
2431 break;
2432 }
2433 default:
2434 return -EINVAL;
2435 }
2436 return 0;
2437 }
2438
2439 static void cnic_ulp_init(struct cnic_dev *dev)
2440 {
2441 int i;
2442 struct cnic_local *cp = dev->cnic_priv;
2443
2444 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
2445 struct cnic_ulp_ops *ulp_ops;
2446
2447 mutex_lock(&cnic_lock);
2448 ulp_ops = cnic_ulp_tbl[i];
2449 if (!ulp_ops || !ulp_ops->cnic_init) {
2450 mutex_unlock(&cnic_lock);
2451 continue;
2452 }
2453 ulp_get(ulp_ops);
2454 mutex_unlock(&cnic_lock);
2455
2456 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
2457 ulp_ops->cnic_init(dev);
2458
2459 ulp_put(ulp_ops);
2460 }
2461 }
2462
2463 static void cnic_ulp_exit(struct cnic_dev *dev)
2464 {
2465 int i;
2466 struct cnic_local *cp = dev->cnic_priv;
2467
2468 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
2469 struct cnic_ulp_ops *ulp_ops;
2470
2471 mutex_lock(&cnic_lock);
2472 ulp_ops = cnic_ulp_tbl[i];
2473 if (!ulp_ops || !ulp_ops->cnic_exit) {
2474 mutex_unlock(&cnic_lock);
2475 continue;
2476 }
2477 ulp_get(ulp_ops);
2478 mutex_unlock(&cnic_lock);
2479
2480 if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
2481 ulp_ops->cnic_exit(dev);
2482
2483 ulp_put(ulp_ops);
2484 }
2485 }
2486
2487 static int cnic_cm_offload_pg(struct cnic_sock *csk)
2488 {
2489 struct cnic_dev *dev = csk->dev;
2490 struct l4_kwq_offload_pg *l4kwqe;
2491 struct kwqe *wqes[1];
2492
2493 l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
2494 memset(l4kwqe, 0, sizeof(*l4kwqe));
2495 wqes[0] = (struct kwqe *) l4kwqe;
2496
2497 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
2498 l4kwqe->flags =
2499 L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
2500 l4kwqe->l2hdr_nbytes = ETH_HLEN;
2501
2502 l4kwqe->da0 = csk->ha[0];
2503 l4kwqe->da1 = csk->ha[1];
2504 l4kwqe->da2 = csk->ha[2];
2505 l4kwqe->da3 = csk->ha[3];
2506 l4kwqe->da4 = csk->ha[4];
2507 l4kwqe->da5 = csk->ha[5];
2508
2509 l4kwqe->sa0 = dev->mac_addr[0];
2510 l4kwqe->sa1 = dev->mac_addr[1];
2511 l4kwqe->sa2 = dev->mac_addr[2];
2512 l4kwqe->sa3 = dev->mac_addr[3];
2513 l4kwqe->sa4 = dev->mac_addr[4];
2514 l4kwqe->sa5 = dev->mac_addr[5];
2515
2516 l4kwqe->etype = ETH_P_IP;
2517 l4kwqe->ipid_start = DEF_IPID_START;
2518 l4kwqe->host_opaque = csk->l5_cid;
2519
2520 if (csk->vlan_id) {
2521 l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
2522 l4kwqe->vlan_tag = csk->vlan_id;
2523 l4kwqe->l2hdr_nbytes += 4;
2524 }
2525
2526 return dev->submit_kwqes(dev, wqes, 1);
2527 }
2528
2529 static int cnic_cm_update_pg(struct cnic_sock *csk)
2530 {
2531 struct cnic_dev *dev = csk->dev;
2532 struct l4_kwq_update_pg *l4kwqe;
2533 struct kwqe *wqes[1];
2534
2535 l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
2536 memset(l4kwqe, 0, sizeof(*l4kwqe));
2537 wqes[0] = (struct kwqe *) l4kwqe;
2538
2539 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
2540 l4kwqe->flags =
2541 L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
2542 l4kwqe->pg_cid = csk->pg_cid;
2543
2544 l4kwqe->da0 = csk->ha[0];
2545 l4kwqe->da1 = csk->ha[1];
2546 l4kwqe->da2 = csk->ha[2];
2547 l4kwqe->da3 = csk->ha[3];
2548 l4kwqe->da4 = csk->ha[4];
2549 l4kwqe->da5 = csk->ha[5];
2550
2551 l4kwqe->pg_host_opaque = csk->l5_cid;
2552 l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
2553
2554 return dev->submit_kwqes(dev, wqes, 1);
2555 }
2556
2557 static int cnic_cm_upload_pg(struct cnic_sock *csk)
2558 {
2559 struct cnic_dev *dev = csk->dev;
2560 struct l4_kwq_upload *l4kwqe;
2561 struct kwqe *wqes[1];
2562
2563 l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
2564 memset(l4kwqe, 0, sizeof(*l4kwqe));
2565 wqes[0] = (struct kwqe *) l4kwqe;
2566
2567 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
2568 l4kwqe->flags =
2569 L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
2570 l4kwqe->cid = csk->pg_cid;
2571
2572 return dev->submit_kwqes(dev, wqes, 1);
2573 }
2574
2575 static int cnic_cm_conn_req(struct cnic_sock *csk)
2576 {
2577 struct cnic_dev *dev = csk->dev;
2578 struct l4_kwq_connect_req1 *l4kwqe1;
2579 struct l4_kwq_connect_req2 *l4kwqe2;
2580 struct l4_kwq_connect_req3 *l4kwqe3;
2581 struct kwqe *wqes[3];
2582 u8 tcp_flags = 0;
2583 int num_wqes = 2;
2584
2585 l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
2586 l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
2587 l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
2588 memset(l4kwqe1, 0, sizeof(*l4kwqe1));
2589 memset(l4kwqe2, 0, sizeof(*l4kwqe2));
2590 memset(l4kwqe3, 0, sizeof(*l4kwqe3));
2591
2592 l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
2593 l4kwqe3->flags =
2594 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
2595 l4kwqe3->ka_timeout = csk->ka_timeout;
2596 l4kwqe3->ka_interval = csk->ka_interval;
2597 l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
2598 l4kwqe3->tos = csk->tos;
2599 l4kwqe3->ttl = csk->ttl;
2600 l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
2601 l4kwqe3->pmtu = csk->mtu;
2602 l4kwqe3->rcv_buf = csk->rcv_buf;
2603 l4kwqe3->snd_buf = csk->snd_buf;
2604 l4kwqe3->seed = csk->seed;
2605
2606 wqes[0] = (struct kwqe *) l4kwqe1;
2607 if (test_bit(SK_F_IPV6, &csk->flags)) {
2608 wqes[1] = (struct kwqe *) l4kwqe2;
2609 wqes[2] = (struct kwqe *) l4kwqe3;
2610 num_wqes = 3;
2611
2612 l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
2613 l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
2614 l4kwqe2->flags =
2615 L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
2616 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
2617 l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
2618 l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
2619 l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
2620 l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
2621 l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
2622 l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
2623 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
2624 sizeof(struct tcphdr);
2625 } else {
2626 wqes[1] = (struct kwqe *) l4kwqe3;
2627 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
2628 sizeof(struct tcphdr);
2629 }
2630
2631 l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
2632 l4kwqe1->flags =
2633 (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
2634 L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
2635 l4kwqe1->cid = csk->cid;
2636 l4kwqe1->pg_cid = csk->pg_cid;
2637 l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
2638 l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
2639 l4kwqe1->src_port = be16_to_cpu(csk->src_port);
2640 l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
2641 if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
2642 tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
2643 if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
2644 tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
2645 if (csk->tcp_flags & SK_TCP_NAGLE)
2646 tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
2647 if (csk->tcp_flags & SK_TCP_TIMESTAMP)
2648 tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
2649 if (csk->tcp_flags & SK_TCP_SACK)
2650 tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
2651 if (csk->tcp_flags & SK_TCP_SEG_SCALING)
2652 tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
2653
2654 l4kwqe1->tcp_flags = tcp_flags;
2655
2656 return dev->submit_kwqes(dev, wqes, num_wqes);
2657 }
2658
2659 static int cnic_cm_close_req(struct cnic_sock *csk)
2660 {
2661 struct cnic_dev *dev = csk->dev;
2662 struct l4_kwq_close_req *l4kwqe;
2663 struct kwqe *wqes[1];
2664
2665 l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
2666 memset(l4kwqe, 0, sizeof(*l4kwqe));
2667 wqes[0] = (struct kwqe *) l4kwqe;
2668
2669 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
2670 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
2671 l4kwqe->cid = csk->cid;
2672
2673 return dev->submit_kwqes(dev, wqes, 1);
2674 }
2675
2676 static int cnic_cm_abort_req(struct cnic_sock *csk)
2677 {
2678 struct cnic_dev *dev = csk->dev;
2679 struct l4_kwq_reset_req *l4kwqe;
2680 struct kwqe *wqes[1];
2681
2682 l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
2683 memset(l4kwqe, 0, sizeof(*l4kwqe));
2684 wqes[0] = (struct kwqe *) l4kwqe;
2685
2686 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
2687 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
2688 l4kwqe->cid = csk->cid;
2689
2690 return dev->submit_kwqes(dev, wqes, 1);
2691 }
2692
2693 static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
2694 u32 l5_cid, struct cnic_sock **csk, void *context)
2695 {
2696 struct cnic_local *cp = dev->cnic_priv;
2697 struct cnic_sock *csk1;
2698
2699 if (l5_cid >= MAX_CM_SK_TBL_SZ)
2700 return -EINVAL;
2701
2702 csk1 = &cp->csk_tbl[l5_cid];
2703 if (atomic_read(&csk1->ref_count))
2704 return -EAGAIN;
2705
2706 if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
2707 return -EBUSY;
2708
2709 csk1->dev = dev;
2710 csk1->cid = cid;
2711 csk1->l5_cid = l5_cid;
2712 csk1->ulp_type = ulp_type;
2713 csk1->context = context;
2714
2715 csk1->ka_timeout = DEF_KA_TIMEOUT;
2716 csk1->ka_interval = DEF_KA_INTERVAL;
2717 csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
2718 csk1->tos = DEF_TOS;
2719 csk1->ttl = DEF_TTL;
2720 csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
2721 csk1->rcv_buf = DEF_RCV_BUF;
2722 csk1->snd_buf = DEF_SND_BUF;
2723 csk1->seed = DEF_SEED;
2724
2725 *csk = csk1;
2726 return 0;
2727 }
2728
2729 static void cnic_cm_cleanup(struct cnic_sock *csk)
2730 {
2731 if (csk->src_port) {
2732 struct cnic_dev *dev = csk->dev;
2733 struct cnic_local *cp = dev->cnic_priv;
2734
2735 cnic_free_id(&cp->csk_port_tbl, csk->src_port);
2736 csk->src_port = 0;
2737 }
2738 }
2739
2740 static void cnic_close_conn(struct cnic_sock *csk)
2741 {
2742 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
2743 cnic_cm_upload_pg(csk);
2744 clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
2745 }
2746 cnic_cm_cleanup(csk);
2747 }
2748
2749 static int cnic_cm_destroy(struct cnic_sock *csk)
2750 {
2751 if (!cnic_in_use(csk))
2752 return -EINVAL;
2753
2754 csk_hold(csk);
2755 clear_bit(SK_F_INUSE, &csk->flags);
2756 smp_mb__after_clear_bit();
2757 while (atomic_read(&csk->ref_count) != 1)
2758 msleep(1);
2759 cnic_cm_cleanup(csk);
2760
2761 csk->flags = 0;
2762 csk_put(csk);
2763 return 0;
2764 }
2765
2766 static inline u16 cnic_get_vlan(struct net_device *dev,
2767 struct net_device **vlan_dev)
2768 {
2769 if (dev->priv_flags & IFF_802_1Q_VLAN) {
2770 *vlan_dev = vlan_dev_real_dev(dev);
2771 return vlan_dev_vlan_id(dev);
2772 }
2773 *vlan_dev = dev;
2774 return 0;
2775 }
2776
2777 static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
2778 struct dst_entry **dst)
2779 {
2780 #if defined(CONFIG_INET)
2781 struct flowi fl;
2782 int err;
2783 struct rtable *rt;
2784
2785 memset(&fl, 0, sizeof(fl));
2786 fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
2787
2788 err = ip_route_output_key(&init_net, &rt, &fl);
2789 if (!err)
2790 *dst = &rt->u.dst;
2791 return err;
2792 #else
2793 return -ENETUNREACH;
2794 #endif
2795 }
2796
2797 static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
2798 struct dst_entry **dst)
2799 {
2800 #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
2801 struct flowi fl;
2802
2803 memset(&fl, 0, sizeof(fl));
2804 ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
2805 if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
2806 fl.oif = dst_addr->sin6_scope_id;
2807
2808 *dst = ip6_route_output(&init_net, NULL, &fl);
2809 if (*dst)
2810 return 0;
2811 #endif
2812
2813 return -ENETUNREACH;
2814 }
2815
2816 static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
2817 int ulp_type)
2818 {
2819 struct cnic_dev *dev = NULL;
2820 struct dst_entry *dst;
2821 struct net_device *netdev = NULL;
2822 int err = -ENETUNREACH;
2823
2824 if (dst_addr->sin_family == AF_INET)
2825 err = cnic_get_v4_route(dst_addr, &dst);
2826 else if (dst_addr->sin_family == AF_INET6) {
2827 struct sockaddr_in6 *dst_addr6 =
2828 (struct sockaddr_in6 *) dst_addr;
2829
2830 err = cnic_get_v6_route(dst_addr6, &dst);
2831 } else
2832 return NULL;
2833
2834 if (err)
2835 return NULL;
2836
2837 if (!dst->dev)
2838 goto done;
2839
2840 cnic_get_vlan(dst->dev, &netdev);
2841
2842 dev = cnic_from_netdev(netdev);
2843
2844 done:
2845 dst_release(dst);
2846 if (dev)
2847 cnic_put(dev);
2848 return dev;
2849 }
2850
2851 static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
2852 {
2853 struct cnic_dev *dev = csk->dev;
2854 struct cnic_local *cp = dev->cnic_priv;
2855
2856 return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
2857 }
2858
2859 static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
2860 {
2861 struct cnic_dev *dev = csk->dev;
2862 struct cnic_local *cp = dev->cnic_priv;
2863 int is_v6, rc = 0;
2864 struct dst_entry *dst = NULL;
2865 struct net_device *realdev;
2866 u32 local_port;
2867
2868 if (saddr->local.v6.sin6_family == AF_INET6 &&
2869 saddr->remote.v6.sin6_family == AF_INET6)
2870 is_v6 = 1;
2871 else if (saddr->local.v4.sin_family == AF_INET &&
2872 saddr->remote.v4.sin_family == AF_INET)
2873 is_v6 = 0;
2874 else
2875 return -EINVAL;
2876
2877 clear_bit(SK_F_IPV6, &csk->flags);
2878
2879 if (is_v6) {
2880 set_bit(SK_F_IPV6, &csk->flags);
2881 cnic_get_v6_route(&saddr->remote.v6, &dst);
2882
2883 memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
2884 sizeof(struct in6_addr));
2885 csk->dst_port = saddr->remote.v6.sin6_port;
2886 local_port = saddr->local.v6.sin6_port;
2887
2888 } else {
2889 cnic_get_v4_route(&saddr->remote.v4, &dst);
2890
2891 csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
2892 csk->dst_port = saddr->remote.v4.sin_port;
2893 local_port = saddr->local.v4.sin_port;
2894 }
2895
2896 csk->vlan_id = 0;
2897 csk->mtu = dev->netdev->mtu;
2898 if (dst && dst->dev) {
2899 u16 vlan = cnic_get_vlan(dst->dev, &realdev);
2900 if (realdev == dev->netdev) {
2901 csk->vlan_id = vlan;
2902 csk->mtu = dst_mtu(dst);
2903 }
2904 }
2905
2906 if (local_port >= CNIC_LOCAL_PORT_MIN &&
2907 local_port < CNIC_LOCAL_PORT_MAX) {
2908 if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
2909 local_port = 0;
2910 } else
2911 local_port = 0;
2912
2913 if (!local_port) {
2914 local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
2915 if (local_port == -1) {
2916 rc = -ENOMEM;
2917 goto err_out;
2918 }
2919 }
2920 csk->src_port = local_port;
2921
2922 err_out:
2923 dst_release(dst);
2924 return rc;
2925 }
2926
2927 static void cnic_init_csk_state(struct cnic_sock *csk)
2928 {
2929 csk->state = 0;
2930 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
2931 clear_bit(SK_F_CLOSING, &csk->flags);
2932 }
2933
2934 static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
2935 {
2936 int err = 0;
2937
2938 if (!cnic_in_use(csk))
2939 return -EINVAL;
2940
2941 if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
2942 return -EINVAL;
2943
2944 cnic_init_csk_state(csk);
2945
2946 err = cnic_get_route(csk, saddr);
2947 if (err)
2948 goto err_out;
2949
2950 err = cnic_resolve_addr(csk, saddr);
2951 if (!err)
2952 return 0;
2953
2954 err_out:
2955 clear_bit(SK_F_CONNECT_START, &csk->flags);
2956 return err;
2957 }
2958
2959 static int cnic_cm_abort(struct cnic_sock *csk)
2960 {
2961 struct cnic_local *cp = csk->dev->cnic_priv;
2962 u32 opcode;
2963
2964 if (!cnic_in_use(csk))
2965 return -EINVAL;
2966
2967 if (cnic_abort_prep(csk))
2968 return cnic_cm_abort_req(csk);
2969
2970 /* Getting here means that we haven't started connect, or
2971 * connect was not successful.
2972 */
2973
2974 csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
2975 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
2976 opcode = csk->state;
2977 else
2978 opcode = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
2979 cp->close_conn(csk, opcode);
2980
2981 return 0;
2982 }
2983
2984 static int cnic_cm_close(struct cnic_sock *csk)
2985 {
2986 if (!cnic_in_use(csk))
2987 return -EINVAL;
2988
2989 if (cnic_close_prep(csk)) {
2990 csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
2991 return cnic_cm_close_req(csk);
2992 }
2993 return 0;
2994 }
2995
2996 static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
2997 u8 opcode)
2998 {
2999 struct cnic_ulp_ops *ulp_ops;
3000 int ulp_type = csk->ulp_type;
3001
3002 rcu_read_lock();
3003 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
3004 if (ulp_ops) {
3005 if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
3006 ulp_ops->cm_connect_complete(csk);
3007 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
3008 ulp_ops->cm_close_complete(csk);
3009 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
3010 ulp_ops->cm_remote_abort(csk);
3011 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
3012 ulp_ops->cm_abort_complete(csk);
3013 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
3014 ulp_ops->cm_remote_close(csk);
3015 }
3016 rcu_read_unlock();
3017 }
3018
3019 static int cnic_cm_set_pg(struct cnic_sock *csk)
3020 {
3021 if (cnic_offld_prep(csk)) {
3022 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3023 cnic_cm_update_pg(csk);
3024 else
3025 cnic_cm_offload_pg(csk);
3026 }
3027 return 0;
3028 }
3029
3030 static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
3031 {
3032 struct cnic_local *cp = dev->cnic_priv;
3033 u32 l5_cid = kcqe->pg_host_opaque;
3034 u8 opcode = kcqe->op_code;
3035 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
3036
3037 csk_hold(csk);
3038 if (!cnic_in_use(csk))
3039 goto done;
3040
3041 if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3042 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3043 goto done;
3044 }
3045 /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
3046 if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
3047 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3048 cnic_cm_upcall(cp, csk,
3049 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3050 goto done;
3051 }
3052
3053 csk->pg_cid = kcqe->pg_cid;
3054 set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3055 cnic_cm_conn_req(csk);
3056
3057 done:
3058 csk_put(csk);
3059 }
3060
3061 static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
3062 {
3063 struct cnic_local *cp = dev->cnic_priv;
3064 struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
3065 u8 opcode = l4kcqe->op_code;
3066 u32 l5_cid;
3067 struct cnic_sock *csk;
3068
3069 if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
3070 opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3071 cnic_cm_process_offld_pg(dev, l4kcqe);
3072 return;
3073 }
3074
3075 l5_cid = l4kcqe->conn_id;
3076 if (opcode & 0x80)
3077 l5_cid = l4kcqe->cid;
3078 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3079 return;
3080
3081 csk = &cp->csk_tbl[l5_cid];
3082 csk_hold(csk);
3083
3084 if (!cnic_in_use(csk)) {
3085 csk_put(csk);
3086 return;
3087 }
3088
3089 switch (opcode) {
3090 case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
3091 if (l4kcqe->status != 0) {
3092 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3093 cnic_cm_upcall(cp, csk,
3094 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3095 }
3096 break;
3097 case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
3098 if (l4kcqe->status == 0)
3099 set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
3100
3101 smp_mb__before_clear_bit();
3102 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3103 cnic_cm_upcall(cp, csk, opcode);
3104 break;
3105
3106 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3107 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
3108 cnic_cm_upcall(cp, csk, opcode);
3109 break;
3110 } else if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags))
3111 csk->state = opcode;
3112 /* fall through */
3113 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3114 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3115 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3116 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3117 cp->close_conn(csk, opcode);
3118 break;
3119
3120 case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
3121 cnic_cm_upcall(cp, csk, opcode);
3122 break;
3123 }
3124 csk_put(csk);
3125 }
3126
3127 static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
3128 {
3129 struct cnic_dev *dev = data;
3130 int i;
3131
3132 for (i = 0; i < num; i++)
3133 cnic_cm_process_kcqe(dev, kcqe[i]);
3134 }
3135
3136 static struct cnic_ulp_ops cm_ulp_ops = {
3137 .indicate_kcqes = cnic_cm_indicate_kcqe,
3138 };
3139
3140 static void cnic_cm_free_mem(struct cnic_dev *dev)
3141 {
3142 struct cnic_local *cp = dev->cnic_priv;
3143
3144 kfree(cp->csk_tbl);
3145 cp->csk_tbl = NULL;
3146 cnic_free_id_tbl(&cp->csk_port_tbl);
3147 }
3148
3149 static int cnic_cm_alloc_mem(struct cnic_dev *dev)
3150 {
3151 struct cnic_local *cp = dev->cnic_priv;
3152
3153 cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
3154 GFP_KERNEL);
3155 if (!cp->csk_tbl)
3156 return -ENOMEM;
3157
3158 if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
3159 CNIC_LOCAL_PORT_MIN)) {
3160 cnic_cm_free_mem(dev);
3161 return -ENOMEM;
3162 }
3163 return 0;
3164 }
3165
3166 static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
3167 {
3168 if ((opcode == csk->state) ||
3169 (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED &&
3170 csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)) {
3171 if (!test_and_set_bit(SK_F_CLOSING, &csk->flags))
3172 return 1;
3173 }
3174 /* 57710+ only workaround to handle unsolicited RESET_COMP
3175 * which will be treated like a RESET RCVD notification
3176 * which triggers the clean up procedure
3177 */
3178 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
3179 if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
3180 csk->state = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
3181 return 1;
3182 }
3183 }
3184 return 0;
3185 }
3186
3187 static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
3188 {
3189 struct cnic_dev *dev = csk->dev;
3190 struct cnic_local *cp = dev->cnic_priv;
3191
3192 clear_bit(SK_F_CONNECT_START, &csk->flags);
3193 cnic_close_conn(csk);
3194 cnic_cm_upcall(cp, csk, opcode);
3195 }
3196
3197 static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
3198 {
3199 }
3200
3201 static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
3202 {
3203 u32 seed;
3204
3205 get_random_bytes(&seed, 4);
3206 cnic_ctx_wr(dev, 45, 0, seed);
3207 return 0;
3208 }
3209
3210 static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
3211 {
3212 struct cnic_dev *dev = csk->dev;
3213 struct cnic_local *cp = dev->cnic_priv;
3214 struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
3215 union l5cm_specific_data l5_data;
3216 u32 cmd = 0;
3217 int close_complete = 0;
3218
3219 switch (opcode) {
3220 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3221 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3222 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3223 if (cnic_ready_to_close(csk, opcode))
3224 cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
3225 break;
3226 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3227 cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
3228 break;
3229 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3230 close_complete = 1;
3231 break;
3232 }
3233 if (cmd) {
3234 memset(&l5_data, 0, sizeof(l5_data));
3235
3236 cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
3237 &l5_data);
3238 } else if (close_complete) {
3239 ctx->timestamp = jiffies;
3240 cnic_close_conn(csk);
3241 cnic_cm_upcall(cp, csk, csk->state);
3242 }
3243 }
3244
3245 static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
3246 {
3247 }
3248
3249 static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
3250 {
3251 struct cnic_local *cp = dev->cnic_priv;
3252 int func = CNIC_FUNC(cp);
3253
3254 cnic_init_bnx2x_mac(dev);
3255 cnic_bnx2x_set_tcp_timestamp(dev, 1);
3256
3257 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
3258 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(func), 0);
3259
3260 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3261 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(func), 1);
3262 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3263 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(func),
3264 DEF_MAX_DA_COUNT);
3265
3266 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3267 XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(func), DEF_TTL);
3268 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3269 XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(func), DEF_TOS);
3270 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3271 XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(func), 2);
3272 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3273 XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(func), DEF_SWS_TIMER);
3274
3275 CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(func),
3276 DEF_MAX_CWND);
3277 return 0;
3278 }
3279
3280 static int cnic_cm_open(struct cnic_dev *dev)
3281 {
3282 struct cnic_local *cp = dev->cnic_priv;
3283 int err;
3284
3285 err = cnic_cm_alloc_mem(dev);
3286 if (err)
3287 return err;
3288
3289 err = cp->start_cm(dev);
3290
3291 if (err)
3292 goto err_out;
3293
3294 dev->cm_create = cnic_cm_create;
3295 dev->cm_destroy = cnic_cm_destroy;
3296 dev->cm_connect = cnic_cm_connect;
3297 dev->cm_abort = cnic_cm_abort;
3298 dev->cm_close = cnic_cm_close;
3299 dev->cm_select_dev = cnic_cm_select_dev;
3300
3301 cp->ulp_handle[CNIC_ULP_L4] = dev;
3302 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
3303 return 0;
3304
3305 err_out:
3306 cnic_cm_free_mem(dev);
3307 return err;
3308 }
3309
3310 static int cnic_cm_shutdown(struct cnic_dev *dev)
3311 {
3312 struct cnic_local *cp = dev->cnic_priv;
3313 int i;
3314
3315 cp->stop_cm(dev);
3316
3317 if (!cp->csk_tbl)
3318 return 0;
3319
3320 for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
3321 struct cnic_sock *csk = &cp->csk_tbl[i];
3322
3323 clear_bit(SK_F_INUSE, &csk->flags);
3324 cnic_cm_cleanup(csk);
3325 }
3326 cnic_cm_free_mem(dev);
3327
3328 return 0;
3329 }
3330
3331 static void cnic_init_context(struct cnic_dev *dev, u32 cid)
3332 {
3333 struct cnic_local *cp = dev->cnic_priv;
3334 u32 cid_addr;
3335 int i;
3336
3337 if (CHIP_NUM(cp) == CHIP_NUM_5709)
3338 return;
3339
3340 cid_addr = GET_CID_ADDR(cid);
3341
3342 for (i = 0; i < CTX_SIZE; i += 4)
3343 cnic_ctx_wr(dev, cid_addr, i, 0);
3344 }
3345
3346 static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
3347 {
3348 struct cnic_local *cp = dev->cnic_priv;
3349 int ret = 0, i;
3350 u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
3351
3352 if (CHIP_NUM(cp) != CHIP_NUM_5709)
3353 return 0;
3354
3355 for (i = 0; i < cp->ctx_blks; i++) {
3356 int j;
3357 u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
3358 u32 val;
3359
3360 memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
3361
3362 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
3363 (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
3364 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
3365 (u64) cp->ctx_arr[i].mapping >> 32);
3366 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
3367 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3368 for (j = 0; j < 10; j++) {
3369
3370 val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
3371 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
3372 break;
3373 udelay(5);
3374 }
3375 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
3376 ret = -EBUSY;
3377 break;
3378 }
3379 }
3380 return ret;
3381 }
3382
3383 static void cnic_free_irq(struct cnic_dev *dev)
3384 {
3385 struct cnic_local *cp = dev->cnic_priv;
3386 struct cnic_eth_dev *ethdev = cp->ethdev;
3387
3388 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3389 cp->disable_int_sync(dev);
3390 tasklet_disable(&cp->cnic_irq_task);
3391 free_irq(ethdev->irq_arr[0].vector, dev);
3392 }
3393 }
3394
3395 static int cnic_init_bnx2_irq(struct cnic_dev *dev)
3396 {
3397 struct cnic_local *cp = dev->cnic_priv;
3398 struct cnic_eth_dev *ethdev = cp->ethdev;
3399
3400 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3401 int err, i = 0;
3402 int sblk_num = cp->status_blk_num;
3403 u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
3404 BNX2_HC_SB_CONFIG_1;
3405
3406 CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
3407
3408 CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
3409 CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
3410 CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
3411
3412 cp->last_status_idx = cp->status_blk.bnx2->status_idx;
3413 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
3414 (unsigned long) dev);
3415 err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
3416 "cnic", dev);
3417 if (err) {
3418 tasklet_disable(&cp->cnic_irq_task);
3419 return err;
3420 }
3421 while (cp->status_blk.bnx2->status_completion_producer_index &&
3422 i < 10) {
3423 CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
3424 1 << (11 + sblk_num));
3425 udelay(10);
3426 i++;
3427 barrier();
3428 }
3429 if (cp->status_blk.bnx2->status_completion_producer_index) {
3430 cnic_free_irq(dev);
3431 goto failed;
3432 }
3433
3434 } else {
3435 struct status_block *sblk = cp->status_blk.gen;
3436 u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
3437 int i = 0;
3438
3439 while (sblk->status_completion_producer_index && i < 10) {
3440 CNIC_WR(dev, BNX2_HC_COMMAND,
3441 hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3442 udelay(10);
3443 i++;
3444 barrier();
3445 }
3446 if (sblk->status_completion_producer_index)
3447 goto failed;
3448
3449 }
3450 return 0;
3451
3452 failed:
3453 netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
3454 return -EBUSY;
3455 }
3456
3457 static void cnic_enable_bnx2_int(struct cnic_dev *dev)
3458 {
3459 struct cnic_local *cp = dev->cnic_priv;
3460 struct cnic_eth_dev *ethdev = cp->ethdev;
3461
3462 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
3463 return;
3464
3465 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
3466 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
3467 }
3468
3469 static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
3470 {
3471 struct cnic_local *cp = dev->cnic_priv;
3472 struct cnic_eth_dev *ethdev = cp->ethdev;
3473
3474 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
3475 return;
3476
3477 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
3478 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3479 CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
3480 synchronize_irq(ethdev->irq_arr[0].vector);
3481 }
3482
3483 static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
3484 {
3485 struct cnic_local *cp = dev->cnic_priv;
3486 struct cnic_eth_dev *ethdev = cp->ethdev;
3487 u32 cid_addr, tx_cid, sb_id;
3488 u32 val, offset0, offset1, offset2, offset3;
3489 int i;
3490 struct tx_bd *txbd;
3491 dma_addr_t buf_map;
3492 struct status_block *s_blk = cp->status_blk.gen;
3493
3494 sb_id = cp->status_blk_num;
3495 tx_cid = 20;
3496 cnic_init_context(dev, tx_cid);
3497 cnic_init_context(dev, tx_cid + 1);
3498 cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
3499 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3500 struct status_block_msix *sblk = cp->status_blk.bnx2;
3501
3502 tx_cid = TX_TSS_CID + sb_id - 1;
3503 cnic_init_context(dev, tx_cid);
3504 CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
3505 (TX_TSS_CID << 7));
3506 cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
3507 }
3508 cp->tx_cons = *cp->tx_cons_ptr;
3509
3510 cid_addr = GET_CID_ADDR(tx_cid);
3511 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
3512 u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
3513
3514 for (i = 0; i < PHY_CTX_SIZE; i += 4)
3515 cnic_ctx_wr(dev, cid_addr2, i, 0);
3516
3517 offset0 = BNX2_L2CTX_TYPE_XI;
3518 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
3519 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
3520 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
3521 } else {
3522 offset0 = BNX2_L2CTX_TYPE;
3523 offset1 = BNX2_L2CTX_CMD_TYPE;
3524 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
3525 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
3526 }
3527 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
3528 cnic_ctx_wr(dev, cid_addr, offset0, val);
3529
3530 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
3531 cnic_ctx_wr(dev, cid_addr, offset1, val);
3532
3533 txbd = (struct tx_bd *) cp->l2_ring;
3534
3535 buf_map = cp->l2_buf_map;
3536 for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
3537 txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
3538 txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
3539 }
3540 val = (u64) cp->l2_ring_map >> 32;
3541 cnic_ctx_wr(dev, cid_addr, offset2, val);
3542 txbd->tx_bd_haddr_hi = val;
3543
3544 val = (u64) cp->l2_ring_map & 0xffffffff;
3545 cnic_ctx_wr(dev, cid_addr, offset3, val);
3546 txbd->tx_bd_haddr_lo = val;
3547 }
3548
3549 static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
3550 {
3551 struct cnic_local *cp = dev->cnic_priv;
3552 struct cnic_eth_dev *ethdev = cp->ethdev;
3553 u32 cid_addr, sb_id, val, coal_reg, coal_val;
3554 int i;
3555 struct rx_bd *rxbd;
3556 struct status_block *s_blk = cp->status_blk.gen;
3557
3558 sb_id = cp->status_blk_num;
3559 cnic_init_context(dev, 2);
3560 cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
3561 coal_reg = BNX2_HC_COMMAND;
3562 coal_val = CNIC_RD(dev, coal_reg);
3563 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3564 struct status_block_msix *sblk = cp->status_blk.bnx2;
3565
3566 cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
3567 coal_reg = BNX2_HC_COALESCE_NOW;
3568 coal_val = 1 << (11 + sb_id);
3569 }
3570 i = 0;
3571 while (!(*cp->rx_cons_ptr != 0) && i < 10) {
3572 CNIC_WR(dev, coal_reg, coal_val);
3573 udelay(10);
3574 i++;
3575 barrier();
3576 }
3577 cp->rx_cons = *cp->rx_cons_ptr;
3578
3579 cid_addr = GET_CID_ADDR(2);
3580 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
3581 BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
3582 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
3583
3584 if (sb_id == 0)
3585 val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
3586 else
3587 val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
3588 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
3589
3590 rxbd = (struct rx_bd *) (cp->l2_ring + BCM_PAGE_SIZE);
3591 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3592 dma_addr_t buf_map;
3593 int n = (i % cp->l2_rx_ring_size) + 1;
3594
3595 buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
3596 rxbd->rx_bd_len = cp->l2_single_buf_size;
3597 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3598 rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
3599 rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
3600 }
3601 val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
3602 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
3603 rxbd->rx_bd_haddr_hi = val;
3604
3605 val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
3606 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
3607 rxbd->rx_bd_haddr_lo = val;
3608
3609 val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
3610 cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
3611 }
3612
3613 static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
3614 {
3615 struct kwqe *wqes[1], l2kwqe;
3616
3617 memset(&l2kwqe, 0, sizeof(l2kwqe));
3618 wqes[0] = &l2kwqe;
3619 l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
3620 (L2_KWQE_OPCODE_VALUE_FLUSH <<
3621 KWQE_OPCODE_SHIFT) | 2;
3622 dev->submit_kwqes(dev, wqes, 1);
3623 }
3624
3625 static void cnic_set_bnx2_mac(struct cnic_dev *dev)
3626 {
3627 struct cnic_local *cp = dev->cnic_priv;
3628 u32 val;
3629
3630 val = cp->func << 2;
3631
3632 cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
3633
3634 val = cnic_reg_rd_ind(dev, cp->shmem_base +
3635 BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
3636 dev->mac_addr[0] = (u8) (val >> 8);
3637 dev->mac_addr[1] = (u8) val;
3638
3639 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
3640
3641 val = cnic_reg_rd_ind(dev, cp->shmem_base +
3642 BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
3643 dev->mac_addr[2] = (u8) (val >> 24);
3644 dev->mac_addr[3] = (u8) (val >> 16);
3645 dev->mac_addr[4] = (u8) (val >> 8);
3646 dev->mac_addr[5] = (u8) val;
3647
3648 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
3649
3650 val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
3651 if (CHIP_NUM(cp) != CHIP_NUM_5709)
3652 val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
3653
3654 CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
3655 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
3656 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
3657 }
3658
3659 static int cnic_start_bnx2_hw(struct cnic_dev *dev)
3660 {
3661 struct cnic_local *cp = dev->cnic_priv;
3662 struct cnic_eth_dev *ethdev = cp->ethdev;
3663 struct status_block *sblk = cp->status_blk.gen;
3664 u32 val;
3665 int err;
3666
3667 cnic_set_bnx2_mac(dev);
3668
3669 val = CNIC_RD(dev, BNX2_MQ_CONFIG);
3670 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3671 if (BCM_PAGE_BITS > 12)
3672 val |= (12 - 8) << 4;
3673 else
3674 val |= (BCM_PAGE_BITS - 8) << 4;
3675
3676 CNIC_WR(dev, BNX2_MQ_CONFIG, val);
3677
3678 CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
3679 CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
3680 CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
3681
3682 err = cnic_setup_5709_context(dev, 1);
3683 if (err)
3684 return err;
3685
3686 cnic_init_context(dev, KWQ_CID);
3687 cnic_init_context(dev, KCQ_CID);
3688
3689 cp->kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
3690 cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
3691
3692 cp->max_kwq_idx = MAX_KWQ_IDX;
3693 cp->kwq_prod_idx = 0;
3694 cp->kwq_con_idx = 0;
3695 cp->cnic_local_flags |= CNIC_LCL_FL_KWQ_INIT;
3696
3697 if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
3698 cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
3699 else
3700 cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
3701
3702 /* Initialize the kernel work queue context. */
3703 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
3704 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
3705 cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_TYPE, val);
3706
3707 val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
3708 cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
3709
3710 val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
3711 cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
3712
3713 val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
3714 cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
3715
3716 val = (u32) cp->kwq_info.pgtbl_map;
3717 cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
3718
3719 cp->kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
3720 cp->kcq_io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
3721
3722 cp->kcq_prod_idx = 0;
3723
3724 /* Initialize the kernel complete queue context. */
3725 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
3726 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
3727 cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_TYPE, val);
3728
3729 val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
3730 cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
3731
3732 val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
3733 cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
3734
3735 val = (u32) ((u64) cp->kcq_info.pgtbl_map >> 32);
3736 cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
3737
3738 val = (u32) cp->kcq_info.pgtbl_map;
3739 cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
3740
3741 cp->int_num = 0;
3742 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3743 u32 sb_id = cp->status_blk_num;
3744 u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
3745
3746 cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
3747 cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
3748 cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
3749 }
3750
3751 /* Enable Commnad Scheduler notification when we write to the
3752 * host producer index of the kernel contexts. */
3753 CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
3754
3755 /* Enable Command Scheduler notification when we write to either
3756 * the Send Queue or Receive Queue producer indexes of the kernel
3757 * bypass contexts. */
3758 CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
3759 CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
3760
3761 /* Notify COM when the driver post an application buffer. */
3762 CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
3763
3764 /* Set the CP and COM doorbells. These two processors polls the
3765 * doorbell for a non zero value before running. This must be done
3766 * after setting up the kernel queue contexts. */
3767 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
3768 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
3769
3770 cnic_init_bnx2_tx_ring(dev);
3771 cnic_init_bnx2_rx_ring(dev);
3772
3773 err = cnic_init_bnx2_irq(dev);
3774 if (err) {
3775 netdev_err(dev->netdev, "cnic_init_irq failed\n");
3776 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
3777 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
3778 return err;
3779 }
3780
3781 return 0;
3782 }
3783
3784 static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
3785 {
3786 struct cnic_local *cp = dev->cnic_priv;
3787 struct cnic_eth_dev *ethdev = cp->ethdev;
3788 u32 start_offset = ethdev->ctx_tbl_offset;
3789 int i;
3790
3791 for (i = 0; i < cp->ctx_blks; i++) {
3792 struct cnic_ctx *ctx = &cp->ctx_arr[i];
3793 dma_addr_t map = ctx->mapping;
3794
3795 if (cp->ctx_align) {
3796 unsigned long mask = cp->ctx_align - 1;
3797
3798 map = (map + mask) & ~mask;
3799 }
3800
3801 cnic_ctx_tbl_wr(dev, start_offset + i, map);
3802 }
3803 }
3804
3805 static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
3806 {
3807 struct cnic_local *cp = dev->cnic_priv;
3808 struct cnic_eth_dev *ethdev = cp->ethdev;
3809 int err = 0;
3810
3811 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
3812 (unsigned long) dev);
3813 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3814 err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
3815 "cnic", dev);
3816 if (err)
3817 tasklet_disable(&cp->cnic_irq_task);
3818 }
3819 return err;
3820 }
3821
3822 static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
3823 {
3824 struct cnic_local *cp = dev->cnic_priv;
3825 u8 sb_id = cp->status_blk_num;
3826 int port = CNIC_PORT(cp);
3827
3828 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
3829 CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
3830 HC_INDEX_C_ISCSI_EQ_CONS),
3831 64 / 12);
3832 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
3833 CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
3834 HC_INDEX_C_ISCSI_EQ_CONS), 0);
3835 }
3836
3837 static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
3838 {
3839 }
3840
3841 static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev)
3842 {
3843 struct cnic_local *cp = dev->cnic_priv;
3844 union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) cp->l2_ring;
3845 struct eth_context *context;
3846 struct regpair context_addr;
3847 dma_addr_t buf_map;
3848 int func = CNIC_FUNC(cp);
3849 int port = CNIC_PORT(cp);
3850 int i;
3851 int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
3852 u32 val;
3853
3854 memset(txbd, 0, BCM_PAGE_SIZE);
3855
3856 buf_map = cp->l2_buf_map;
3857 for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
3858 struct eth_tx_start_bd *start_bd = &txbd->start_bd;
3859 struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
3860
3861 start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
3862 start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
3863 reg_bd->addr_hi = start_bd->addr_hi;
3864 reg_bd->addr_lo = start_bd->addr_lo + 0x10;
3865 start_bd->nbytes = cpu_to_le16(0x10);
3866 start_bd->nbd = cpu_to_le16(3);
3867 start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
3868 start_bd->general_data = (UNICAST_ADDRESS <<
3869 ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
3870 start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
3871
3872 }
3873 context = cnic_get_bnx2x_ctx(dev, BNX2X_ISCSI_L2_CID, 1, &context_addr);
3874
3875 val = (u64) cp->l2_ring_map >> 32;
3876 txbd->next_bd.addr_hi = cpu_to_le32(val);
3877
3878 context->xstorm_st_context.tx_bd_page_base_hi = val;
3879
3880 val = (u64) cp->l2_ring_map & 0xffffffff;
3881 txbd->next_bd.addr_lo = cpu_to_le32(val);
3882
3883 context->xstorm_st_context.tx_bd_page_base_lo = val;
3884
3885 context->cstorm_st_context.sb_index_number =
3886 HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS;
3887 context->cstorm_st_context.status_block_id = BNX2X_DEF_SB_ID;
3888
3889 context->xstorm_st_context.statistics_data = (cli |
3890 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
3891
3892 context->xstorm_ag_context.cdu_reserved =
3893 CDU_RSRVD_VALUE_TYPE_A(BNX2X_HW_CID(BNX2X_ISCSI_L2_CID, func),
3894 CDU_REGION_NUMBER_XCM_AG,
3895 ETH_CONNECTION_TYPE);
3896
3897 /* reset xstorm per client statistics */
3898 val = BAR_XSTRORM_INTMEM +
3899 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
3900 for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
3901 CNIC_WR(dev, val + i * 4, 0);
3902
3903 cp->tx_cons_ptr =
3904 &cp->bnx2x_def_status_blk->c_def_status_block.index_values[
3905 HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS];
3906 }
3907
3908 static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev)
3909 {
3910 struct cnic_local *cp = dev->cnic_priv;
3911 struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (cp->l2_ring +
3912 BCM_PAGE_SIZE);
3913 struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
3914 (cp->l2_ring + (2 * BCM_PAGE_SIZE));
3915 struct eth_context *context;
3916 struct regpair context_addr;
3917 int i;
3918 int port = CNIC_PORT(cp);
3919 int func = CNIC_FUNC(cp);
3920 int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
3921 u32 val;
3922 struct tstorm_eth_client_config tstorm_client = {0};
3923
3924 for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
3925 dma_addr_t buf_map;
3926 int n = (i % cp->l2_rx_ring_size) + 1;
3927
3928 buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
3929 rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
3930 rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
3931 }
3932 context = cnic_get_bnx2x_ctx(dev, BNX2X_ISCSI_L2_CID, 0, &context_addr);
3933
3934 val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
3935 rxbd->addr_hi = cpu_to_le32(val);
3936
3937 context->ustorm_st_context.common.bd_page_base_hi = val;
3938
3939 val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
3940 rxbd->addr_lo = cpu_to_le32(val);
3941
3942 context->ustorm_st_context.common.bd_page_base_lo = val;
3943
3944 context->ustorm_st_context.common.sb_index_numbers =
3945 BNX2X_ISCSI_RX_SB_INDEX_NUM;
3946 context->ustorm_st_context.common.clientId = cli;
3947 context->ustorm_st_context.common.status_block_id = BNX2X_DEF_SB_ID;
3948 context->ustorm_st_context.common.flags =
3949 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS;
3950 context->ustorm_st_context.common.statistics_counter_id = cli;
3951 context->ustorm_st_context.common.mc_alignment_log_size = 0;
3952 context->ustorm_st_context.common.bd_buff_size =
3953 cp->l2_single_buf_size;
3954
3955 context->ustorm_ag_context.cdu_usage =
3956 CDU_RSRVD_VALUE_TYPE_A(BNX2X_HW_CID(BNX2X_ISCSI_L2_CID, func),
3957 CDU_REGION_NUMBER_UCM_AG,
3958 ETH_CONNECTION_TYPE);
3959
3960 rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
3961 val = (u64) (cp->l2_ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
3962 rxcqe->addr_hi = cpu_to_le32(val);
3963
3964 CNIC_WR(dev, BAR_USTRORM_INTMEM +
3965 USTORM_CQE_PAGE_BASE_OFFSET(port, cli) + 4, val);
3966
3967 CNIC_WR(dev, BAR_USTRORM_INTMEM +
3968 USTORM_CQE_PAGE_NEXT_OFFSET(port, cli) + 4, val);
3969
3970 val = (u64) (cp->l2_ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
3971 rxcqe->addr_lo = cpu_to_le32(val);
3972
3973 CNIC_WR(dev, BAR_USTRORM_INTMEM +
3974 USTORM_CQE_PAGE_BASE_OFFSET(port, cli), val);
3975
3976 CNIC_WR(dev, BAR_USTRORM_INTMEM +
3977 USTORM_CQE_PAGE_NEXT_OFFSET(port, cli), val);
3978
3979 /* client tstorm info */
3980 tstorm_client.mtu = cp->l2_single_buf_size - 14;
3981 tstorm_client.config_flags =
3982 (TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE |
3983 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE);
3984 tstorm_client.statistics_counter_id = cli;
3985
3986 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
3987 TSTORM_CLIENT_CONFIG_OFFSET(port, cli),
3988 ((u32 *)&tstorm_client)[0]);
3989 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
3990 TSTORM_CLIENT_CONFIG_OFFSET(port, cli) + 4,
3991 ((u32 *)&tstorm_client)[1]);
3992
3993 /* reset tstorm per client statistics */
3994 val = BAR_TSTRORM_INTMEM +
3995 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
3996 for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
3997 CNIC_WR(dev, val + i * 4, 0);
3998
3999 /* reset ustorm per client statistics */
4000 val = BAR_USTRORM_INTMEM +
4001 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4002 for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
4003 CNIC_WR(dev, val + i * 4, 0);
4004
4005 cp->rx_cons_ptr =
4006 &cp->bnx2x_def_status_blk->u_def_status_block.index_values[
4007 HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS];
4008 }
4009
4010 static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
4011 {
4012 struct cnic_local *cp = dev->cnic_priv;
4013 u32 base, addr, val;
4014 int port = CNIC_PORT(cp);
4015
4016 dev->max_iscsi_conn = 0;
4017 base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
4018 if (base < 0xa0000 || base >= 0xc0000)
4019 return;
4020
4021 addr = BNX2X_SHMEM_ADDR(base,
4022 dev_info.port_hw_config[port].iscsi_mac_upper);
4023
4024 val = CNIC_RD(dev, addr);
4025
4026 dev->mac_addr[0] = (u8) (val >> 8);
4027 dev->mac_addr[1] = (u8) val;
4028
4029 addr = BNX2X_SHMEM_ADDR(base,
4030 dev_info.port_hw_config[port].iscsi_mac_lower);
4031
4032 val = CNIC_RD(dev, addr);
4033
4034 dev->mac_addr[2] = (u8) (val >> 24);
4035 dev->mac_addr[3] = (u8) (val >> 16);
4036 dev->mac_addr[4] = (u8) (val >> 8);
4037 dev->mac_addr[5] = (u8) val;
4038
4039 addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
4040 val = CNIC_RD(dev, addr);
4041
4042 if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
4043 u16 val16;
4044
4045 addr = BNX2X_SHMEM_ADDR(base,
4046 drv_lic_key[port].max_iscsi_init_conn);
4047 val16 = CNIC_RD16(dev, addr);
4048
4049 if (val16)
4050 val16 ^= 0x1e1e;
4051 dev->max_iscsi_conn = val16;
4052 }
4053 if (BNX2X_CHIP_IS_E1H(cp->chip_id)) {
4054 int func = CNIC_FUNC(cp);
4055
4056 addr = BNX2X_SHMEM_ADDR(base,
4057 mf_cfg.func_mf_config[func].e1hov_tag);
4058 val = CNIC_RD(dev, addr);
4059 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
4060 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
4061 addr = BNX2X_SHMEM_ADDR(base,
4062 mf_cfg.func_mf_config[func].config);
4063 val = CNIC_RD(dev, addr);
4064 val &= FUNC_MF_CFG_PROTOCOL_MASK;
4065 if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
4066 dev->max_iscsi_conn = 0;
4067 }
4068 }
4069 }
4070
4071 static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
4072 {
4073 struct cnic_local *cp = dev->cnic_priv;
4074 int func = CNIC_FUNC(cp), ret, i;
4075 int port = CNIC_PORT(cp);
4076 u16 eq_idx;
4077 u8 sb_id = cp->status_blk_num;
4078
4079 ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
4080 BNX2X_ISCSI_START_CID);
4081
4082 if (ret)
4083 return -ENOMEM;
4084
4085 cp->kcq_io_addr = BAR_CSTRORM_INTMEM +
4086 CSTORM_ISCSI_EQ_PROD_OFFSET(func, 0);
4087 cp->kcq_prod_idx = 0;
4088
4089 cnic_get_bnx2x_iscsi_info(dev);
4090
4091 /* Only 1 EQ */
4092 CNIC_WR16(dev, cp->kcq_io_addr, MAX_KCQ_IDX);
4093 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4094 CSTORM_ISCSI_EQ_CONS_OFFSET(func, 0), 0);
4095 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4096 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0),
4097 cp->kcq_info.pg_map_arr[1] & 0xffffffff);
4098 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4099 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0) + 4,
4100 (u64) cp->kcq_info.pg_map_arr[1] >> 32);
4101 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4102 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0),
4103 cp->kcq_info.pg_map_arr[0] & 0xffffffff);
4104 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4105 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0) + 4,
4106 (u64) cp->kcq_info.pg_map_arr[0] >> 32);
4107 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4108 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(func, 0), 1);
4109 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
4110 CSTORM_ISCSI_EQ_SB_NUM_OFFSET(func, 0), cp->status_blk_num);
4111 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4112 CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(func, 0),
4113 HC_INDEX_C_ISCSI_EQ_CONS);
4114
4115 for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
4116 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4117 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i),
4118 cp->conn_buf_info.pgtbl[2 * i]);
4119 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4120 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i) + 4,
4121 cp->conn_buf_info.pgtbl[(2 * i) + 1]);
4122 }
4123
4124 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4125 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func),
4126 cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
4127 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4128 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func) + 4,
4129 (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
4130
4131 cnic_setup_bnx2x_context(dev);
4132
4133 eq_idx = CNIC_RD16(dev, BAR_CSTRORM_INTMEM +
4134 CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) +
4135 offsetof(struct cstorm_status_block_c,
4136 index_values[HC_INDEX_C_ISCSI_EQ_CONS]));
4137 if (eq_idx != 0) {
4138 netdev_err(dev->netdev, "EQ cons index %x != 0\n", eq_idx);
4139 return -EBUSY;
4140 }
4141 ret = cnic_init_bnx2x_irq(dev);
4142 if (ret)
4143 return ret;
4144
4145 cnic_init_bnx2x_tx_ring(dev);
4146 cnic_init_bnx2x_rx_ring(dev);
4147
4148 return 0;
4149 }
4150
4151 static void cnic_init_rings(struct cnic_dev *dev)
4152 {
4153 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4154 cnic_init_bnx2_tx_ring(dev);
4155 cnic_init_bnx2_rx_ring(dev);
4156 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4157 struct cnic_local *cp = dev->cnic_priv;
4158 u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
4159 union l5cm_specific_data l5_data;
4160 struct ustorm_eth_rx_producers rx_prods = {0};
4161 u32 off, i;
4162
4163 rx_prods.bd_prod = 0;
4164 rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
4165 barrier();
4166
4167 off = BAR_USTRORM_INTMEM +
4168 USTORM_RX_PRODS_OFFSET(CNIC_PORT(cp), cli);
4169
4170 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
4171 CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
4172
4173 cnic_init_bnx2x_tx_ring(dev);
4174 cnic_init_bnx2x_rx_ring(dev);
4175
4176 l5_data.phy_address.lo = cli;
4177 l5_data.phy_address.hi = 0;
4178 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4179 BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
4180 cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
4181 }
4182 }
4183
4184 static void cnic_shutdown_rings(struct cnic_dev *dev)
4185 {
4186 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4187 cnic_shutdown_bnx2_rx_ring(dev);
4188 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4189 struct cnic_local *cp = dev->cnic_priv;
4190 u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
4191 union l5cm_specific_data l5_data;
4192
4193 cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
4194
4195 l5_data.phy_address.lo = cli;
4196 l5_data.phy_address.hi = 0;
4197 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
4198 BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
4199 msleep(10);
4200
4201 memset(&l5_data, 0, sizeof(l5_data));
4202 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CFC_DEL,
4203 BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE |
4204 (1 << SPE_HDR_COMMON_RAMROD_SHIFT), &l5_data);
4205 msleep(10);
4206 }
4207 }
4208
4209 static int cnic_register_netdev(struct cnic_dev *dev)
4210 {
4211 struct cnic_local *cp = dev->cnic_priv;
4212 struct cnic_eth_dev *ethdev = cp->ethdev;
4213 int err;
4214
4215 if (!ethdev)
4216 return -ENODEV;
4217
4218 if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
4219 return 0;
4220
4221 err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
4222 if (err)
4223 netdev_err(dev->netdev, "register_cnic failed\n");
4224
4225 return err;
4226 }
4227
4228 static void cnic_unregister_netdev(struct cnic_dev *dev)
4229 {
4230 struct cnic_local *cp = dev->cnic_priv;
4231 struct cnic_eth_dev *ethdev = cp->ethdev;
4232
4233 if (!ethdev)
4234 return;
4235
4236 ethdev->drv_unregister_cnic(dev->netdev);
4237 }
4238
4239 static int cnic_start_hw(struct cnic_dev *dev)
4240 {
4241 struct cnic_local *cp = dev->cnic_priv;
4242 struct cnic_eth_dev *ethdev = cp->ethdev;
4243 int err;
4244
4245 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
4246 return -EALREADY;
4247
4248 dev->regview = ethdev->io_base;
4249 cp->chip_id = ethdev->chip_id;
4250 pci_dev_get(dev->pcidev);
4251 cp->func = PCI_FUNC(dev->pcidev->devfn);
4252 cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
4253 cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
4254
4255 err = cp->alloc_resc(dev);
4256 if (err) {
4257 netdev_err(dev->netdev, "allocate resource failure\n");
4258 goto err1;
4259 }
4260
4261 err = cp->start_hw(dev);
4262 if (err)
4263 goto err1;
4264
4265 err = cnic_cm_open(dev);
4266 if (err)
4267 goto err1;
4268
4269 set_bit(CNIC_F_CNIC_UP, &dev->flags);
4270
4271 cp->enable_int(dev);
4272
4273 return 0;
4274
4275 err1:
4276 cp->free_resc(dev);
4277 pci_dev_put(dev->pcidev);
4278 return err;
4279 }
4280
4281 static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
4282 {
4283 cnic_disable_bnx2_int_sync(dev);
4284
4285 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
4286 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
4287
4288 cnic_init_context(dev, KWQ_CID);
4289 cnic_init_context(dev, KCQ_CID);
4290
4291 cnic_setup_5709_context(dev, 0);
4292 cnic_free_irq(dev);
4293
4294 cnic_free_resc(dev);
4295 }
4296
4297
4298 static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
4299 {
4300 struct cnic_local *cp = dev->cnic_priv;
4301 u8 sb_id = cp->status_blk_num;
4302 int port = CNIC_PORT(cp);
4303
4304 cnic_free_irq(dev);
4305 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
4306 CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) +
4307 offsetof(struct cstorm_status_block_c,
4308 index_values[HC_INDEX_C_ISCSI_EQ_CONS]),
4309 0);
4310 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4311 CSTORM_ISCSI_EQ_CONS_OFFSET(cp->func, 0), 0);
4312 CNIC_WR16(dev, cp->kcq_io_addr, 0);
4313 cnic_free_resc(dev);
4314 }
4315
4316 static void cnic_stop_hw(struct cnic_dev *dev)
4317 {
4318 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
4319 struct cnic_local *cp = dev->cnic_priv;
4320
4321 clear_bit(CNIC_F_CNIC_UP, &dev->flags);
4322 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
4323 synchronize_rcu();
4324 cnic_cm_shutdown(dev);
4325 cp->stop_hw(dev);
4326 pci_dev_put(dev->pcidev);
4327 }
4328 }
4329
4330 static void cnic_free_dev(struct cnic_dev *dev)
4331 {
4332 int i = 0;
4333
4334 while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
4335 msleep(100);
4336 i++;
4337 }
4338 if (atomic_read(&dev->ref_count) != 0)
4339 netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
4340
4341 netdev_info(dev->netdev, "Removed CNIC device\n");
4342 dev_put(dev->netdev);
4343 kfree(dev);
4344 }
4345
4346 static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
4347 struct pci_dev *pdev)
4348 {
4349 struct cnic_dev *cdev;
4350 struct cnic_local *cp;
4351 int alloc_size;
4352
4353 alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
4354
4355 cdev = kzalloc(alloc_size , GFP_KERNEL);
4356 if (cdev == NULL) {
4357 netdev_err(dev, "allocate dev struct failure\n");
4358 return NULL;
4359 }
4360
4361 cdev->netdev = dev;
4362 cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
4363 cdev->register_device = cnic_register_device;
4364 cdev->unregister_device = cnic_unregister_device;
4365 cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
4366
4367 cp = cdev->cnic_priv;
4368 cp->dev = cdev;
4369 cp->uio_dev = -1;
4370 cp->l2_single_buf_size = 0x400;
4371 cp->l2_rx_ring_size = 3;
4372
4373 spin_lock_init(&cp->cnic_ulp_lock);
4374
4375 netdev_info(dev, "Added CNIC device\n");
4376
4377 return cdev;
4378 }
4379
4380 static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
4381 {
4382 struct pci_dev *pdev;
4383 struct cnic_dev *cdev;
4384 struct cnic_local *cp;
4385 struct cnic_eth_dev *ethdev = NULL;
4386 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
4387
4388 probe = symbol_get(bnx2_cnic_probe);
4389 if (probe) {
4390 ethdev = (*probe)(dev);
4391 symbol_put(bnx2_cnic_probe);
4392 }
4393 if (!ethdev)
4394 return NULL;
4395
4396 pdev = ethdev->pdev;
4397 if (!pdev)
4398 return NULL;
4399
4400 dev_hold(dev);
4401 pci_dev_get(pdev);
4402 if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
4403 pdev->device == PCI_DEVICE_ID_NX2_5709S) {
4404 u8 rev;
4405
4406 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
4407 if (rev < 0x10) {
4408 pci_dev_put(pdev);
4409 goto cnic_err;
4410 }
4411 }
4412 pci_dev_put(pdev);
4413
4414 cdev = cnic_alloc_dev(dev, pdev);
4415 if (cdev == NULL)
4416 goto cnic_err;
4417
4418 set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
4419 cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
4420
4421 cp = cdev->cnic_priv;
4422 cp->ethdev = ethdev;
4423 cdev->pcidev = pdev;
4424
4425 cp->cnic_ops = &cnic_bnx2_ops;
4426 cp->start_hw = cnic_start_bnx2_hw;
4427 cp->stop_hw = cnic_stop_bnx2_hw;
4428 cp->setup_pgtbl = cnic_setup_page_tbl;
4429 cp->alloc_resc = cnic_alloc_bnx2_resc;
4430 cp->free_resc = cnic_free_resc;
4431 cp->start_cm = cnic_cm_init_bnx2_hw;
4432 cp->stop_cm = cnic_cm_stop_bnx2_hw;
4433 cp->enable_int = cnic_enable_bnx2_int;
4434 cp->disable_int_sync = cnic_disable_bnx2_int_sync;
4435 cp->close_conn = cnic_close_bnx2_conn;
4436 cp->next_idx = cnic_bnx2_next_idx;
4437 cp->hw_idx = cnic_bnx2_hw_idx;
4438 return cdev;
4439
4440 cnic_err:
4441 dev_put(dev);
4442 return NULL;
4443 }
4444
4445 static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
4446 {
4447 struct pci_dev *pdev;
4448 struct cnic_dev *cdev;
4449 struct cnic_local *cp;
4450 struct cnic_eth_dev *ethdev = NULL;
4451 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
4452
4453 probe = symbol_get(bnx2x_cnic_probe);
4454 if (probe) {
4455 ethdev = (*probe)(dev);
4456 symbol_put(bnx2x_cnic_probe);
4457 }
4458 if (!ethdev)
4459 return NULL;
4460
4461 pdev = ethdev->pdev;
4462 if (!pdev)
4463 return NULL;
4464
4465 dev_hold(dev);
4466 cdev = cnic_alloc_dev(dev, pdev);
4467 if (cdev == NULL) {
4468 dev_put(dev);
4469 return NULL;
4470 }
4471
4472 set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
4473 cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
4474
4475 cp = cdev->cnic_priv;
4476 cp->ethdev = ethdev;
4477 cdev->pcidev = pdev;
4478
4479 cp->cnic_ops = &cnic_bnx2x_ops;
4480 cp->start_hw = cnic_start_bnx2x_hw;
4481 cp->stop_hw = cnic_stop_bnx2x_hw;
4482 cp->setup_pgtbl = cnic_setup_page_tbl_le;
4483 cp->alloc_resc = cnic_alloc_bnx2x_resc;
4484 cp->free_resc = cnic_free_resc;
4485 cp->start_cm = cnic_cm_init_bnx2x_hw;
4486 cp->stop_cm = cnic_cm_stop_bnx2x_hw;
4487 cp->enable_int = cnic_enable_bnx2x_int;
4488 cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
4489 cp->ack_int = cnic_ack_bnx2x_msix;
4490 cp->close_conn = cnic_close_bnx2x_conn;
4491 cp->next_idx = cnic_bnx2x_next_idx;
4492 cp->hw_idx = cnic_bnx2x_hw_idx;
4493 return cdev;
4494 }
4495
4496 static struct cnic_dev *is_cnic_dev(struct net_device *dev)
4497 {
4498 struct ethtool_drvinfo drvinfo;
4499 struct cnic_dev *cdev = NULL;
4500
4501 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
4502 memset(&drvinfo, 0, sizeof(drvinfo));
4503 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
4504
4505 if (!strcmp(drvinfo.driver, "bnx2"))
4506 cdev = init_bnx2_cnic(dev);
4507 if (!strcmp(drvinfo.driver, "bnx2x"))
4508 cdev = init_bnx2x_cnic(dev);
4509 if (cdev) {
4510 write_lock(&cnic_dev_lock);
4511 list_add(&cdev->list, &cnic_dev_list);
4512 write_unlock(&cnic_dev_lock);
4513 }
4514 }
4515 return cdev;
4516 }
4517
4518 /**
4519 * netdev event handler
4520 */
4521 static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
4522 void *ptr)
4523 {
4524 struct net_device *netdev = ptr;
4525 struct cnic_dev *dev;
4526 int if_type;
4527 int new_dev = 0;
4528
4529 dev = cnic_from_netdev(netdev);
4530
4531 if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
4532 /* Check for the hot-plug device */
4533 dev = is_cnic_dev(netdev);
4534 if (dev) {
4535 new_dev = 1;
4536 cnic_hold(dev);
4537 }
4538 }
4539 if (dev) {
4540 struct cnic_local *cp = dev->cnic_priv;
4541
4542 if (new_dev)
4543 cnic_ulp_init(dev);
4544 else if (event == NETDEV_UNREGISTER)
4545 cnic_ulp_exit(dev);
4546
4547 if (event == NETDEV_UP) {
4548 if (cnic_register_netdev(dev) != 0) {
4549 cnic_put(dev);
4550 goto done;
4551 }
4552 if (!cnic_start_hw(dev))
4553 cnic_ulp_start(dev);
4554 }
4555
4556 rcu_read_lock();
4557 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
4558 struct cnic_ulp_ops *ulp_ops;
4559 void *ctx;
4560
4561 ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
4562 if (!ulp_ops || !ulp_ops->indicate_netevent)
4563 continue;
4564
4565 ctx = cp->ulp_handle[if_type];
4566
4567 ulp_ops->indicate_netevent(ctx, event);
4568 }
4569 rcu_read_unlock();
4570
4571 if (event == NETDEV_GOING_DOWN) {
4572 cnic_ulp_stop(dev);
4573 cnic_stop_hw(dev);
4574 cnic_unregister_netdev(dev);
4575 } else if (event == NETDEV_UNREGISTER) {
4576 write_lock(&cnic_dev_lock);
4577 list_del_init(&dev->list);
4578 write_unlock(&cnic_dev_lock);
4579
4580 cnic_put(dev);
4581 cnic_free_dev(dev);
4582 goto done;
4583 }
4584 cnic_put(dev);
4585 }
4586 done:
4587 return NOTIFY_DONE;
4588 }
4589
4590 static struct notifier_block cnic_netdev_notifier = {
4591 .notifier_call = cnic_netdev_event
4592 };
4593
4594 static void cnic_release(void)
4595 {
4596 struct cnic_dev *dev;
4597
4598 while (!list_empty(&cnic_dev_list)) {
4599 dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
4600 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
4601 cnic_ulp_stop(dev);
4602 cnic_stop_hw(dev);
4603 }
4604
4605 cnic_ulp_exit(dev);
4606 cnic_unregister_netdev(dev);
4607 list_del_init(&dev->list);
4608 cnic_free_dev(dev);
4609 }
4610 }
4611
4612 static int __init cnic_init(void)
4613 {
4614 int rc = 0;
4615
4616 pr_info("%s", version);
4617
4618 rc = register_netdevice_notifier(&cnic_netdev_notifier);
4619 if (rc) {
4620 cnic_release();
4621 return rc;
4622 }
4623
4624 return 0;
4625 }
4626
4627 static void __exit cnic_exit(void)
4628 {
4629 unregister_netdevice_notifier(&cnic_netdev_notifier);
4630 cnic_release();
4631 return;
4632 }
4633
4634 module_init(cnic_init);
4635 module_exit(cnic_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree