drivers/staging/olpc_dcon/olpc_dcon_xo_1_5.c

   1 /*
   2  * Copyright (c) 2009,2010       One Laptop per Child
   3  *
   4  * This program is free software.  You can redistribute it and/or
   5  * modify it under the terms of version 2 of the GNU General Public
   6  * License as published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/delay.h>
  11 #include <linux/pci.h>
  12 #include <linux/gpio.h>
  13 #include <asm/olpc.h>
  14
  15 /* TODO: this eventually belongs in linux/vx855.h */
  16 #define NR_VX855_GPI    14
  17 #define NR_VX855_GPO    13
  18 #define NR_VX855_GPIO   15
  19
  20 #define VX855_GPI(n)    (n)
  21 #define VX855_GPO(n)    (NR_VX855_GPI + (n))
  22 #define VX855_GPIO(n)   (NR_VX855_GPI + NR_VX855_GPO + (n))
  23
  24 #include "olpc_dcon.h"
  25
  26 /* Hardware setup on the XO 1.5:
  27  *      DCONLOAD connects to VX855_GPIO1 (not SMBCK2)
  28  *      DCONBLANK connects to VX855_GPIO8 (not SSPICLK)  unused in driver
  29  *      DCONSTAT0 connects to VX855_GPI10 (not SSPISDI)
  30  *      DCONSTAT1 connects to VX855_GPI11 (not nSSPISS)
  31  *      DCONIRQ connects to VX855_GPIO12
  32  *      DCONSMBDATA connects to VX855 graphics CRTSPD
  33  *      DCONSMBCLK connects to VX855 graphics CRTSPCLK
  34  */
  35
  36 #define VX855_GENL_PURPOSE_OUTPUT 0x44c /* PMIO_Rx4c-4f */
  37 #define VX855_GPI_STATUS_CHG 0x450  /* PMIO_Rx50 */
  38 #define VX855_GPI_SCI_SMI 0x452  /* PMIO_Rx52 */
  39 #define BIT_GPIO12 0x40
  40
  41 #define PREFIX "OLPC DCON:"
  42
  43 static void dcon_clear_irq(void)
  44 {
  45         /* irq status will appear in PMIO_Rx50[6] (RW1C) on gpio12 */
  46         outb(BIT_GPIO12, VX855_GPI_STATUS_CHG);
  47 }
  48
  49 static int dcon_was_irq(void)
  50 {
  51         u_int8_t tmp;
  52
  53         /* irq status will appear in PMIO_Rx50[6] on gpio12 */
  54         tmp = inb(VX855_GPI_STATUS_CHG);
  55         return !!(tmp & BIT_GPIO12);
  56
  57         return 0;
  58 }
  59
  60 static int dcon_init_xo_1_5(struct dcon_priv *dcon)
  61 {
  62         unsigned int irq;
  63         u_int8_t tmp;
  64         struct pci_dev *pdev;
  65
  66         pdev = pci_get_device(PCI_VENDOR_ID_VIA,
  67                               PCI_DEVICE_ID_VIA_VX855, NULL);
  68         if (!pdev) {
  69                 printk(KERN_ERR "cannot find VX855 PCI ID\n");
  70                 return 1;
  71         }
  72
  73         pci_read_config_byte(pdev, 0x95, &tmp);
  74         pci_write_config_byte(pdev, 0x95, tmp|0x0c);
  75
  76         /* Set GPIO8 to GPIO mode, not SSPICLK */
  77         pci_read_config_byte(pdev, 0xe3, &tmp);
  78         pci_write_config_byte(pdev, 0xe3, tmp | 0x04);
  79
  80         /* Set GPI10/GPI11 to GPI mode, not SSPISDI/SSPISS */
  81         pci_read_config_byte(pdev, 0xe4, &tmp);
  82         pci_write_config_byte(pdev, 0xe4, tmp|0x08);
  83
  84         /* clear PMU_RxE1[6] to select SCI on GPIO12 */
  85         /* clear PMU_RxE0[6] to choose falling edge */
  86         pci_read_config_byte(pdev, 0xe1, &tmp);
  87         pci_write_config_byte(pdev, 0xe1, tmp & ~BIT_GPIO12);
  88         pci_read_config_byte(pdev, 0xe0, &tmp);
  89         pci_write_config_byte(pdev, 0xe0, tmp & ~BIT_GPIO12);
  90
  91         dcon_clear_irq();
  92
  93         /* set   PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
  94         outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
  95
  96         /* Determine the current state of DCONLOAD, likely set by firmware */
  97         /* GPIO1 */
  98         dcon->curr_src = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x1000) ?
  99                         DCON_SOURCE_CPU : DCON_SOURCE_DCON;
 100         dcon->pending_src = dcon->curr_src;
 101
 102         pci_dev_put(pdev);
 103
 104         /* we're sharing the IRQ with ACPI */
 105         irq = acpi_gbl_FADT.sci_interrupt;
 106         if (request_irq(irq, &dcon_interrupt, IRQF_SHARED, "DCON", dcon)) {
 107                 printk(KERN_ERR PREFIX "DCON (IRQ%d) allocation failed\n", irq);
 108                 return 1;
 109         }
 110
 111         return 0;
 112 }
 113
 114 static void set_i2c_line(int sda, int scl)
 115 {
 116         unsigned char tmp;
 117         unsigned int port = 0x26;
 118
 119         /* FIXME: This directly accesses the CRT GPIO controller !!! */
 120         outb(port, 0x3c4);
 121         tmp = inb(0x3c5);
 122
 123         if (scl)
 124                 tmp |= 0x20;
 125         else
 126                 tmp &= ~0x20;
 127
 128         if (sda)
 129                 tmp |= 0x10;
 130         else
 131                 tmp &= ~0x10;
 132
 133         tmp |= 0x01;
 134
 135         outb(port, 0x3c4);
 136         outb(tmp, 0x3c5);
 137 }
 138
 139
 140 static void dcon_wiggle_xo_1_5(void)
 141 {
 142         int x;
 143
 144         /*
 145          * According to HiMax, when powering the DCON up we should hold
 146          * SMB_DATA high for 8 SMB_CLK cycles.  This will force the DCON
 147          * state machine to reset to a (sane) initial state.  Mitch Bradley
 148          * did some testing and discovered that holding for 16 SMB_CLK cycles
 149          * worked a lot more reliably, so that's what we do here.
 150          */
 151         set_i2c_line(1, 1);
 152
 153         for (x = 0; x < 16; x++) {
 154                 udelay(5);
 155                 set_i2c_line(1, 0);
 156                 udelay(5);
 157                 set_i2c_line(1, 1);
 158         }
 159         udelay(5);
 160
 161         /* set   PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
 162         outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
 163 }
 164
 165 static void dcon_set_dconload_xo_1_5(int val)
 166 {
 167         gpio_set_value(VX855_GPIO(1), val);
 168 }
 169
 170 static u8 dcon_read_status_xo_1_5(void)
 171 {
 172         u8 status;
 173
 174         if (!dcon_was_irq())
 175                 return -1;
 176
 177         /* i believe this is the same as "inb(0x44b) & 3" */
 178         status = gpio_get_value(VX855_GPI(10));
 179         status |= gpio_get_value(VX855_GPI(11)) << 1;
 180
 181         dcon_clear_irq();
 182
 183         return status;
 184 }
 185
 186 struct dcon_platform_data dcon_pdata_xo_1_5 = {
 187         .init = dcon_init_xo_1_5,
 188         .bus_stabilize_wiggle = dcon_wiggle_xo_1_5,
 189         .set_dconload = dcon_set_dconload_xo_1_5,
 190         .read_status = dcon_read_status_xo_1_5,
 191 };