2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/gfp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/pci.h>
32 #include <linux/spinlock.h>
35 #include <asm/system.h>
37 #ifdef CONFIG_PPC_PMAC
38 #include <asm/pmac_feature.h>
42 #include "fw-transaction.h"
44 #define DESCRIPTOR_OUTPUT_MORE 0
45 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
46 #define DESCRIPTOR_INPUT_MORE (2 << 12)
47 #define DESCRIPTOR_INPUT_LAST (3 << 12)
48 #define DESCRIPTOR_STATUS (1 << 11)
49 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
50 #define DESCRIPTOR_PING (1 << 7)
51 #define DESCRIPTOR_YY (1 << 6)
52 #define DESCRIPTOR_NO_IRQ (0 << 4)
53 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
54 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
55 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
56 #define DESCRIPTOR_WAIT (3 << 0)
62 __le32 branch_address
;
64 __le16 transfer_status
;
65 } __attribute__((aligned(16)));
67 struct db_descriptor
{
70 __le16 second_req_count
;
71 __le16 first_req_count
;
72 __le32 branch_address
;
73 __le16 second_res_count
;
74 __le16 first_res_count
;
79 } __attribute__((aligned(16)));
81 #define CONTROL_SET(regs) (regs)
82 #define CONTROL_CLEAR(regs) ((regs) + 4)
83 #define COMMAND_PTR(regs) ((regs) + 12)
84 #define CONTEXT_MATCH(regs) ((regs) + 16)
87 struct descriptor descriptor
;
88 struct ar_buffer
*next
;
94 struct ar_buffer
*current_buffer
;
95 struct ar_buffer
*last_buffer
;
98 struct tasklet_struct tasklet
;
103 typedef int (*descriptor_callback_t
)(struct context
*ctx
,
104 struct descriptor
*d
,
105 struct descriptor
*last
);
108 * A buffer that contains a block of DMA-able coherent memory used for
109 * storing a portion of a DMA descriptor program.
111 struct descriptor_buffer
{
112 struct list_head list
;
113 dma_addr_t buffer_bus
;
116 struct descriptor buffer
[0];
120 struct fw_ohci
*ohci
;
122 int total_allocation
;
125 * List of page-sized buffers for storing DMA descriptors.
126 * Head of list contains buffers in use and tail of list contains
129 struct list_head buffer_list
;
132 * Pointer to a buffer inside buffer_list that contains the tail
133 * end of the current DMA program.
135 struct descriptor_buffer
*buffer_tail
;
138 * The descriptor containing the branch address of the first
139 * descriptor that has not yet been filled by the device.
141 struct descriptor
*last
;
144 * The last descriptor in the DMA program. It contains the branch
145 * address that must be updated upon appending a new descriptor.
147 struct descriptor
*prev
;
149 descriptor_callback_t callback
;
151 struct tasklet_struct tasklet
;
154 #define IT_HEADER_SY(v) ((v) << 0)
155 #define IT_HEADER_TCODE(v) ((v) << 4)
156 #define IT_HEADER_CHANNEL(v) ((v) << 8)
157 #define IT_HEADER_TAG(v) ((v) << 14)
158 #define IT_HEADER_SPEED(v) ((v) << 16)
159 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
162 struct fw_iso_context base
;
163 struct context context
;
166 size_t header_length
;
169 #define CONFIG_ROM_SIZE 1024
174 __iomem
char *registers
;
175 dma_addr_t self_id_bus
;
177 struct tasklet_struct bus_reset_tasklet
;
180 int request_generation
; /* for timestamping incoming requests */
185 bool bus_reset_packet_quirk
;
188 * Spinlock for accessing fw_ohci data. Never call out of
189 * this driver with this lock held.
192 u32 self_id_buffer
[512];
194 /* Config rom buffers */
196 dma_addr_t config_rom_bus
;
197 __be32
*next_config_rom
;
198 dma_addr_t next_config_rom_bus
;
201 struct ar_context ar_request_ctx
;
202 struct ar_context ar_response_ctx
;
203 struct context at_request_ctx
;
204 struct context at_response_ctx
;
207 struct iso_context
*it_context_list
;
209 struct iso_context
*ir_context_list
;
212 static inline struct fw_ohci
*fw_ohci(struct fw_card
*card
)
214 return container_of(card
, struct fw_ohci
, card
);
217 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
218 #define IR_CONTEXT_BUFFER_FILL 0x80000000
219 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
220 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
221 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
222 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
224 #define CONTEXT_RUN 0x8000
225 #define CONTEXT_WAKE 0x1000
226 #define CONTEXT_DEAD 0x0800
227 #define CONTEXT_ACTIVE 0x0400
229 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
230 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
231 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
233 #define FW_OHCI_MAJOR 240
234 #define OHCI1394_REGISTER_SIZE 0x800
235 #define OHCI_LOOP_COUNT 500
236 #define OHCI1394_PCI_HCI_Control 0x40
237 #define SELF_ID_BUF_SIZE 0x800
238 #define OHCI_TCODE_PHY_PACKET 0x0e
239 #define OHCI_VERSION_1_1 0x010010
241 static char ohci_driver_name
[] = KBUILD_MODNAME
;
243 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
245 #define OHCI_PARAM_DEBUG_AT_AR 1
246 #define OHCI_PARAM_DEBUG_SELFIDS 2
247 #define OHCI_PARAM_DEBUG_IRQS 4
248 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
250 static int param_debug
;
251 module_param_named(debug
, param_debug
, int, 0644);
252 MODULE_PARM_DESC(debug
, "Verbose logging (default = 0"
253 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR
)
254 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS
)
255 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS
)
256 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS
)
257 ", or a combination, or all = -1)");
259 static void log_irqs(u32 evt
)
261 if (likely(!(param_debug
&
262 (OHCI_PARAM_DEBUG_IRQS
| OHCI_PARAM_DEBUG_BUSRESETS
))))
265 if (!(param_debug
& OHCI_PARAM_DEBUG_IRQS
) &&
266 !(evt
& OHCI1394_busReset
))
269 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt
,
270 evt
& OHCI1394_selfIDComplete
? " selfID" : "",
271 evt
& OHCI1394_RQPkt
? " AR_req" : "",
272 evt
& OHCI1394_RSPkt
? " AR_resp" : "",
273 evt
& OHCI1394_reqTxComplete
? " AT_req" : "",
274 evt
& OHCI1394_respTxComplete
? " AT_resp" : "",
275 evt
& OHCI1394_isochRx
? " IR" : "",
276 evt
& OHCI1394_isochTx
? " IT" : "",
277 evt
& OHCI1394_postedWriteErr
? " postedWriteErr" : "",
278 evt
& OHCI1394_cycleTooLong
? " cycleTooLong" : "",
279 evt
& OHCI1394_cycle64Seconds
? " cycle64Seconds" : "",
280 evt
& OHCI1394_regAccessFail
? " regAccessFail" : "",
281 evt
& OHCI1394_busReset
? " busReset" : "",
282 evt
& ~(OHCI1394_selfIDComplete
| OHCI1394_RQPkt
|
283 OHCI1394_RSPkt
| OHCI1394_reqTxComplete
|
284 OHCI1394_respTxComplete
| OHCI1394_isochRx
|
285 OHCI1394_isochTx
| OHCI1394_postedWriteErr
|
286 OHCI1394_cycleTooLong
| OHCI1394_cycle64Seconds
|
287 OHCI1394_regAccessFail
| OHCI1394_busReset
)
291 static const char *speed
[] = {
292 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
294 static const char *power
[] = {
295 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
296 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
298 static const char port
[] = { '.', '-', 'p', 'c', };
300 static char _p(u32
*s
, int shift
)
302 return port
[*s
>> shift
& 3];
305 static void log_selfids(int node_id
, int generation
, int self_id_count
, u32
*s
)
307 if (likely(!(param_debug
& OHCI_PARAM_DEBUG_SELFIDS
)))
310 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
311 self_id_count
, generation
, node_id
);
313 for (; self_id_count
--; ++s
)
314 if ((*s
& 1 << 23) == 0)
315 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
316 "%s gc=%d %s %s%s%s\n",
317 *s
, *s
>> 24 & 63, _p(s
, 6), _p(s
, 4), _p(s
, 2),
318 speed
[*s
>> 14 & 3], *s
>> 16 & 63,
319 power
[*s
>> 8 & 7], *s
>> 22 & 1 ? "L" : "",
320 *s
>> 11 & 1 ? "c" : "", *s
& 2 ? "i" : "");
322 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
324 _p(s
, 16), _p(s
, 14), _p(s
, 12), _p(s
, 10),
325 _p(s
, 8), _p(s
, 6), _p(s
, 4), _p(s
, 2));
328 static const char *evts
[] = {
329 [0x00] = "evt_no_status", [0x01] = "-reserved-",
330 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
331 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
332 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
333 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
334 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
335 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
336 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
337 [0x10] = "-reserved-", [0x11] = "ack_complete",
338 [0x12] = "ack_pending ", [0x13] = "-reserved-",
339 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
340 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
341 [0x18] = "-reserved-", [0x19] = "-reserved-",
342 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
343 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
344 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
345 [0x20] = "pending/cancelled",
347 static const char *tcodes
[] = {
348 [0x0] = "QW req", [0x1] = "BW req",
349 [0x2] = "W resp", [0x3] = "-reserved-",
350 [0x4] = "QR req", [0x5] = "BR req",
351 [0x6] = "QR resp", [0x7] = "BR resp",
352 [0x8] = "cycle start", [0x9] = "Lk req",
353 [0xa] = "async stream packet", [0xb] = "Lk resp",
354 [0xc] = "-reserved-", [0xd] = "-reserved-",
355 [0xe] = "link internal", [0xf] = "-reserved-",
357 static const char *phys
[] = {
358 [0x0] = "phy config packet", [0x1] = "link-on packet",
359 [0x2] = "self-id packet", [0x3] = "-reserved-",
362 static void log_ar_at_event(char dir
, int speed
, u32
*header
, int evt
)
364 int tcode
= header
[0] >> 4 & 0xf;
367 if (likely(!(param_debug
& OHCI_PARAM_DEBUG_AT_AR
)))
370 if (unlikely(evt
>= ARRAY_SIZE(evts
)))
373 if (evt
== OHCI1394_evt_bus_reset
) {
374 fw_notify("A%c evt_bus_reset, generation %d\n",
375 dir
, (header
[2] >> 16) & 0xff);
379 if (header
[0] == ~header
[1]) {
380 fw_notify("A%c %s, %s, %08x\n",
381 dir
, evts
[evt
], phys
[header
[0] >> 30 & 0x3], header
[0]);
386 case 0x0: case 0x6: case 0x8:
387 snprintf(specific
, sizeof(specific
), " = %08x",
388 be32_to_cpu((__force __be32
)header
[3]));
390 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
391 snprintf(specific
, sizeof(specific
), " %x,%x",
392 header
[3] >> 16, header
[3] & 0xffff);
400 fw_notify("A%c %s, %s\n", dir
, evts
[evt
], tcodes
[tcode
]);
402 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
403 fw_notify("A%c spd %x tl %02x, "
406 dir
, speed
, header
[0] >> 10 & 0x3f,
407 header
[1] >> 16, header
[0] >> 16, evts
[evt
],
408 tcodes
[tcode
], header
[1] & 0xffff, header
[2], specific
);
411 fw_notify("A%c spd %x tl %02x, "
414 dir
, speed
, header
[0] >> 10 & 0x3f,
415 header
[1] >> 16, header
[0] >> 16, evts
[evt
],
416 tcodes
[tcode
], specific
);
422 #define log_irqs(evt)
423 #define log_selfids(node_id, generation, self_id_count, sid)
424 #define log_ar_at_event(dir, speed, header, evt)
426 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
428 static inline void reg_write(const struct fw_ohci
*ohci
, int offset
, u32 data
)
430 writel(data
, ohci
->registers
+ offset
);
433 static inline u32
reg_read(const struct fw_ohci
*ohci
, int offset
)
435 return readl(ohci
->registers
+ offset
);
438 static inline void flush_writes(const struct fw_ohci
*ohci
)
440 /* Do a dummy read to flush writes. */
441 reg_read(ohci
, OHCI1394_Version
);
445 ohci_update_phy_reg(struct fw_card
*card
, int addr
,
446 int clear_bits
, int set_bits
)
448 struct fw_ohci
*ohci
= fw_ohci(card
);
451 reg_write(ohci
, OHCI1394_PhyControl
, OHCI1394_PhyControl_Read(addr
));
454 val
= reg_read(ohci
, OHCI1394_PhyControl
);
455 if ((val
& OHCI1394_PhyControl_ReadDone
) == 0) {
456 fw_error("failed to set phy reg bits.\n");
460 old
= OHCI1394_PhyControl_ReadData(val
);
461 old
= (old
& ~clear_bits
) | set_bits
;
462 reg_write(ohci
, OHCI1394_PhyControl
,
463 OHCI1394_PhyControl_Write(addr
, old
));
468 static int ar_context_add_page(struct ar_context
*ctx
)
470 struct device
*dev
= ctx
->ohci
->card
.device
;
471 struct ar_buffer
*ab
;
472 dma_addr_t
uninitialized_var(ab_bus
);
475 ab
= dma_alloc_coherent(dev
, PAGE_SIZE
, &ab_bus
, GFP_ATOMIC
);
479 memset(&ab
->descriptor
, 0, sizeof(ab
->descriptor
));
480 ab
->descriptor
.control
= cpu_to_le16(DESCRIPTOR_INPUT_MORE
|
482 DESCRIPTOR_BRANCH_ALWAYS
);
483 offset
= offsetof(struct ar_buffer
, data
);
484 ab
->descriptor
.req_count
= cpu_to_le16(PAGE_SIZE
- offset
);
485 ab
->descriptor
.data_address
= cpu_to_le32(ab_bus
+ offset
);
486 ab
->descriptor
.res_count
= cpu_to_le16(PAGE_SIZE
- offset
);
487 ab
->descriptor
.branch_address
= 0;
489 ctx
->last_buffer
->descriptor
.branch_address
= cpu_to_le32(ab_bus
| 1);
490 ctx
->last_buffer
->next
= ab
;
491 ctx
->last_buffer
= ab
;
493 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
494 flush_writes(ctx
->ohci
);
499 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
500 #define cond_le32_to_cpu(v) \
501 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
503 #define cond_le32_to_cpu(v) le32_to_cpu(v)
506 static __le32
*handle_ar_packet(struct ar_context
*ctx
, __le32
*buffer
)
508 struct fw_ohci
*ohci
= ctx
->ohci
;
510 u32 status
, length
, tcode
;
513 p
.header
[0] = cond_le32_to_cpu(buffer
[0]);
514 p
.header
[1] = cond_le32_to_cpu(buffer
[1]);
515 p
.header
[2] = cond_le32_to_cpu(buffer
[2]);
517 tcode
= (p
.header
[0] >> 4) & 0x0f;
519 case TCODE_WRITE_QUADLET_REQUEST
:
520 case TCODE_READ_QUADLET_RESPONSE
:
521 p
.header
[3] = (__force __u32
) buffer
[3];
522 p
.header_length
= 16;
523 p
.payload_length
= 0;
526 case TCODE_READ_BLOCK_REQUEST
:
527 p
.header
[3] = cond_le32_to_cpu(buffer
[3]);
528 p
.header_length
= 16;
529 p
.payload_length
= 0;
532 case TCODE_WRITE_BLOCK_REQUEST
:
533 case TCODE_READ_BLOCK_RESPONSE
:
534 case TCODE_LOCK_REQUEST
:
535 case TCODE_LOCK_RESPONSE
:
536 p
.header
[3] = cond_le32_to_cpu(buffer
[3]);
537 p
.header_length
= 16;
538 p
.payload_length
= p
.header
[3] >> 16;
541 case TCODE_WRITE_RESPONSE
:
542 case TCODE_READ_QUADLET_REQUEST
:
543 case OHCI_TCODE_PHY_PACKET
:
544 p
.header_length
= 12;
545 p
.payload_length
= 0;
549 /* FIXME: Stop context, discard everything, and restart? */
551 p
.payload_length
= 0;
554 p
.payload
= (void *) buffer
+ p
.header_length
;
556 /* FIXME: What to do about evt_* errors? */
557 length
= (p
.header_length
+ p
.payload_length
+ 3) / 4;
558 status
= cond_le32_to_cpu(buffer
[length
]);
559 evt
= (status
>> 16) & 0x1f;
562 p
.speed
= (status
>> 21) & 0x7;
563 p
.timestamp
= status
& 0xffff;
564 p
.generation
= ohci
->request_generation
;
566 log_ar_at_event('R', p
.speed
, p
.header
, evt
);
569 * The OHCI bus reset handler synthesizes a phy packet with
570 * the new generation number when a bus reset happens (see
571 * section 8.4.2.3). This helps us determine when a request
572 * was received and make sure we send the response in the same
573 * generation. We only need this for requests; for responses
574 * we use the unique tlabel for finding the matching
577 * Alas some chips sometimes emit bus reset packets with a
578 * wrong generation. We set the correct generation for these
579 * at a slightly incorrect time (in bus_reset_tasklet).
581 if (evt
== OHCI1394_evt_bus_reset
) {
582 if (!ohci
->bus_reset_packet_quirk
)
583 ohci
->request_generation
= (p
.header
[2] >> 16) & 0xff;
584 } else if (ctx
== &ohci
->ar_request_ctx
) {
585 fw_core_handle_request(&ohci
->card
, &p
);
587 fw_core_handle_response(&ohci
->card
, &p
);
590 return buffer
+ length
+ 1;
593 static void ar_context_tasklet(unsigned long data
)
595 struct ar_context
*ctx
= (struct ar_context
*)data
;
596 struct fw_ohci
*ohci
= ctx
->ohci
;
597 struct ar_buffer
*ab
;
598 struct descriptor
*d
;
601 ab
= ctx
->current_buffer
;
604 if (d
->res_count
== 0) {
605 size_t size
, rest
, offset
;
606 dma_addr_t start_bus
;
610 * This descriptor is finished and we may have a
611 * packet split across this and the next buffer. We
612 * reuse the page for reassembling the split packet.
615 offset
= offsetof(struct ar_buffer
, data
);
617 start_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
621 size
= buffer
+ PAGE_SIZE
- ctx
->pointer
;
622 rest
= le16_to_cpu(d
->req_count
) - le16_to_cpu(d
->res_count
);
623 memmove(buffer
, ctx
->pointer
, size
);
624 memcpy(buffer
+ size
, ab
->data
, rest
);
625 ctx
->current_buffer
= ab
;
626 ctx
->pointer
= (void *) ab
->data
+ rest
;
627 end
= buffer
+ size
+ rest
;
630 buffer
= handle_ar_packet(ctx
, buffer
);
632 dma_free_coherent(ohci
->card
.device
, PAGE_SIZE
,
634 ar_context_add_page(ctx
);
636 buffer
= ctx
->pointer
;
638 (void *) ab
+ PAGE_SIZE
- le16_to_cpu(d
->res_count
);
641 buffer
= handle_ar_packet(ctx
, buffer
);
646 ar_context_init(struct ar_context
*ctx
, struct fw_ohci
*ohci
, u32 regs
)
652 ctx
->last_buffer
= &ab
;
653 tasklet_init(&ctx
->tasklet
, ar_context_tasklet
, (unsigned long)ctx
);
655 ar_context_add_page(ctx
);
656 ar_context_add_page(ctx
);
657 ctx
->current_buffer
= ab
.next
;
658 ctx
->pointer
= ctx
->current_buffer
->data
;
663 static void ar_context_run(struct ar_context
*ctx
)
665 struct ar_buffer
*ab
= ctx
->current_buffer
;
669 offset
= offsetof(struct ar_buffer
, data
);
670 ab_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
672 reg_write(ctx
->ohci
, COMMAND_PTR(ctx
->regs
), ab_bus
| 1);
673 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
);
674 flush_writes(ctx
->ohci
);
677 static struct descriptor
*
678 find_branch_descriptor(struct descriptor
*d
, int z
)
682 b
= (le16_to_cpu(d
->control
) & DESCRIPTOR_BRANCH_ALWAYS
) >> 2;
683 key
= (le16_to_cpu(d
->control
) & DESCRIPTOR_KEY_IMMEDIATE
) >> 8;
685 /* figure out which descriptor the branch address goes in */
686 if (z
== 2 && (b
== 3 || key
== 2))
692 static void context_tasklet(unsigned long data
)
694 struct context
*ctx
= (struct context
*) data
;
695 struct descriptor
*d
, *last
;
698 struct descriptor_buffer
*desc
;
700 desc
= list_entry(ctx
->buffer_list
.next
,
701 struct descriptor_buffer
, list
);
703 while (last
->branch_address
!= 0) {
704 struct descriptor_buffer
*old_desc
= desc
;
705 address
= le32_to_cpu(last
->branch_address
);
709 /* If the branch address points to a buffer outside of the
710 * current buffer, advance to the next buffer. */
711 if (address
< desc
->buffer_bus
||
712 address
>= desc
->buffer_bus
+ desc
->used
)
713 desc
= list_entry(desc
->list
.next
,
714 struct descriptor_buffer
, list
);
715 d
= desc
->buffer
+ (address
- desc
->buffer_bus
) / sizeof(*d
);
716 last
= find_branch_descriptor(d
, z
);
718 if (!ctx
->callback(ctx
, d
, last
))
721 if (old_desc
!= desc
) {
722 /* If we've advanced to the next buffer, move the
723 * previous buffer to the free list. */
726 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
727 list_move_tail(&old_desc
->list
, &ctx
->buffer_list
);
728 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
735 * Allocate a new buffer and add it to the list of free buffers for this
736 * context. Must be called with ohci->lock held.
739 context_add_buffer(struct context
*ctx
)
741 struct descriptor_buffer
*desc
;
742 dma_addr_t
uninitialized_var(bus_addr
);
746 * 16MB of descriptors should be far more than enough for any DMA
747 * program. This will catch run-away userspace or DoS attacks.
749 if (ctx
->total_allocation
>= 16*1024*1024)
752 desc
= dma_alloc_coherent(ctx
->ohci
->card
.device
, PAGE_SIZE
,
753 &bus_addr
, GFP_ATOMIC
);
757 offset
= (void *)&desc
->buffer
- (void *)desc
;
758 desc
->buffer_size
= PAGE_SIZE
- offset
;
759 desc
->buffer_bus
= bus_addr
+ offset
;
762 list_add_tail(&desc
->list
, &ctx
->buffer_list
);
763 ctx
->total_allocation
+= PAGE_SIZE
;
769 context_init(struct context
*ctx
, struct fw_ohci
*ohci
,
770 u32 regs
, descriptor_callback_t callback
)
774 ctx
->total_allocation
= 0;
776 INIT_LIST_HEAD(&ctx
->buffer_list
);
777 if (context_add_buffer(ctx
) < 0)
780 ctx
->buffer_tail
= list_entry(ctx
->buffer_list
.next
,
781 struct descriptor_buffer
, list
);
783 tasklet_init(&ctx
->tasklet
, context_tasklet
, (unsigned long)ctx
);
784 ctx
->callback
= callback
;
787 * We put a dummy descriptor in the buffer that has a NULL
788 * branch address and looks like it's been sent. That way we
789 * have a descriptor to append DMA programs to.
791 memset(ctx
->buffer_tail
->buffer
, 0, sizeof(*ctx
->buffer_tail
->buffer
));
792 ctx
->buffer_tail
->buffer
->control
= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
);
793 ctx
->buffer_tail
->buffer
->transfer_status
= cpu_to_le16(0x8011);
794 ctx
->buffer_tail
->used
+= sizeof(*ctx
->buffer_tail
->buffer
);
795 ctx
->last
= ctx
->buffer_tail
->buffer
;
796 ctx
->prev
= ctx
->buffer_tail
->buffer
;
802 context_release(struct context
*ctx
)
804 struct fw_card
*card
= &ctx
->ohci
->card
;
805 struct descriptor_buffer
*desc
, *tmp
;
807 list_for_each_entry_safe(desc
, tmp
, &ctx
->buffer_list
, list
)
808 dma_free_coherent(card
->device
, PAGE_SIZE
, desc
,
810 ((void *)&desc
->buffer
- (void *)desc
));
813 /* Must be called with ohci->lock held */
814 static struct descriptor
*
815 context_get_descriptors(struct context
*ctx
, int z
, dma_addr_t
*d_bus
)
817 struct descriptor
*d
= NULL
;
818 struct descriptor_buffer
*desc
= ctx
->buffer_tail
;
820 if (z
* sizeof(*d
) > desc
->buffer_size
)
823 if (z
* sizeof(*d
) > desc
->buffer_size
- desc
->used
) {
824 /* No room for the descriptor in this buffer, so advance to the
827 if (desc
->list
.next
== &ctx
->buffer_list
) {
828 /* If there is no free buffer next in the list,
830 if (context_add_buffer(ctx
) < 0)
833 desc
= list_entry(desc
->list
.next
,
834 struct descriptor_buffer
, list
);
835 ctx
->buffer_tail
= desc
;
838 d
= desc
->buffer
+ desc
->used
/ sizeof(*d
);
839 memset(d
, 0, z
* sizeof(*d
));
840 *d_bus
= desc
->buffer_bus
+ desc
->used
;
845 static void context_run(struct context
*ctx
, u32 extra
)
847 struct fw_ohci
*ohci
= ctx
->ohci
;
849 reg_write(ohci
, COMMAND_PTR(ctx
->regs
),
850 le32_to_cpu(ctx
->last
->branch_address
));
851 reg_write(ohci
, CONTROL_CLEAR(ctx
->regs
), ~0);
852 reg_write(ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
| extra
);
856 static void context_append(struct context
*ctx
,
857 struct descriptor
*d
, int z
, int extra
)
860 struct descriptor_buffer
*desc
= ctx
->buffer_tail
;
862 d_bus
= desc
->buffer_bus
+ (d
- desc
->buffer
) * sizeof(*d
);
864 desc
->used
+= (z
+ extra
) * sizeof(*d
);
865 ctx
->prev
->branch_address
= cpu_to_le32(d_bus
| z
);
866 ctx
->prev
= find_branch_descriptor(d
, z
);
868 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
869 flush_writes(ctx
->ohci
);
872 static void context_stop(struct context
*ctx
)
877 reg_write(ctx
->ohci
, CONTROL_CLEAR(ctx
->regs
), CONTEXT_RUN
);
878 flush_writes(ctx
->ohci
);
880 for (i
= 0; i
< 10; i
++) {
881 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
882 if ((reg
& CONTEXT_ACTIVE
) == 0)
885 fw_notify("context_stop: still active (0x%08x)\n", reg
);
891 struct fw_packet
*packet
;
895 * This function apppends a packet to the DMA queue for transmission.
896 * Must always be called with the ochi->lock held to ensure proper
897 * generation handling and locking around packet queue manipulation.
900 at_context_queue_packet(struct context
*ctx
, struct fw_packet
*packet
)
902 struct fw_ohci
*ohci
= ctx
->ohci
;
903 dma_addr_t d_bus
, uninitialized_var(payload_bus
);
904 struct driver_data
*driver_data
;
905 struct descriptor
*d
, *last
;
910 d
= context_get_descriptors(ctx
, 4, &d_bus
);
912 packet
->ack
= RCODE_SEND_ERROR
;
916 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
917 d
[0].res_count
= cpu_to_le16(packet
->timestamp
);
920 * The DMA format for asyncronous link packets is different
921 * from the IEEE1394 layout, so shift the fields around
922 * accordingly. If header_length is 8, it's a PHY packet, to
923 * which we need to prepend an extra quadlet.
926 header
= (__le32
*) &d
[1];
927 if (packet
->header_length
> 8) {
928 header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
929 (packet
->speed
<< 16));
930 header
[1] = cpu_to_le32((packet
->header
[1] & 0xffff) |
931 (packet
->header
[0] & 0xffff0000));
932 header
[2] = cpu_to_le32(packet
->header
[2]);
934 tcode
= (packet
->header
[0] >> 4) & 0x0f;
935 if (TCODE_IS_BLOCK_PACKET(tcode
))
936 header
[3] = cpu_to_le32(packet
->header
[3]);
938 header
[3] = (__force __le32
) packet
->header
[3];
940 d
[0].req_count
= cpu_to_le16(packet
->header_length
);
942 header
[0] = cpu_to_le32((OHCI1394_phy_tcode
<< 4) |
943 (packet
->speed
<< 16));
944 header
[1] = cpu_to_le32(packet
->header
[0]);
945 header
[2] = cpu_to_le32(packet
->header
[1]);
946 d
[0].req_count
= cpu_to_le16(12);
949 driver_data
= (struct driver_data
*) &d
[3];
950 driver_data
->packet
= packet
;
951 packet
->driver_data
= driver_data
;
953 if (packet
->payload_length
> 0) {
955 dma_map_single(ohci
->card
.device
, packet
->payload
,
956 packet
->payload_length
, DMA_TO_DEVICE
);
957 if (dma_mapping_error(ohci
->card
.device
, payload_bus
)) {
958 packet
->ack
= RCODE_SEND_ERROR
;
961 packet
->payload_bus
= payload_bus
;
963 d
[2].req_count
= cpu_to_le16(packet
->payload_length
);
964 d
[2].data_address
= cpu_to_le32(payload_bus
);
972 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
973 DESCRIPTOR_IRQ_ALWAYS
|
974 DESCRIPTOR_BRANCH_ALWAYS
);
977 * If the controller and packet generations don't match, we need to
978 * bail out and try again. If IntEvent.busReset is set, the AT context
979 * is halted, so appending to the context and trying to run it is
980 * futile. Most controllers do the right thing and just flush the AT
981 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
982 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
983 * up stalling out. So we just bail out in software and try again
984 * later, and everyone is happy.
985 * FIXME: Document how the locking works.
987 if (ohci
->generation
!= packet
->generation
||
988 reg_read(ohci
, OHCI1394_IntEventSet
) & OHCI1394_busReset
) {
989 if (packet
->payload_length
> 0)
990 dma_unmap_single(ohci
->card
.device
, payload_bus
,
991 packet
->payload_length
, DMA_TO_DEVICE
);
992 packet
->ack
= RCODE_GENERATION
;
996 context_append(ctx
, d
, z
, 4 - z
);
998 /* If the context isn't already running, start it up. */
999 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
1000 if ((reg
& CONTEXT_RUN
) == 0)
1001 context_run(ctx
, 0);
1006 static int handle_at_packet(struct context
*context
,
1007 struct descriptor
*d
,
1008 struct descriptor
*last
)
1010 struct driver_data
*driver_data
;
1011 struct fw_packet
*packet
;
1012 struct fw_ohci
*ohci
= context
->ohci
;
1015 if (last
->transfer_status
== 0)
1016 /* This descriptor isn't done yet, stop iteration. */
1019 driver_data
= (struct driver_data
*) &d
[3];
1020 packet
= driver_data
->packet
;
1022 /* This packet was cancelled, just continue. */
1025 if (packet
->payload_bus
)
1026 dma_unmap_single(ohci
->card
.device
, packet
->payload_bus
,
1027 packet
->payload_length
, DMA_TO_DEVICE
);
1029 evt
= le16_to_cpu(last
->transfer_status
) & 0x1f;
1030 packet
->timestamp
= le16_to_cpu(last
->res_count
);
1032 log_ar_at_event('T', packet
->speed
, packet
->header
, evt
);
1035 case OHCI1394_evt_timeout
:
1036 /* Async response transmit timed out. */
1037 packet
->ack
= RCODE_CANCELLED
;
1040 case OHCI1394_evt_flushed
:
1042 * The packet was flushed should give same error as
1043 * when we try to use a stale generation count.
1045 packet
->ack
= RCODE_GENERATION
;
1048 case OHCI1394_evt_missing_ack
:
1050 * Using a valid (current) generation count, but the
1051 * node is not on the bus or not sending acks.
1053 packet
->ack
= RCODE_NO_ACK
;
1056 case ACK_COMPLETE
+ 0x10:
1057 case ACK_PENDING
+ 0x10:
1058 case ACK_BUSY_X
+ 0x10:
1059 case ACK_BUSY_A
+ 0x10:
1060 case ACK_BUSY_B
+ 0x10:
1061 case ACK_DATA_ERROR
+ 0x10:
1062 case ACK_TYPE_ERROR
+ 0x10:
1063 packet
->ack
= evt
- 0x10;
1067 packet
->ack
= RCODE_SEND_ERROR
;
1071 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1076 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1077 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1078 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1079 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1080 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1083 handle_local_rom(struct fw_ohci
*ohci
, struct fw_packet
*packet
, u32 csr
)
1085 struct fw_packet response
;
1086 int tcode
, length
, i
;
1088 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
1089 if (TCODE_IS_BLOCK_PACKET(tcode
))
1090 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
1094 i
= csr
- CSR_CONFIG_ROM
;
1095 if (i
+ length
> CONFIG_ROM_SIZE
) {
1096 fw_fill_response(&response
, packet
->header
,
1097 RCODE_ADDRESS_ERROR
, NULL
, 0);
1098 } else if (!TCODE_IS_READ_REQUEST(tcode
)) {
1099 fw_fill_response(&response
, packet
->header
,
1100 RCODE_TYPE_ERROR
, NULL
, 0);
1102 fw_fill_response(&response
, packet
->header
, RCODE_COMPLETE
,
1103 (void *) ohci
->config_rom
+ i
, length
);
1106 fw_core_handle_response(&ohci
->card
, &response
);
1110 handle_local_lock(struct fw_ohci
*ohci
, struct fw_packet
*packet
, u32 csr
)
1112 struct fw_packet response
;
1113 int tcode
, length
, ext_tcode
, sel
;
1114 __be32
*payload
, lock_old
;
1115 u32 lock_arg
, lock_data
;
1117 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
1118 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
1119 payload
= packet
->payload
;
1120 ext_tcode
= HEADER_GET_EXTENDED_TCODE(packet
->header
[3]);
1122 if (tcode
== TCODE_LOCK_REQUEST
&&
1123 ext_tcode
== EXTCODE_COMPARE_SWAP
&& length
== 8) {
1124 lock_arg
= be32_to_cpu(payload
[0]);
1125 lock_data
= be32_to_cpu(payload
[1]);
1126 } else if (tcode
== TCODE_READ_QUADLET_REQUEST
) {
1130 fw_fill_response(&response
, packet
->header
,
1131 RCODE_TYPE_ERROR
, NULL
, 0);
1135 sel
= (csr
- CSR_BUS_MANAGER_ID
) / 4;
1136 reg_write(ohci
, OHCI1394_CSRData
, lock_data
);
1137 reg_write(ohci
, OHCI1394_CSRCompareData
, lock_arg
);
1138 reg_write(ohci
, OHCI1394_CSRControl
, sel
);
1140 if (reg_read(ohci
, OHCI1394_CSRControl
) & 0x80000000)
1141 lock_old
= cpu_to_be32(reg_read(ohci
, OHCI1394_CSRData
));
1143 fw_notify("swap not done yet\n");
1145 fw_fill_response(&response
, packet
->header
,
1146 RCODE_COMPLETE
, &lock_old
, sizeof(lock_old
));
1148 fw_core_handle_response(&ohci
->card
, &response
);
1152 handle_local_request(struct context
*ctx
, struct fw_packet
*packet
)
1157 if (ctx
== &ctx
->ohci
->at_request_ctx
) {
1158 packet
->ack
= ACK_PENDING
;
1159 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1163 ((unsigned long long)
1164 HEADER_GET_OFFSET_HIGH(packet
->header
[1]) << 32) |
1166 csr
= offset
- CSR_REGISTER_BASE
;
1168 /* Handle config rom reads. */
1169 if (csr
>= CSR_CONFIG_ROM
&& csr
< CSR_CONFIG_ROM_END
)
1170 handle_local_rom(ctx
->ohci
, packet
, csr
);
1172 case CSR_BUS_MANAGER_ID
:
1173 case CSR_BANDWIDTH_AVAILABLE
:
1174 case CSR_CHANNELS_AVAILABLE_HI
:
1175 case CSR_CHANNELS_AVAILABLE_LO
:
1176 handle_local_lock(ctx
->ohci
, packet
, csr
);
1179 if (ctx
== &ctx
->ohci
->at_request_ctx
)
1180 fw_core_handle_request(&ctx
->ohci
->card
, packet
);
1182 fw_core_handle_response(&ctx
->ohci
->card
, packet
);
1186 if (ctx
== &ctx
->ohci
->at_response_ctx
) {
1187 packet
->ack
= ACK_COMPLETE
;
1188 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1193 at_context_transmit(struct context
*ctx
, struct fw_packet
*packet
)
1195 unsigned long flags
;
1198 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
1200 if (HEADER_GET_DESTINATION(packet
->header
[0]) == ctx
->ohci
->node_id
&&
1201 ctx
->ohci
->generation
== packet
->generation
) {
1202 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
1203 handle_local_request(ctx
, packet
);
1207 retval
= at_context_queue_packet(ctx
, packet
);
1208 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
1211 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1215 static void bus_reset_tasklet(unsigned long data
)
1217 struct fw_ohci
*ohci
= (struct fw_ohci
*)data
;
1218 int self_id_count
, i
, j
, reg
;
1219 int generation
, new_generation
;
1220 unsigned long flags
;
1221 void *free_rom
= NULL
;
1222 dma_addr_t free_rom_bus
= 0;
1224 reg
= reg_read(ohci
, OHCI1394_NodeID
);
1225 if (!(reg
& OHCI1394_NodeID_idValid
)) {
1226 fw_notify("node ID not valid, new bus reset in progress\n");
1229 if ((reg
& OHCI1394_NodeID_nodeNumber
) == 63) {
1230 fw_notify("malconfigured bus\n");
1233 ohci
->node_id
= reg
& (OHCI1394_NodeID_busNumber
|
1234 OHCI1394_NodeID_nodeNumber
);
1236 reg
= reg_read(ohci
, OHCI1394_SelfIDCount
);
1237 if (reg
& OHCI1394_SelfIDCount_selfIDError
) {
1238 fw_notify("inconsistent self IDs\n");
1242 * The count in the SelfIDCount register is the number of
1243 * bytes in the self ID receive buffer. Since we also receive
1244 * the inverted quadlets and a header quadlet, we shift one
1245 * bit extra to get the actual number of self IDs.
1247 self_id_count
= (reg
>> 3) & 0x3ff;
1248 if (self_id_count
== 0) {
1249 fw_notify("inconsistent self IDs\n");
1252 generation
= (cond_le32_to_cpu(ohci
->self_id_cpu
[0]) >> 16) & 0xff;
1255 for (i
= 1, j
= 0; j
< self_id_count
; i
+= 2, j
++) {
1256 if (ohci
->self_id_cpu
[i
] != ~ohci
->self_id_cpu
[i
+ 1]) {
1257 fw_notify("inconsistent self IDs\n");
1260 ohci
->self_id_buffer
[j
] =
1261 cond_le32_to_cpu(ohci
->self_id_cpu
[i
]);
1266 * Check the consistency of the self IDs we just read. The
1267 * problem we face is that a new bus reset can start while we
1268 * read out the self IDs from the DMA buffer. If this happens,
1269 * the DMA buffer will be overwritten with new self IDs and we
1270 * will read out inconsistent data. The OHCI specification
1271 * (section 11.2) recommends a technique similar to
1272 * linux/seqlock.h, where we remember the generation of the
1273 * self IDs in the buffer before reading them out and compare
1274 * it to the current generation after reading them out. If
1275 * the two generations match we know we have a consistent set
1279 new_generation
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 16) & 0xff;
1280 if (new_generation
!= generation
) {
1281 fw_notify("recursive bus reset detected, "
1282 "discarding self ids\n");
1286 /* FIXME: Document how the locking works. */
1287 spin_lock_irqsave(&ohci
->lock
, flags
);
1289 ohci
->generation
= generation
;
1290 context_stop(&ohci
->at_request_ctx
);
1291 context_stop(&ohci
->at_response_ctx
);
1292 reg_write(ohci
, OHCI1394_IntEventClear
, OHCI1394_busReset
);
1294 if (ohci
->bus_reset_packet_quirk
)
1295 ohci
->request_generation
= generation
;
1298 * This next bit is unrelated to the AT context stuff but we
1299 * have to do it under the spinlock also. If a new config rom
1300 * was set up before this reset, the old one is now no longer
1301 * in use and we can free it. Update the config rom pointers
1302 * to point to the current config rom and clear the
1303 * next_config_rom pointer so a new udpate can take place.
1306 if (ohci
->next_config_rom
!= NULL
) {
1307 if (ohci
->next_config_rom
!= ohci
->config_rom
) {
1308 free_rom
= ohci
->config_rom
;
1309 free_rom_bus
= ohci
->config_rom_bus
;
1311 ohci
->config_rom
= ohci
->next_config_rom
;
1312 ohci
->config_rom_bus
= ohci
->next_config_rom_bus
;
1313 ohci
->next_config_rom
= NULL
;
1316 * Restore config_rom image and manually update
1317 * config_rom registers. Writing the header quadlet
1318 * will indicate that the config rom is ready, so we
1321 reg_write(ohci
, OHCI1394_BusOptions
,
1322 be32_to_cpu(ohci
->config_rom
[2]));
1323 ohci
->config_rom
[0] = cpu_to_be32(ohci
->next_header
);
1324 reg_write(ohci
, OHCI1394_ConfigROMhdr
, ohci
->next_header
);
1327 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1328 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, ~0);
1329 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, ~0);
1332 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1335 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1336 free_rom
, free_rom_bus
);
1338 log_selfids(ohci
->node_id
, generation
,
1339 self_id_count
, ohci
->self_id_buffer
);
1341 fw_core_handle_bus_reset(&ohci
->card
, ohci
->node_id
, generation
,
1342 self_id_count
, ohci
->self_id_buffer
);
1345 static irqreturn_t
irq_handler(int irq
, void *data
)
1347 struct fw_ohci
*ohci
= data
;
1348 u32 event
, iso_event
, cycle_time
;
1351 event
= reg_read(ohci
, OHCI1394_IntEventClear
);
1353 if (!event
|| !~event
)
1356 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1357 reg_write(ohci
, OHCI1394_IntEventClear
, event
& ~OHCI1394_busReset
);
1360 if (event
& OHCI1394_selfIDComplete
)
1361 tasklet_schedule(&ohci
->bus_reset_tasklet
);
1363 if (event
& OHCI1394_RQPkt
)
1364 tasklet_schedule(&ohci
->ar_request_ctx
.tasklet
);
1366 if (event
& OHCI1394_RSPkt
)
1367 tasklet_schedule(&ohci
->ar_response_ctx
.tasklet
);
1369 if (event
& OHCI1394_reqTxComplete
)
1370 tasklet_schedule(&ohci
->at_request_ctx
.tasklet
);
1372 if (event
& OHCI1394_respTxComplete
)
1373 tasklet_schedule(&ohci
->at_response_ctx
.tasklet
);
1375 iso_event
= reg_read(ohci
, OHCI1394_IsoRecvIntEventClear
);
1376 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, iso_event
);
1379 i
= ffs(iso_event
) - 1;
1380 tasklet_schedule(&ohci
->ir_context_list
[i
].context
.tasklet
);
1381 iso_event
&= ~(1 << i
);
1384 iso_event
= reg_read(ohci
, OHCI1394_IsoXmitIntEventClear
);
1385 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, iso_event
);
1388 i
= ffs(iso_event
) - 1;
1389 tasklet_schedule(&ohci
->it_context_list
[i
].context
.tasklet
);
1390 iso_event
&= ~(1 << i
);
1393 if (unlikely(event
& OHCI1394_regAccessFail
))
1394 fw_error("Register access failure - "
1395 "please notify linux1394-devel@lists.sf.net\n");
1397 if (unlikely(event
& OHCI1394_postedWriteErr
))
1398 fw_error("PCI posted write error\n");
1400 if (unlikely(event
& OHCI1394_cycleTooLong
)) {
1401 if (printk_ratelimit())
1402 fw_notify("isochronous cycle too long\n");
1403 reg_write(ohci
, OHCI1394_LinkControlSet
,
1404 OHCI1394_LinkControl_cycleMaster
);
1407 if (event
& OHCI1394_cycle64Seconds
) {
1408 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1409 if ((cycle_time
& 0x80000000) == 0)
1410 ohci
->bus_seconds
++;
1416 static int software_reset(struct fw_ohci
*ohci
)
1420 reg_write(ohci
, OHCI1394_HCControlSet
, OHCI1394_HCControl_softReset
);
1422 for (i
= 0; i
< OHCI_LOOP_COUNT
; i
++) {
1423 if ((reg_read(ohci
, OHCI1394_HCControlSet
) &
1424 OHCI1394_HCControl_softReset
) == 0)
1432 static int ohci_enable(struct fw_card
*card
, u32
*config_rom
, size_t length
)
1434 struct fw_ohci
*ohci
= fw_ohci(card
);
1435 struct pci_dev
*dev
= to_pci_dev(card
->device
);
1439 if (software_reset(ohci
)) {
1440 fw_error("Failed to reset ohci card.\n");
1445 * Now enable LPS, which we need in order to start accessing
1446 * most of the registers. In fact, on some cards (ALI M5251),
1447 * accessing registers in the SClk domain without LPS enabled
1448 * will lock up the machine. Wait 50msec to make sure we have
1449 * full link enabled. However, with some cards (well, at least
1450 * a JMicron PCIe card), we have to try again sometimes.
1452 reg_write(ohci
, OHCI1394_HCControlSet
,
1453 OHCI1394_HCControl_LPS
|
1454 OHCI1394_HCControl_postedWriteEnable
);
1457 for (lps
= 0, i
= 0; !lps
&& i
< 3; i
++) {
1459 lps
= reg_read(ohci
, OHCI1394_HCControlSet
) &
1460 OHCI1394_HCControl_LPS
;
1464 fw_error("Failed to set Link Power Status\n");
1468 reg_write(ohci
, OHCI1394_HCControlClear
,
1469 OHCI1394_HCControl_noByteSwapData
);
1471 reg_write(ohci
, OHCI1394_SelfIDBuffer
, ohci
->self_id_bus
);
1472 reg_write(ohci
, OHCI1394_LinkControlClear
,
1473 OHCI1394_LinkControl_rcvPhyPkt
);
1474 reg_write(ohci
, OHCI1394_LinkControlSet
,
1475 OHCI1394_LinkControl_rcvSelfID
|
1476 OHCI1394_LinkControl_cycleTimerEnable
|
1477 OHCI1394_LinkControl_cycleMaster
);
1479 reg_write(ohci
, OHCI1394_ATRetries
,
1480 OHCI1394_MAX_AT_REQ_RETRIES
|
1481 (OHCI1394_MAX_AT_RESP_RETRIES
<< 4) |
1482 (OHCI1394_MAX_PHYS_RESP_RETRIES
<< 8));
1484 ar_context_run(&ohci
->ar_request_ctx
);
1485 ar_context_run(&ohci
->ar_response_ctx
);
1487 reg_write(ohci
, OHCI1394_PhyUpperBound
, 0x00010000);
1488 reg_write(ohci
, OHCI1394_IntEventClear
, ~0);
1489 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1490 reg_write(ohci
, OHCI1394_IntMaskSet
,
1491 OHCI1394_selfIDComplete
|
1492 OHCI1394_RQPkt
| OHCI1394_RSPkt
|
1493 OHCI1394_reqTxComplete
| OHCI1394_respTxComplete
|
1494 OHCI1394_isochRx
| OHCI1394_isochTx
|
1495 OHCI1394_postedWriteErr
| OHCI1394_cycleTooLong
|
1496 OHCI1394_cycle64Seconds
| OHCI1394_regAccessFail
|
1497 OHCI1394_masterIntEnable
);
1498 if (param_debug
& OHCI_PARAM_DEBUG_BUSRESETS
)
1499 reg_write(ohci
, OHCI1394_IntMaskSet
, OHCI1394_busReset
);
1501 /* Activate link_on bit and contender bit in our self ID packets.*/
1502 if (ohci_update_phy_reg(card
, 4, 0,
1503 PHY_LINK_ACTIVE
| PHY_CONTENDER
) < 0)
1507 * When the link is not yet enabled, the atomic config rom
1508 * update mechanism described below in ohci_set_config_rom()
1509 * is not active. We have to update ConfigRomHeader and
1510 * BusOptions manually, and the write to ConfigROMmap takes
1511 * effect immediately. We tie this to the enabling of the
1512 * link, so we have a valid config rom before enabling - the
1513 * OHCI requires that ConfigROMhdr and BusOptions have valid
1514 * values before enabling.
1516 * However, when the ConfigROMmap is written, some controllers
1517 * always read back quadlets 0 and 2 from the config rom to
1518 * the ConfigRomHeader and BusOptions registers on bus reset.
1519 * They shouldn't do that in this initial case where the link
1520 * isn't enabled. This means we have to use the same
1521 * workaround here, setting the bus header to 0 and then write
1522 * the right values in the bus reset tasklet.
1526 ohci
->next_config_rom
=
1527 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1528 &ohci
->next_config_rom_bus
,
1530 if (ohci
->next_config_rom
== NULL
)
1533 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
1534 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
, length
* 4);
1537 * In the suspend case, config_rom is NULL, which
1538 * means that we just reuse the old config rom.
1540 ohci
->next_config_rom
= ohci
->config_rom
;
1541 ohci
->next_config_rom_bus
= ohci
->config_rom_bus
;
1544 ohci
->next_header
= be32_to_cpu(ohci
->next_config_rom
[0]);
1545 ohci
->next_config_rom
[0] = 0;
1546 reg_write(ohci
, OHCI1394_ConfigROMhdr
, 0);
1547 reg_write(ohci
, OHCI1394_BusOptions
,
1548 be32_to_cpu(ohci
->next_config_rom
[2]));
1549 reg_write(ohci
, OHCI1394_ConfigROMmap
, ohci
->next_config_rom_bus
);
1551 reg_write(ohci
, OHCI1394_AsReqFilterHiSet
, 0x80000000);
1553 if (request_irq(dev
->irq
, irq_handler
,
1554 IRQF_SHARED
, ohci_driver_name
, ohci
)) {
1555 fw_error("Failed to allocate shared interrupt %d.\n",
1557 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1558 ohci
->config_rom
, ohci
->config_rom_bus
);
1562 reg_write(ohci
, OHCI1394_HCControlSet
,
1563 OHCI1394_HCControl_linkEnable
|
1564 OHCI1394_HCControl_BIBimageValid
);
1568 * We are ready to go, initiate bus reset to finish the
1572 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1578 ohci_set_config_rom(struct fw_card
*card
, u32
*config_rom
, size_t length
)
1580 struct fw_ohci
*ohci
;
1581 unsigned long flags
;
1582 int retval
= -EBUSY
;
1583 __be32
*next_config_rom
;
1584 dma_addr_t
uninitialized_var(next_config_rom_bus
);
1586 ohci
= fw_ohci(card
);
1589 * When the OHCI controller is enabled, the config rom update
1590 * mechanism is a bit tricky, but easy enough to use. See
1591 * section 5.5.6 in the OHCI specification.
1593 * The OHCI controller caches the new config rom address in a
1594 * shadow register (ConfigROMmapNext) and needs a bus reset
1595 * for the changes to take place. When the bus reset is
1596 * detected, the controller loads the new values for the
1597 * ConfigRomHeader and BusOptions registers from the specified
1598 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1599 * shadow register. All automatically and atomically.
1601 * Now, there's a twist to this story. The automatic load of
1602 * ConfigRomHeader and BusOptions doesn't honor the
1603 * noByteSwapData bit, so with a be32 config rom, the
1604 * controller will load be32 values in to these registers
1605 * during the atomic update, even on litte endian
1606 * architectures. The workaround we use is to put a 0 in the
1607 * header quadlet; 0 is endian agnostic and means that the
1608 * config rom isn't ready yet. In the bus reset tasklet we
1609 * then set up the real values for the two registers.
1611 * We use ohci->lock to avoid racing with the code that sets
1612 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1616 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1617 &next_config_rom_bus
, GFP_KERNEL
);
1618 if (next_config_rom
== NULL
)
1621 spin_lock_irqsave(&ohci
->lock
, flags
);
1623 if (ohci
->next_config_rom
== NULL
) {
1624 ohci
->next_config_rom
= next_config_rom
;
1625 ohci
->next_config_rom_bus
= next_config_rom_bus
;
1627 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
1628 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
,
1631 ohci
->next_header
= config_rom
[0];
1632 ohci
->next_config_rom
[0] = 0;
1634 reg_write(ohci
, OHCI1394_ConfigROMmap
,
1635 ohci
->next_config_rom_bus
);
1639 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1642 * Now initiate a bus reset to have the changes take
1643 * effect. We clean up the old config rom memory and DMA
1644 * mappings in the bus reset tasklet, since the OHCI
1645 * controller could need to access it before the bus reset
1649 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1651 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1652 next_config_rom
, next_config_rom_bus
);
1657 static void ohci_send_request(struct fw_card
*card
, struct fw_packet
*packet
)
1659 struct fw_ohci
*ohci
= fw_ohci(card
);
1661 at_context_transmit(&ohci
->at_request_ctx
, packet
);
1664 static void ohci_send_response(struct fw_card
*card
, struct fw_packet
*packet
)
1666 struct fw_ohci
*ohci
= fw_ohci(card
);
1668 at_context_transmit(&ohci
->at_response_ctx
, packet
);
1671 static int ohci_cancel_packet(struct fw_card
*card
, struct fw_packet
*packet
)
1673 struct fw_ohci
*ohci
= fw_ohci(card
);
1674 struct context
*ctx
= &ohci
->at_request_ctx
;
1675 struct driver_data
*driver_data
= packet
->driver_data
;
1676 int retval
= -ENOENT
;
1678 tasklet_disable(&ctx
->tasklet
);
1680 if (packet
->ack
!= 0)
1683 if (packet
->payload_bus
)
1684 dma_unmap_single(ohci
->card
.device
, packet
->payload_bus
,
1685 packet
->payload_length
, DMA_TO_DEVICE
);
1687 log_ar_at_event('T', packet
->speed
, packet
->header
, 0x20);
1688 driver_data
->packet
= NULL
;
1689 packet
->ack
= RCODE_CANCELLED
;
1690 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1694 tasklet_enable(&ctx
->tasklet
);
1700 ohci_enable_phys_dma(struct fw_card
*card
, int node_id
, int generation
)
1702 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1705 struct fw_ohci
*ohci
= fw_ohci(card
);
1706 unsigned long flags
;
1710 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1711 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1714 spin_lock_irqsave(&ohci
->lock
, flags
);
1716 if (ohci
->generation
!= generation
) {
1722 * Note, if the node ID contains a non-local bus ID, physical DMA is
1723 * enabled for _all_ nodes on remote buses.
1726 n
= (node_id
& 0xffc0) == LOCAL_BUS
? node_id
& 0x3f : 63;
1728 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, 1 << n
);
1730 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, 1 << (n
- 32));
1734 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1736 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1740 ohci_get_bus_time(struct fw_card
*card
)
1742 struct fw_ohci
*ohci
= fw_ohci(card
);
1746 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1747 bus_time
= ((u64
) ohci
->bus_seconds
<< 32) | cycle_time
;
1752 static int handle_ir_dualbuffer_packet(struct context
*context
,
1753 struct descriptor
*d
,
1754 struct descriptor
*last
)
1756 struct iso_context
*ctx
=
1757 container_of(context
, struct iso_context
, context
);
1758 struct db_descriptor
*db
= (struct db_descriptor
*) d
;
1760 size_t header_length
;
1764 if (db
->first_res_count
!= 0 && db
->second_res_count
!= 0) {
1765 if (ctx
->excess_bytes
<= le16_to_cpu(db
->second_req_count
)) {
1766 /* This descriptor isn't done yet, stop iteration. */
1769 ctx
->excess_bytes
-= le16_to_cpu(db
->second_req_count
);
1772 header_length
= le16_to_cpu(db
->first_req_count
) -
1773 le16_to_cpu(db
->first_res_count
);
1775 i
= ctx
->header_length
;
1777 end
= p
+ header_length
;
1778 while (p
< end
&& i
+ ctx
->base
.header_size
<= PAGE_SIZE
) {
1780 * The iso header is byteswapped to little endian by
1781 * the controller, but the remaining header quadlets
1782 * are big endian. We want to present all the headers
1783 * as big endian, so we have to swap the first
1786 *(u32
*) (ctx
->header
+ i
) = __swab32(*(u32
*) (p
+ 4));
1787 memcpy(ctx
->header
+ i
+ 4, p
+ 8, ctx
->base
.header_size
- 4);
1788 i
+= ctx
->base
.header_size
;
1789 ctx
->excess_bytes
+=
1790 (le32_to_cpu(*(__le32
*)(p
+ 4)) >> 16) & 0xffff;
1791 p
+= ctx
->base
.header_size
+ 4;
1793 ctx
->header_length
= i
;
1795 ctx
->excess_bytes
-= le16_to_cpu(db
->second_req_count
) -
1796 le16_to_cpu(db
->second_res_count
);
1798 if (le16_to_cpu(db
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1799 ir_header
= (__le32
*) (db
+ 1);
1800 ctx
->base
.callback(&ctx
->base
,
1801 le32_to_cpu(ir_header
[0]) & 0xffff,
1802 ctx
->header_length
, ctx
->header
,
1803 ctx
->base
.callback_data
);
1804 ctx
->header_length
= 0;
1810 static int handle_ir_packet_per_buffer(struct context
*context
,
1811 struct descriptor
*d
,
1812 struct descriptor
*last
)
1814 struct iso_context
*ctx
=
1815 container_of(context
, struct iso_context
, context
);
1816 struct descriptor
*pd
;
1821 for (pd
= d
; pd
<= last
; pd
++) {
1822 if (pd
->transfer_status
)
1826 /* Descriptor(s) not done yet, stop iteration */
1829 i
= ctx
->header_length
;
1832 if (ctx
->base
.header_size
> 0 &&
1833 i
+ ctx
->base
.header_size
<= PAGE_SIZE
) {
1835 * The iso header is byteswapped to little endian by
1836 * the controller, but the remaining header quadlets
1837 * are big endian. We want to present all the headers
1838 * as big endian, so we have to swap the first quadlet.
1840 *(u32
*) (ctx
->header
+ i
) = __swab32(*(u32
*) (p
+ 4));
1841 memcpy(ctx
->header
+ i
+ 4, p
+ 8, ctx
->base
.header_size
- 4);
1842 ctx
->header_length
+= ctx
->base
.header_size
;
1845 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1846 ir_header
= (__le32
*) p
;
1847 ctx
->base
.callback(&ctx
->base
,
1848 le32_to_cpu(ir_header
[0]) & 0xffff,
1849 ctx
->header_length
, ctx
->header
,
1850 ctx
->base
.callback_data
);
1851 ctx
->header_length
= 0;
1857 static int handle_it_packet(struct context
*context
,
1858 struct descriptor
*d
,
1859 struct descriptor
*last
)
1861 struct iso_context
*ctx
=
1862 container_of(context
, struct iso_context
, context
);
1864 if (last
->transfer_status
== 0)
1865 /* This descriptor isn't done yet, stop iteration. */
1868 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
)
1869 ctx
->base
.callback(&ctx
->base
, le16_to_cpu(last
->res_count
),
1870 0, NULL
, ctx
->base
.callback_data
);
1875 static struct fw_iso_context
*
1876 ohci_allocate_iso_context(struct fw_card
*card
, int type
, size_t header_size
)
1878 struct fw_ohci
*ohci
= fw_ohci(card
);
1879 struct iso_context
*ctx
, *list
;
1880 descriptor_callback_t callback
;
1882 unsigned long flags
;
1883 int index
, retval
= -ENOMEM
;
1885 if (type
== FW_ISO_CONTEXT_TRANSMIT
) {
1886 mask
= &ohci
->it_context_mask
;
1887 list
= ohci
->it_context_list
;
1888 callback
= handle_it_packet
;
1890 mask
= &ohci
->ir_context_mask
;
1891 list
= ohci
->ir_context_list
;
1892 if (ohci
->use_dualbuffer
)
1893 callback
= handle_ir_dualbuffer_packet
;
1895 callback
= handle_ir_packet_per_buffer
;
1898 spin_lock_irqsave(&ohci
->lock
, flags
);
1899 index
= ffs(*mask
) - 1;
1901 *mask
&= ~(1 << index
);
1902 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1905 return ERR_PTR(-EBUSY
);
1907 if (type
== FW_ISO_CONTEXT_TRANSMIT
)
1908 regs
= OHCI1394_IsoXmitContextBase(index
);
1910 regs
= OHCI1394_IsoRcvContextBase(index
);
1913 memset(ctx
, 0, sizeof(*ctx
));
1914 ctx
->header_length
= 0;
1915 ctx
->header
= (void *) __get_free_page(GFP_KERNEL
);
1916 if (ctx
->header
== NULL
)
1919 retval
= context_init(&ctx
->context
, ohci
, regs
, callback
);
1921 goto out_with_header
;
1926 free_page((unsigned long)ctx
->header
);
1928 spin_lock_irqsave(&ohci
->lock
, flags
);
1929 *mask
|= 1 << index
;
1930 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1932 return ERR_PTR(retval
);
1935 static int ohci_start_iso(struct fw_iso_context
*base
,
1936 s32 cycle
, u32 sync
, u32 tags
)
1938 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1939 struct fw_ohci
*ohci
= ctx
->context
.ohci
;
1943 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1944 index
= ctx
- ohci
->it_context_list
;
1947 match
= IT_CONTEXT_CYCLE_MATCH_ENABLE
|
1948 (cycle
& 0x7fff) << 16;
1950 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, 1 << index
);
1951 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, 1 << index
);
1952 context_run(&ctx
->context
, match
);
1954 index
= ctx
- ohci
->ir_context_list
;
1955 control
= IR_CONTEXT_ISOCH_HEADER
;
1956 if (ohci
->use_dualbuffer
)
1957 control
|= IR_CONTEXT_DUAL_BUFFER_MODE
;
1958 match
= (tags
<< 28) | (sync
<< 8) | ctx
->base
.channel
;
1960 match
|= (cycle
& 0x07fff) << 12;
1961 control
|= IR_CONTEXT_CYCLE_MATCH_ENABLE
;
1964 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, 1 << index
);
1965 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, 1 << index
);
1966 reg_write(ohci
, CONTEXT_MATCH(ctx
->context
.regs
), match
);
1967 context_run(&ctx
->context
, control
);
1973 static int ohci_stop_iso(struct fw_iso_context
*base
)
1975 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
1976 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1979 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1980 index
= ctx
- ohci
->it_context_list
;
1981 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, 1 << index
);
1983 index
= ctx
- ohci
->ir_context_list
;
1984 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, 1 << index
);
1987 context_stop(&ctx
->context
);
1992 static void ohci_free_iso_context(struct fw_iso_context
*base
)
1994 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
1995 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1996 unsigned long flags
;
1999 ohci_stop_iso(base
);
2000 context_release(&ctx
->context
);
2001 free_page((unsigned long)ctx
->header
);
2003 spin_lock_irqsave(&ohci
->lock
, flags
);
2005 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
2006 index
= ctx
- ohci
->it_context_list
;
2007 ohci
->it_context_mask
|= 1 << index
;
2009 index
= ctx
- ohci
->ir_context_list
;
2010 ohci
->ir_context_mask
|= 1 << index
;
2013 spin_unlock_irqrestore(&ohci
->lock
, flags
);
2017 ohci_queue_iso_transmit(struct fw_iso_context
*base
,
2018 struct fw_iso_packet
*packet
,
2019 struct fw_iso_buffer
*buffer
,
2020 unsigned long payload
)
2022 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2023 struct descriptor
*d
, *last
, *pd
;
2024 struct fw_iso_packet
*p
;
2026 dma_addr_t d_bus
, page_bus
;
2027 u32 z
, header_z
, payload_z
, irq
;
2028 u32 payload_index
, payload_end_index
, next_page_index
;
2029 int page
, end_page
, i
, length
, offset
;
2032 * FIXME: Cycle lost behavior should be configurable: lose
2033 * packet, retransmit or terminate..
2037 payload_index
= payload
;
2043 if (p
->header_length
> 0)
2046 /* Determine the first page the payload isn't contained in. */
2047 end_page
= PAGE_ALIGN(payload_index
+ p
->payload_length
) >> PAGE_SHIFT
;
2048 if (p
->payload_length
> 0)
2049 payload_z
= end_page
- (payload_index
>> PAGE_SHIFT
);
2055 /* Get header size in number of descriptors. */
2056 header_z
= DIV_ROUND_UP(p
->header_length
, sizeof(*d
));
2058 d
= context_get_descriptors(&ctx
->context
, z
+ header_z
, &d_bus
);
2063 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
2064 d
[0].req_count
= cpu_to_le16(8);
2066 header
= (__le32
*) &d
[1];
2067 header
[0] = cpu_to_le32(IT_HEADER_SY(p
->sy
) |
2068 IT_HEADER_TAG(p
->tag
) |
2069 IT_HEADER_TCODE(TCODE_STREAM_DATA
) |
2070 IT_HEADER_CHANNEL(ctx
->base
.channel
) |
2071 IT_HEADER_SPEED(ctx
->base
.speed
));
2073 cpu_to_le32(IT_HEADER_DATA_LENGTH(p
->header_length
+
2074 p
->payload_length
));
2077 if (p
->header_length
> 0) {
2078 d
[2].req_count
= cpu_to_le16(p
->header_length
);
2079 d
[2].data_address
= cpu_to_le32(d_bus
+ z
* sizeof(*d
));
2080 memcpy(&d
[z
], p
->header
, p
->header_length
);
2083 pd
= d
+ z
- payload_z
;
2084 payload_end_index
= payload_index
+ p
->payload_length
;
2085 for (i
= 0; i
< payload_z
; i
++) {
2086 page
= payload_index
>> PAGE_SHIFT
;
2087 offset
= payload_index
& ~PAGE_MASK
;
2088 next_page_index
= (page
+ 1) << PAGE_SHIFT
;
2090 min(next_page_index
, payload_end_index
) - payload_index
;
2091 pd
[i
].req_count
= cpu_to_le16(length
);
2093 page_bus
= page_private(buffer
->pages
[page
]);
2094 pd
[i
].data_address
= cpu_to_le32(page_bus
+ offset
);
2096 payload_index
+= length
;
2100 irq
= DESCRIPTOR_IRQ_ALWAYS
;
2102 irq
= DESCRIPTOR_NO_IRQ
;
2104 last
= z
== 2 ? d
: d
+ z
- 1;
2105 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
2107 DESCRIPTOR_BRANCH_ALWAYS
|
2110 context_append(&ctx
->context
, d
, z
, header_z
);
2116 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context
*base
,
2117 struct fw_iso_packet
*packet
,
2118 struct fw_iso_buffer
*buffer
,
2119 unsigned long payload
)
2121 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2122 struct db_descriptor
*db
= NULL
;
2123 struct descriptor
*d
;
2124 struct fw_iso_packet
*p
;
2125 dma_addr_t d_bus
, page_bus
;
2126 u32 z
, header_z
, length
, rest
;
2127 int page
, offset
, packet_count
, header_size
;
2130 * FIXME: Cycle lost behavior should be configurable: lose
2131 * packet, retransmit or terminate..
2138 * The OHCI controller puts the status word in the header
2139 * buffer too, so we need 4 extra bytes per packet.
2141 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
2142 header_size
= packet_count
* (ctx
->base
.header_size
+ 4);
2144 /* Get header size in number of descriptors. */
2145 header_z
= DIV_ROUND_UP(header_size
, sizeof(*d
));
2146 page
= payload
>> PAGE_SHIFT
;
2147 offset
= payload
& ~PAGE_MASK
;
2148 rest
= p
->payload_length
;
2150 /* FIXME: make packet-per-buffer/dual-buffer a context option */
2152 d
= context_get_descriptors(&ctx
->context
,
2153 z
+ header_z
, &d_bus
);
2157 db
= (struct db_descriptor
*) d
;
2158 db
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2159 DESCRIPTOR_BRANCH_ALWAYS
);
2160 db
->first_size
= cpu_to_le16(ctx
->base
.header_size
+ 4);
2161 if (p
->skip
&& rest
== p
->payload_length
) {
2162 db
->control
|= cpu_to_le16(DESCRIPTOR_WAIT
);
2163 db
->first_req_count
= db
->first_size
;
2165 db
->first_req_count
= cpu_to_le16(header_size
);
2167 db
->first_res_count
= db
->first_req_count
;
2168 db
->first_buffer
= cpu_to_le32(d_bus
+ sizeof(*db
));
2170 if (p
->skip
&& rest
== p
->payload_length
)
2172 else if (offset
+ rest
< PAGE_SIZE
)
2175 length
= PAGE_SIZE
- offset
;
2177 db
->second_req_count
= cpu_to_le16(length
);
2178 db
->second_res_count
= db
->second_req_count
;
2179 page_bus
= page_private(buffer
->pages
[page
]);
2180 db
->second_buffer
= cpu_to_le32(page_bus
+ offset
);
2182 if (p
->interrupt
&& length
== rest
)
2183 db
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
2185 context_append(&ctx
->context
, d
, z
, header_z
);
2186 offset
= (offset
+ length
) & ~PAGE_MASK
;
2196 ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context
*base
,
2197 struct fw_iso_packet
*packet
,
2198 struct fw_iso_buffer
*buffer
,
2199 unsigned long payload
)
2201 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2202 struct descriptor
*d
= NULL
, *pd
= NULL
;
2203 struct fw_iso_packet
*p
= packet
;
2204 dma_addr_t d_bus
, page_bus
;
2205 u32 z
, header_z
, rest
;
2207 int page
, offset
, packet_count
, header_size
, payload_per_buffer
;
2210 * The OHCI controller puts the status word in the
2211 * buffer too, so we need 4 extra bytes per packet.
2213 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
2214 header_size
= ctx
->base
.header_size
+ 4;
2216 /* Get header size in number of descriptors. */
2217 header_z
= DIV_ROUND_UP(header_size
, sizeof(*d
));
2218 page
= payload
>> PAGE_SHIFT
;
2219 offset
= payload
& ~PAGE_MASK
;
2220 payload_per_buffer
= p
->payload_length
/ packet_count
;
2222 for (i
= 0; i
< packet_count
; i
++) {
2223 /* d points to the header descriptor */
2224 z
= DIV_ROUND_UP(payload_per_buffer
+ offset
, PAGE_SIZE
) + 1;
2225 d
= context_get_descriptors(&ctx
->context
,
2226 z
+ header_z
, &d_bus
);
2230 d
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2231 DESCRIPTOR_INPUT_MORE
);
2232 if (p
->skip
&& i
== 0)
2233 d
->control
|= cpu_to_le16(DESCRIPTOR_WAIT
);
2234 d
->req_count
= cpu_to_le16(header_size
);
2235 d
->res_count
= d
->req_count
;
2236 d
->transfer_status
= 0;
2237 d
->data_address
= cpu_to_le32(d_bus
+ (z
* sizeof(*d
)));
2239 rest
= payload_per_buffer
;
2240 for (j
= 1; j
< z
; j
++) {
2242 pd
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2243 DESCRIPTOR_INPUT_MORE
);
2245 if (offset
+ rest
< PAGE_SIZE
)
2248 length
= PAGE_SIZE
- offset
;
2249 pd
->req_count
= cpu_to_le16(length
);
2250 pd
->res_count
= pd
->req_count
;
2251 pd
->transfer_status
= 0;
2253 page_bus
= page_private(buffer
->pages
[page
]);
2254 pd
->data_address
= cpu_to_le32(page_bus
+ offset
);
2256 offset
= (offset
+ length
) & ~PAGE_MASK
;
2261 pd
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2262 DESCRIPTOR_INPUT_LAST
|
2263 DESCRIPTOR_BRANCH_ALWAYS
);
2264 if (p
->interrupt
&& i
== packet_count
- 1)
2265 pd
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
2267 context_append(&ctx
->context
, d
, z
, header_z
);
2274 ohci_queue_iso(struct fw_iso_context
*base
,
2275 struct fw_iso_packet
*packet
,
2276 struct fw_iso_buffer
*buffer
,
2277 unsigned long payload
)
2279 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2280 unsigned long flags
;
2283 spin_lock_irqsave(&ctx
->context
.ohci
->lock
, flags
);
2284 if (base
->type
== FW_ISO_CONTEXT_TRANSMIT
)
2285 retval
= ohci_queue_iso_transmit(base
, packet
, buffer
, payload
);
2286 else if (ctx
->context
.ohci
->use_dualbuffer
)
2287 retval
= ohci_queue_iso_receive_dualbuffer(base
, packet
,
2290 retval
= ohci_queue_iso_receive_packet_per_buffer(base
, packet
,
2293 spin_unlock_irqrestore(&ctx
->context
.ohci
->lock
, flags
);
2298 static const struct fw_card_driver ohci_driver
= {
2299 .enable
= ohci_enable
,
2300 .update_phy_reg
= ohci_update_phy_reg
,
2301 .set_config_rom
= ohci_set_config_rom
,
2302 .send_request
= ohci_send_request
,
2303 .send_response
= ohci_send_response
,
2304 .cancel_packet
= ohci_cancel_packet
,
2305 .enable_phys_dma
= ohci_enable_phys_dma
,
2306 .get_bus_time
= ohci_get_bus_time
,
2308 .allocate_iso_context
= ohci_allocate_iso_context
,
2309 .free_iso_context
= ohci_free_iso_context
,
2310 .queue_iso
= ohci_queue_iso
,
2311 .start_iso
= ohci_start_iso
,
2312 .stop_iso
= ohci_stop_iso
,
2315 #ifdef CONFIG_PPC_PMAC
2316 static void ohci_pmac_on(struct pci_dev
*dev
)
2318 if (machine_is(powermac
)) {
2319 struct device_node
*ofn
= pci_device_to_OF_node(dev
);
2322 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, ofn
, 0, 1);
2323 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 1);
2328 static void ohci_pmac_off(struct pci_dev
*dev
)
2330 if (machine_is(powermac
)) {
2331 struct device_node
*ofn
= pci_device_to_OF_node(dev
);
2334 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 0);
2335 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, ofn
, 0, 0);
2340 #define ohci_pmac_on(dev)
2341 #define ohci_pmac_off(dev)
2342 #endif /* CONFIG_PPC_PMAC */
2344 static int __devinit
2345 pci_probe(struct pci_dev
*dev
, const struct pci_device_id
*ent
)
2347 struct fw_ohci
*ohci
;
2348 u32 bus_options
, max_receive
, link_speed
, version
;
2353 ohci
= kzalloc(sizeof(*ohci
), GFP_KERNEL
);
2355 fw_error("Could not malloc fw_ohci data.\n");
2359 fw_card_initialize(&ohci
->card
, &ohci_driver
, &dev
->dev
);
2363 err
= pci_enable_device(dev
);
2365 fw_error("Failed to enable OHCI hardware.\n");
2369 pci_set_master(dev
);
2370 pci_write_config_dword(dev
, OHCI1394_PCI_HCI_Control
, 0);
2371 pci_set_drvdata(dev
, ohci
);
2373 spin_lock_init(&ohci
->lock
);
2375 tasklet_init(&ohci
->bus_reset_tasklet
,
2376 bus_reset_tasklet
, (unsigned long)ohci
);
2378 err
= pci_request_region(dev
, 0, ohci_driver_name
);
2380 fw_error("MMIO resource unavailable\n");
2384 ohci
->registers
= pci_iomap(dev
, 0, OHCI1394_REGISTER_SIZE
);
2385 if (ohci
->registers
== NULL
) {
2386 fw_error("Failed to remap registers\n");
2391 version
= reg_read(ohci
, OHCI1394_Version
) & 0x00ff00ff;
2392 ohci
->use_dualbuffer
= version
>= OHCI_VERSION_1_1
;
2394 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2395 #if !defined(CONFIG_X86_32)
2396 /* dual-buffer mode is broken with descriptor addresses above 2G */
2397 if (dev
->vendor
== PCI_VENDOR_ID_TI
&&
2398 dev
->device
== PCI_DEVICE_ID_TI_TSB43AB22
)
2399 ohci
->use_dualbuffer
= false;
2402 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2403 ohci
->old_uninorth
= dev
->vendor
== PCI_VENDOR_ID_APPLE
&&
2404 dev
->device
== PCI_DEVICE_ID_APPLE_UNI_N_FW
;
2406 ohci
->bus_reset_packet_quirk
= dev
->vendor
== PCI_VENDOR_ID_TI
;
2408 ar_context_init(&ohci
->ar_request_ctx
, ohci
,
2409 OHCI1394_AsReqRcvContextControlSet
);
2411 ar_context_init(&ohci
->ar_response_ctx
, ohci
,
2412 OHCI1394_AsRspRcvContextControlSet
);
2414 context_init(&ohci
->at_request_ctx
, ohci
,
2415 OHCI1394_AsReqTrContextControlSet
, handle_at_packet
);
2417 context_init(&ohci
->at_response_ctx
, ohci
,
2418 OHCI1394_AsRspTrContextControlSet
, handle_at_packet
);
2420 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, ~0);
2421 ohci
->it_context_mask
= reg_read(ohci
, OHCI1394_IsoRecvIntMaskSet
);
2422 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, ~0);
2423 size
= sizeof(struct iso_context
) * hweight32(ohci
->it_context_mask
);
2424 ohci
->it_context_list
= kzalloc(size
, GFP_KERNEL
);
2426 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, ~0);
2427 ohci
->ir_context_mask
= reg_read(ohci
, OHCI1394_IsoXmitIntMaskSet
);
2428 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, ~0);
2429 size
= sizeof(struct iso_context
) * hweight32(ohci
->ir_context_mask
);
2430 ohci
->ir_context_list
= kzalloc(size
, GFP_KERNEL
);
2432 if (ohci
->it_context_list
== NULL
|| ohci
->ir_context_list
== NULL
) {
2433 fw_error("Out of memory for it/ir contexts.\n");
2435 goto fail_registers
;
2438 /* self-id dma buffer allocation */
2439 ohci
->self_id_cpu
= dma_alloc_coherent(ohci
->card
.device
,
2443 if (ohci
->self_id_cpu
== NULL
) {
2444 fw_error("Out of memory for self ID buffer.\n");
2446 goto fail_registers
;
2449 bus_options
= reg_read(ohci
, OHCI1394_BusOptions
);
2450 max_receive
= (bus_options
>> 12) & 0xf;
2451 link_speed
= bus_options
& 0x7;
2452 guid
= ((u64
) reg_read(ohci
, OHCI1394_GUIDHi
) << 32) |
2453 reg_read(ohci
, OHCI1394_GUIDLo
);
2455 err
= fw_card_add(&ohci
->card
, max_receive
, link_speed
, guid
);
2459 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2460 dev
->dev
.bus_id
, version
>> 16, version
& 0xff);
2464 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
2465 ohci
->self_id_cpu
, ohci
->self_id_bus
);
2467 kfree(ohci
->it_context_list
);
2468 kfree(ohci
->ir_context_list
);
2469 pci_iounmap(dev
, ohci
->registers
);
2471 pci_release_region(dev
, 0);
2473 pci_disable_device(dev
);
2481 static void pci_remove(struct pci_dev
*dev
)
2483 struct fw_ohci
*ohci
;
2485 ohci
= pci_get_drvdata(dev
);
2486 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
2488 fw_core_remove_card(&ohci
->card
);
2491 * FIXME: Fail all pending packets here, now that the upper
2492 * layers can't queue any more.
2495 software_reset(ohci
);
2496 free_irq(dev
->irq
, ohci
);
2497 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
2498 ohci
->self_id_cpu
, ohci
->self_id_bus
);
2499 kfree(ohci
->it_context_list
);
2500 kfree(ohci
->ir_context_list
);
2501 pci_iounmap(dev
, ohci
->registers
);
2502 pci_release_region(dev
, 0);
2503 pci_disable_device(dev
);
2507 fw_notify("Removed fw-ohci device.\n");
2511 static int pci_suspend(struct pci_dev
*dev
, pm_message_t state
)
2513 struct fw_ohci
*ohci
= pci_get_drvdata(dev
);
2516 software_reset(ohci
);
2517 free_irq(dev
->irq
, ohci
);
2518 err
= pci_save_state(dev
);
2520 fw_error("pci_save_state failed\n");
2523 err
= pci_set_power_state(dev
, pci_choose_state(dev
, state
));
2525 fw_error("pci_set_power_state failed with %d\n", err
);
2531 static int pci_resume(struct pci_dev
*dev
)
2533 struct fw_ohci
*ohci
= pci_get_drvdata(dev
);
2537 pci_set_power_state(dev
, PCI_D0
);
2538 pci_restore_state(dev
);
2539 err
= pci_enable_device(dev
);
2541 fw_error("pci_enable_device failed\n");
2545 return ohci_enable(&ohci
->card
, NULL
, 0);
2549 static struct pci_device_id pci_table
[] = {
2550 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI
, ~0) },
2554 MODULE_DEVICE_TABLE(pci
, pci_table
);
2556 static struct pci_driver fw_ohci_pci_driver
= {
2557 .name
= ohci_driver_name
,
2558 .id_table
= pci_table
,
2560 .remove
= pci_remove
,
2562 .resume
= pci_resume
,
2563 .suspend
= pci_suspend
,
2567 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2568 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2569 MODULE_LICENSE("GPL");
2571 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2572 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2573 MODULE_ALIAS("ohci1394");
2576 static int __init
fw_ohci_init(void)
2578 return pci_register_driver(&fw_ohci_pci_driver
);
2581 static void __exit
fw_ohci_cleanup(void)
2583 pci_unregister_driver(&fw_ohci_pci_driver
);
2586 module_init(fw_ohci_init
);
2587 module_exit(fw_ohci_cleanup
);