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Revert "staging: tidspbridge - rename bridge_brd_mem_map/unmap to a proper name"
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / tidspbridge / core / tiomap3430.c
blob7ab272ca643d79beee0ba57c895a0cd7fc077165
1 /*
2 * tiomap.c
3 *
4 * DSP-BIOS Bridge driver support functions for TI OMAP processors.
5 *
6 * Processor Manager Driver for TI OMAP3430 EVM.
7 *
8 * Copyright (C) 2005-2006 Texas Instruments, Inc.
9 *
10 * This package is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
17 */
18
19 #include <plat/dsp.h>
20
21 #include <linux/types.h>
22 /* ----------------------------------- Host OS */
23 #include <dspbridge/host_os.h>
24 #include <linux/mm.h>
25 #include <linux/mmzone.h>
26
27 /* ----------------------------------- DSP/BIOS Bridge */
28 #include <dspbridge/dbdefs.h>
29
30 /* ----------------------------------- Trace & Debug */
31 #include <dspbridge/dbc.h>
32
33 /* ----------------------------------- OS Adaptation Layer */
34 #include <dspbridge/drv.h>
35 #include <dspbridge/sync.h>
36
37 /* ------------------------------------ Hardware Abstraction Layer */
38 #include <hw_defs.h>
39 #include <hw_mmu.h>
40
41 /* ----------------------------------- Link Driver */
42 #include <dspbridge/dspdefs.h>
43 #include <dspbridge/dspchnl.h>
44 #include <dspbridge/dspdeh.h>
45 #include <dspbridge/dspio.h>
46 #include <dspbridge/dspmsg.h>
47 #include <dspbridge/pwr.h>
48 #include <dspbridge/io_sm.h>
49
50 /* ----------------------------------- Platform Manager */
51 #include <dspbridge/dev.h>
52 #include <dspbridge/dspapi.h>
53 #include <dspbridge/dmm.h>
54 #include <dspbridge/wdt.h>
55
56 /* ----------------------------------- Local */
57 #include "_tiomap.h"
58 #include "_tiomap_pwr.h"
59 #include "tiomap_io.h"
60
61 /* Offset in shared mem to write to in order to synchronize start with DSP */
62 #define SHMSYNCOFFSET 4 /* GPP byte offset */
63
64 #define BUFFERSIZE 1024
65
66 #define TIHELEN_ACKTIMEOUT 10000
67
68 #define MMU_SECTION_ADDR_MASK 0xFFF00000
69 #define MMU_SSECTION_ADDR_MASK 0xFF000000
70 #define MMU_LARGE_PAGE_MASK 0xFFFF0000
71 #define MMU_SMALL_PAGE_MASK 0xFFFFF000
72 #define OMAP3_IVA2_BOOTADDR_MASK 0xFFFFFC00
73 #define PAGES_II_LVL_TABLE 512
74 #define PHYS_TO_PAGE(phys) pfn_to_page((phys) >> PAGE_SHIFT)
75
76 /*
77 * This is a totally ugly layer violation, but needed until
78 * omap_ctrl_set_dsp_boot*() are provided.
79 */
80 #define OMAP3_IVA2_BOOTMOD_IDLE 1
81 #define OMAP2_CONTROL_GENERAL 0x270
82 #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
83 #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
84
85 #define OMAP343X_CTRL_REGADDR(reg) \
86 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
87
88
89 /* Forward Declarations: */
90 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt);
91 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
92 u8 *host_buff,
93 u32 dsp_addr, u32 ul_num_bytes,
94 u32 mem_type);
95 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
96 u32 dsp_addr);
97 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
98 int *board_state);
99 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt);
100 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
101 u8 *host_buff,
102 u32 dsp_addr, u32 ul_num_bytes,
103 u32 mem_type);
104 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
105 u32 brd_state);
106 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
107 u32 dsp_dest_addr, u32 dsp_src_addr,
108 u32 ul_num_bytes, u32 mem_type);
109 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
110 u8 *host_buff, u32 dsp_addr,
111 u32 ul_num_bytes, u32 mem_type);
112 static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt,
113 u32 ul_mpu_addr, u32 virt_addr,
114 u32 ul_num_bytes, u32 ul_map_attr,
115 struct page **mapped_pages);
116 static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
117 u32 da);
118 static int bridge_dev_create(struct bridge_dev_context
119 **dev_cntxt,
120 struct dev_object *hdev_obj,
121 struct cfg_hostres *config_param);
122 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
123 u32 dw_cmd, void *pargs);
124 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt);
125 static int get_io_pages(struct mm_struct *mm, u32 uva, unsigned pages,
126 struct page **usr_pgs);
127 static u32 user_va2_pa(struct mm_struct *mm, u32 address);
128 static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
129 u32 va, u32 size,
130 struct hw_mmu_map_attrs_t *map_attrs);
131 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
132 u32 size, struct hw_mmu_map_attrs_t *attrs);
133 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
134 u32 ul_mpu_addr, u32 virt_addr,
135 u32 ul_num_bytes,
136 struct hw_mmu_map_attrs_t *hw_attrs);
137
138 bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr);
139
140 /* ----------------------------------- Globals */
141
142 /* Attributes of L2 page tables for DSP MMU */
143 struct page_info {
144 u32 num_entries; /* Number of valid PTEs in the L2 PT */
145 };
146
147 /* Attributes used to manage the DSP MMU page tables */
148 struct pg_table_attrs {
149 spinlock_t pg_lock; /* Critical section object handle */
150
151 u32 l1_base_pa; /* Physical address of the L1 PT */
152 u32 l1_base_va; /* Virtual address of the L1 PT */
153 u32 l1_size; /* Size of the L1 PT */
154 u32 l1_tbl_alloc_pa;
155 /* Physical address of Allocated mem for L1 table. May not be aligned */
156 u32 l1_tbl_alloc_va;
157 /* Virtual address of Allocated mem for L1 table. May not be aligned */
158 u32 l1_tbl_alloc_sz;
159 /* Size of consistent memory allocated for L1 table.
160 * May not be aligned */
161
162 u32 l2_base_pa; /* Physical address of the L2 PT */
163 u32 l2_base_va; /* Virtual address of the L2 PT */
164 u32 l2_size; /* Size of the L2 PT */
165 u32 l2_tbl_alloc_pa;
166 /* Physical address of Allocated mem for L2 table. May not be aligned */
167 u32 l2_tbl_alloc_va;
168 /* Virtual address of Allocated mem for L2 table. May not be aligned */
169 u32 l2_tbl_alloc_sz;
170 /* Size of consistent memory allocated for L2 table.
171 * May not be aligned */
172
173 u32 l2_num_pages; /* Number of allocated L2 PT */
174 /* Array [l2_num_pages] of L2 PT info structs */
175 struct page_info *pg_info;
176 };
177
178 /*
179 * This Bridge driver's function interface table.
180 */
181 static struct bridge_drv_interface drv_interface_fxns = {
182 /* Bridge API ver. for which this bridge driver is built. */
183 BRD_API_MAJOR_VERSION,
184 BRD_API_MINOR_VERSION,
185 bridge_dev_create,
186 bridge_dev_destroy,
187 bridge_dev_ctrl,
188 bridge_brd_monitor,
189 bridge_brd_start,
190 bridge_brd_stop,
191 bridge_brd_status,
192 bridge_brd_read,
193 bridge_brd_write,
194 bridge_brd_set_state,
195 bridge_brd_mem_copy,
196 bridge_brd_mem_write,
197 bridge_brd_mem_map,
198 bridge_brd_mem_un_map,
199 /* The following CHNL functions are provided by chnl_io.lib: */
200 bridge_chnl_create,
201 bridge_chnl_destroy,
202 bridge_chnl_open,
203 bridge_chnl_close,
204 bridge_chnl_add_io_req,
205 bridge_chnl_get_ioc,
206 bridge_chnl_cancel_io,
207 bridge_chnl_flush_io,
208 bridge_chnl_get_info,
209 bridge_chnl_get_mgr_info,
210 bridge_chnl_idle,
211 bridge_chnl_register_notify,
212 /* The following IO functions are provided by chnl_io.lib: */
213 bridge_io_create,
214 bridge_io_destroy,
215 bridge_io_on_loaded,
216 bridge_io_get_proc_load,
217 /* The following msg_ctrl functions are provided by chnl_io.lib: */
218 bridge_msg_create,
219 bridge_msg_create_queue,
220 bridge_msg_delete,
221 bridge_msg_delete_queue,
222 bridge_msg_get,
223 bridge_msg_put,
224 bridge_msg_register_notify,
225 bridge_msg_set_queue_id,
226 };
227
228 static inline void flush_all(struct bridge_dev_context *dev_context)
229 {
230 if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION ||
231 dev_context->dw_brd_state == BRD_HIBERNATION)
232 wake_dsp(dev_context, NULL);
233
234 hw_mmu_tlb_flush_all(dev_context->dw_dsp_mmu_base);
235 }
236
237 static void bad_page_dump(u32 pa, struct page *pg)
238 {
239 pr_emerg("DSPBRIDGE: MAP function: COUNT 0 FOR PA 0x%x\n", pa);
240 pr_emerg("Bad page state in process '%s'\n"
241 "page:%p flags:0x%0*lx mapping:%p mapcount:%d count:%d\n"
242 "Backtrace:\n",
243 current->comm, pg, (int)(2 * sizeof(unsigned long)),
244 (unsigned long)pg->flags, pg->mapping,
245 page_mapcount(pg), page_count(pg));
246 dump_stack();
247 }
248
249 /*
250 * ======== bridge_drv_entry ========
251 * purpose:
252 * Bridge Driver entry point.
253 */
254 void bridge_drv_entry(struct bridge_drv_interface **drv_intf,
255 const char *driver_file_name)
256 {
257
258 DBC_REQUIRE(driver_file_name != NULL);
259
260 io_sm_init(); /* Initialization of io_sm module */
261
262 if (strcmp(driver_file_name, "UMA") == 0)
263 *drv_intf = &drv_interface_fxns;
264 else
265 dev_dbg(bridge, "%s Unknown Bridge file name", __func__);
266
267 }
268
269 /*
270 * ======== bridge_brd_monitor ========
271 * purpose:
272 * This bridge_brd_monitor puts DSP into a Loadable state.
273 * i.e Application can load and start the device.
274 *
275 * Preconditions:
276 * Device in 'OFF' state.
277 */
278 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt)
279 {
280 struct bridge_dev_context *dev_context = dev_ctxt;
281 u32 temp;
282 struct omap_dsp_platform_data *pdata =
283 omap_dspbridge_dev->dev.platform_data;
284
285 temp = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
286 OMAP_POWERSTATEST_MASK;
287 if (!(temp & 0x02)) {
288 /* IVA2 is not in ON state */
289 /* Read and set PM_PWSTCTRL_IVA2 to ON */
290 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
291 PWRDM_POWER_ON, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
292 /* Set the SW supervised state transition */
293 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP,
294 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
295
296 /* Wait until the state has moved to ON */
297 while ((*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
298 OMAP_INTRANSITION_MASK)
299 ;
300 /* Disable Automatic transition */
301 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_DISABLE_AUTO,
302 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
303 }
304
305 dsp_clk_enable(DSP_CLK_IVA2);
306
307 /* set the device state to IDLE */
308 dev_context->dw_brd_state = BRD_IDLE;
309
310 return 0;
311 }
312
313 /*
314 * ======== bridge_brd_read ========
315 * purpose:
316 * Reads buffers for DSP memory.
317 */
318 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
319 u8 *host_buff, u32 dsp_addr,
320 u32 ul_num_bytes, u32 mem_type)
321 {
322 int status = 0;
323 struct bridge_dev_context *dev_context = dev_ctxt;
324 u32 offset;
325 u32 dsp_base_addr = dev_ctxt->dw_dsp_base_addr;
326
327 if (dsp_addr < dev_context->dw_dsp_start_add) {
328 status = -EPERM;
329 return status;
330 }
331 /* change here to account for the 3 bands of the DSP internal memory */
332 if ((dsp_addr - dev_context->dw_dsp_start_add) <
333 dev_context->dw_internal_size) {
334 offset = dsp_addr - dev_context->dw_dsp_start_add;
335 } else {
336 status = read_ext_dsp_data(dev_context, host_buff, dsp_addr,
337 ul_num_bytes, mem_type);
338 return status;
339 }
340 /* copy the data from DSP memory, */
341 memcpy(host_buff, (void *)(dsp_base_addr + offset), ul_num_bytes);
342 return status;
343 }
344
345 /*
346 * ======== bridge_brd_set_state ========
347 * purpose:
348 * This routine updates the Board status.
349 */
350 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
351 u32 brd_state)
352 {
353 int status = 0;
354 struct bridge_dev_context *dev_context = dev_ctxt;
355
356 dev_context->dw_brd_state = brd_state;
357 return status;
358 }
359
360 /*
361 * ======== bridge_brd_start ========
362 * purpose:
363 * Initializes DSP MMU and Starts DSP.
364 *
365 * Preconditions:
366 * a) DSP domain is 'ACTIVE'.
367 * b) DSP_RST1 is asserted.
368 * b) DSP_RST2 is released.
369 */
370 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
371 u32 dsp_addr)
372 {
373 int status = 0;
374 struct bridge_dev_context *dev_context = dev_ctxt;
375 struct iommu *mmu = NULL;
376 struct shm_segs *sm_sg;
377 int l4_i = 0, tlb_i = 0;
378 u32 sg0_da = 0, sg1_da = 0;
379 struct bridge_ioctl_extproc *tlb = dev_context->atlb_entry;
380 u32 dw_sync_addr = 0;
381 u32 ul_shm_base; /* Gpp Phys SM base addr(byte) */
382 u32 ul_shm_base_virt; /* Dsp Virt SM base addr */
383 u32 ul_tlb_base_virt; /* Base of MMU TLB entry */
384 /* Offset of shm_base_virt from tlb_base_virt */
385 u32 ul_shm_offset_virt;
386 struct cfg_hostres *resources = NULL;
387 u32 temp;
388 u32 ul_dsp_clk_rate;
389 u32 ul_dsp_clk_addr;
390 u32 ul_bios_gp_timer;
391 u32 clk_cmd;
392 struct io_mgr *hio_mgr;
393 u32 ul_load_monitor_timer;
394 struct omap_dsp_platform_data *pdata =
395 omap_dspbridge_dev->dev.platform_data;
396
397 /* The device context contains all the mmu setup info from when the
398 * last dsp base image was loaded. The first entry is always
399 * SHMMEM base. */
400 /* Get SHM_BEG - convert to byte address */
401 (void)dev_get_symbol(dev_context->hdev_obj, SHMBASENAME,
402 &ul_shm_base_virt);
403 ul_shm_base_virt *= DSPWORDSIZE;
404 DBC_ASSERT(ul_shm_base_virt != 0);
405 /* DSP Virtual address */
406 ul_tlb_base_virt = dev_context->sh_s.seg0_da;
407 DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt);
408 ul_shm_offset_virt =
409 ul_shm_base_virt - (ul_tlb_base_virt * DSPWORDSIZE);
410 /* Kernel logical address */
411 ul_shm_base = dev_context->sh_s.seg0_va + ul_shm_offset_virt;
412
413 DBC_ASSERT(ul_shm_base != 0);
414 /* 2nd wd is used as sync field */
415 dw_sync_addr = ul_shm_base + SHMSYNCOFFSET;
416 /* Write a signature into the shm base + offset; this will
417 * get cleared when the DSP program starts. */
418 if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) {
419 pr_err("%s: Illegal SM base\n", __func__);
420 status = -EPERM;
421 } else
422 __raw_writel(0xffffffff, dw_sync_addr);
423
424 if (!status) {
425 resources = dev_context->resources;
426 if (!resources)
427 status = -EPERM;
428
429 /* Assert RST1 i.e only the RST only for DSP megacell */
430 if (!status) {
431 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
432 OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
433 OMAP2_RM_RSTCTRL);
434 /* Mask address with 1K for compatibility */
435 __raw_writel(dsp_addr & OMAP3_IVA2_BOOTADDR_MASK,
436 OMAP343X_CTRL_REGADDR(
437 OMAP343X_CONTROL_IVA2_BOOTADDR));
438 /*
439 * Set bootmode to self loop if dsp_debug flag is true
440 */
441 __raw_writel((dsp_debug) ? OMAP3_IVA2_BOOTMOD_IDLE : 0,
442 OMAP343X_CTRL_REGADDR(
443 OMAP343X_CONTROL_IVA2_BOOTMOD));
444 }
445 }
446
447 if (!status) {
448 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
449 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
450 mmu = dev_context->dsp_mmu;
451 if (mmu)
452 iommu_put(mmu);
453 mmu = iommu_get("iva2");
454 if (IS_ERR(mmu)) {
455 dev_err(bridge, "iommu_get failed!\n");
456 dev_context->dsp_mmu = NULL;
457 status = (int)mmu;
458 }
459 }
460 if (!status) {
461 dev_context->dsp_mmu = mmu;
462 sm_sg = &dev_context->sh_s;
463 sg0_da = iommu_kmap(mmu, sm_sg->seg0_da, sm_sg->seg0_pa,
464 sm_sg->seg0_size, IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_32);
465 if (IS_ERR_VALUE(sg0_da)) {
466 status = (int)sg0_da;
467 sg0_da = 0;
468 }
469 }
470 if (!status) {
471 sg1_da = iommu_kmap(mmu, sm_sg->seg1_da, sm_sg->seg1_pa,
472 sm_sg->seg1_size, IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_32);
473 if (IS_ERR_VALUE(sg1_da)) {
474 status = (int)sg1_da;
475 sg1_da = 0;
476 }
477 }
478 if (!status) {
479 u32 da;
480 for (tlb_i = 0; tlb_i < BRDIOCTL_NUMOFMMUTLB; tlb_i++) {
481 if (!tlb[tlb_i].ul_gpp_pa)
482 continue;
483
484 dev_dbg(bridge, "IOMMU %d GppPa: 0x%x DspVa 0x%x Size"
485 " 0x%x\n", tlb_i, tlb[tlb_i].ul_gpp_pa,
486 tlb[tlb_i].ul_dsp_va, tlb[tlb_i].ul_size);
487
488 da = iommu_kmap(mmu, tlb[tlb_i].ul_dsp_va,
489 tlb[tlb_i].ul_gpp_pa, PAGE_SIZE,
490 IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_32);
491 if (IS_ERR_VALUE(da)) {
492 status = (int)da;
493 break;
494 }
495 }
496 }
497 if (!status) {
498 u32 da;
499 l4_i = 0;
500 while (l4_peripheral_table[l4_i].phys_addr) {
501 da = iommu_kmap(mmu, l4_peripheral_table[l4_i].
502 dsp_virt_addr, l4_peripheral_table[l4_i].
503 phys_addr, PAGE_SIZE,
504 IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_32);
505 if (IS_ERR_VALUE(da)) {
506 status = (int)da;
507 break;
508 }
509 l4_i++;
510 }
511 }
512
513 /* Lock the above TLB entries and get the BIOS and load monitor timer
514 * information */
515 if (!status) {
516 /* Enable the BIOS clock */
517 (void)dev_get_symbol(dev_context->hdev_obj,
518 BRIDGEINIT_BIOSGPTIMER, &ul_bios_gp_timer);
519 (void)dev_get_symbol(dev_context->hdev_obj,
520 BRIDGEINIT_LOADMON_GPTIMER,
521 &ul_load_monitor_timer);
522
523 if (ul_load_monitor_timer != 0xFFFF) {
524 clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
525 ul_load_monitor_timer;
526 dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
527 } else {
528 dev_dbg(bridge, "Not able to get the symbol for Load "
529 "Monitor Timer\n");
530 }
531
532 if (ul_bios_gp_timer != 0xFFFF) {
533 clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
534 ul_bios_gp_timer;
535 dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
536 } else {
537 dev_dbg(bridge,
538 "Not able to get the symbol for BIOS Timer\n");
539 }
540
541 /* Set the DSP clock rate */
542 (void)dev_get_symbol(dev_context->hdev_obj,
543 "_BRIDGEINIT_DSP_FREQ", &ul_dsp_clk_addr);
544 /*Set Autoidle Mode for IVA2 PLL */
545 (*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
546 OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
547
548 if ((unsigned int *)ul_dsp_clk_addr != NULL) {
549 /* Get the clock rate */
550 ul_dsp_clk_rate = dsp_clk_get_iva2_rate();
551 dev_dbg(bridge, "%s: DSP clock rate (KHZ): 0x%x \n",
552 __func__, ul_dsp_clk_rate);
553 (void)bridge_brd_write(dev_context,
554 (u8 *) &ul_dsp_clk_rate,
555 ul_dsp_clk_addr, sizeof(u32), 0);
556 }
557 /*
558 * Enable Mailbox events and also drain any pending
559 * stale messages.
560 */
561 dev_context->mbox = omap_mbox_get("dsp");
562 if (IS_ERR(dev_context->mbox)) {
563 dev_context->mbox = NULL;
564 pr_err("%s: Failed to get dsp mailbox handle\n",
565 __func__);
566 status = -EPERM;
567 }
568
569 }
570 if (!status) {
571 dev_context->mbox->rxq->callback = (int (*)(void *))io_mbox_msg;
572
573 /*PM_IVA2GRPSEL_PER = 0xC0;*/
574 temp = readl(resources->dw_per_pm_base + 0xA8);
575 temp = (temp & 0xFFFFFF30) | 0xC0;
576 writel(temp, resources->dw_per_pm_base + 0xA8);
577
578 /*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */
579 temp = readl(resources->dw_per_pm_base + 0xA4);
580 temp = (temp & 0xFFFFFF3F);
581 writel(temp, resources->dw_per_pm_base + 0xA4);
582 /*CM_SLEEPDEP_PER |= 0x04; */
583 temp = readl(resources->dw_per_base + 0x44);
584 temp = (temp & 0xFFFFFFFB) | 0x04;
585 writel(temp, resources->dw_per_base + 0x44);
586
587 /*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */
588 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO,
589 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
590
591 /* Let DSP go */
592 dev_dbg(bridge, "%s Unreset\n", __func__);
593 /* release the RST1, DSP starts executing now .. */
594 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0,
595 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
596
597 dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", dw_sync_addr);
598 dev_dbg(bridge, "DSP c_int00 Address = 0x%x\n", dsp_addr);
599 if (dsp_debug)
600 while (__raw_readw(dw_sync_addr))
601 ;;
602
603 /* Wait for DSP to clear word in shared memory */
604 /* Read the Location */
605 if (!wait_for_start(dev_context, dw_sync_addr))
606 status = -ETIMEDOUT;
607
608 /* Start wdt */
609 dsp_wdt_sm_set((void *)ul_shm_base);
610 dsp_wdt_enable(true);
611
612 status = dev_get_io_mgr(dev_context->hdev_obj, &hio_mgr);
613 if (hio_mgr) {
614 io_sh_msetting(hio_mgr, SHM_OPPINFO, NULL);
615 /* Write the synchronization bit to indicate the
616 * completion of OPP table update to DSP
617 */
618 __raw_writel(0XCAFECAFE, dw_sync_addr);
619
620 /* update board state */
621 dev_context->dw_brd_state = BRD_RUNNING;
622 return 0;
623 } else {
624 dev_context->dw_brd_state = BRD_UNKNOWN;
625 }
626 }
627
628 while (tlb_i--) {
629 if (!tlb[tlb_i].ul_gpp_pa)
630 continue;
631 iommu_kunmap(mmu, tlb[tlb_i].ul_gpp_va);
632 }
633 while (l4_i--)
634 iommu_kunmap(mmu, l4_peripheral_table[l4_i].dsp_virt_addr);
635 if (sg0_da)
636 iommu_kunmap(mmu, sg0_da);
637 if (sg1_da)
638 iommu_kunmap(mmu, sg1_da);
639 return status;
640 }
641
642 /*
643 * ======== bridge_brd_stop ========
644 * purpose:
645 * Puts DSP in self loop.
646 *
647 * Preconditions :
648 * a) None
649 */
650 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
651 {
652 int status = 0;
653 struct bridge_dev_context *dev_context = dev_ctxt;
654 struct pg_table_attrs *pt_attrs;
655 u32 dsp_pwr_state;
656 int i;
657 struct bridge_ioctl_extproc *tlb = dev_context->atlb_entry;
658 struct omap_dsp_platform_data *pdata =
659 omap_dspbridge_dev->dev.platform_data;
660
661 if (dev_context->dw_brd_state == BRD_STOPPED)
662 return status;
663
664 /* as per TRM, it is advised to first drive the IVA2 to 'Standby' mode,
665 * before turning off the clocks.. This is to ensure that there are no
666 * pending L3 or other transactons from IVA2 */
667 dsp_pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
668 OMAP_POWERSTATEST_MASK;
669 if (dsp_pwr_state != PWRDM_POWER_OFF) {
670 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
671 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
672 sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE);
673 mdelay(10);
674
675 /* IVA2 is not in OFF state */
676 /* Set PM_PWSTCTRL_IVA2 to OFF */
677 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
678 PWRDM_POWER_OFF, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
679 /* Set the SW supervised state transition for Sleep */
680 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP,
681 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
682 }
683 udelay(10);
684 /* Release the Ext Base virtual Address as the next DSP Program
685 * may have a different load address */
686 if (dev_context->dw_dsp_ext_base_addr)
687 dev_context->dw_dsp_ext_base_addr = 0;
688
689 dev_context->dw_brd_state = BRD_STOPPED; /* update board state */
690
691 dsp_wdt_enable(false);
692
693 /* This is a good place to clear the MMU page tables as well */
694 if (dev_context->pt_attrs) {
695 pt_attrs = dev_context->pt_attrs;
696 memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size);
697 memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size);
698 memset((u8 *) pt_attrs->pg_info, 0x00,
699 (pt_attrs->l2_num_pages * sizeof(struct page_info)));
700 }
701 /* Reset DSP */
702 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
703 OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
704
705 /* Disable the mailbox interrupts */
706 if (dev_context->mbox) {
707 omap_mbox_disable_irq(dev_context->mbox, IRQ_RX);
708 omap_mbox_put(dev_context->mbox);
709 dev_context->mbox = NULL;
710 }
711 if (dev_context->dsp_mmu) {
712 pr_err("Proc stop mmu if statement\n");
713 for (i = 0; i < BRDIOCTL_NUMOFMMUTLB; i++) {
714 if (!tlb[i].ul_gpp_pa)
715 continue;
716 iommu_kunmap(dev_context->dsp_mmu, tlb[i].ul_gpp_va);
717 }
718 i = 0;
719 while (l4_peripheral_table[i].phys_addr) {
720 iommu_kunmap(dev_context->dsp_mmu,
721 l4_peripheral_table[i].dsp_virt_addr);
722 i++;
723 }
724 iommu_kunmap(dev_context->dsp_mmu, dev_context->sh_s.seg0_da);
725 iommu_kunmap(dev_context->dsp_mmu, dev_context->sh_s.seg1_da);
726 iommu_put(dev_context->dsp_mmu);
727 dev_context->dsp_mmu = NULL;
728 }
729 /* Reset IVA IOMMU*/
730 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK,
731 OMAP3430_RST2_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
732
733 dsp_clock_disable_all(dev_context->dsp_per_clks);
734 dsp_clk_disable(DSP_CLK_IVA2);
735
736 return status;
737 }
738
739 /*
740 * ======== bridge_brd_status ========
741 * Returns the board status.
742 */
743 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
744 int *board_state)
745 {
746 struct bridge_dev_context *dev_context = dev_ctxt;
747 *board_state = dev_context->dw_brd_state;
748 return 0;
749 }
750
751 /*
752 * ======== bridge_brd_write ========
753 * Copies the buffers to DSP internal or external memory.
754 */
755 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
756 u8 *host_buff, u32 dsp_addr,
757 u32 ul_num_bytes, u32 mem_type)
758 {
759 int status = 0;
760 struct bridge_dev_context *dev_context = dev_ctxt;
761
762 if (dsp_addr < dev_context->dw_dsp_start_add) {
763 status = -EPERM;
764 return status;
765 }
766 if ((dsp_addr - dev_context->dw_dsp_start_add) <
767 dev_context->dw_internal_size) {
768 status = write_dsp_data(dev_ctxt, host_buff, dsp_addr,
769 ul_num_bytes, mem_type);
770 } else {
771 status = write_ext_dsp_data(dev_context, host_buff, dsp_addr,
772 ul_num_bytes, mem_type, false);
773 }
774
775 return status;
776 }
777
778 /*
779 * ======== bridge_dev_create ========
780 * Creates a driver object. Puts DSP in self loop.
781 */
782 static int bridge_dev_create(struct bridge_dev_context
783 **dev_cntxt,
784 struct dev_object *hdev_obj,
785 struct cfg_hostres *config_param)
786 {
787 int status = 0;
788 struct bridge_dev_context *dev_context = NULL;
789 s32 entry_ndx;
790 struct cfg_hostres *resources = config_param;
791 struct pg_table_attrs *pt_attrs;
792 u32 pg_tbl_pa;
793 u32 pg_tbl_va;
794 u32 align_size;
795 struct drv_data *drv_datap = dev_get_drvdata(bridge);
796
797 /* Allocate and initialize a data structure to contain the bridge driver
798 * state, which becomes the context for later calls into this driver */
799 dev_context = kzalloc(sizeof(struct bridge_dev_context), GFP_KERNEL);
800 if (!dev_context) {
801 status = -ENOMEM;
802 goto func_end;
803 }
804
805 dev_context->dw_dsp_start_add = (u32) OMAP_GEM_BASE;
806 dev_context->dw_self_loop = (u32) NULL;
807 dev_context->dsp_per_clks = 0;
808 dev_context->dw_internal_size = OMAP_DSP_SIZE;
809 /* Clear dev context MMU table entries.
810 * These get set on bridge_io_on_loaded() call after program loaded. */
811 for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB; entry_ndx++) {
812 dev_context->atlb_entry[entry_ndx].ul_gpp_pa =
813 dev_context->atlb_entry[entry_ndx].ul_dsp_va = 0;
814 }
815 dev_context->dw_dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)
816 (config_param->
817 dw_mem_base
818 [3]),
819 config_param->
820 dw_mem_length
821 [3]);
822 if (!dev_context->dw_dsp_base_addr)
823 status = -EPERM;
824
825 pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
826 if (pt_attrs != NULL) {
827 /* Assuming that we use only DSP's memory map
828 * until 0x4000:0000 , we would need only 1024
829 * L1 enties i.e L1 size = 4K */
830 pt_attrs->l1_size = 0x1000;
831 align_size = pt_attrs->l1_size;
832 /* Align sizes are expected to be power of 2 */
833 /* we like to get aligned on L1 table size */
834 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l1_size,
835 align_size, &pg_tbl_pa);
836
837 /* Check if the PA is aligned for us */
838 if ((pg_tbl_pa) & (align_size - 1)) {
839 /* PA not aligned to page table size ,
840 * try with more allocation and align */
841 mem_free_phys_mem((void *)pg_tbl_va, pg_tbl_pa,
842 pt_attrs->l1_size);
843 /* we like to get aligned on L1 table size */
844 pg_tbl_va =
845 (u32) mem_alloc_phys_mem((pt_attrs->l1_size) * 2,
846 align_size, &pg_tbl_pa);
847 /* We should be able to get aligned table now */
848 pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
849 pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
850 pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size * 2;
851 /* Align the PA to the next 'align' boundary */
852 pt_attrs->l1_base_pa =
853 ((pg_tbl_pa) +
854 (align_size - 1)) & (~(align_size - 1));
855 pt_attrs->l1_base_va =
856 pg_tbl_va + (pt_attrs->l1_base_pa - pg_tbl_pa);
857 } else {
858 /* We got aligned PA, cool */
859 pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
860 pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
861 pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size;
862 pt_attrs->l1_base_pa = pg_tbl_pa;
863 pt_attrs->l1_base_va = pg_tbl_va;
864 }
865 if (pt_attrs->l1_base_va)
866 memset((u8 *) pt_attrs->l1_base_va, 0x00,
867 pt_attrs->l1_size);
868
869 /* number of L2 page tables = DMM pool used + SHMMEM +EXTMEM +
870 * L4 pages */
871 pt_attrs->l2_num_pages = ((DMMPOOLSIZE >> 20) + 6);
872 pt_attrs->l2_size = HW_MMU_COARSE_PAGE_SIZE *
873 pt_attrs->l2_num_pages;
874 align_size = 4; /* Make it u32 aligned */
875 /* we like to get aligned on L1 table size */
876 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l2_size,
877 align_size, &pg_tbl_pa);
878 pt_attrs->l2_tbl_alloc_pa = pg_tbl_pa;
879 pt_attrs->l2_tbl_alloc_va = pg_tbl_va;
880 pt_attrs->l2_tbl_alloc_sz = pt_attrs->l2_size;
881 pt_attrs->l2_base_pa = pg_tbl_pa;
882 pt_attrs->l2_base_va = pg_tbl_va;
883
884 if (pt_attrs->l2_base_va)
885 memset((u8 *) pt_attrs->l2_base_va, 0x00,
886 pt_attrs->l2_size);
887
888 pt_attrs->pg_info = kzalloc(pt_attrs->l2_num_pages *
889 sizeof(struct page_info), GFP_KERNEL);
890 dev_dbg(bridge,
891 "L1 pa %x, va %x, size %x\n L2 pa %x, va "
892 "%x, size %x\n", pt_attrs->l1_base_pa,
893 pt_attrs->l1_base_va, pt_attrs->l1_size,
894 pt_attrs->l2_base_pa, pt_attrs->l2_base_va,
895 pt_attrs->l2_size);
896 dev_dbg(bridge, "pt_attrs %p L2 NumPages %x pg_info %p\n",
897 pt_attrs, pt_attrs->l2_num_pages, pt_attrs->pg_info);
898 }
899 if ((pt_attrs != NULL) && (pt_attrs->l1_base_va != 0) &&
900 (pt_attrs->l2_base_va != 0) && (pt_attrs->pg_info != NULL))
901 dev_context->pt_attrs = pt_attrs;
902 else
903 status = -ENOMEM;
904
905 if (!status) {
906 spin_lock_init(&pt_attrs->pg_lock);
907 dev_context->tc_word_swap_on = drv_datap->tc_wordswapon;
908
909 /* Set the Clock Divisor for the DSP module */
910 udelay(5);
911 /* MMU address is obtained from the host
912 * resources struct */
913 dev_context->dw_dsp_mmu_base = resources->dw_dmmu_base;
914 }
915 if (!status) {
916 dev_context->hdev_obj = hdev_obj;
917 /* Store current board state. */
918 dev_context->dw_brd_state = BRD_UNKNOWN;
919 dev_context->resources = resources;
920 dsp_clk_enable(DSP_CLK_IVA2);
921 bridge_brd_stop(dev_context);
922 /* Return ptr to our device state to the DSP API for storage */
923 *dev_cntxt = dev_context;
924 } else {
925 if (pt_attrs != NULL) {
926 kfree(pt_attrs->pg_info);
927
928 if (pt_attrs->l2_tbl_alloc_va) {
929 mem_free_phys_mem((void *)
930 pt_attrs->l2_tbl_alloc_va,
931 pt_attrs->l2_tbl_alloc_pa,
932 pt_attrs->l2_tbl_alloc_sz);
933 }
934 if (pt_attrs->l1_tbl_alloc_va) {
935 mem_free_phys_mem((void *)
936 pt_attrs->l1_tbl_alloc_va,
937 pt_attrs->l1_tbl_alloc_pa,
938 pt_attrs->l1_tbl_alloc_sz);
939 }
940 }
941 kfree(pt_attrs);
942 kfree(dev_context);
943 }
944 func_end:
945 return status;
946 }
947
948 /*
949 * ======== bridge_dev_ctrl ========
950 * Receives device specific commands.
951 */
952 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
953 u32 dw_cmd, void *pargs)
954 {
955 int status = 0;
956 struct bridge_ioctl_extproc *pa_ext_proc =
957 (struct bridge_ioctl_extproc *)pargs;
958 s32 ndx;
959
960 switch (dw_cmd) {
961 case BRDIOCTL_CHNLREAD:
962 break;
963 case BRDIOCTL_CHNLWRITE:
964 break;
965 case BRDIOCTL_SETMMUCONFIG:
966 /* store away dsp-mmu setup values for later use */
967 for (ndx = 0; ndx < BRDIOCTL_NUMOFMMUTLB; ndx++, pa_ext_proc++)
968 dev_context->atlb_entry[ndx] = *pa_ext_proc;
969 break;
970 case BRDIOCTL_DEEPSLEEP:
971 case BRDIOCTL_EMERGENCYSLEEP:
972 /* Currently only DSP Idle is supported Need to update for
973 * later releases */
974 status = sleep_dsp(dev_context, PWR_DEEPSLEEP, pargs);
975 break;
976 case BRDIOCTL_WAKEUP:
977 status = wake_dsp(dev_context, pargs);
978 break;
979 case BRDIOCTL_CLK_CTRL:
980 status = 0;
981 /* Looking For Baseport Fix for Clocks */
982 status = dsp_peripheral_clk_ctrl(dev_context, pargs);
983 break;
984 case BRDIOCTL_PWR_HIBERNATE:
985 status = handle_hibernation_from_dsp(dev_context);
986 break;
987 case BRDIOCTL_PRESCALE_NOTIFY:
988 status = pre_scale_dsp(dev_context, pargs);
989 break;
990 case BRDIOCTL_POSTSCALE_NOTIFY:
991 status = post_scale_dsp(dev_context, pargs);
992 break;
993 case BRDIOCTL_CONSTRAINT_REQUEST:
994 status = handle_constraints_set(dev_context, pargs);
995 break;
996 default:
997 status = -EPERM;
998 break;
999 }
1000 return status;
1001 }
1002
1003 /*
1004 * ======== bridge_dev_destroy ========
1005 * Destroys the driver object.
1006 */
1007 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
1008 {
1009 struct pg_table_attrs *pt_attrs;
1010 int status = 0;
1011 struct bridge_dev_context *dev_context = (struct bridge_dev_context *)
1012 dev_ctxt;
1013 struct cfg_hostres *host_res;
1014 u32 shm_size;
1015 struct drv_data *drv_datap = dev_get_drvdata(bridge);
1016
1017 /* It should never happen */
1018 if (!dev_ctxt)
1019 return -EFAULT;
1020
1021 /* first put the device to stop state */
1022 bridge_brd_stop(dev_context);
1023 if (dev_context->pt_attrs) {
1024 pt_attrs = dev_context->pt_attrs;
1025 kfree(pt_attrs->pg_info);
1026
1027 if (pt_attrs->l2_tbl_alloc_va) {
1028 mem_free_phys_mem((void *)pt_attrs->l2_tbl_alloc_va,
1029 pt_attrs->l2_tbl_alloc_pa,
1030 pt_attrs->l2_tbl_alloc_sz);
1031 }
1032 if (pt_attrs->l1_tbl_alloc_va) {
1033 mem_free_phys_mem((void *)pt_attrs->l1_tbl_alloc_va,
1034 pt_attrs->l1_tbl_alloc_pa,
1035 pt_attrs->l1_tbl_alloc_sz);
1036 }
1037 kfree(pt_attrs);
1038
1039 }
1040
1041 if (dev_context->resources) {
1042 host_res = dev_context->resources;
1043 shm_size = drv_datap->shm_size;
1044 if (shm_size >= 0x10000) {
1045 if ((host_res->dw_mem_base[1]) &&
1046 (host_res->dw_mem_phys[1])) {
1047 mem_free_phys_mem((void *)
1048 host_res->dw_mem_base
1049 [1],
1050 host_res->dw_mem_phys
1051 [1], shm_size);
1052 }
1053 } else {
1054 dev_dbg(bridge, "%s: Error getting shm size "
1055 "from registry: %x. Not calling "
1056 "mem_free_phys_mem\n", __func__,
1057 status);
1058 }
1059 host_res->dw_mem_base[1] = 0;
1060 host_res->dw_mem_phys[1] = 0;
1061
1062 if (host_res->dw_mem_base[0])
1063 iounmap((void *)host_res->dw_mem_base[0]);
1064 if (host_res->dw_mem_base[2])
1065 iounmap((void *)host_res->dw_mem_base[2]);
1066 if (host_res->dw_mem_base[3])
1067 iounmap((void *)host_res->dw_mem_base[3]);
1068 if (host_res->dw_mem_base[4])
1069 iounmap((void *)host_res->dw_mem_base[4]);
1070 if (host_res->dw_dmmu_base)
1071 iounmap(host_res->dw_dmmu_base);
1072 if (host_res->dw_per_base)
1073 iounmap(host_res->dw_per_base);
1074 if (host_res->dw_per_pm_base)
1075 iounmap((void *)host_res->dw_per_pm_base);
1076 if (host_res->dw_core_pm_base)
1077 iounmap((void *)host_res->dw_core_pm_base);
1078 if (host_res->dw_sys_ctrl_base)
1079 iounmap(host_res->dw_sys_ctrl_base);
1080
1081 host_res->dw_mem_base[0] = (u32) NULL;
1082 host_res->dw_mem_base[2] = (u32) NULL;
1083 host_res->dw_mem_base[3] = (u32) NULL;
1084 host_res->dw_mem_base[4] = (u32) NULL;
1085 host_res->dw_dmmu_base = NULL;
1086 host_res->dw_sys_ctrl_base = NULL;
1087
1088 kfree(host_res);
1089 }
1090
1091 /* Free the driver's device context: */
1092 kfree(drv_datap->base_img);
1093 kfree(drv_datap);
1094 dev_set_drvdata(bridge, NULL);
1095 kfree((void *)dev_ctxt);
1096 return status;
1097 }
1098
1099 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
1100 u32 dsp_dest_addr, u32 dsp_src_addr,
1101 u32 ul_num_bytes, u32 mem_type)
1102 {
1103 int status = 0;
1104 u32 src_addr = dsp_src_addr;
1105 u32 dest_addr = dsp_dest_addr;
1106 u32 copy_bytes = 0;
1107 u32 total_bytes = ul_num_bytes;
1108 u8 host_buf[BUFFERSIZE];
1109 struct bridge_dev_context *dev_context = dev_ctxt;
1110 while (total_bytes > 0 && !status) {
1111 copy_bytes =
1112 total_bytes > BUFFERSIZE ? BUFFERSIZE : total_bytes;
1113 /* Read from External memory */
1114 status = read_ext_dsp_data(dev_ctxt, host_buf, src_addr,
1115 copy_bytes, mem_type);
1116 if (!status) {
1117 if (dest_addr < (dev_context->dw_dsp_start_add +
1118 dev_context->dw_internal_size)) {
1119 /* Write to Internal memory */
1120 status = write_dsp_data(dev_ctxt, host_buf,
1121 dest_addr, copy_bytes,
1122 mem_type);
1123 } else {
1124 /* Write to External memory */
1125 status =
1126 write_ext_dsp_data(dev_ctxt, host_buf,
1127 dest_addr, copy_bytes,
1128 mem_type, false);
1129 }
1130 }
1131 total_bytes -= copy_bytes;
1132 src_addr += copy_bytes;
1133 dest_addr += copy_bytes;
1134 }
1135 return status;
1136 }
1137
1138 /* Mem Write does not halt the DSP to write unlike bridge_brd_write */
1139 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
1140 u8 *host_buff, u32 dsp_addr,
1141 u32 ul_num_bytes, u32 mem_type)
1142 {
1143 int status = 0;
1144 struct bridge_dev_context *dev_context = dev_ctxt;
1145 u32 ul_remain_bytes = 0;
1146 u32 ul_bytes = 0;
1147 ul_remain_bytes = ul_num_bytes;
1148 while (ul_remain_bytes > 0 && !status) {
1149 ul_bytes =
1150 ul_remain_bytes > BUFFERSIZE ? BUFFERSIZE : ul_remain_bytes;
1151 if (dsp_addr < (dev_context->dw_dsp_start_add +
1152 dev_context->dw_internal_size)) {
1153 status =
1154 write_dsp_data(dev_ctxt, host_buff, dsp_addr,
1155 ul_bytes, mem_type);
1156 } else {
1157 status = write_ext_dsp_data(dev_ctxt, host_buff,
1158 dsp_addr, ul_bytes,
1159 mem_type, true);
1160 }
1161 ul_remain_bytes -= ul_bytes;
1162 dsp_addr += ul_bytes;
1163 host_buff = host_buff + ul_bytes;
1164 }
1165 return status;
1166 }
1167
1168 /*
1169 * ======== bridge_brd_mem_map ========
1170 * This function maps MPU buffer to the DSP address space. It performs
1171 * linear to physical address translation if required. It translates each
1172 * page since linear addresses can be physically non-contiguous
1173 * All address & size arguments are assumed to be page aligned (in proc.c)
1174 *
1175 * TODO: Disable MMU while updating the page tables (but that'll stall DSP)
1176 */
1177 static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctx,
1178 u32 uva, u32 da, u32 size, u32 attr,
1179 struct page **usr_pgs)
1180
1181 {
1182 int res, w;
1183 unsigned pages, i;
1184 struct iommu *mmu = dev_ctx->dsp_mmu;
1185 struct vm_area_struct *vma;
1186 struct mm_struct *mm = current->mm;
1187 struct sg_table *sgt;
1188 struct scatterlist *sg;
1189
1190 if (!size || !usr_pgs)
1191 return -EINVAL;
1192
1193 pages = size / PG_SIZE4K;
1194
1195 down_read(&mm->mmap_sem);
1196 vma = find_vma(mm, uva);
1197 while (vma && (uva + size > vma->vm_end))
1198 vma = find_vma(mm, vma->vm_end + 1);
1199
1200 if (!vma) {
1201 pr_err("%s: Failed to get VMA region for 0x%x (%d)\n",
1202 __func__, uva, size);
1203 up_read(&mm->mmap_sem);
1204 return -EINVAL;
1205 }
1206 if (vma->vm_flags & (VM_WRITE | VM_MAYWRITE))
1207 w = 1;
1208
1209 if (vma->vm_flags & VM_IO)
1210 i = get_io_pages(mm, uva, pages, usr_pgs);
1211 else
1212 i = get_user_pages(current, mm, uva, pages, w, 1,
1213 usr_pgs, NULL);
1214 up_read(&mm->mmap_sem);
1215
1216 if (i < 0)
1217 return i;
1218
1219 if (i < pages) {
1220 res = -EFAULT;
1221 goto err_pages;
1222 }
1223
1224 sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
1225 if (!sgt) {
1226 res = -ENOMEM;
1227 goto err_pages;
1228 }
1229
1230 res = sg_alloc_table(sgt, pages, GFP_KERNEL);
1231
1232 if (res < 0)
1233 goto err_sg;
1234
1235 for_each_sg(sgt->sgl, sg, sgt->nents, i)
1236 sg_set_page(sg, usr_pgs[i], PAGE_SIZE, 0);
1237
1238 da = iommu_vmap(mmu, da, sgt, IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_32);
1239
1240 if (!IS_ERR_VALUE(da))
1241 return 0;
1242 res = (int)da;
1243
1244 sg_free_table(sgt);
1245 err_sg:
1246 kfree(sgt);
1247 i = pages;
1248 err_pages:
1249 while (i--)
1250 put_page(usr_pgs[i]);
1251 return res;
1252 }
1253
1254 /*
1255 * ======== bridge_brd_mem_un_map ========
1256 * Invalidate the PTEs for the DSP VA block to be unmapped.
1257 *
1258 * PTEs of a mapped memory block are contiguous in any page table
1259 * So, instead of looking up the PTE address for every 4K block,
1260 * we clear consecutive PTEs until we unmap all the bytes
1261 */
1262 static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctx, u32 da)
1263 {
1264 unsigned i;
1265 struct sg_table *sgt;
1266 struct scatterlist *sg;
1267
1268 sgt = iommu_vunmap(dev_ctx->dsp_mmu, da);
1269 if (!sgt)
1270 return -EFAULT;
1271
1272 for_each_sg(sgt->sgl, sg, sgt->nents, i)
1273 put_page(sg_page(sg));
1274 sg_free_table(sgt);
1275 kfree(sgt);
1276
1277 return 0;
1278 }
1279
1280
1281 static int get_io_pages(struct mm_struct *mm, u32 uva, unsigned pages,
1282 struct page **usr_pgs)
1283 {
1284 u32 pa;
1285 int i;
1286 struct page *pg;
1287
1288 for (i = 0; i < pages; i++) {
1289 pa = user_va2_pa(mm, uva);
1290
1291 if (!pfn_valid(__phys_to_pfn(pa)))
1292 break;
1293
1294 pg = PHYS_TO_PAGE(pa);
1295 usr_pgs[i] = pg;
1296 get_page(pg);
1297 }
1298 return i;
1299 }
1300
1301 /*
1302 * ======== user_va2_pa ========
1303 * Purpose:
1304 * This function walks through the page tables to convert a userland
1305 * virtual address to physical address
1306 */
1307 static u32 user_va2_pa(struct mm_struct *mm, u32 address)
1308 {
1309 pgd_t *pgd;
1310 pmd_t *pmd;
1311 pte_t *ptep, pte;
1312
1313 pgd = pgd_offset(mm, address);
1314 if (!(pgd_none(*pgd) || pgd_bad(*pgd))) {
1315 pmd = pmd_offset(pgd, address);
1316 if (!(pmd_none(*pmd) || pmd_bad(*pmd))) {
1317 ptep = pte_offset_map(pmd, address);
1318 if (ptep) {
1319 pte = *ptep;
1320 if (pte_present(pte))
1321 return pte & PAGE_MASK;
1322 }
1323 }
1324 }
1325
1326 return 0;
1327 }
1328
1329 /*
1330 * ======== pte_update ========
1331 * This function calculates the optimum page-aligned addresses and sizes
1332 * Caller must pass page-aligned values
1333 */
1334 static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
1335 u32 va, u32 size,
1336 struct hw_mmu_map_attrs_t *map_attrs)
1337 {
1338 u32 i;
1339 u32 all_bits;
1340 u32 pa_curr = pa;
1341 u32 va_curr = va;
1342 u32 num_bytes = size;
1343 struct bridge_dev_context *dev_context = dev_ctxt;
1344 int status = 0;
1345 u32 page_size[] = { HW_PAGE_SIZE16MB, HW_PAGE_SIZE1MB,
1346 HW_PAGE_SIZE64KB, HW_PAGE_SIZE4KB
1347 };
1348
1349 while (num_bytes && !status) {
1350 /* To find the max. page size with which both PA & VA are
1351 * aligned */
1352 all_bits = pa_curr | va_curr;
1353
1354 for (i = 0; i < 4; i++) {
1355 if ((num_bytes >= page_size[i]) && ((all_bits &
1356 (page_size[i] -
1357 1)) == 0)) {
1358 status =
1359 pte_set(dev_context->pt_attrs, pa_curr,
1360 va_curr, page_size[i], map_attrs);
1361 pa_curr += page_size[i];
1362 va_curr += page_size[i];
1363 num_bytes -= page_size[i];
1364 /* Don't try smaller sizes. Hopefully we have
1365 * reached an address aligned to a bigger page
1366 * size */
1367 break;
1368 }
1369 }
1370 }
1371
1372 return status;
1373 }
1374
1375 /*
1376 * ======== pte_set ========
1377 * This function calculates PTE address (MPU virtual) to be updated
1378 * It also manages the L2 page tables
1379 */
1380 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
1381 u32 size, struct hw_mmu_map_attrs_t *attrs)
1382 {
1383 u32 i;
1384 u32 pte_val;
1385 u32 pte_addr_l1;
1386 u32 pte_size;
1387 /* Base address of the PT that will be updated */
1388 u32 pg_tbl_va;
1389 u32 l1_base_va;
1390 /* Compiler warns that the next three variables might be used
1391 * uninitialized in this function. Doesn't seem so. Working around,
1392 * anyways. */
1393 u32 l2_base_va = 0;
1394 u32 l2_base_pa = 0;
1395 u32 l2_page_num = 0;
1396 int status = 0;
1397
1398 l1_base_va = pt->l1_base_va;
1399 pg_tbl_va = l1_base_va;
1400 if ((size == HW_PAGE_SIZE64KB) || (size == HW_PAGE_SIZE4KB)) {
1401 /* Find whether the L1 PTE points to a valid L2 PT */
1402 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va);
1403 if (pte_addr_l1 <= (pt->l1_base_va + pt->l1_size)) {
1404 pte_val = *(u32 *) pte_addr_l1;
1405 pte_size = hw_mmu_pte_size_l1(pte_val);
1406 } else {
1407 return -EPERM;
1408 }
1409 spin_lock(&pt->pg_lock);
1410 if (pte_size == HW_MMU_COARSE_PAGE_SIZE) {
1411 /* Get the L2 PA from the L1 PTE, and find
1412 * corresponding L2 VA */
1413 l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1414 l2_base_va =
1415 l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1416 l2_page_num =
1417 (l2_base_pa -
1418 pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1419 } else if (pte_size == 0) {
1420 /* L1 PTE is invalid. Allocate a L2 PT and
1421 * point the L1 PTE to it */
1422 /* Find a free L2 PT. */
1423 for (i = 0; (i < pt->l2_num_pages) &&
1424 (pt->pg_info[i].num_entries != 0); i++)
1425 ;;
1426 if (i < pt->l2_num_pages) {
1427 l2_page_num = i;
1428 l2_base_pa = pt->l2_base_pa + (l2_page_num *
1429 HW_MMU_COARSE_PAGE_SIZE);
1430 l2_base_va = pt->l2_base_va + (l2_page_num *
1431 HW_MMU_COARSE_PAGE_SIZE);
1432 /* Endianness attributes are ignored for
1433 * HW_MMU_COARSE_PAGE_SIZE */
1434 status =
1435 hw_mmu_pte_set(l1_base_va, l2_base_pa, va,
1436 HW_MMU_COARSE_PAGE_SIZE,
1437 attrs);
1438 } else {
1439 status = -ENOMEM;
1440 }
1441 } else {
1442 /* Found valid L1 PTE of another size.
1443 * Should not overwrite it. */
1444 status = -EPERM;
1445 }
1446 if (!status) {
1447 pg_tbl_va = l2_base_va;
1448 if (size == HW_PAGE_SIZE64KB)
1449 pt->pg_info[l2_page_num].num_entries += 16;
1450 else
1451 pt->pg_info[l2_page_num].num_entries++;
1452 dev_dbg(bridge, "PTE: L2 BaseVa %x, BasePa %x, PageNum "
1453 "%x, num_entries %x\n", l2_base_va,
1454 l2_base_pa, l2_page_num,
1455 pt->pg_info[l2_page_num].num_entries);
1456 }
1457 spin_unlock(&pt->pg_lock);
1458 }
1459 if (!status) {
1460 dev_dbg(bridge, "PTE: pg_tbl_va %x, pa %x, va %x, size %x\n",
1461 pg_tbl_va, pa, va, size);
1462 dev_dbg(bridge, "PTE: endianism %x, element_size %x, "
1463 "mixed_size %x\n", attrs->endianism,
1464 attrs->element_size, attrs->mixed_size);
1465 status = hw_mmu_pte_set(pg_tbl_va, pa, va, size, attrs);
1466 }
1467
1468 return status;
1469 }
1470
1471 /* Memory map kernel VA -- memory allocated with vmalloc */
1472 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
1473 u32 ul_mpu_addr, u32 virt_addr,
1474 u32 ul_num_bytes,
1475 struct hw_mmu_map_attrs_t *hw_attrs)
1476 {
1477 int status = 0;
1478 struct page *page[1];
1479 u32 i;
1480 u32 pa_curr;
1481 u32 pa_next;
1482 u32 va_curr;
1483 u32 size_curr;
1484 u32 num_pages;
1485 u32 pa;
1486 u32 num_of4k_pages;
1487 u32 temp = 0;
1488
1489 /*
1490 * Do Kernel va to pa translation.
1491 * Combine physically contiguous regions to reduce TLBs.
1492 * Pass the translated pa to pte_update.
1493 */
1494 num_pages = ul_num_bytes / PAGE_SIZE; /* PAGE_SIZE = OS page size */
1495 i = 0;
1496 va_curr = ul_mpu_addr;
1497 page[0] = vmalloc_to_page((void *)va_curr);
1498 pa_next = page_to_phys(page[0]);
1499 while (!status && (i < num_pages)) {
1500 /*
1501 * Reuse pa_next from the previous iteraion to avoid
1502 * an extra va2pa call
1503 */
1504 pa_curr = pa_next;
1505 size_curr = PAGE_SIZE;
1506 /*
1507 * If the next page is physically contiguous,
1508 * map it with the current one by increasing
1509 * the size of the region to be mapped
1510 */
1511 while (++i < num_pages) {
1512 page[0] =
1513 vmalloc_to_page((void *)(va_curr + size_curr));
1514 pa_next = page_to_phys(page[0]);
1515
1516 if (pa_next == (pa_curr + size_curr))
1517 size_curr += PAGE_SIZE;
1518 else
1519 break;
1520
1521 }
1522 if (pa_next == 0) {
1523 status = -ENOMEM;
1524 break;
1525 }
1526 pa = pa_curr;
1527 num_of4k_pages = size_curr / HW_PAGE_SIZE4KB;
1528 while (temp++ < num_of4k_pages) {
1529 get_page(PHYS_TO_PAGE(pa));
1530 pa += HW_PAGE_SIZE4KB;
1531 }
1532 status = pte_update(dev_context, pa_curr, virt_addr +
1533 (va_curr - ul_mpu_addr), size_curr,
1534 hw_attrs);
1535 va_curr += size_curr;
1536 }
1537 /*
1538 * In any case, flush the TLB
1539 * This is called from here instead from pte_update to avoid unnecessary
1540 * repetition while mapping non-contiguous physical regions of a virtual
1541 * region
1542 */
1543 flush_all(dev_context);
1544 dev_dbg(bridge, "%s status %x\n", __func__, status);
1545 return status;
1546 }
1547
1548 /*
1549 * ======== wait_for_start ========
1550 * Wait for the singal from DSP that it has started, or time out.
1551 */
1552 bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr)
1553 {
1554 u16 timeout = TIHELEN_ACKTIMEOUT;
1555
1556 /* Wait for response from board */
1557 while (__raw_readw(dw_sync_addr) && --timeout)
1558 udelay(10);
1559
1560 /* If timed out: return false */
1561 if (!timeout) {
1562 pr_err("%s: Timed out waiting DSP to Start\n", __func__);
1563 return false;
1564 }
1565 return true;
1566 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree