3 * device driver for Conexant 2388x based TV cards
4 * MPEG Transport Stream (DVB) routines
6 * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
7 * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/device.h>
28 #include <linux/kthread.h>
29 #include <linux/file.h>
30 #include <linux/suspend.h>
34 #include <media/v4l2-common.h>
38 # include "mt352_priv.h"
39 # ifdef HAVE_VP3054_I2C
40 # include "cx88-vp3054-i2c.h"
53 # include "lgdt330x.h"
62 MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
63 MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
64 MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
65 MODULE_LICENSE("GPL");
67 static unsigned int debug
= 0;
68 module_param(debug
, int, 0644);
69 MODULE_PARM_DESC(debug
,"enable debug messages [dvb]");
71 #define dprintk(level,fmt, arg...) if (debug >= level) \
72 printk(KERN_DEBUG "%s/2-dvb: " fmt, dev->core->name , ## arg)
74 /* ------------------------------------------------------------------ */
76 static int dvb_buf_setup(struct videobuf_queue
*q
,
77 unsigned int *count
, unsigned int *size
)
79 struct cx8802_dev
*dev
= q
->priv_data
;
81 dev
->ts_packet_size
= 188 * 4;
82 dev
->ts_packet_count
= 32;
84 *size
= dev
->ts_packet_size
* dev
->ts_packet_count
;
89 static int dvb_buf_prepare(struct videobuf_queue
*q
, struct videobuf_buffer
*vb
,
90 enum v4l2_field field
)
92 struct cx8802_dev
*dev
= q
->priv_data
;
93 return cx8802_buf_prepare(q
, dev
, (struct cx88_buffer
*)vb
,field
);
96 static void dvb_buf_queue(struct videobuf_queue
*q
, struct videobuf_buffer
*vb
)
98 struct cx8802_dev
*dev
= q
->priv_data
;
99 cx8802_buf_queue(dev
, (struct cx88_buffer
*)vb
);
102 static void dvb_buf_release(struct videobuf_queue
*q
, struct videobuf_buffer
*vb
)
104 cx88_free_buffer(q
, (struct cx88_buffer
*)vb
);
107 static struct videobuf_queue_ops dvb_qops
= {
108 .buf_setup
= dvb_buf_setup
,
109 .buf_prepare
= dvb_buf_prepare
,
110 .buf_queue
= dvb_buf_queue
,
111 .buf_release
= dvb_buf_release
,
114 /* ------------------------------------------------------------------ */
116 #if defined(HAVE_MT352) || defined(HAVE_ZL10353)
117 static int zarlink_pll_set(struct dvb_frontend
*fe
,
118 struct dvb_frontend_parameters
*params
,
121 struct cx8802_dev
*dev
= fe
->dvb
->priv
;
123 pllbuf
[0] = dev
->core
->pll_addr
<< 1;
124 dvb_pll_configure(dev
->core
->pll_desc
, pllbuf
+ 1,
126 params
->u
.ofdm
.bandwidth
);
132 static int dvico_fusionhdtv_demod_init(struct dvb_frontend
* fe
)
134 static u8 clock_config
[] = { CLOCK_CTL
, 0x38, 0x39 };
135 static u8 reset
[] = { RESET
, 0x80 };
136 static u8 adc_ctl_1_cfg
[] = { ADC_CTL_1
, 0x40 };
137 static u8 agc_cfg
[] = { AGC_TARGET
, 0x24, 0x20 };
138 static u8 gpp_ctl_cfg
[] = { GPP_CTL
, 0x33 };
139 static u8 capt_range_cfg
[] = { CAPT_RANGE
, 0x32 };
141 mt352_write(fe
, clock_config
, sizeof(clock_config
));
143 mt352_write(fe
, reset
, sizeof(reset
));
144 mt352_write(fe
, adc_ctl_1_cfg
, sizeof(adc_ctl_1_cfg
));
146 mt352_write(fe
, agc_cfg
, sizeof(agc_cfg
));
147 mt352_write(fe
, gpp_ctl_cfg
, sizeof(gpp_ctl_cfg
));
148 mt352_write(fe
, capt_range_cfg
, sizeof(capt_range_cfg
));
152 static int dvico_dual_demod_init(struct dvb_frontend
*fe
)
154 static u8 clock_config
[] = { CLOCK_CTL
, 0x38, 0x38 };
155 static u8 reset
[] = { RESET
, 0x80 };
156 static u8 adc_ctl_1_cfg
[] = { ADC_CTL_1
, 0x40 };
157 static u8 agc_cfg
[] = { AGC_TARGET
, 0x28, 0x20 };
158 static u8 gpp_ctl_cfg
[] = { GPP_CTL
, 0x33 };
159 static u8 capt_range_cfg
[] = { CAPT_RANGE
, 0x32 };
161 mt352_write(fe
, clock_config
, sizeof(clock_config
));
163 mt352_write(fe
, reset
, sizeof(reset
));
164 mt352_write(fe
, adc_ctl_1_cfg
, sizeof(adc_ctl_1_cfg
));
166 mt352_write(fe
, agc_cfg
, sizeof(agc_cfg
));
167 mt352_write(fe
, gpp_ctl_cfg
, sizeof(gpp_ctl_cfg
));
168 mt352_write(fe
, capt_range_cfg
, sizeof(capt_range_cfg
));
173 static int dntv_live_dvbt_demod_init(struct dvb_frontend
* fe
)
175 static u8 clock_config
[] = { 0x89, 0x38, 0x39 };
176 static u8 reset
[] = { 0x50, 0x80 };
177 static u8 adc_ctl_1_cfg
[] = { 0x8E, 0x40 };
178 static u8 agc_cfg
[] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
179 0x00, 0xFF, 0x00, 0x40, 0x40 };
180 static u8 dntv_extra
[] = { 0xB5, 0x7A };
181 static u8 capt_range_cfg
[] = { 0x75, 0x32 };
183 mt352_write(fe
, clock_config
, sizeof(clock_config
));
185 mt352_write(fe
, reset
, sizeof(reset
));
186 mt352_write(fe
, adc_ctl_1_cfg
, sizeof(adc_ctl_1_cfg
));
188 mt352_write(fe
, agc_cfg
, sizeof(agc_cfg
));
190 mt352_write(fe
, dntv_extra
, sizeof(dntv_extra
));
191 mt352_write(fe
, capt_range_cfg
, sizeof(capt_range_cfg
));
196 static struct mt352_config dvico_fusionhdtv
= {
197 .demod_address
= 0x0F,
198 .demod_init
= dvico_fusionhdtv_demod_init
,
199 .pll_set
= zarlink_pll_set
,
202 static struct mt352_config dntv_live_dvbt_config
= {
203 .demod_address
= 0x0f,
204 .demod_init
= dntv_live_dvbt_demod_init
,
205 .pll_set
= zarlink_pll_set
,
208 static struct mt352_config dvico_fusionhdtv_dual
= {
209 .demod_address
= 0x0F,
210 .demod_init
= dvico_dual_demod_init
,
211 .pll_set
= zarlink_pll_set
,
214 #ifdef HAVE_VP3054_I2C
215 static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend
* fe
)
217 static u8 clock_config
[] = { 0x89, 0x38, 0x38 };
218 static u8 reset
[] = { 0x50, 0x80 };
219 static u8 adc_ctl_1_cfg
[] = { 0x8E, 0x40 };
220 static u8 agc_cfg
[] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
221 0x00, 0xFF, 0x00, 0x40, 0x40 };
222 static u8 dntv_extra
[] = { 0xB5, 0x7A };
223 static u8 capt_range_cfg
[] = { 0x75, 0x32 };
225 mt352_write(fe
, clock_config
, sizeof(clock_config
));
227 mt352_write(fe
, reset
, sizeof(reset
));
228 mt352_write(fe
, adc_ctl_1_cfg
, sizeof(adc_ctl_1_cfg
));
230 mt352_write(fe
, agc_cfg
, sizeof(agc_cfg
));
232 mt352_write(fe
, dntv_extra
, sizeof(dntv_extra
));
233 mt352_write(fe
, capt_range_cfg
, sizeof(capt_range_cfg
));
238 static int philips_fmd1216_pll_init(struct dvb_frontend
*fe
)
240 struct cx8802_dev
*dev
= fe
->dvb
->priv
;
242 /* this message is to set up ATC and ALC */
243 static u8 fmd1216_init
[] = { 0x0b, 0xdc, 0x9c, 0xa0 };
245 { .addr
= dev
->core
->pll_addr
, .flags
= 0,
246 .buf
= fmd1216_init
, .len
= sizeof(fmd1216_init
) };
249 if ((err
= i2c_transfer(&dev
->core
->i2c_adap
, &msg
, 1)) != 1) {
259 static int dntv_live_dvbt_pro_pll_set(struct dvb_frontend
* fe
,
260 struct dvb_frontend_parameters
* params
,
263 struct cx8802_dev
*dev
= fe
->dvb
->priv
;
265 { .addr
= dev
->core
->pll_addr
, .flags
= 0,
266 .buf
= pllbuf
+1, .len
= 4 };
269 /* Switch PLL to DVB mode */
270 err
= philips_fmd1216_pll_init(fe
);
275 pllbuf
[0] = dev
->core
->pll_addr
<< 1;
276 dvb_pll_configure(dev
->core
->pll_desc
, pllbuf
+1,
278 params
->u
.ofdm
.bandwidth
);
279 if ((err
= i2c_transfer(&dev
->core
->i2c_adap
, &msg
, 1)) != 1) {
280 printk(KERN_WARNING
"cx88-dvb: %s error "
281 "(addr %02x <- %02x, err = %i)\n",
282 __FUNCTION__
, pllbuf
[0], pllbuf
[1], err
);
292 static struct mt352_config dntv_live_dvbt_pro_config
= {
293 .demod_address
= 0x0f,
295 .demod_init
= dntv_live_dvbt_pro_demod_init
,
296 .pll_set
= dntv_live_dvbt_pro_pll_set
,
302 static int dvico_hybrid_tune_pll(struct dvb_frontend
*fe
,
303 struct dvb_frontend_parameters
*params
,
306 struct cx8802_dev
*dev
= fe
->dvb
->priv
;
308 { .addr
= dev
->core
->pll_addr
, .flags
= 0,
309 .buf
= pllbuf
+ 1, .len
= 4 };
312 pllbuf
[0] = dev
->core
->pll_addr
<< 1;
313 dvb_pll_configure(dev
->core
->pll_desc
, pllbuf
+ 1,
315 params
->u
.ofdm
.bandwidth
);
317 if ((err
= i2c_transfer(&dev
->core
->i2c_adap
, &msg
, 1)) != 1) {
318 printk(KERN_WARNING
"cx88-dvb: %s error "
319 "(addr %02x <- %02x, err = %i)\n",
320 __FUNCTION__
, pllbuf
[0], pllbuf
[1], err
);
330 static struct zl10353_config dvico_fusionhdtv_hybrid
= {
331 .demod_address
= 0x0F,
332 .pll_set
= dvico_hybrid_tune_pll
,
335 static struct zl10353_config dvico_fusionhdtv_plus_v1_1
= {
336 .demod_address
= 0x0F,
337 .pll_set
= zarlink_pll_set
,
342 static struct cx22702_config connexant_refboard_config
= {
343 .demod_address
= 0x43,
344 .output_mode
= CX22702_SERIAL_OUTPUT
,
346 .pll_desc
= &dvb_pll_thomson_dtt7579
,
349 static struct cx22702_config hauppauge_novat_config
= {
350 .demod_address
= 0x43,
351 .output_mode
= CX22702_SERIAL_OUTPUT
,
353 .pll_desc
= &dvb_pll_thomson_dtt759x
,
355 static struct cx22702_config hauppauge_hvr1100_config
= {
356 .demod_address
= 0x63,
357 .output_mode
= CX22702_SERIAL_OUTPUT
,
359 .pll_desc
= &dvb_pll_fmd1216me
,
364 static int or51132_set_ts_param(struct dvb_frontend
* fe
,
367 struct cx8802_dev
*dev
= fe
->dvb
->priv
;
368 dev
->ts_gen_cntrl
= is_punctured
? 0x04 : 0x00;
372 static struct or51132_config pchdtv_hd3000
= {
373 .demod_address
= 0x15,
375 .pll_desc
= &dvb_pll_thomson_dtt761x
,
376 .set_ts_params
= or51132_set_ts_param
,
381 static int lgdt330x_pll_set(struct dvb_frontend
* fe
,
382 struct dvb_frontend_parameters
* params
)
384 /* FIXME make this routine use the tuner-simple code.
385 * It could probably be shared with a number of ATSC
386 * frontends. Many share the same tuner with analog TV. */
388 struct cx8802_dev
*dev
= fe
->dvb
->priv
;
389 struct cx88_core
*core
= dev
->core
;
392 { .addr
= dev
->core
->pll_addr
, .flags
= 0, .buf
= buf
, .len
= 4 };
395 /* Put the analog decoder in standby to keep it quiet */
396 cx88_call_i2c_clients (dev
->core
, TUNER_SET_STANDBY
, NULL
);
398 dvb_pll_configure(core
->pll_desc
, buf
, params
->frequency
, 0);
399 dprintk(1, "%s: tuner at 0x%02x bytes: 0x%02x 0x%02x 0x%02x 0x%02x\n",
400 __FUNCTION__
, msg
.addr
, buf
[0],buf
[1],buf
[2],buf
[3]);
401 if ((err
= i2c_transfer(&core
->i2c_adap
, &msg
, 1)) != 1) {
402 printk(KERN_WARNING
"cx88-dvb: %s error "
403 "(addr %02x <- %02x, err = %i)\n",
404 __FUNCTION__
, buf
[0], buf
[1], err
);
410 if (core
->tuner_type
== TUNER_LG_TDVS_H062F
) {
411 /* Set the Auxiliary Byte. */
415 i2c_transfer(&core
->i2c_adap
, &msg
, 1);
420 static int lgdt330x_pll_rf_set(struct dvb_frontend
* fe
, int index
)
422 struct cx8802_dev
*dev
= fe
->dvb
->priv
;
423 struct cx88_core
*core
= dev
->core
;
425 dprintk(1, "%s: index = %d\n", __FUNCTION__
, index
);
427 cx_clear(MO_GP0_IO
, 8);
429 cx_set(MO_GP0_IO
, 8);
433 static int lgdt330x_set_ts_param(struct dvb_frontend
* fe
, int is_punctured
)
435 struct cx8802_dev
*dev
= fe
->dvb
->priv
;
437 dev
->ts_gen_cntrl
|= 0x04;
439 dev
->ts_gen_cntrl
&= ~0x04;
443 static struct lgdt330x_config fusionhdtv_3_gold
= {
444 .demod_address
= 0x0e,
445 .demod_chip
= LGDT3302
,
446 .serial_mpeg
= 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
447 .pll_set
= lgdt330x_pll_set
,
448 .set_ts_params
= lgdt330x_set_ts_param
,
451 static struct lgdt330x_config fusionhdtv_5_gold
= {
452 .demod_address
= 0x0e,
453 .demod_chip
= LGDT3303
,
454 .serial_mpeg
= 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
455 .pll_set
= lgdt330x_pll_set
,
456 .set_ts_params
= lgdt330x_set_ts_param
,
459 static struct lgdt330x_config pchdtv_hd5500
= {
460 .demod_address
= 0x59,
461 .demod_chip
= LGDT3303
,
462 .serial_mpeg
= 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
463 .pll_set
= lgdt330x_pll_set
,
464 .set_ts_params
= lgdt330x_set_ts_param
,
469 static int nxt200x_set_ts_param(struct dvb_frontend
* fe
,
472 struct cx8802_dev
*dev
= fe
->dvb
->priv
;
473 dev
->ts_gen_cntrl
= is_punctured
? 0x04 : 0x00;
477 static int nxt200x_set_pll_input(u8
* buf
, int input
)
486 static struct nxt200x_config ati_hdtvwonder
= {
487 .demod_address
= 0x0a,
489 .pll_desc
= &dvb_pll_tuv1236d
,
490 .set_pll_input
= nxt200x_set_pll_input
,
491 .set_ts_params
= nxt200x_set_ts_param
,
496 static int cx24123_set_ts_param(struct dvb_frontend
* fe
,
499 struct cx8802_dev
*dev
= fe
->dvb
->priv
;
500 dev
->ts_gen_cntrl
= 0x2;
504 static void cx24123_enable_lnb_voltage(struct dvb_frontend
* fe
, int on
)
506 struct cx8802_dev
*dev
= fe
->dvb
->priv
;
507 struct cx88_core
*core
= dev
->core
;
510 cx_write(MO_GP0_IO
, 0x000006f9);
512 cx_write(MO_GP0_IO
, 0x000006fB);
515 static struct cx24123_config hauppauge_novas_config
= {
516 .demod_address
= 0x55,
518 .set_ts_params
= cx24123_set_ts_param
,
521 static struct cx24123_config kworld_dvbs_100_config
= {
522 .demod_address
= 0x15,
524 .set_ts_params
= cx24123_set_ts_param
,
525 .enable_lnb_voltage
= cx24123_enable_lnb_voltage
,
529 static int dvb_register(struct cx8802_dev
*dev
)
531 /* init struct videobuf_dvb */
532 dev
->dvb
.name
= dev
->core
->name
;
533 dev
->ts_gen_cntrl
= 0x0c;
536 switch (dev
->core
->board
) {
538 case CX88_BOARD_HAUPPAUGE_DVB_T1
:
539 dev
->dvb
.frontend
= cx22702_attach(&hauppauge_novat_config
,
540 &dev
->core
->i2c_adap
);
542 case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1
:
543 case CX88_BOARD_CONEXANT_DVB_T1
:
544 case CX88_BOARD_KWORLD_DVB_T_CX22702
:
545 case CX88_BOARD_WINFAST_DTV1000
:
546 dev
->dvb
.frontend
= cx22702_attach(&connexant_refboard_config
,
547 &dev
->core
->i2c_adap
);
549 case CX88_BOARD_HAUPPAUGE_HVR1100
:
550 case CX88_BOARD_HAUPPAUGE_HVR1100LP
:
551 dev
->dvb
.frontend
= cx22702_attach(&hauppauge_hvr1100_config
,
552 &dev
->core
->i2c_adap
);
555 #if defined(HAVE_MT352) || defined(HAVE_ZL10353)
556 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS
:
557 dev
->core
->pll_addr
= 0x60;
558 dev
->core
->pll_desc
= &dvb_pll_thomson_dtt7579
;
560 dev
->dvb
.frontend
= mt352_attach(&dvico_fusionhdtv
,
561 &dev
->core
->i2c_adap
);
562 if (dev
->dvb
.frontend
!= NULL
)
566 /* ZL10353 replaces MT352 on later cards */
567 dev
->dvb
.frontend
= zl10353_attach(&dvico_fusionhdtv_plus_v1_1
,
568 &dev
->core
->i2c_adap
);
571 #endif /* HAVE_MT352 || HAVE_ZL10353 */
573 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1
:
574 dev
->core
->pll_addr
= 0x61;
575 dev
->core
->pll_desc
= &dvb_pll_lg_z201
;
576 dev
->dvb
.frontend
= mt352_attach(&dvico_fusionhdtv
,
577 &dev
->core
->i2c_adap
);
579 case CX88_BOARD_KWORLD_DVB_T
:
580 case CX88_BOARD_DNTV_LIVE_DVB_T
:
581 case CX88_BOARD_ADSTECH_DVB_T_PCI
:
582 dev
->core
->pll_addr
= 0x61;
583 dev
->core
->pll_desc
= &dvb_pll_unknown_1
;
584 dev
->dvb
.frontend
= mt352_attach(&dntv_live_dvbt_config
,
585 &dev
->core
->i2c_adap
);
587 case CX88_BOARD_DNTV_LIVE_DVB_T_PRO
:
588 #ifdef HAVE_VP3054_I2C
589 dev
->core
->pll_addr
= 0x61;
590 dev
->core
->pll_desc
= &dvb_pll_fmd1216me
;
591 dev
->dvb
.frontend
= mt352_attach(&dntv_live_dvbt_pro_config
,
592 &((struct vp3054_i2c_state
*)dev
->card_priv
)->adap
);
594 printk("%s: built without vp3054 support\n", dev
->core
->name
);
597 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL
:
598 /* The tin box says DEE1601, but it seems to be DTT7579
599 * compatible, with a slightly different MT352 AGC gain. */
600 dev
->core
->pll_addr
= 0x61;
601 dev
->core
->pll_desc
= &dvb_pll_thomson_dtt7579
;
602 dev
->dvb
.frontend
= mt352_attach(&dvico_fusionhdtv_dual
,
603 &dev
->core
->i2c_adap
);
607 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID
:
608 dev
->core
->pll_addr
= 0x61;
609 dev
->core
->pll_desc
= &dvb_pll_thomson_fe6600
;
610 dev
->dvb
.frontend
= zl10353_attach(&dvico_fusionhdtv_hybrid
,
611 &dev
->core
->i2c_adap
);
615 case CX88_BOARD_PCHDTV_HD3000
:
616 dev
->dvb
.frontend
= or51132_attach(&pchdtv_hd3000
,
617 &dev
->core
->i2c_adap
);
621 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q
:
622 dev
->ts_gen_cntrl
= 0x08;
624 /* Do a hardware reset of chip before using it. */
625 struct cx88_core
*core
= dev
->core
;
627 cx_clear(MO_GP0_IO
, 1);
629 cx_set(MO_GP0_IO
, 1);
632 /* Select RF connector callback */
633 fusionhdtv_3_gold
.pll_rf_set
= lgdt330x_pll_rf_set
;
634 dev
->core
->pll_addr
= 0x61;
635 dev
->core
->pll_desc
= &dvb_pll_microtune_4042
;
636 dev
->dvb
.frontend
= lgdt330x_attach(&fusionhdtv_3_gold
,
637 &dev
->core
->i2c_adap
);
640 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T
:
641 dev
->ts_gen_cntrl
= 0x08;
643 /* Do a hardware reset of chip before using it. */
644 struct cx88_core
*core
= dev
->core
;
646 cx_clear(MO_GP0_IO
, 1);
648 cx_set(MO_GP0_IO
, 9);
650 dev
->core
->pll_addr
= 0x61;
651 dev
->core
->pll_desc
= &dvb_pll_thomson_dtt761x
;
652 dev
->dvb
.frontend
= lgdt330x_attach(&fusionhdtv_3_gold
,
653 &dev
->core
->i2c_adap
);
656 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD
:
657 dev
->ts_gen_cntrl
= 0x08;
659 /* Do a hardware reset of chip before using it. */
660 struct cx88_core
*core
= dev
->core
;
662 cx_clear(MO_GP0_IO
, 1);
664 cx_set(MO_GP0_IO
, 1);
666 dev
->core
->pll_addr
= 0x61;
667 dev
->core
->pll_desc
= &dvb_pll_tdvs_tua6034
;
668 dev
->dvb
.frontend
= lgdt330x_attach(&fusionhdtv_5_gold
,
669 &dev
->core
->i2c_adap
);
672 case CX88_BOARD_PCHDTV_HD5500
:
673 dev
->ts_gen_cntrl
= 0x08;
675 /* Do a hardware reset of chip before using it. */
676 struct cx88_core
*core
= dev
->core
;
678 cx_clear(MO_GP0_IO
, 1);
680 cx_set(MO_GP0_IO
, 1);
682 dev
->core
->pll_addr
= 0x61;
683 dev
->core
->pll_desc
= &dvb_pll_tdvs_tua6034
;
684 dev
->dvb
.frontend
= lgdt330x_attach(&pchdtv_hd5500
,
685 &dev
->core
->i2c_adap
);
690 case CX88_BOARD_ATI_HDTVWONDER
:
691 dev
->dvb
.frontend
= nxt200x_attach(&ati_hdtvwonder
,
692 &dev
->core
->i2c_adap
);
696 case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1
:
697 case CX88_BOARD_HAUPPAUGE_NOVASE2_S1
:
698 dev
->dvb
.frontend
= cx24123_attach(&hauppauge_novas_config
,
699 &dev
->core
->i2c_adap
);
701 case CX88_BOARD_KWORLD_DVBS_100
:
702 dev
->dvb
.frontend
= cx24123_attach(&kworld_dvbs_100_config
,
703 &dev
->core
->i2c_adap
);
707 printk("%s: The frontend of your DVB/ATSC card isn't supported yet\n",
711 if (NULL
== dev
->dvb
.frontend
) {
712 printk("%s: frontend initialization failed\n",dev
->core
->name
);
716 if (dev
->core
->pll_desc
) {
717 dev
->dvb
.frontend
->ops
->info
.frequency_min
= dev
->core
->pll_desc
->min
;
718 dev
->dvb
.frontend
->ops
->info
.frequency_max
= dev
->core
->pll_desc
->max
;
721 /* Put the analog decoder in standby to keep it quiet */
722 cx88_call_i2c_clients (dev
->core
, TUNER_SET_STANDBY
, NULL
);
724 /* register everything */
725 return videobuf_dvb_register(&dev
->dvb
, THIS_MODULE
, dev
, &dev
->pci
->dev
);
728 /* ----------------------------------------------------------- */
730 static int __devinit
dvb_probe(struct pci_dev
*pci_dev
,
731 const struct pci_device_id
*pci_id
)
733 struct cx8802_dev
*dev
;
734 struct cx88_core
*core
;
738 core
= cx88_core_get(pci_dev
);
743 if (!cx88_boards
[core
->board
].dvb
)
747 dev
= kzalloc(sizeof(*dev
),GFP_KERNEL
);
753 err
= cx8802_init_common(dev
);
757 #ifdef HAVE_VP3054_I2C
758 err
= vp3054_i2c_probe(dev
);
764 printk("%s/2: cx2388x based dvb card\n", core
->name
);
765 videobuf_queue_init(&dev
->dvb
.dvbq
, &dvb_qops
,
766 dev
->pci
, &dev
->slock
,
767 V4L2_BUF_TYPE_VIDEO_CAPTURE
,
769 sizeof(struct cx88_buffer
),
771 err
= dvb_register(dev
);
775 /* Maintain a reference to cx88-video can query the 8802 device. */
780 cx8802_fini_common(dev
);
784 cx88_core_put(core
,pci_dev
);
788 static void __devexit
dvb_remove(struct pci_dev
*pci_dev
)
790 struct cx8802_dev
*dev
= pci_get_drvdata(pci_dev
);
792 /* Destroy any 8802 reference. */
793 dev
->core
->dvbdev
= NULL
;
796 videobuf_dvb_unregister(&dev
->dvb
);
798 #ifdef HAVE_VP3054_I2C
799 vp3054_i2c_remove(dev
);
803 cx8802_fini_common(dev
);
804 cx88_core_put(dev
->core
,dev
->pci
);
808 static struct pci_device_id cx8802_pci_tbl
[] = {
812 .subvendor
= PCI_ANY_ID
,
813 .subdevice
= PCI_ANY_ID
,
815 /* --- end of list --- */
818 MODULE_DEVICE_TABLE(pci
, cx8802_pci_tbl
);
820 static struct pci_driver dvb_pci_driver
= {
822 .id_table
= cx8802_pci_tbl
,
824 .remove
= __devexit_p(dvb_remove
),
825 .suspend
= cx8802_suspend_common
,
826 .resume
= cx8802_resume_common
,
829 static int dvb_init(void)
831 printk(KERN_INFO
"cx2388x dvb driver version %d.%d.%d loaded\n",
832 (CX88_VERSION_CODE
>> 16) & 0xff,
833 (CX88_VERSION_CODE
>> 8) & 0xff,
834 CX88_VERSION_CODE
& 0xff);
836 printk(KERN_INFO
"cx2388x: snapshot date %04d-%02d-%02d\n",
837 SNAPSHOT
/10000, (SNAPSHOT
/100)%100, SNAPSHOT
%100);
839 return pci_register_driver(&dvb_pci_driver
);
842 static void dvb_fini(void)
844 pci_unregister_driver(&dvb_pci_driver
);
847 module_init(dvb_init
);
848 module_exit(dvb_fini
);
853 * compile-command: "make DVB=1"