arch/arm/plat-orion/gpio.c

   1 /*
   2  * arch/arm/plat-orion/gpio.c
   3  *
   4  * Marvell Orion SoC GPIO handling.
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/irq.h>
  14 #include <linux/module.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/bitops.h>
  17 #include <linux/io.h>
  18 #include <asm/gpio.h>
  19
  20 static DEFINE_SPINLOCK(gpio_lock);
  21 static const char *gpio_label[GPIO_MAX];  /* non null for allocated GPIOs */
  22 static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
  23 static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
  24
  25 static inline void __set_direction(unsigned pin, int input)
  26 {
  27         u32 u;
  28
  29         u = readl(GPIO_IO_CONF(pin));
  30         if (input)
  31                 u |= 1 << (pin & 31);
  32         else
  33                 u &= ~(1 << (pin & 31));
  34         writel(u, GPIO_IO_CONF(pin));
  35 }
  36
  37 static void __set_level(unsigned pin, int high)
  38 {
  39         u32 u;
  40
  41         u = readl(GPIO_OUT(pin));
  42         if (high)
  43                 u |= 1 << (pin & 31);
  44         else
  45                 u &= ~(1 << (pin & 31));
  46         writel(u, GPIO_OUT(pin));
  47 }
  48
  49
  50 /*
  51  * GENERIC_GPIO primitives.
  52  */
  53 int gpio_direction_input(unsigned pin)
  54 {
  55         unsigned long flags;
  56
  57         if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid_input)) {
  58                 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
  59                 return -EINVAL;
  60         }
  61
  62         spin_lock_irqsave(&gpio_lock, flags);
  63
  64         /*
  65          * Some callers might not have used gpio_request(),
  66          * so flag this pin as requested now.
  67          */
  68         if (gpio_label[pin] == NULL)
  69                 gpio_label[pin] = "?";
  70
  71         /*
  72          * Configure GPIO direction.
  73          */
  74         __set_direction(pin, 1);
  75
  76         spin_unlock_irqrestore(&gpio_lock, flags);
  77
  78         return 0;
  79 }
  80 EXPORT_SYMBOL(gpio_direction_input);
  81
  82 int gpio_direction_output(unsigned pin, int value)
  83 {
  84         unsigned long flags;
  85         u32 u;
  86
  87         if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid_output)) {
  88                 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
  89                 return -EINVAL;
  90         }
  91
  92         spin_lock_irqsave(&gpio_lock, flags);
  93
  94         /*
  95          * Some callers might not have used gpio_request(),
  96          * so flag this pin as requested now.
  97          */
  98         if (gpio_label[pin] == NULL)
  99                 gpio_label[pin] = "?";
 100
 101         /*
 102          * Disable blinking.
 103          */
 104         u = readl(GPIO_BLINK_EN(pin));
 105         u &= ~(1 << (pin & 31));
 106         writel(u, GPIO_BLINK_EN(pin));
 107
 108         /*
 109          * Configure GPIO output value.
 110          */
 111         __set_level(pin, value);
 112
 113         /*
 114          * Configure GPIO direction.
 115          */
 116         __set_direction(pin, 0);
 117
 118         spin_unlock_irqrestore(&gpio_lock, flags);
 119
 120         return 0;
 121 }
 122 EXPORT_SYMBOL(gpio_direction_output);
 123
 124 int gpio_get_value(unsigned pin)
 125 {
 126         int val;
 127
 128         if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)))
 129                 val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin));
 130         else
 131                 val = readl(GPIO_OUT(pin));
 132
 133         return (val >> (pin & 31)) & 1;
 134 }
 135 EXPORT_SYMBOL(gpio_get_value);
 136
 137 void gpio_set_value(unsigned pin, int value)
 138 {
 139         unsigned long flags;
 140         u32 u;
 141
 142         spin_lock_irqsave(&gpio_lock, flags);
 143
 144         /*
 145          * Disable blinking.
 146          */
 147         u = readl(GPIO_BLINK_EN(pin));
 148         u &= ~(1 << (pin & 31));
 149         writel(u, GPIO_BLINK_EN(pin));
 150
 151         /*
 152          * Configure GPIO output value.
 153          */
 154         __set_level(pin, value);
 155
 156         spin_unlock_irqrestore(&gpio_lock, flags);
 157 }
 158 EXPORT_SYMBOL(gpio_set_value);
 159
 160 int gpio_request(unsigned pin, const char *label)
 161 {
 162         unsigned long flags;
 163         int ret;
 164
 165         if (pin >= GPIO_MAX ||
 166             !(test_bit(pin, gpio_valid_input) ||
 167               test_bit(pin, gpio_valid_output))) {
 168                 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
 169                 return -EINVAL;
 170         }
 171
 172         spin_lock_irqsave(&gpio_lock, flags);
 173         if (gpio_label[pin] == NULL) {
 174                 gpio_label[pin] = label ? label : "?";
 175                 ret = 0;
 176         } else {
 177                 pr_debug("%s: GPIO %d already used as %s\n",
 178                          __func__, pin, gpio_label[pin]);
 179                 ret = -EBUSY;
 180         }
 181         spin_unlock_irqrestore(&gpio_lock, flags);
 182
 183         return ret;
 184 }
 185 EXPORT_SYMBOL(gpio_request);
 186
 187 void gpio_free(unsigned pin)
 188 {
 189         if (pin >= GPIO_MAX ||
 190             !(test_bit(pin, gpio_valid_input) ||
 191               test_bit(pin, gpio_valid_output))) {
 192                 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
 193                 return;
 194         }
 195
 196         if (gpio_label[pin] == NULL)
 197                 pr_warning("%s: GPIO %d already freed\n", __func__, pin);
 198         else
 199                 gpio_label[pin] = NULL;
 200 }
 201 EXPORT_SYMBOL(gpio_free);
 202
 203
 204 /*
 205  * Orion-specific GPIO API extensions.
 206  */
 207 void __init orion_gpio_set_unused(unsigned pin)
 208 {
 209         /*
 210          * Configure as output, drive low.
 211          */
 212         __set_level(pin, 0);
 213         __set_direction(pin, 0);
 214 }
 215
 216 void __init orion_gpio_set_valid(unsigned pin, int mode)
 217 {
 218         if (mode == 1)
 219                 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
 220         if (mode & GPIO_INPUT_OK)
 221                 __set_bit(pin, gpio_valid_input);
 222         else
 223                 __clear_bit(pin, gpio_valid_input);
 224         if (mode & GPIO_OUTPUT_OK)
 225                 __set_bit(pin, gpio_valid_output);
 226         else
 227                 __clear_bit(pin, gpio_valid_output);
 228 }
 229
 230 void orion_gpio_set_blink(unsigned pin, int blink)
 231 {
 232         unsigned long flags;
 233         u32 u;
 234
 235         spin_lock_irqsave(&gpio_lock, flags);
 236
 237         /*
 238          * Set output value to zero.
 239          */
 240         __set_level(pin, 0);
 241
 242         u = readl(GPIO_BLINK_EN(pin));
 243         if (blink)
 244                 u |= 1 << (pin & 31);
 245         else
 246                 u &= ~(1 << (pin & 31));
 247         writel(u, GPIO_BLINK_EN(pin));
 248
 249         spin_unlock_irqrestore(&gpio_lock, flags);
 250 }
 251 EXPORT_SYMBOL(orion_gpio_set_blink);
 252
 253
 254 /*****************************************************************************
 255  * Orion GPIO IRQ
 256  *
 257  * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
 258  * value of the line or the opposite value.
 259  *
 260  * Level IRQ handlers: DATA_IN is used directly as cause register.
 261  *                     Interrupt are masked by LEVEL_MASK registers.
 262  * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
 263  *                     Interrupt are masked by EDGE_MASK registers.
 264  * Both-edge handlers: Similar to regular Edge handlers, but also swaps
 265  *                     the polarity to catch the next line transaction.
 266  *                     This is a race condition that might not perfectly
 267  *                     work on some use cases.
 268  *
 269  * Every eight GPIO lines are grouped (OR'ed) before going up to main
 270  * cause register.
 271  *
 272  *                    EDGE  cause    mask
 273  *        data-in   /--------| |-----| |----\
 274  *     -----| |-----                         ---- to main cause reg
 275  *           X      \----------------| |----/
 276  *        polarity    LEVEL          mask
 277  *
 278  ****************************************************************************/
 279
 280 static void gpio_irq_ack(u32 irq)
 281 {
 282         int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
 283         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 284                 int pin = irq_to_gpio(irq);
 285                 writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
 286         }
 287 }
 288
 289 static void gpio_irq_mask(u32 irq)
 290 {
 291         int pin = irq_to_gpio(irq);
 292         int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
 293         u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
 294                 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
 295         u32 u = readl(reg);
 296         u &= ~(1 << (pin & 31));
 297         writel(u, reg);
 298 }
 299
 300 static void gpio_irq_unmask(u32 irq)
 301 {
 302         int pin = irq_to_gpio(irq);
 303         int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
 304         u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
 305                 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
 306         u32 u = readl(reg);
 307         u |= 1 << (pin & 31);
 308         writel(u, reg);
 309 }
 310
 311 static int gpio_irq_set_type(u32 irq, u32 type)
 312 {
 313         int pin = irq_to_gpio(irq);
 314         struct irq_desc *desc;
 315         u32 u;
 316
 317         u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31));
 318         if (!u) {
 319                 printk(KERN_ERR "orion gpio_irq_set_type failed "
 320                                 "(irq %d, pin %d).\n", irq, pin);
 321                 return -EINVAL;
 322         }
 323
 324         desc = irq_desc + irq;
 325
 326         /*
 327          * Set edge/level type.
 328          */
 329         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 330                 desc->handle_irq = handle_edge_irq;
 331         } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 332                 desc->handle_irq = handle_level_irq;
 333         } else {
 334                 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
 335                 return -EINVAL;
 336         }
 337
 338         /*
 339          * Configure interrupt polarity.
 340          */
 341         if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
 342                 u = readl(GPIO_IN_POL(pin));
 343                 u &= ~(1 << (pin & 31));
 344                 writel(u, GPIO_IN_POL(pin));
 345         } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
 346                 u = readl(GPIO_IN_POL(pin));
 347                 u |= 1 << (pin & 31);
 348                 writel(u, GPIO_IN_POL(pin));
 349         } else if (type == IRQ_TYPE_EDGE_BOTH) {
 350                 u32 v;
 351
 352                 v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin));
 353
 354                 /*
 355                  * set initial polarity based on current input level
 356                  */
 357                 u = readl(GPIO_IN_POL(pin));
 358                 if (v & (1 << (pin & 31)))
 359                         u |= 1 << (pin & 31);           /* falling */
 360                 else
 361                         u &= ~(1 << (pin & 31));        /* rising */
 362                 writel(u, GPIO_IN_POL(pin));
 363         }
 364
 365         desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) | type;
 366
 367         return 0;
 368 }
 369
 370 struct irq_chip orion_gpio_irq_chip = {
 371         .name           = "orion_gpio",
 372         .ack            = gpio_irq_ack,
 373         .mask           = gpio_irq_mask,
 374         .unmask         = gpio_irq_unmask,
 375         .set_type       = gpio_irq_set_type,
 376 };
 377
 378 void orion_gpio_irq_handler(int pinoff)
 379 {
 380         u32 cause;
 381         int pin;
 382
 383         cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff));
 384         cause |= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff));
 385
 386         for (pin = pinoff; pin < pinoff + 8; pin++) {
 387                 int irq = gpio_to_irq(pin);
 388                 struct irq_desc *desc = irq_desc + irq;
 389
 390                 if (!(cause & (1 << (pin & 31))))
 391                         continue;
 392
 393                 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 394                         /* Swap polarity (race with GPIO line) */
 395                         u32 polarity;
 396
 397                         polarity = readl(GPIO_IN_POL(pin));
 398                         polarity ^= 1 << (pin & 31);
 399                         writel(polarity, GPIO_IN_POL(pin));
 400                 }
 401                 desc_handle_irq(irq, desc);
 402         }
 403 }