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spi/pxa2xx: Consider CE4100's FIFO depth
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / spi / pxa2xx_spi.c
blob81cfbbc58e94aef54f4d2ad7f342849276e1246a
1 /*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/spi/pxa2xx_spi.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/spi/spi.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/gpio.h>
32 #include <linux/slab.h>
33
34 #include <asm/io.h>
35 #include <asm/irq.h>
36 #include <asm/delay.h>
37
38
39 MODULE_AUTHOR("Stephen Street");
40 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
41 MODULE_LICENSE("GPL");
42 MODULE_ALIAS("platform:pxa2xx-spi");
43
44 #define MAX_BUSES 3
45
46 #define TIMOUT_DFLT 1000
47
48 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
49 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
50 #define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0)
51 #define MAX_DMA_LEN 8191
52 #define DMA_ALIGNMENT 8
53
54 /*
55 * for testing SSCR1 changes that require SSP restart, basically
56 * everything except the service and interrupt enables, the pxa270 developer
57 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
58 * list, but the PXA255 dev man says all bits without really meaning the
59 * service and interrupt enables
60 */
61 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
62 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
63 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
64 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
65 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
66 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
67
68 #define DEFINE_SSP_REG(reg, off) \
69 static inline u32 read_##reg(void const __iomem *p) \
70 { return __raw_readl(p + (off)); } \
71 \
72 static inline void write_##reg(u32 v, void __iomem *p) \
73 { __raw_writel(v, p + (off)); }
74
75 DEFINE_SSP_REG(SSCR0, 0x00)
76 DEFINE_SSP_REG(SSCR1, 0x04)
77 DEFINE_SSP_REG(SSSR, 0x08)
78 DEFINE_SSP_REG(SSITR, 0x0c)
79 DEFINE_SSP_REG(SSDR, 0x10)
80 DEFINE_SSP_REG(SSTO, 0x28)
81 DEFINE_SSP_REG(SSPSP, 0x2c)
82
83 #define START_STATE ((void*)0)
84 #define RUNNING_STATE ((void*)1)
85 #define DONE_STATE ((void*)2)
86 #define ERROR_STATE ((void*)-1)
87
88 #define QUEUE_RUNNING 0
89 #define QUEUE_STOPPED 1
90
91 struct driver_data {
92 /* Driver model hookup */
93 struct platform_device *pdev;
94
95 /* SSP Info */
96 struct ssp_device *ssp;
97
98 /* SPI framework hookup */
99 enum pxa_ssp_type ssp_type;
100 struct spi_master *master;
101
102 /* PXA hookup */
103 struct pxa2xx_spi_master *master_info;
104
105 /* DMA setup stuff */
106 int rx_channel;
107 int tx_channel;
108 u32 *null_dma_buf;
109
110 /* SSP register addresses */
111 void __iomem *ioaddr;
112 u32 ssdr_physical;
113
114 /* SSP masks*/
115 u32 dma_cr1;
116 u32 int_cr1;
117 u32 clear_sr;
118 u32 mask_sr;
119
120 /* Driver message queue */
121 struct workqueue_struct *workqueue;
122 struct work_struct pump_messages;
123 spinlock_t lock;
124 struct list_head queue;
125 int busy;
126 int run;
127
128 /* Message Transfer pump */
129 struct tasklet_struct pump_transfers;
130
131 /* Current message transfer state info */
132 struct spi_message* cur_msg;
133 struct spi_transfer* cur_transfer;
134 struct chip_data *cur_chip;
135 size_t len;
136 void *tx;
137 void *tx_end;
138 void *rx;
139 void *rx_end;
140 int dma_mapped;
141 dma_addr_t rx_dma;
142 dma_addr_t tx_dma;
143 size_t rx_map_len;
144 size_t tx_map_len;
145 u8 n_bytes;
146 u32 dma_width;
147 int (*write)(struct driver_data *drv_data);
148 int (*read)(struct driver_data *drv_data);
149 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
150 void (*cs_control)(u32 command);
151 };
152
153 struct chip_data {
154 u32 cr0;
155 u32 cr1;
156 u32 psp;
157 u32 timeout;
158 u8 n_bytes;
159 u32 dma_width;
160 u32 dma_burst_size;
161 u32 threshold;
162 u32 dma_threshold;
163 u8 enable_dma;
164 u8 bits_per_word;
165 u32 speed_hz;
166 int gpio_cs;
167 int gpio_cs_inverted;
168 int (*write)(struct driver_data *drv_data);
169 int (*read)(struct driver_data *drv_data);
170 void (*cs_control)(u32 command);
171 };
172
173 static void pump_messages(struct work_struct *work);
174
175 static void cs_assert(struct driver_data *drv_data)
176 {
177 struct chip_data *chip = drv_data->cur_chip;
178
179 if (chip->cs_control) {
180 chip->cs_control(PXA2XX_CS_ASSERT);
181 return;
182 }
183
184 if (gpio_is_valid(chip->gpio_cs))
185 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
186 }
187
188 static void cs_deassert(struct driver_data *drv_data)
189 {
190 struct chip_data *chip = drv_data->cur_chip;
191
192 if (chip->cs_control) {
193 chip->cs_control(PXA2XX_CS_DEASSERT);
194 return;
195 }
196
197 if (gpio_is_valid(chip->gpio_cs))
198 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
199 }
200
201 static int flush(struct driver_data *drv_data)
202 {
203 unsigned long limit = loops_per_jiffy << 1;
204
205 void __iomem *reg = drv_data->ioaddr;
206
207 do {
208 while (read_SSSR(reg) & SSSR_RNE) {
209 read_SSDR(reg);
210 }
211 } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
212 write_SSSR(SSSR_ROR, reg);
213
214 return limit;
215 }
216
217 static int null_writer(struct driver_data *drv_data)
218 {
219 void __iomem *reg = drv_data->ioaddr;
220 u8 n_bytes = drv_data->n_bytes;
221
222 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
223 || (drv_data->tx == drv_data->tx_end))
224 return 0;
225
226 write_SSDR(0, reg);
227 drv_data->tx += n_bytes;
228
229 return 1;
230 }
231
232 static int null_reader(struct driver_data *drv_data)
233 {
234 void __iomem *reg = drv_data->ioaddr;
235 u8 n_bytes = drv_data->n_bytes;
236
237 while ((read_SSSR(reg) & SSSR_RNE)
238 && (drv_data->rx < drv_data->rx_end)) {
239 read_SSDR(reg);
240 drv_data->rx += n_bytes;
241 }
242
243 return drv_data->rx == drv_data->rx_end;
244 }
245
246 static int u8_writer(struct driver_data *drv_data)
247 {
248 void __iomem *reg = drv_data->ioaddr;
249
250 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
251 || (drv_data->tx == drv_data->tx_end))
252 return 0;
253
254 write_SSDR(*(u8 *)(drv_data->tx), reg);
255 ++drv_data->tx;
256
257 return 1;
258 }
259
260 static int u8_reader(struct driver_data *drv_data)
261 {
262 void __iomem *reg = drv_data->ioaddr;
263
264 while ((read_SSSR(reg) & SSSR_RNE)
265 && (drv_data->rx < drv_data->rx_end)) {
266 *(u8 *)(drv_data->rx) = read_SSDR(reg);
267 ++drv_data->rx;
268 }
269
270 return drv_data->rx == drv_data->rx_end;
271 }
272
273 static int u16_writer(struct driver_data *drv_data)
274 {
275 void __iomem *reg = drv_data->ioaddr;
276
277 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
278 || (drv_data->tx == drv_data->tx_end))
279 return 0;
280
281 write_SSDR(*(u16 *)(drv_data->tx), reg);
282 drv_data->tx += 2;
283
284 return 1;
285 }
286
287 static int u16_reader(struct driver_data *drv_data)
288 {
289 void __iomem *reg = drv_data->ioaddr;
290
291 while ((read_SSSR(reg) & SSSR_RNE)
292 && (drv_data->rx < drv_data->rx_end)) {
293 *(u16 *)(drv_data->rx) = read_SSDR(reg);
294 drv_data->rx += 2;
295 }
296
297 return drv_data->rx == drv_data->rx_end;
298 }
299
300 static int u32_writer(struct driver_data *drv_data)
301 {
302 void __iomem *reg = drv_data->ioaddr;
303
304 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
305 || (drv_data->tx == drv_data->tx_end))
306 return 0;
307
308 write_SSDR(*(u32 *)(drv_data->tx), reg);
309 drv_data->tx += 4;
310
311 return 1;
312 }
313
314 static int u32_reader(struct driver_data *drv_data)
315 {
316 void __iomem *reg = drv_data->ioaddr;
317
318 while ((read_SSSR(reg) & SSSR_RNE)
319 && (drv_data->rx < drv_data->rx_end)) {
320 *(u32 *)(drv_data->rx) = read_SSDR(reg);
321 drv_data->rx += 4;
322 }
323
324 return drv_data->rx == drv_data->rx_end;
325 }
326
327 static void *next_transfer(struct driver_data *drv_data)
328 {
329 struct spi_message *msg = drv_data->cur_msg;
330 struct spi_transfer *trans = drv_data->cur_transfer;
331
332 /* Move to next transfer */
333 if (trans->transfer_list.next != &msg->transfers) {
334 drv_data->cur_transfer =
335 list_entry(trans->transfer_list.next,
336 struct spi_transfer,
337 transfer_list);
338 return RUNNING_STATE;
339 } else
340 return DONE_STATE;
341 }
342
343 static int map_dma_buffers(struct driver_data *drv_data)
344 {
345 struct spi_message *msg = drv_data->cur_msg;
346 struct device *dev = &msg->spi->dev;
347
348 if (!drv_data->cur_chip->enable_dma)
349 return 0;
350
351 if (msg->is_dma_mapped)
352 return drv_data->rx_dma && drv_data->tx_dma;
353
354 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
355 return 0;
356
357 /* Modify setup if rx buffer is null */
358 if (drv_data->rx == NULL) {
359 *drv_data->null_dma_buf = 0;
360 drv_data->rx = drv_data->null_dma_buf;
361 drv_data->rx_map_len = 4;
362 } else
363 drv_data->rx_map_len = drv_data->len;
364
365
366 /* Modify setup if tx buffer is null */
367 if (drv_data->tx == NULL) {
368 *drv_data->null_dma_buf = 0;
369 drv_data->tx = drv_data->null_dma_buf;
370 drv_data->tx_map_len = 4;
371 } else
372 drv_data->tx_map_len = drv_data->len;
373
374 /* Stream map the tx buffer. Always do DMA_TO_DEVICE first
375 * so we flush the cache *before* invalidating it, in case
376 * the tx and rx buffers overlap.
377 */
378 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
379 drv_data->tx_map_len, DMA_TO_DEVICE);
380 if (dma_mapping_error(dev, drv_data->tx_dma))
381 return 0;
382
383 /* Stream map the rx buffer */
384 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
385 drv_data->rx_map_len, DMA_FROM_DEVICE);
386 if (dma_mapping_error(dev, drv_data->rx_dma)) {
387 dma_unmap_single(dev, drv_data->tx_dma,
388 drv_data->tx_map_len, DMA_TO_DEVICE);
389 return 0;
390 }
391
392 return 1;
393 }
394
395 static void unmap_dma_buffers(struct driver_data *drv_data)
396 {
397 struct device *dev;
398
399 if (!drv_data->dma_mapped)
400 return;
401
402 if (!drv_data->cur_msg->is_dma_mapped) {
403 dev = &drv_data->cur_msg->spi->dev;
404 dma_unmap_single(dev, drv_data->rx_dma,
405 drv_data->rx_map_len, DMA_FROM_DEVICE);
406 dma_unmap_single(dev, drv_data->tx_dma,
407 drv_data->tx_map_len, DMA_TO_DEVICE);
408 }
409
410 drv_data->dma_mapped = 0;
411 }
412
413 /* caller already set message->status; dma and pio irqs are blocked */
414 static void giveback(struct driver_data *drv_data)
415 {
416 struct spi_transfer* last_transfer;
417 unsigned long flags;
418 struct spi_message *msg;
419
420 spin_lock_irqsave(&drv_data->lock, flags);
421 msg = drv_data->cur_msg;
422 drv_data->cur_msg = NULL;
423 drv_data->cur_transfer = NULL;
424 queue_work(drv_data->workqueue, &drv_data->pump_messages);
425 spin_unlock_irqrestore(&drv_data->lock, flags);
426
427 last_transfer = list_entry(msg->transfers.prev,
428 struct spi_transfer,
429 transfer_list);
430
431 /* Delay if requested before any change in chip select */
432 if (last_transfer->delay_usecs)
433 udelay(last_transfer->delay_usecs);
434
435 /* Drop chip select UNLESS cs_change is true or we are returning
436 * a message with an error, or next message is for another chip
437 */
438 if (!last_transfer->cs_change)
439 cs_deassert(drv_data);
440 else {
441 struct spi_message *next_msg;
442
443 /* Holding of cs was hinted, but we need to make sure
444 * the next message is for the same chip. Don't waste
445 * time with the following tests unless this was hinted.
446 *
447 * We cannot postpone this until pump_messages, because
448 * after calling msg->complete (below) the driver that
449 * sent the current message could be unloaded, which
450 * could invalidate the cs_control() callback...
451 */
452
453 /* get a pointer to the next message, if any */
454 spin_lock_irqsave(&drv_data->lock, flags);
455 if (list_empty(&drv_data->queue))
456 next_msg = NULL;
457 else
458 next_msg = list_entry(drv_data->queue.next,
459 struct spi_message, queue);
460 spin_unlock_irqrestore(&drv_data->lock, flags);
461
462 /* see if the next and current messages point
463 * to the same chip
464 */
465 if (next_msg && next_msg->spi != msg->spi)
466 next_msg = NULL;
467 if (!next_msg || msg->state == ERROR_STATE)
468 cs_deassert(drv_data);
469 }
470
471 msg->state = NULL;
472 if (msg->complete)
473 msg->complete(msg->context);
474
475 drv_data->cur_chip = NULL;
476 }
477
478 static int wait_ssp_rx_stall(void const __iomem *ioaddr)
479 {
480 unsigned long limit = loops_per_jiffy << 1;
481
482 while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit)
483 cpu_relax();
484
485 return limit;
486 }
487
488 static int wait_dma_channel_stop(int channel)
489 {
490 unsigned long limit = loops_per_jiffy << 1;
491
492 while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit)
493 cpu_relax();
494
495 return limit;
496 }
497
498 static void dma_error_stop(struct driver_data *drv_data, const char *msg)
499 {
500 void __iomem *reg = drv_data->ioaddr;
501
502 /* Stop and reset */
503 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
504 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
505 write_SSSR(drv_data->clear_sr, reg);
506 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
507 if (drv_data->ssp_type != PXA25x_SSP)
508 write_SSTO(0, reg);
509 flush(drv_data);
510 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
511
512 unmap_dma_buffers(drv_data);
513
514 dev_err(&drv_data->pdev->dev, "%s\n", msg);
515
516 drv_data->cur_msg->state = ERROR_STATE;
517 tasklet_schedule(&drv_data->pump_transfers);
518 }
519
520 static void dma_transfer_complete(struct driver_data *drv_data)
521 {
522 void __iomem *reg = drv_data->ioaddr;
523 struct spi_message *msg = drv_data->cur_msg;
524
525 /* Clear and disable interrupts on SSP and DMA channels*/
526 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
527 write_SSSR(drv_data->clear_sr, reg);
528 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
529 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
530
531 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
532 dev_err(&drv_data->pdev->dev,
533 "dma_handler: dma rx channel stop failed\n");
534
535 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
536 dev_err(&drv_data->pdev->dev,
537 "dma_transfer: ssp rx stall failed\n");
538
539 unmap_dma_buffers(drv_data);
540
541 /* update the buffer pointer for the amount completed in dma */
542 drv_data->rx += drv_data->len -
543 (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
544
545 /* read trailing data from fifo, it does not matter how many
546 * bytes are in the fifo just read until buffer is full
547 * or fifo is empty, which ever occurs first */
548 drv_data->read(drv_data);
549
550 /* return count of what was actually read */
551 msg->actual_length += drv_data->len -
552 (drv_data->rx_end - drv_data->rx);
553
554 /* Transfer delays and chip select release are
555 * handled in pump_transfers or giveback
556 */
557
558 /* Move to next transfer */
559 msg->state = next_transfer(drv_data);
560
561 /* Schedule transfer tasklet */
562 tasklet_schedule(&drv_data->pump_transfers);
563 }
564
565 static void dma_handler(int channel, void *data)
566 {
567 struct driver_data *drv_data = data;
568 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
569
570 if (irq_status & DCSR_BUSERR) {
571
572 if (channel == drv_data->tx_channel)
573 dma_error_stop(drv_data,
574 "dma_handler: "
575 "bad bus address on tx channel");
576 else
577 dma_error_stop(drv_data,
578 "dma_handler: "
579 "bad bus address on rx channel");
580 return;
581 }
582
583 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
584 if ((channel == drv_data->tx_channel)
585 && (irq_status & DCSR_ENDINTR)
586 && (drv_data->ssp_type == PXA25x_SSP)) {
587
588 /* Wait for rx to stall */
589 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
590 dev_err(&drv_data->pdev->dev,
591 "dma_handler: ssp rx stall failed\n");
592
593 /* finish this transfer, start the next */
594 dma_transfer_complete(drv_data);
595 }
596 }
597
598 static irqreturn_t dma_transfer(struct driver_data *drv_data)
599 {
600 u32 irq_status;
601 void __iomem *reg = drv_data->ioaddr;
602
603 irq_status = read_SSSR(reg) & drv_data->mask_sr;
604 if (irq_status & SSSR_ROR) {
605 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
606 return IRQ_HANDLED;
607 }
608
609 /* Check for false positive timeout */
610 if ((irq_status & SSSR_TINT)
611 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
612 write_SSSR(SSSR_TINT, reg);
613 return IRQ_HANDLED;
614 }
615
616 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
617
618 /* Clear and disable timeout interrupt, do the rest in
619 * dma_transfer_complete */
620 if (drv_data->ssp_type != PXA25x_SSP)
621 write_SSTO(0, reg);
622
623 /* finish this transfer, start the next */
624 dma_transfer_complete(drv_data);
625
626 return IRQ_HANDLED;
627 }
628
629 /* Opps problem detected */
630 return IRQ_NONE;
631 }
632
633 static void int_error_stop(struct driver_data *drv_data, const char* msg)
634 {
635 void __iomem *reg = drv_data->ioaddr;
636
637 /* Stop and reset SSP */
638 write_SSSR(drv_data->clear_sr, reg);
639 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
640 if (drv_data->ssp_type != PXA25x_SSP)
641 write_SSTO(0, reg);
642 flush(drv_data);
643 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
644
645 dev_err(&drv_data->pdev->dev, "%s\n", msg);
646
647 drv_data->cur_msg->state = ERROR_STATE;
648 tasklet_schedule(&drv_data->pump_transfers);
649 }
650
651 static void int_transfer_complete(struct driver_data *drv_data)
652 {
653 void __iomem *reg = drv_data->ioaddr;
654
655 /* Stop SSP */
656 write_SSSR(drv_data->clear_sr, reg);
657 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
658 if (drv_data->ssp_type != PXA25x_SSP)
659 write_SSTO(0, reg);
660
661 /* Update total byte transfered return count actual bytes read */
662 drv_data->cur_msg->actual_length += drv_data->len -
663 (drv_data->rx_end - drv_data->rx);
664
665 /* Transfer delays and chip select release are
666 * handled in pump_transfers or giveback
667 */
668
669 /* Move to next transfer */
670 drv_data->cur_msg->state = next_transfer(drv_data);
671
672 /* Schedule transfer tasklet */
673 tasklet_schedule(&drv_data->pump_transfers);
674 }
675
676 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
677 {
678 void __iomem *reg = drv_data->ioaddr;
679
680 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
681 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
682
683 u32 irq_status = read_SSSR(reg) & irq_mask;
684
685 if (irq_status & SSSR_ROR) {
686 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
687 return IRQ_HANDLED;
688 }
689
690 if (irq_status & SSSR_TINT) {
691 write_SSSR(SSSR_TINT, reg);
692 if (drv_data->read(drv_data)) {
693 int_transfer_complete(drv_data);
694 return IRQ_HANDLED;
695 }
696 }
697
698 /* Drain rx fifo, Fill tx fifo and prevent overruns */
699 do {
700 if (drv_data->read(drv_data)) {
701 int_transfer_complete(drv_data);
702 return IRQ_HANDLED;
703 }
704 } while (drv_data->write(drv_data));
705
706 if (drv_data->read(drv_data)) {
707 int_transfer_complete(drv_data);
708 return IRQ_HANDLED;
709 }
710
711 if (drv_data->tx == drv_data->tx_end) {
712 write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
713 /* PXA25x_SSP has no timeout, read trailing bytes */
714 if (drv_data->ssp_type == PXA25x_SSP) {
715 if (!wait_ssp_rx_stall(reg))
716 {
717 int_error_stop(drv_data, "interrupt_transfer: "
718 "rx stall failed");
719 return IRQ_HANDLED;
720 }
721 if (!drv_data->read(drv_data))
722 {
723 int_error_stop(drv_data,
724 "interrupt_transfer: "
725 "trailing byte read failed");
726 return IRQ_HANDLED;
727 }
728 int_transfer_complete(drv_data);
729 }
730 }
731
732 /* We did something */
733 return IRQ_HANDLED;
734 }
735
736 static irqreturn_t ssp_int(int irq, void *dev_id)
737 {
738 struct driver_data *drv_data = dev_id;
739 void __iomem *reg = drv_data->ioaddr;
740 u32 sccr1_reg = read_SSCR1(reg);
741 u32 mask = drv_data->mask_sr;
742 u32 status;
743
744 status = read_SSSR(reg);
745
746 /* Ignore possible writes if we don't need to write */
747 if (!(sccr1_reg & SSCR1_TIE))
748 mask &= ~SSSR_TFS;
749
750 if (!(status & mask))
751 return IRQ_NONE;
752
753 if (!drv_data->cur_msg) {
754
755 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
756 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
757 if (drv_data->ssp_type != PXA25x_SSP)
758 write_SSTO(0, reg);
759 write_SSSR(drv_data->clear_sr, reg);
760
761 dev_err(&drv_data->pdev->dev, "bad message state "
762 "in interrupt handler\n");
763
764 /* Never fail */
765 return IRQ_HANDLED;
766 }
767
768 return drv_data->transfer_handler(drv_data);
769 }
770
771 static int set_dma_burst_and_threshold(struct chip_data *chip,
772 struct spi_device *spi,
773 u8 bits_per_word, u32 *burst_code,
774 u32 *threshold)
775 {
776 struct pxa2xx_spi_chip *chip_info =
777 (struct pxa2xx_spi_chip *)spi->controller_data;
778 int bytes_per_word;
779 int burst_bytes;
780 int thresh_words;
781 int req_burst_size;
782 int retval = 0;
783
784 /* Set the threshold (in registers) to equal the same amount of data
785 * as represented by burst size (in bytes). The computation below
786 * is (burst_size rounded up to nearest 8 byte, word or long word)
787 * divided by (bytes/register); the tx threshold is the inverse of
788 * the rx, so that there will always be enough data in the rx fifo
789 * to satisfy a burst, and there will always be enough space in the
790 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
791 * there is not enough space), there must always remain enough empty
792 * space in the rx fifo for any data loaded to the tx fifo.
793 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
794 * will be 8, or half the fifo;
795 * The threshold can only be set to 2, 4 or 8, but not 16, because
796 * to burst 16 to the tx fifo, the fifo would have to be empty;
797 * however, the minimum fifo trigger level is 1, and the tx will
798 * request service when the fifo is at this level, with only 15 spaces.
799 */
800
801 /* find bytes/word */
802 if (bits_per_word <= 8)
803 bytes_per_word = 1;
804 else if (bits_per_word <= 16)
805 bytes_per_word = 2;
806 else
807 bytes_per_word = 4;
808
809 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
810 if (chip_info)
811 req_burst_size = chip_info->dma_burst_size;
812 else {
813 switch (chip->dma_burst_size) {
814 default:
815 /* if the default burst size is not set,
816 * do it now */
817 chip->dma_burst_size = DCMD_BURST8;
818 case DCMD_BURST8:
819 req_burst_size = 8;
820 break;
821 case DCMD_BURST16:
822 req_burst_size = 16;
823 break;
824 case DCMD_BURST32:
825 req_burst_size = 32;
826 break;
827 }
828 }
829 if (req_burst_size <= 8) {
830 *burst_code = DCMD_BURST8;
831 burst_bytes = 8;
832 } else if (req_burst_size <= 16) {
833 if (bytes_per_word == 1) {
834 /* don't burst more than 1/2 the fifo */
835 *burst_code = DCMD_BURST8;
836 burst_bytes = 8;
837 retval = 1;
838 } else {
839 *burst_code = DCMD_BURST16;
840 burst_bytes = 16;
841 }
842 } else {
843 if (bytes_per_word == 1) {
844 /* don't burst more than 1/2 the fifo */
845 *burst_code = DCMD_BURST8;
846 burst_bytes = 8;
847 retval = 1;
848 } else if (bytes_per_word == 2) {
849 /* don't burst more than 1/2 the fifo */
850 *burst_code = DCMD_BURST16;
851 burst_bytes = 16;
852 retval = 1;
853 } else {
854 *burst_code = DCMD_BURST32;
855 burst_bytes = 32;
856 }
857 }
858
859 thresh_words = burst_bytes / bytes_per_word;
860
861 /* thresh_words will be between 2 and 8 */
862 *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
863 | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
864
865 return retval;
866 }
867
868 static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
869 {
870 unsigned long ssp_clk = clk_get_rate(ssp->clk);
871
872 if (ssp->type == PXA25x_SSP)
873 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
874 else
875 return ((ssp_clk / rate - 1) & 0xfff) << 8;
876 }
877
878 static void pump_transfers(unsigned long data)
879 {
880 struct driver_data *drv_data = (struct driver_data *)data;
881 struct spi_message *message = NULL;
882 struct spi_transfer *transfer = NULL;
883 struct spi_transfer *previous = NULL;
884 struct chip_data *chip = NULL;
885 struct ssp_device *ssp = drv_data->ssp;
886 void __iomem *reg = drv_data->ioaddr;
887 u32 clk_div = 0;
888 u8 bits = 0;
889 u32 speed = 0;
890 u32 cr0;
891 u32 cr1;
892 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
893 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
894
895 /* Get current state information */
896 message = drv_data->cur_msg;
897 transfer = drv_data->cur_transfer;
898 chip = drv_data->cur_chip;
899
900 /* Handle for abort */
901 if (message->state == ERROR_STATE) {
902 message->status = -EIO;
903 giveback(drv_data);
904 return;
905 }
906
907 /* Handle end of message */
908 if (message->state == DONE_STATE) {
909 message->status = 0;
910 giveback(drv_data);
911 return;
912 }
913
914 /* Delay if requested at end of transfer before CS change */
915 if (message->state == RUNNING_STATE) {
916 previous = list_entry(transfer->transfer_list.prev,
917 struct spi_transfer,
918 transfer_list);
919 if (previous->delay_usecs)
920 udelay(previous->delay_usecs);
921
922 /* Drop chip select only if cs_change is requested */
923 if (previous->cs_change)
924 cs_deassert(drv_data);
925 }
926
927 /* Check for transfers that need multiple DMA segments */
928 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
929
930 /* reject already-mapped transfers; PIO won't always work */
931 if (message->is_dma_mapped
932 || transfer->rx_dma || transfer->tx_dma) {
933 dev_err(&drv_data->pdev->dev,
934 "pump_transfers: mapped transfer length "
935 "of %u is greater than %d\n",
936 transfer->len, MAX_DMA_LEN);
937 message->status = -EINVAL;
938 giveback(drv_data);
939 return;
940 }
941
942 /* warn ... we force this to PIO mode */
943 if (printk_ratelimit())
944 dev_warn(&message->spi->dev, "pump_transfers: "
945 "DMA disabled for transfer length %ld "
946 "greater than %d\n",
947 (long)drv_data->len, MAX_DMA_LEN);
948 }
949
950 /* Setup the transfer state based on the type of transfer */
951 if (flush(drv_data) == 0) {
952 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
953 message->status = -EIO;
954 giveback(drv_data);
955 return;
956 }
957 drv_data->n_bytes = chip->n_bytes;
958 drv_data->dma_width = chip->dma_width;
959 drv_data->tx = (void *)transfer->tx_buf;
960 drv_data->tx_end = drv_data->tx + transfer->len;
961 drv_data->rx = transfer->rx_buf;
962 drv_data->rx_end = drv_data->rx + transfer->len;
963 drv_data->rx_dma = transfer->rx_dma;
964 drv_data->tx_dma = transfer->tx_dma;
965 drv_data->len = transfer->len & DCMD_LENGTH;
966 drv_data->write = drv_data->tx ? chip->write : null_writer;
967 drv_data->read = drv_data->rx ? chip->read : null_reader;
968
969 /* Change speed and bit per word on a per transfer */
970 cr0 = chip->cr0;
971 if (transfer->speed_hz || transfer->bits_per_word) {
972
973 bits = chip->bits_per_word;
974 speed = chip->speed_hz;
975
976 if (transfer->speed_hz)
977 speed = transfer->speed_hz;
978
979 if (transfer->bits_per_word)
980 bits = transfer->bits_per_word;
981
982 clk_div = ssp_get_clk_div(ssp, speed);
983
984 if (bits <= 8) {
985 drv_data->n_bytes = 1;
986 drv_data->dma_width = DCMD_WIDTH1;
987 drv_data->read = drv_data->read != null_reader ?
988 u8_reader : null_reader;
989 drv_data->write = drv_data->write != null_writer ?
990 u8_writer : null_writer;
991 } else if (bits <= 16) {
992 drv_data->n_bytes = 2;
993 drv_data->dma_width = DCMD_WIDTH2;
994 drv_data->read = drv_data->read != null_reader ?
995 u16_reader : null_reader;
996 drv_data->write = drv_data->write != null_writer ?
997 u16_writer : null_writer;
998 } else if (bits <= 32) {
999 drv_data->n_bytes = 4;
1000 drv_data->dma_width = DCMD_WIDTH4;
1001 drv_data->read = drv_data->read != null_reader ?
1002 u32_reader : null_reader;
1003 drv_data->write = drv_data->write != null_writer ?
1004 u32_writer : null_writer;
1005 }
1006 /* if bits/word is changed in dma mode, then must check the
1007 * thresholds and burst also */
1008 if (chip->enable_dma) {
1009 if (set_dma_burst_and_threshold(chip, message->spi,
1010 bits, &dma_burst,
1011 &dma_thresh))
1012 if (printk_ratelimit())
1013 dev_warn(&message->spi->dev,
1014 "pump_transfers: "
1015 "DMA burst size reduced to "
1016 "match bits_per_word\n");
1017 }
1018
1019 cr0 = clk_div
1020 | SSCR0_Motorola
1021 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
1022 | SSCR0_SSE
1023 | (bits > 16 ? SSCR0_EDSS : 0);
1024 }
1025
1026 message->state = RUNNING_STATE;
1027
1028 /* Try to map dma buffer and do a dma transfer if successful, but
1029 * only if the length is non-zero and less than MAX_DMA_LEN.
1030 *
1031 * Zero-length non-descriptor DMA is illegal on PXA2xx; force use
1032 * of PIO instead. Care is needed above because the transfer may
1033 * have have been passed with buffers that are already dma mapped.
1034 * A zero-length transfer in PIO mode will not try to write/read
1035 * to/from the buffers
1036 *
1037 * REVISIT large transfers are exactly where we most want to be
1038 * using DMA. If this happens much, split those transfers into
1039 * multiple DMA segments rather than forcing PIO.
1040 */
1041 drv_data->dma_mapped = 0;
1042 if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN)
1043 drv_data->dma_mapped = map_dma_buffers(drv_data);
1044 if (drv_data->dma_mapped) {
1045
1046 /* Ensure we have the correct interrupt handler */
1047 drv_data->transfer_handler = dma_transfer;
1048
1049 /* Setup rx DMA Channel */
1050 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
1051 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
1052 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
1053 if (drv_data->rx == drv_data->null_dma_buf)
1054 /* No target address increment */
1055 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
1056 | drv_data->dma_width
1057 | dma_burst
1058 | drv_data->len;
1059 else
1060 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
1061 | DCMD_FLOWSRC
1062 | drv_data->dma_width
1063 | dma_burst
1064 | drv_data->len;
1065
1066 /* Setup tx DMA Channel */
1067 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
1068 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
1069 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
1070 if (drv_data->tx == drv_data->null_dma_buf)
1071 /* No source address increment */
1072 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
1073 | drv_data->dma_width
1074 | dma_burst
1075 | drv_data->len;
1076 else
1077 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
1078 | DCMD_FLOWTRG
1079 | drv_data->dma_width
1080 | dma_burst
1081 | drv_data->len;
1082
1083 /* Enable dma end irqs on SSP to detect end of transfer */
1084 if (drv_data->ssp_type == PXA25x_SSP)
1085 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
1086
1087 /* Clear status and start DMA engine */
1088 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1089 write_SSSR(drv_data->clear_sr, reg);
1090 DCSR(drv_data->rx_channel) |= DCSR_RUN;
1091 DCSR(drv_data->tx_channel) |= DCSR_RUN;
1092 } else {
1093 /* Ensure we have the correct interrupt handler */
1094 drv_data->transfer_handler = interrupt_transfer;
1095
1096 /* Clear status */
1097 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1098 write_SSSR(drv_data->clear_sr, reg);
1099 }
1100
1101 /* see if we need to reload the config registers */
1102 if ((read_SSCR0(reg) != cr0)
1103 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
1104 (cr1 & SSCR1_CHANGE_MASK)) {
1105
1106 /* stop the SSP, and update the other bits */
1107 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
1108 if (drv_data->ssp_type != PXA25x_SSP)
1109 write_SSTO(chip->timeout, reg);
1110 /* first set CR1 without interrupt and service enables */
1111 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
1112 /* restart the SSP */
1113 write_SSCR0(cr0, reg);
1114
1115 } else {
1116 if (drv_data->ssp_type != PXA25x_SSP)
1117 write_SSTO(chip->timeout, reg);
1118 }
1119
1120 cs_assert(drv_data);
1121
1122 /* after chip select, release the data by enabling service
1123 * requests and interrupts, without changing any mode bits */
1124 write_SSCR1(cr1, reg);
1125 }
1126
1127 static void pump_messages(struct work_struct *work)
1128 {
1129 struct driver_data *drv_data =
1130 container_of(work, struct driver_data, pump_messages);
1131 unsigned long flags;
1132
1133 /* Lock queue and check for queue work */
1134 spin_lock_irqsave(&drv_data->lock, flags);
1135 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1136 drv_data->busy = 0;
1137 spin_unlock_irqrestore(&drv_data->lock, flags);
1138 return;
1139 }
1140
1141 /* Make sure we are not already running a message */
1142 if (drv_data->cur_msg) {
1143 spin_unlock_irqrestore(&drv_data->lock, flags);
1144 return;
1145 }
1146
1147 /* Extract head of queue */
1148 drv_data->cur_msg = list_entry(drv_data->queue.next,
1149 struct spi_message, queue);
1150 list_del_init(&drv_data->cur_msg->queue);
1151
1152 /* Initial message state*/
1153 drv_data->cur_msg->state = START_STATE;
1154 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1155 struct spi_transfer,
1156 transfer_list);
1157
1158 /* prepare to setup the SSP, in pump_transfers, using the per
1159 * chip configuration */
1160 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1161
1162 /* Mark as busy and launch transfers */
1163 tasklet_schedule(&drv_data->pump_transfers);
1164
1165 drv_data->busy = 1;
1166 spin_unlock_irqrestore(&drv_data->lock, flags);
1167 }
1168
1169 static int transfer(struct spi_device *spi, struct spi_message *msg)
1170 {
1171 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1172 unsigned long flags;
1173
1174 spin_lock_irqsave(&drv_data->lock, flags);
1175
1176 if (drv_data->run == QUEUE_STOPPED) {
1177 spin_unlock_irqrestore(&drv_data->lock, flags);
1178 return -ESHUTDOWN;
1179 }
1180
1181 msg->actual_length = 0;
1182 msg->status = -EINPROGRESS;
1183 msg->state = START_STATE;
1184
1185 list_add_tail(&msg->queue, &drv_data->queue);
1186
1187 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1188 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1189
1190 spin_unlock_irqrestore(&drv_data->lock, flags);
1191
1192 return 0;
1193 }
1194
1195 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1196 struct pxa2xx_spi_chip *chip_info)
1197 {
1198 int err = 0;
1199
1200 if (chip == NULL || chip_info == NULL)
1201 return 0;
1202
1203 /* NOTE: setup() can be called multiple times, possibly with
1204 * different chip_info, release previously requested GPIO
1205 */
1206 if (gpio_is_valid(chip->gpio_cs))
1207 gpio_free(chip->gpio_cs);
1208
1209 /* If (*cs_control) is provided, ignore GPIO chip select */
1210 if (chip_info->cs_control) {
1211 chip->cs_control = chip_info->cs_control;
1212 return 0;
1213 }
1214
1215 if (gpio_is_valid(chip_info->gpio_cs)) {
1216 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1217 if (err) {
1218 dev_err(&spi->dev, "failed to request chip select "
1219 "GPIO%d\n", chip_info->gpio_cs);
1220 return err;
1221 }
1222
1223 chip->gpio_cs = chip_info->gpio_cs;
1224 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1225
1226 err = gpio_direction_output(chip->gpio_cs,
1227 !chip->gpio_cs_inverted);
1228 }
1229
1230 return err;
1231 }
1232
1233 static int setup(struct spi_device *spi)
1234 {
1235 struct pxa2xx_spi_chip *chip_info = NULL;
1236 struct chip_data *chip;
1237 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1238 struct ssp_device *ssp = drv_data->ssp;
1239 unsigned int clk_div;
1240 uint tx_thres = TX_THRESH_DFLT;
1241 uint rx_thres = RX_THRESH_DFLT;
1242
1243 if (drv_data->ssp_type != PXA25x_SSP
1244 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1245 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1246 "b/w not 4-32 for type non-PXA25x_SSP\n",
1247 drv_data->ssp_type, spi->bits_per_word);
1248 return -EINVAL;
1249 }
1250 else if (drv_data->ssp_type == PXA25x_SSP
1251 && (spi->bits_per_word < 4
1252 || spi->bits_per_word > 16)) {
1253 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1254 "b/w not 4-16 for type PXA25x_SSP\n",
1255 drv_data->ssp_type, spi->bits_per_word);
1256 return -EINVAL;
1257 }
1258
1259 /* Only alloc on first setup */
1260 chip = spi_get_ctldata(spi);
1261 if (!chip) {
1262 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1263 if (!chip) {
1264 dev_err(&spi->dev,
1265 "failed setup: can't allocate chip data\n");
1266 return -ENOMEM;
1267 }
1268
1269 chip->gpio_cs = -1;
1270 chip->enable_dma = 0;
1271 chip->timeout = TIMOUT_DFLT;
1272 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1273 DCMD_BURST8 : 0;
1274 }
1275
1276 /* protocol drivers may change the chip settings, so...
1277 * if chip_info exists, use it */
1278 chip_info = spi->controller_data;
1279
1280 /* chip_info isn't always needed */
1281 chip->cr1 = 0;
1282 if (chip_info) {
1283 if (chip_info->timeout)
1284 chip->timeout = chip_info->timeout;
1285 if (chip_info->tx_threshold)
1286 tx_thres = chip_info->tx_threshold;
1287 if (chip_info->rx_threshold)
1288 rx_thres = chip_info->rx_threshold;
1289 chip->enable_dma = drv_data->master_info->enable_dma;
1290 chip->dma_threshold = 0;
1291 if (chip_info->enable_loopback)
1292 chip->cr1 = SSCR1_LBM;
1293 }
1294
1295 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1296 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1297
1298 /* set dma burst and threshold outside of chip_info path so that if
1299 * chip_info goes away after setting chip->enable_dma, the
1300 * burst and threshold can still respond to changes in bits_per_word */
1301 if (chip->enable_dma) {
1302 /* set up legal burst and threshold for dma */
1303 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1304 &chip->dma_burst_size,
1305 &chip->dma_threshold)) {
1306 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1307 "to match bits_per_word\n");
1308 }
1309 }
1310
1311 clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
1312 chip->speed_hz = spi->max_speed_hz;
1313
1314 chip->cr0 = clk_div
1315 | SSCR0_Motorola
1316 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1317 spi->bits_per_word - 16 : spi->bits_per_word)
1318 | SSCR0_SSE
1319 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1320 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1321 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1322 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1323
1324 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1325 if (drv_data->ssp_type != PXA25x_SSP)
1326 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1327 clk_get_rate(ssp->clk)
1328 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
1329 chip->enable_dma ? "DMA" : "PIO");
1330 else
1331 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1332 clk_get_rate(ssp->clk) / 2
1333 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1334 chip->enable_dma ? "DMA" : "PIO");
1335
1336 if (spi->bits_per_word <= 8) {
1337 chip->n_bytes = 1;
1338 chip->dma_width = DCMD_WIDTH1;
1339 chip->read = u8_reader;
1340 chip->write = u8_writer;
1341 } else if (spi->bits_per_word <= 16) {
1342 chip->n_bytes = 2;
1343 chip->dma_width = DCMD_WIDTH2;
1344 chip->read = u16_reader;
1345 chip->write = u16_writer;
1346 } else if (spi->bits_per_word <= 32) {
1347 chip->cr0 |= SSCR0_EDSS;
1348 chip->n_bytes = 4;
1349 chip->dma_width = DCMD_WIDTH4;
1350 chip->read = u32_reader;
1351 chip->write = u32_writer;
1352 } else {
1353 dev_err(&spi->dev, "invalid wordsize\n");
1354 return -ENODEV;
1355 }
1356 chip->bits_per_word = spi->bits_per_word;
1357
1358 spi_set_ctldata(spi, chip);
1359
1360 return setup_cs(spi, chip, chip_info);
1361 }
1362
1363 static void cleanup(struct spi_device *spi)
1364 {
1365 struct chip_data *chip = spi_get_ctldata(spi);
1366
1367 if (!chip)
1368 return;
1369
1370 if (gpio_is_valid(chip->gpio_cs))
1371 gpio_free(chip->gpio_cs);
1372
1373 kfree(chip);
1374 }
1375
1376 static int __devinit init_queue(struct driver_data *drv_data)
1377 {
1378 INIT_LIST_HEAD(&drv_data->queue);
1379 spin_lock_init(&drv_data->lock);
1380
1381 drv_data->run = QUEUE_STOPPED;
1382 drv_data->busy = 0;
1383
1384 tasklet_init(&drv_data->pump_transfers,
1385 pump_transfers, (unsigned long)drv_data);
1386
1387 INIT_WORK(&drv_data->pump_messages, pump_messages);
1388 drv_data->workqueue = create_singlethread_workqueue(
1389 dev_name(drv_data->master->dev.parent));
1390 if (drv_data->workqueue == NULL)
1391 return -EBUSY;
1392
1393 return 0;
1394 }
1395
1396 static int start_queue(struct driver_data *drv_data)
1397 {
1398 unsigned long flags;
1399
1400 spin_lock_irqsave(&drv_data->lock, flags);
1401
1402 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1403 spin_unlock_irqrestore(&drv_data->lock, flags);
1404 return -EBUSY;
1405 }
1406
1407 drv_data->run = QUEUE_RUNNING;
1408 drv_data->cur_msg = NULL;
1409 drv_data->cur_transfer = NULL;
1410 drv_data->cur_chip = NULL;
1411 spin_unlock_irqrestore(&drv_data->lock, flags);
1412
1413 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1414
1415 return 0;
1416 }
1417
1418 static int stop_queue(struct driver_data *drv_data)
1419 {
1420 unsigned long flags;
1421 unsigned limit = 500;
1422 int status = 0;
1423
1424 spin_lock_irqsave(&drv_data->lock, flags);
1425
1426 /* This is a bit lame, but is optimized for the common execution path.
1427 * A wait_queue on the drv_data->busy could be used, but then the common
1428 * execution path (pump_messages) would be required to call wake_up or
1429 * friends on every SPI message. Do this instead */
1430 drv_data->run = QUEUE_STOPPED;
1431 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1432 spin_unlock_irqrestore(&drv_data->lock, flags);
1433 msleep(10);
1434 spin_lock_irqsave(&drv_data->lock, flags);
1435 }
1436
1437 if (!list_empty(&drv_data->queue) || drv_data->busy)
1438 status = -EBUSY;
1439
1440 spin_unlock_irqrestore(&drv_data->lock, flags);
1441
1442 return status;
1443 }
1444
1445 static int destroy_queue(struct driver_data *drv_data)
1446 {
1447 int status;
1448
1449 status = stop_queue(drv_data);
1450 /* we are unloading the module or failing to load (only two calls
1451 * to this routine), and neither call can handle a return value.
1452 * However, destroy_workqueue calls flush_workqueue, and that will
1453 * block until all work is done. If the reason that stop_queue
1454 * timed out is that the work will never finish, then it does no
1455 * good to call destroy_workqueue, so return anyway. */
1456 if (status != 0)
1457 return status;
1458
1459 destroy_workqueue(drv_data->workqueue);
1460
1461 return 0;
1462 }
1463
1464 static int __devinit pxa2xx_spi_probe(struct platform_device *pdev)
1465 {
1466 struct device *dev = &pdev->dev;
1467 struct pxa2xx_spi_master *platform_info;
1468 struct spi_master *master;
1469 struct driver_data *drv_data;
1470 struct ssp_device *ssp;
1471 int status;
1472
1473 platform_info = dev->platform_data;
1474
1475 ssp = pxa_ssp_request(pdev->id, pdev->name);
1476 if (ssp == NULL) {
1477 dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
1478 return -ENODEV;
1479 }
1480
1481 /* Allocate master with space for drv_data and null dma buffer */
1482 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1483 if (!master) {
1484 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1485 pxa_ssp_free(ssp);
1486 return -ENOMEM;
1487 }
1488 drv_data = spi_master_get_devdata(master);
1489 drv_data->master = master;
1490 drv_data->master_info = platform_info;
1491 drv_data->pdev = pdev;
1492 drv_data->ssp = ssp;
1493
1494 /* the spi->mode bits understood by this driver: */
1495 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1496
1497 master->bus_num = pdev->id;
1498 master->num_chipselect = platform_info->num_chipselect;
1499 master->dma_alignment = DMA_ALIGNMENT;
1500 master->cleanup = cleanup;
1501 master->setup = setup;
1502 master->transfer = transfer;
1503
1504 drv_data->ssp_type = ssp->type;
1505 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1506 sizeof(struct driver_data)), 8);
1507
1508 drv_data->ioaddr = ssp->mmio_base;
1509 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1510 if (ssp->type == PXA25x_SSP) {
1511 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1512 drv_data->dma_cr1 = 0;
1513 drv_data->clear_sr = SSSR_ROR;
1514 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1515 } else {
1516 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1517 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1518 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1519 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1520 }
1521
1522 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1523 drv_data);
1524 if (status < 0) {
1525 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1526 goto out_error_master_alloc;
1527 }
1528
1529 /* Setup DMA if requested */
1530 drv_data->tx_channel = -1;
1531 drv_data->rx_channel = -1;
1532 if (platform_info->enable_dma) {
1533
1534 /* Get two DMA channels (rx and tx) */
1535 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1536 DMA_PRIO_HIGH,
1537 dma_handler,
1538 drv_data);
1539 if (drv_data->rx_channel < 0) {
1540 dev_err(dev, "problem (%d) requesting rx channel\n",
1541 drv_data->rx_channel);
1542 status = -ENODEV;
1543 goto out_error_irq_alloc;
1544 }
1545 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1546 DMA_PRIO_MEDIUM,
1547 dma_handler,
1548 drv_data);
1549 if (drv_data->tx_channel < 0) {
1550 dev_err(dev, "problem (%d) requesting tx channel\n",
1551 drv_data->tx_channel);
1552 status = -ENODEV;
1553 goto out_error_dma_alloc;
1554 }
1555
1556 DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1557 DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
1558 }
1559
1560 /* Enable SOC clock */
1561 clk_enable(ssp->clk);
1562
1563 /* Load default SSP configuration */
1564 write_SSCR0(0, drv_data->ioaddr);
1565 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1566 SSCR1_TxTresh(TX_THRESH_DFLT),
1567 drv_data->ioaddr);
1568 write_SSCR0(SSCR0_SCR(2)
1569 | SSCR0_Motorola
1570 | SSCR0_DataSize(8),
1571 drv_data->ioaddr);
1572 if (drv_data->ssp_type != PXA25x_SSP)
1573 write_SSTO(0, drv_data->ioaddr);
1574 write_SSPSP(0, drv_data->ioaddr);
1575
1576 /* Initial and start queue */
1577 status = init_queue(drv_data);
1578 if (status != 0) {
1579 dev_err(&pdev->dev, "problem initializing queue\n");
1580 goto out_error_clock_enabled;
1581 }
1582 status = start_queue(drv_data);
1583 if (status != 0) {
1584 dev_err(&pdev->dev, "problem starting queue\n");
1585 goto out_error_clock_enabled;
1586 }
1587
1588 /* Register with the SPI framework */
1589 platform_set_drvdata(pdev, drv_data);
1590 status = spi_register_master(master);
1591 if (status != 0) {
1592 dev_err(&pdev->dev, "problem registering spi master\n");
1593 goto out_error_queue_alloc;
1594 }
1595
1596 return status;
1597
1598 out_error_queue_alloc:
1599 destroy_queue(drv_data);
1600
1601 out_error_clock_enabled:
1602 clk_disable(ssp->clk);
1603
1604 out_error_dma_alloc:
1605 if (drv_data->tx_channel != -1)
1606 pxa_free_dma(drv_data->tx_channel);
1607 if (drv_data->rx_channel != -1)
1608 pxa_free_dma(drv_data->rx_channel);
1609
1610 out_error_irq_alloc:
1611 free_irq(ssp->irq, drv_data);
1612
1613 out_error_master_alloc:
1614 spi_master_put(master);
1615 pxa_ssp_free(ssp);
1616 return status;
1617 }
1618
1619 static int pxa2xx_spi_remove(struct platform_device *pdev)
1620 {
1621 struct driver_data *drv_data = platform_get_drvdata(pdev);
1622 struct ssp_device *ssp;
1623 int status = 0;
1624
1625 if (!drv_data)
1626 return 0;
1627 ssp = drv_data->ssp;
1628
1629 /* Remove the queue */
1630 status = destroy_queue(drv_data);
1631 if (status != 0)
1632 /* the kernel does not check the return status of this
1633 * this routine (mod->exit, within the kernel). Therefore
1634 * nothing is gained by returning from here, the module is
1635 * going away regardless, and we should not leave any more
1636 * resources allocated than necessary. We cannot free the
1637 * message memory in drv_data->queue, but we can release the
1638 * resources below. I think the kernel should honor -EBUSY
1639 * returns but... */
1640 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1641 "complete, message memory not freed\n");
1642
1643 /* Disable the SSP at the peripheral and SOC level */
1644 write_SSCR0(0, drv_data->ioaddr);
1645 clk_disable(ssp->clk);
1646
1647 /* Release DMA */
1648 if (drv_data->master_info->enable_dma) {
1649 DRCMR(ssp->drcmr_rx) = 0;
1650 DRCMR(ssp->drcmr_tx) = 0;
1651 pxa_free_dma(drv_data->tx_channel);
1652 pxa_free_dma(drv_data->rx_channel);
1653 }
1654
1655 /* Release IRQ */
1656 free_irq(ssp->irq, drv_data);
1657
1658 /* Release SSP */
1659 pxa_ssp_free(ssp);
1660
1661 /* Disconnect from the SPI framework */
1662 spi_unregister_master(drv_data->master);
1663
1664 /* Prevent double remove */
1665 platform_set_drvdata(pdev, NULL);
1666
1667 return 0;
1668 }
1669
1670 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1671 {
1672 int status = 0;
1673
1674 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1675 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1676 }
1677
1678 #ifdef CONFIG_PM
1679 static int pxa2xx_spi_suspend(struct device *dev)
1680 {
1681 struct driver_data *drv_data = dev_get_drvdata(dev);
1682 struct ssp_device *ssp = drv_data->ssp;
1683 int status = 0;
1684
1685 status = stop_queue(drv_data);
1686 if (status != 0)
1687 return status;
1688 write_SSCR0(0, drv_data->ioaddr);
1689 clk_disable(ssp->clk);
1690
1691 return 0;
1692 }
1693
1694 static int pxa2xx_spi_resume(struct device *dev)
1695 {
1696 struct driver_data *drv_data = dev_get_drvdata(dev);
1697 struct ssp_device *ssp = drv_data->ssp;
1698 int status = 0;
1699
1700 if (drv_data->rx_channel != -1)
1701 DRCMR(drv_data->ssp->drcmr_rx) =
1702 DRCMR_MAPVLD | drv_data->rx_channel;
1703 if (drv_data->tx_channel != -1)
1704 DRCMR(drv_data->ssp->drcmr_tx) =
1705 DRCMR_MAPVLD | drv_data->tx_channel;
1706
1707 /* Enable the SSP clock */
1708 clk_enable(ssp->clk);
1709
1710 /* Start the queue running */
1711 status = start_queue(drv_data);
1712 if (status != 0) {
1713 dev_err(dev, "problem starting queue (%d)\n", status);
1714 return status;
1715 }
1716
1717 return 0;
1718 }
1719
1720 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1721 .suspend = pxa2xx_spi_suspend,
1722 .resume = pxa2xx_spi_resume,
1723 };
1724 #endif
1725
1726 static struct platform_driver driver = {
1727 .driver = {
1728 .name = "pxa2xx-spi",
1729 .owner = THIS_MODULE,
1730 #ifdef CONFIG_PM
1731 .pm = &pxa2xx_spi_pm_ops,
1732 #endif
1733 },
1734 .probe = pxa2xx_spi_probe,
1735 .remove = pxa2xx_spi_remove,
1736 .shutdown = pxa2xx_spi_shutdown,
1737 };
1738
1739 static int __init pxa2xx_spi_init(void)
1740 {
1741 return platform_driver_register(&driver);
1742 }
1743 subsys_initcall(pxa2xx_spi_init);
1744
1745 static void __exit pxa2xx_spi_exit(void)
1746 {
1747 platform_driver_unregister(&driver);
1748 }
1749 module_exit(pxa2xx_spi_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree