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drm/i915/dp: convert eDP checks to functions and document
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_dp.c
blobf2810ade343cec3f7b1654a8b6bb94458097a223
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "drm_dp_helper.h"
38
39
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43 #define DP_LINK_CONFIGURATION_SIZE 9
44
45 struct intel_dp {
46 struct intel_encoder base;
47 uint32_t output_reg;
48 uint32_t DP;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
50 bool has_audio;
51 int dpms_mode;
52 uint8_t link_bw;
53 uint8_t lane_count;
54 uint8_t dpcd[4];
55 struct i2c_adapter adapter;
56 struct i2c_algo_dp_aux_data algo;
57 bool is_pch_edp;
58 uint8_t train_set[4];
59 uint8_t link_status[DP_LINK_STATUS_SIZE];
60 };
61
62 /**
63 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
64 * @intel_dp: DP struct
65 *
66 * If a CPU or PCH DP output is attached to an eDP panel, this function
67 * will return true, and false otherwise.
68 */
69 static bool is_edp(struct intel_dp *intel_dp)
70 {
71 return intel_dp->base.type == INTEL_OUTPUT_EDP;
72 }
73
74 /**
75 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
76 * @intel_dp: DP struct
77 *
78 * Returns true if the given DP struct corresponds to a PCH DP port attached
79 * to an eDP panel, false otherwise. Helpful for determining whether we
80 * may need FDI resources for a given DP output or not.
81 */
82 static bool is_pch_edp(struct intel_dp *intel_dp)
83 {
84 return intel_dp->is_pch_edp;
85 }
86
87 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
88 {
89 return container_of(encoder, struct intel_dp, base.base);
90 }
91
92 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
93 {
94 return container_of(intel_attached_encoder(connector),
95 struct intel_dp, base);
96 }
97
98 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
99 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
100 static void intel_dp_link_down(struct intel_dp *intel_dp);
101
102 void
103 intel_edp_link_config (struct intel_encoder *intel_encoder,
104 int *lane_num, int *link_bw)
105 {
106 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
107
108 *lane_num = intel_dp->lane_count;
109 if (intel_dp->link_bw == DP_LINK_BW_1_62)
110 *link_bw = 162000;
111 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
112 *link_bw = 270000;
113 }
114
115 static int
116 intel_dp_max_lane_count(struct intel_dp *intel_dp)
117 {
118 int max_lane_count = 4;
119
120 if (intel_dp->dpcd[0] >= 0x11) {
121 max_lane_count = intel_dp->dpcd[2] & 0x1f;
122 switch (max_lane_count) {
123 case 1: case 2: case 4:
124 break;
125 default:
126 max_lane_count = 4;
127 }
128 }
129 return max_lane_count;
130 }
131
132 static int
133 intel_dp_max_link_bw(struct intel_dp *intel_dp)
134 {
135 int max_link_bw = intel_dp->dpcd[1];
136
137 switch (max_link_bw) {
138 case DP_LINK_BW_1_62:
139 case DP_LINK_BW_2_7:
140 break;
141 default:
142 max_link_bw = DP_LINK_BW_1_62;
143 break;
144 }
145 return max_link_bw;
146 }
147
148 static int
149 intel_dp_link_clock(uint8_t link_bw)
150 {
151 if (link_bw == DP_LINK_BW_2_7)
152 return 270000;
153 else
154 return 162000;
155 }
156
157 /* I think this is a fiction */
158 static int
159 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
160 {
161 struct drm_i915_private *dev_priv = dev->dev_private;
162
163 if (is_edp(intel_dp) || is_pch_edp(intel_dp))
164 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
165 else
166 return pixel_clock * 3;
167 }
168
169 static int
170 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
171 {
172 return (max_link_clock * max_lanes * 8) / 10;
173 }
174
175 static int
176 intel_dp_mode_valid(struct drm_connector *connector,
177 struct drm_display_mode *mode)
178 {
179 struct intel_dp *intel_dp = intel_attached_dp(connector);
180 struct drm_device *dev = connector->dev;
181 struct drm_i915_private *dev_priv = dev->dev_private;
182 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
183 int max_lanes = intel_dp_max_lane_count(intel_dp);
184
185 if ((is_edp(intel_dp) || is_pch_edp(intel_dp)) &&
186 dev_priv->panel_fixed_mode) {
187 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
188 return MODE_PANEL;
189
190 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
191 return MODE_PANEL;
192 }
193
194 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
195 which are outside spec tolerances but somehow work by magic */
196 if (!is_edp(intel_dp) &&
197 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
198 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
199 return MODE_CLOCK_HIGH;
200
201 if (mode->clock < 10000)
202 return MODE_CLOCK_LOW;
203
204 return MODE_OK;
205 }
206
207 static uint32_t
208 pack_aux(uint8_t *src, int src_bytes)
209 {
210 int i;
211 uint32_t v = 0;
212
213 if (src_bytes > 4)
214 src_bytes = 4;
215 for (i = 0; i < src_bytes; i++)
216 v |= ((uint32_t) src[i]) << ((3-i) * 8);
217 return v;
218 }
219
220 static void
221 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
222 {
223 int i;
224 if (dst_bytes > 4)
225 dst_bytes = 4;
226 for (i = 0; i < dst_bytes; i++)
227 dst[i] = src >> ((3-i) * 8);
228 }
229
230 /* hrawclock is 1/4 the FSB frequency */
231 static int
232 intel_hrawclk(struct drm_device *dev)
233 {
234 struct drm_i915_private *dev_priv = dev->dev_private;
235 uint32_t clkcfg;
236
237 clkcfg = I915_READ(CLKCFG);
238 switch (clkcfg & CLKCFG_FSB_MASK) {
239 case CLKCFG_FSB_400:
240 return 100;
241 case CLKCFG_FSB_533:
242 return 133;
243 case CLKCFG_FSB_667:
244 return 166;
245 case CLKCFG_FSB_800:
246 return 200;
247 case CLKCFG_FSB_1067:
248 return 266;
249 case CLKCFG_FSB_1333:
250 return 333;
251 /* these two are just a guess; one of them might be right */
252 case CLKCFG_FSB_1600:
253 case CLKCFG_FSB_1600_ALT:
254 return 400;
255 default:
256 return 133;
257 }
258 }
259
260 static int
261 intel_dp_aux_ch(struct intel_dp *intel_dp,
262 uint8_t *send, int send_bytes,
263 uint8_t *recv, int recv_size)
264 {
265 uint32_t output_reg = intel_dp->output_reg;
266 struct drm_device *dev = intel_dp->base.base.dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 uint32_t ch_ctl = output_reg + 0x10;
269 uint32_t ch_data = ch_ctl + 4;
270 int i;
271 int recv_bytes;
272 uint32_t status;
273 uint32_t aux_clock_divider;
274 int try, precharge;
275
276 /* The clock divider is based off the hrawclk,
277 * and would like to run at 2MHz. So, take the
278 * hrawclk value and divide by 2 and use that
279 *
280 * Note that PCH attached eDP panels should use a 125MHz input
281 * clock divider.
282 */
283 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
284 if (IS_GEN6(dev))
285 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
286 else
287 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
288 } else if (HAS_PCH_SPLIT(dev))
289 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
290 else
291 aux_clock_divider = intel_hrawclk(dev) / 2;
292
293 if (IS_GEN6(dev))
294 precharge = 3;
295 else
296 precharge = 5;
297
298 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
299 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
300 I915_READ(ch_ctl));
301 return -EBUSY;
302 }
303
304 /* Must try at least 3 times according to DP spec */
305 for (try = 0; try < 5; try++) {
306 /* Load the send data into the aux channel data registers */
307 for (i = 0; i < send_bytes; i += 4)
308 I915_WRITE(ch_data + i,
309 pack_aux(send + i, send_bytes - i));
310
311 /* Send the command and wait for it to complete */
312 I915_WRITE(ch_ctl,
313 DP_AUX_CH_CTL_SEND_BUSY |
314 DP_AUX_CH_CTL_TIME_OUT_400us |
315 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
316 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
317 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
318 DP_AUX_CH_CTL_DONE |
319 DP_AUX_CH_CTL_TIME_OUT_ERROR |
320 DP_AUX_CH_CTL_RECEIVE_ERROR);
321 for (;;) {
322 status = I915_READ(ch_ctl);
323 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
324 break;
325 udelay(100);
326 }
327
328 /* Clear done status and any errors */
329 I915_WRITE(ch_ctl,
330 status |
331 DP_AUX_CH_CTL_DONE |
332 DP_AUX_CH_CTL_TIME_OUT_ERROR |
333 DP_AUX_CH_CTL_RECEIVE_ERROR);
334 if (status & DP_AUX_CH_CTL_DONE)
335 break;
336 }
337
338 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
339 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
340 return -EBUSY;
341 }
342
343 /* Check for timeout or receive error.
344 * Timeouts occur when the sink is not connected
345 */
346 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
347 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
348 return -EIO;
349 }
350
351 /* Timeouts occur when the device isn't connected, so they're
352 * "normal" -- don't fill the kernel log with these */
353 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
354 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
355 return -ETIMEDOUT;
356 }
357
358 /* Unload any bytes sent back from the other side */
359 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
360 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
361 if (recv_bytes > recv_size)
362 recv_bytes = recv_size;
363
364 for (i = 0; i < recv_bytes; i += 4)
365 unpack_aux(I915_READ(ch_data + i),
366 recv + i, recv_bytes - i);
367
368 return recv_bytes;
369 }
370
371 /* Write data to the aux channel in native mode */
372 static int
373 intel_dp_aux_native_write(struct intel_dp *intel_dp,
374 uint16_t address, uint8_t *send, int send_bytes)
375 {
376 int ret;
377 uint8_t msg[20];
378 int msg_bytes;
379 uint8_t ack;
380
381 if (send_bytes > 16)
382 return -1;
383 msg[0] = AUX_NATIVE_WRITE << 4;
384 msg[1] = address >> 8;
385 msg[2] = address & 0xff;
386 msg[3] = send_bytes - 1;
387 memcpy(&msg[4], send, send_bytes);
388 msg_bytes = send_bytes + 4;
389 for (;;) {
390 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
391 if (ret < 0)
392 return ret;
393 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
394 break;
395 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
396 udelay(100);
397 else
398 return -EIO;
399 }
400 return send_bytes;
401 }
402
403 /* Write a single byte to the aux channel in native mode */
404 static int
405 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
406 uint16_t address, uint8_t byte)
407 {
408 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
409 }
410
411 /* read bytes from a native aux channel */
412 static int
413 intel_dp_aux_native_read(struct intel_dp *intel_dp,
414 uint16_t address, uint8_t *recv, int recv_bytes)
415 {
416 uint8_t msg[4];
417 int msg_bytes;
418 uint8_t reply[20];
419 int reply_bytes;
420 uint8_t ack;
421 int ret;
422
423 msg[0] = AUX_NATIVE_READ << 4;
424 msg[1] = address >> 8;
425 msg[2] = address & 0xff;
426 msg[3] = recv_bytes - 1;
427
428 msg_bytes = 4;
429 reply_bytes = recv_bytes + 1;
430
431 for (;;) {
432 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
433 reply, reply_bytes);
434 if (ret == 0)
435 return -EPROTO;
436 if (ret < 0)
437 return ret;
438 ack = reply[0];
439 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
440 memcpy(recv, reply + 1, ret - 1);
441 return ret - 1;
442 }
443 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
444 udelay(100);
445 else
446 return -EIO;
447 }
448 }
449
450 static int
451 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
452 uint8_t write_byte, uint8_t *read_byte)
453 {
454 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
455 struct intel_dp *intel_dp = container_of(adapter,
456 struct intel_dp,
457 adapter);
458 uint16_t address = algo_data->address;
459 uint8_t msg[5];
460 uint8_t reply[2];
461 int msg_bytes;
462 int reply_bytes;
463 int ret;
464
465 /* Set up the command byte */
466 if (mode & MODE_I2C_READ)
467 msg[0] = AUX_I2C_READ << 4;
468 else
469 msg[0] = AUX_I2C_WRITE << 4;
470
471 if (!(mode & MODE_I2C_STOP))
472 msg[0] |= AUX_I2C_MOT << 4;
473
474 msg[1] = address >> 8;
475 msg[2] = address;
476
477 switch (mode) {
478 case MODE_I2C_WRITE:
479 msg[3] = 0;
480 msg[4] = write_byte;
481 msg_bytes = 5;
482 reply_bytes = 1;
483 break;
484 case MODE_I2C_READ:
485 msg[3] = 0;
486 msg_bytes = 4;
487 reply_bytes = 2;
488 break;
489 default:
490 msg_bytes = 3;
491 reply_bytes = 1;
492 break;
493 }
494
495 for (;;) {
496 ret = intel_dp_aux_ch(intel_dp,
497 msg, msg_bytes,
498 reply, reply_bytes);
499 if (ret < 0) {
500 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
501 return ret;
502 }
503 switch (reply[0] & AUX_I2C_REPLY_MASK) {
504 case AUX_I2C_REPLY_ACK:
505 if (mode == MODE_I2C_READ) {
506 *read_byte = reply[1];
507 }
508 return reply_bytes - 1;
509 case AUX_I2C_REPLY_NACK:
510 DRM_DEBUG_KMS("aux_ch nack\n");
511 return -EREMOTEIO;
512 case AUX_I2C_REPLY_DEFER:
513 DRM_DEBUG_KMS("aux_ch defer\n");
514 udelay(100);
515 break;
516 default:
517 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
518 return -EREMOTEIO;
519 }
520 }
521 }
522
523 static int
524 intel_dp_i2c_init(struct intel_dp *intel_dp,
525 struct intel_connector *intel_connector, const char *name)
526 {
527 DRM_DEBUG_KMS("i2c_init %s\n", name);
528 intel_dp->algo.running = false;
529 intel_dp->algo.address = 0;
530 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
531
532 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
533 intel_dp->adapter.owner = THIS_MODULE;
534 intel_dp->adapter.class = I2C_CLASS_DDC;
535 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
536 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
537 intel_dp->adapter.algo_data = &intel_dp->algo;
538 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
539
540 return i2c_dp_aux_add_bus(&intel_dp->adapter);
541 }
542
543 static bool
544 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
545 struct drm_display_mode *adjusted_mode)
546 {
547 struct drm_device *dev = encoder->dev;
548 struct drm_i915_private *dev_priv = dev->dev_private;
549 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
550 int lane_count, clock;
551 int max_lane_count = intel_dp_max_lane_count(intel_dp);
552 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
553 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
554
555 if ((is_edp(intel_dp) || is_pch_edp(intel_dp)) &&
556 dev_priv->panel_fixed_mode) {
557 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
558 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
559 mode, adjusted_mode);
560 /*
561 * the mode->clock is used to calculate the Data&Link M/N
562 * of the pipe. For the eDP the fixed clock should be used.
563 */
564 mode->clock = dev_priv->panel_fixed_mode->clock;
565 }
566
567 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
568 for (clock = 0; clock <= max_clock; clock++) {
569 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
570
571 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
572 <= link_avail) {
573 intel_dp->link_bw = bws[clock];
574 intel_dp->lane_count = lane_count;
575 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
576 DRM_DEBUG_KMS("Display port link bw %02x lane "
577 "count %d clock %d\n",
578 intel_dp->link_bw, intel_dp->lane_count,
579 adjusted_mode->clock);
580 return true;
581 }
582 }
583 }
584
585 if (is_edp(intel_dp) || is_pch_edp(intel_dp)) {
586 /* okay we failed just pick the highest */
587 intel_dp->lane_count = max_lane_count;
588 intel_dp->link_bw = bws[max_clock];
589 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
590 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
591 "count %d clock %d\n",
592 intel_dp->link_bw, intel_dp->lane_count,
593 adjusted_mode->clock);
594
595 return true;
596 }
597
598 return false;
599 }
600
601 struct intel_dp_m_n {
602 uint32_t tu;
603 uint32_t gmch_m;
604 uint32_t gmch_n;
605 uint32_t link_m;
606 uint32_t link_n;
607 };
608
609 static void
610 intel_reduce_ratio(uint32_t *num, uint32_t *den)
611 {
612 while (*num > 0xffffff || *den > 0xffffff) {
613 *num >>= 1;
614 *den >>= 1;
615 }
616 }
617
618 static void
619 intel_dp_compute_m_n(int bpp,
620 int nlanes,
621 int pixel_clock,
622 int link_clock,
623 struct intel_dp_m_n *m_n)
624 {
625 m_n->tu = 64;
626 m_n->gmch_m = (pixel_clock * bpp) >> 3;
627 m_n->gmch_n = link_clock * nlanes;
628 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
629 m_n->link_m = pixel_clock;
630 m_n->link_n = link_clock;
631 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
632 }
633
634 bool intel_pch_has_edp(struct drm_crtc *crtc)
635 {
636 struct drm_device *dev = crtc->dev;
637 struct drm_mode_config *mode_config = &dev->mode_config;
638 struct drm_encoder *encoder;
639
640 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
641 struct intel_dp *intel_dp;
642
643 if (encoder->crtc != crtc)
644 continue;
645
646 intel_dp = enc_to_intel_dp(encoder);
647 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
648 return intel_dp->is_pch_edp;
649 }
650 return false;
651 }
652
653 void
654 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
655 struct drm_display_mode *adjusted_mode)
656 {
657 struct drm_device *dev = crtc->dev;
658 struct drm_mode_config *mode_config = &dev->mode_config;
659 struct drm_encoder *encoder;
660 struct drm_i915_private *dev_priv = dev->dev_private;
661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
662 int lane_count = 4, bpp = 24;
663 struct intel_dp_m_n m_n;
664
665 /*
666 * Find the lane count in the intel_encoder private
667 */
668 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
669 struct intel_dp *intel_dp;
670
671 if (encoder->crtc != crtc)
672 continue;
673
674 intel_dp = enc_to_intel_dp(encoder);
675 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
676 lane_count = intel_dp->lane_count;
677 if (is_pch_edp(intel_dp))
678 bpp = dev_priv->edp.bpp;
679 break;
680 }
681 }
682
683 /*
684 * Compute the GMCH and Link ratios. The '3' here is
685 * the number of bytes_per_pixel post-LUT, which we always
686 * set up for 8-bits of R/G/B, or 3 bytes total.
687 */
688 intel_dp_compute_m_n(bpp, lane_count,
689 mode->clock, adjusted_mode->clock, &m_n);
690
691 if (HAS_PCH_SPLIT(dev)) {
692 if (intel_crtc->pipe == 0) {
693 I915_WRITE(TRANSA_DATA_M1,
694 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
695 m_n.gmch_m);
696 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
697 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
698 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
699 } else {
700 I915_WRITE(TRANSB_DATA_M1,
701 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
702 m_n.gmch_m);
703 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
704 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
705 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
706 }
707 } else {
708 if (intel_crtc->pipe == 0) {
709 I915_WRITE(PIPEA_GMCH_DATA_M,
710 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
711 m_n.gmch_m);
712 I915_WRITE(PIPEA_GMCH_DATA_N,
713 m_n.gmch_n);
714 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
715 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
716 } else {
717 I915_WRITE(PIPEB_GMCH_DATA_M,
718 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
719 m_n.gmch_m);
720 I915_WRITE(PIPEB_GMCH_DATA_N,
721 m_n.gmch_n);
722 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
723 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
724 }
725 }
726 }
727
728 static void
729 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
730 struct drm_display_mode *adjusted_mode)
731 {
732 struct drm_device *dev = encoder->dev;
733 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
734 struct drm_crtc *crtc = intel_dp->base.base.crtc;
735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
736
737 intel_dp->DP = (DP_VOLTAGE_0_4 |
738 DP_PRE_EMPHASIS_0);
739
740 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
741 intel_dp->DP |= DP_SYNC_HS_HIGH;
742 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
743 intel_dp->DP |= DP_SYNC_VS_HIGH;
744
745 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
746 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
747 else
748 intel_dp->DP |= DP_LINK_TRAIN_OFF;
749
750 switch (intel_dp->lane_count) {
751 case 1:
752 intel_dp->DP |= DP_PORT_WIDTH_1;
753 break;
754 case 2:
755 intel_dp->DP |= DP_PORT_WIDTH_2;
756 break;
757 case 4:
758 intel_dp->DP |= DP_PORT_WIDTH_4;
759 break;
760 }
761 if (intel_dp->has_audio)
762 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
763
764 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
765 intel_dp->link_configuration[0] = intel_dp->link_bw;
766 intel_dp->link_configuration[1] = intel_dp->lane_count;
767
768 /*
769 * Check for DPCD version > 1.1 and enhanced framing support
770 */
771 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
772 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
773 intel_dp->DP |= DP_ENHANCED_FRAMING;
774 }
775
776 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
777 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
778 intel_dp->DP |= DP_PIPEB_SELECT;
779
780 if (is_edp(intel_dp)) {
781 /* don't miss out required setting for eDP */
782 intel_dp->DP |= DP_PLL_ENABLE;
783 if (adjusted_mode->clock < 200000)
784 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
785 else
786 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
787 }
788 }
789
790 /* Returns true if the panel was already on when called */
791 static bool ironlake_edp_panel_on (struct drm_device *dev)
792 {
793 struct drm_i915_private *dev_priv = dev->dev_private;
794 u32 pp;
795
796 if (I915_READ(PCH_PP_STATUS) & PP_ON)
797 return true;
798
799 pp = I915_READ(PCH_PP_CONTROL);
800
801 /* ILK workaround: disable reset around power sequence */
802 pp &= ~PANEL_POWER_RESET;
803 I915_WRITE(PCH_PP_CONTROL, pp);
804 POSTING_READ(PCH_PP_CONTROL);
805
806 pp |= POWER_TARGET_ON;
807 I915_WRITE(PCH_PP_CONTROL, pp);
808
809 /* Ouch. We need to wait here for some panels, like Dell e6510
810 * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
811 */
812 msleep(300);
813
814 if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000))
815 DRM_ERROR("panel on wait timed out: 0x%08x\n",
816 I915_READ(PCH_PP_STATUS));
817
818 pp &= ~(PANEL_UNLOCK_REGS);
819 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
820 I915_WRITE(PCH_PP_CONTROL, pp);
821 POSTING_READ(PCH_PP_CONTROL);
822
823 return false;
824 }
825
826 static void ironlake_edp_panel_off (struct drm_device *dev)
827 {
828 struct drm_i915_private *dev_priv = dev->dev_private;
829 u32 pp;
830
831 pp = I915_READ(PCH_PP_CONTROL);
832
833 /* ILK workaround: disable reset around power sequence */
834 pp &= ~PANEL_POWER_RESET;
835 I915_WRITE(PCH_PP_CONTROL, pp);
836 POSTING_READ(PCH_PP_CONTROL);
837
838 pp &= ~POWER_TARGET_ON;
839 I915_WRITE(PCH_PP_CONTROL, pp);
840
841 if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000))
842 DRM_ERROR("panel off wait timed out: 0x%08x\n",
843 I915_READ(PCH_PP_STATUS));
844
845 /* Make sure VDD is enabled so DP AUX will work */
846 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
847 I915_WRITE(PCH_PP_CONTROL, pp);
848 POSTING_READ(PCH_PP_CONTROL);
849
850 /* Ouch. We need to wait here for some panels, like Dell e6510
851 * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
852 */
853 msleep(300);
854 }
855
856 static void ironlake_edp_panel_vdd_on(struct drm_device *dev)
857 {
858 struct drm_i915_private *dev_priv = dev->dev_private;
859 u32 pp;
860
861 pp = I915_READ(PCH_PP_CONTROL);
862 pp |= EDP_FORCE_VDD;
863 I915_WRITE(PCH_PP_CONTROL, pp);
864 POSTING_READ(PCH_PP_CONTROL);
865 msleep(300);
866 }
867
868 static void ironlake_edp_panel_vdd_off(struct drm_device *dev)
869 {
870 struct drm_i915_private *dev_priv = dev->dev_private;
871 u32 pp;
872
873 pp = I915_READ(PCH_PP_CONTROL);
874 pp &= ~EDP_FORCE_VDD;
875 I915_WRITE(PCH_PP_CONTROL, pp);
876 POSTING_READ(PCH_PP_CONTROL);
877 msleep(300);
878 }
879
880 static void ironlake_edp_backlight_on (struct drm_device *dev)
881 {
882 struct drm_i915_private *dev_priv = dev->dev_private;
883 u32 pp;
884
885 DRM_DEBUG_KMS("\n");
886 pp = I915_READ(PCH_PP_CONTROL);
887 pp |= EDP_BLC_ENABLE;
888 I915_WRITE(PCH_PP_CONTROL, pp);
889 }
890
891 static void ironlake_edp_backlight_off (struct drm_device *dev)
892 {
893 struct drm_i915_private *dev_priv = dev->dev_private;
894 u32 pp;
895
896 DRM_DEBUG_KMS("\n");
897 pp = I915_READ(PCH_PP_CONTROL);
898 pp &= ~EDP_BLC_ENABLE;
899 I915_WRITE(PCH_PP_CONTROL, pp);
900 }
901
902 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
903 {
904 struct drm_device *dev = encoder->dev;
905 struct drm_i915_private *dev_priv = dev->dev_private;
906 u32 dpa_ctl;
907
908 DRM_DEBUG_KMS("\n");
909 dpa_ctl = I915_READ(DP_A);
910 dpa_ctl &= ~DP_PLL_ENABLE;
911 I915_WRITE(DP_A, dpa_ctl);
912 }
913
914 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
915 {
916 struct drm_device *dev = encoder->dev;
917 struct drm_i915_private *dev_priv = dev->dev_private;
918 u32 dpa_ctl;
919
920 dpa_ctl = I915_READ(DP_A);
921 dpa_ctl |= DP_PLL_ENABLE;
922 I915_WRITE(DP_A, dpa_ctl);
923 POSTING_READ(DP_A);
924 udelay(200);
925 }
926
927 static void intel_dp_prepare(struct drm_encoder *encoder)
928 {
929 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
930 struct drm_device *dev = encoder->dev;
931 struct drm_i915_private *dev_priv = dev->dev_private;
932 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
933
934 if (is_edp(intel_dp) || is_pch_edp(intel_dp)) {
935 ironlake_edp_panel_off(dev);
936 ironlake_edp_backlight_off(dev);
937 ironlake_edp_panel_vdd_on(dev);
938 ironlake_edp_pll_on(encoder);
939 }
940 if (dp_reg & DP_PORT_EN)
941 intel_dp_link_down(intel_dp);
942 }
943
944 static void intel_dp_commit(struct drm_encoder *encoder)
945 {
946 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
947 struct drm_device *dev = encoder->dev;
948
949 intel_dp_start_link_train(intel_dp);
950
951 if (is_edp(intel_dp) || is_pch_edp(intel_dp))
952 ironlake_edp_panel_on(dev);
953
954 intel_dp_complete_link_train(intel_dp);
955
956 if (is_edp(intel_dp) || is_pch_edp(intel_dp))
957 ironlake_edp_backlight_on(dev);
958 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
959 }
960
961 static void
962 intel_dp_dpms(struct drm_encoder *encoder, int mode)
963 {
964 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
965 struct drm_device *dev = encoder->dev;
966 struct drm_i915_private *dev_priv = dev->dev_private;
967 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
968
969 if (mode != DRM_MODE_DPMS_ON) {
970 if (is_edp(intel_dp) || is_pch_edp(intel_dp)) {
971 ironlake_edp_backlight_off(dev);
972 ironlake_edp_panel_off(dev);
973 }
974 if (dp_reg & DP_PORT_EN)
975 intel_dp_link_down(intel_dp);
976 if (is_edp(intel_dp) || is_pch_edp(intel_dp))
977 ironlake_edp_pll_off(encoder);
978 } else {
979 if (!(dp_reg & DP_PORT_EN)) {
980 intel_dp_start_link_train(intel_dp);
981 if (is_edp(intel_dp) || is_pch_edp(intel_dp))
982 ironlake_edp_panel_on(dev);
983 intel_dp_complete_link_train(intel_dp);
984 if (is_edp(intel_dp) || is_pch_edp(intel_dp))
985 ironlake_edp_backlight_on(dev);
986 }
987 }
988 intel_dp->dpms_mode = mode;
989 }
990
991 /*
992 * Fetch AUX CH registers 0x202 - 0x207 which contain
993 * link status information
994 */
995 static bool
996 intel_dp_get_link_status(struct intel_dp *intel_dp)
997 {
998 int ret;
999
1000 ret = intel_dp_aux_native_read(intel_dp,
1001 DP_LANE0_1_STATUS,
1002 intel_dp->link_status, DP_LINK_STATUS_SIZE);
1003 if (ret != DP_LINK_STATUS_SIZE)
1004 return false;
1005 return true;
1006 }
1007
1008 static uint8_t
1009 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1010 int r)
1011 {
1012 return link_status[r - DP_LANE0_1_STATUS];
1013 }
1014
1015 static uint8_t
1016 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1017 int lane)
1018 {
1019 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1020 int s = ((lane & 1) ?
1021 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1022 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1023 uint8_t l = intel_dp_link_status(link_status, i);
1024
1025 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1026 }
1027
1028 static uint8_t
1029 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1030 int lane)
1031 {
1032 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1033 int s = ((lane & 1) ?
1034 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1035 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1036 uint8_t l = intel_dp_link_status(link_status, i);
1037
1038 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1039 }
1040
1041
1042 #if 0
1043 static char *voltage_names[] = {
1044 "0.4V", "0.6V", "0.8V", "1.2V"
1045 };
1046 static char *pre_emph_names[] = {
1047 "0dB", "3.5dB", "6dB", "9.5dB"
1048 };
1049 static char *link_train_names[] = {
1050 "pattern 1", "pattern 2", "idle", "off"
1051 };
1052 #endif
1053
1054 /*
1055 * These are source-specific values; current Intel hardware supports
1056 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1057 */
1058 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1059
1060 static uint8_t
1061 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1062 {
1063 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1064 case DP_TRAIN_VOLTAGE_SWING_400:
1065 return DP_TRAIN_PRE_EMPHASIS_6;
1066 case DP_TRAIN_VOLTAGE_SWING_600:
1067 return DP_TRAIN_PRE_EMPHASIS_6;
1068 case DP_TRAIN_VOLTAGE_SWING_800:
1069 return DP_TRAIN_PRE_EMPHASIS_3_5;
1070 case DP_TRAIN_VOLTAGE_SWING_1200:
1071 default:
1072 return DP_TRAIN_PRE_EMPHASIS_0;
1073 }
1074 }
1075
1076 static void
1077 intel_get_adjust_train(struct intel_dp *intel_dp)
1078 {
1079 uint8_t v = 0;
1080 uint8_t p = 0;
1081 int lane;
1082
1083 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1084 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1085 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1086
1087 if (this_v > v)
1088 v = this_v;
1089 if (this_p > p)
1090 p = this_p;
1091 }
1092
1093 if (v >= I830_DP_VOLTAGE_MAX)
1094 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1095
1096 if (p >= intel_dp_pre_emphasis_max(v))
1097 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1098
1099 for (lane = 0; lane < 4; lane++)
1100 intel_dp->train_set[lane] = v | p;
1101 }
1102
1103 static uint32_t
1104 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1105 {
1106 uint32_t signal_levels = 0;
1107
1108 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1109 case DP_TRAIN_VOLTAGE_SWING_400:
1110 default:
1111 signal_levels |= DP_VOLTAGE_0_4;
1112 break;
1113 case DP_TRAIN_VOLTAGE_SWING_600:
1114 signal_levels |= DP_VOLTAGE_0_6;
1115 break;
1116 case DP_TRAIN_VOLTAGE_SWING_800:
1117 signal_levels |= DP_VOLTAGE_0_8;
1118 break;
1119 case DP_TRAIN_VOLTAGE_SWING_1200:
1120 signal_levels |= DP_VOLTAGE_1_2;
1121 break;
1122 }
1123 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1124 case DP_TRAIN_PRE_EMPHASIS_0:
1125 default:
1126 signal_levels |= DP_PRE_EMPHASIS_0;
1127 break;
1128 case DP_TRAIN_PRE_EMPHASIS_3_5:
1129 signal_levels |= DP_PRE_EMPHASIS_3_5;
1130 break;
1131 case DP_TRAIN_PRE_EMPHASIS_6:
1132 signal_levels |= DP_PRE_EMPHASIS_6;
1133 break;
1134 case DP_TRAIN_PRE_EMPHASIS_9_5:
1135 signal_levels |= DP_PRE_EMPHASIS_9_5;
1136 break;
1137 }
1138 return signal_levels;
1139 }
1140
1141 /* Gen6's DP voltage swing and pre-emphasis control */
1142 static uint32_t
1143 intel_gen6_edp_signal_levels(uint8_t train_set)
1144 {
1145 switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1146 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1147 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1148 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1149 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1150 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1151 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1152 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1153 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1154 default:
1155 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1156 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1157 }
1158 }
1159
1160 static uint8_t
1161 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1162 int lane)
1163 {
1164 int i = DP_LANE0_1_STATUS + (lane >> 1);
1165 int s = (lane & 1) * 4;
1166 uint8_t l = intel_dp_link_status(link_status, i);
1167
1168 return (l >> s) & 0xf;
1169 }
1170
1171 /* Check for clock recovery is done on all channels */
1172 static bool
1173 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1174 {
1175 int lane;
1176 uint8_t lane_status;
1177
1178 for (lane = 0; lane < lane_count; lane++) {
1179 lane_status = intel_get_lane_status(link_status, lane);
1180 if ((lane_status & DP_LANE_CR_DONE) == 0)
1181 return false;
1182 }
1183 return true;
1184 }
1185
1186 /* Check to see if channel eq is done on all channels */
1187 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1188 DP_LANE_CHANNEL_EQ_DONE|\
1189 DP_LANE_SYMBOL_LOCKED)
1190 static bool
1191 intel_channel_eq_ok(struct intel_dp *intel_dp)
1192 {
1193 uint8_t lane_align;
1194 uint8_t lane_status;
1195 int lane;
1196
1197 lane_align = intel_dp_link_status(intel_dp->link_status,
1198 DP_LANE_ALIGN_STATUS_UPDATED);
1199 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1200 return false;
1201 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1202 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1203 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1204 return false;
1205 }
1206 return true;
1207 }
1208
1209 static bool
1210 intel_dp_set_link_train(struct intel_dp *intel_dp,
1211 uint32_t dp_reg_value,
1212 uint8_t dp_train_pat)
1213 {
1214 struct drm_device *dev = intel_dp->base.base.dev;
1215 struct drm_i915_private *dev_priv = dev->dev_private;
1216 int ret;
1217
1218 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1219 POSTING_READ(intel_dp->output_reg);
1220
1221 intel_dp_aux_native_write_1(intel_dp,
1222 DP_TRAINING_PATTERN_SET,
1223 dp_train_pat);
1224
1225 ret = intel_dp_aux_native_write(intel_dp,
1226 DP_TRAINING_LANE0_SET,
1227 intel_dp->train_set, 4);
1228 if (ret != 4)
1229 return false;
1230
1231 return true;
1232 }
1233
1234 /* Enable corresponding port and start training pattern 1 */
1235 static void
1236 intel_dp_start_link_train(struct intel_dp *intel_dp)
1237 {
1238 struct drm_device *dev = intel_dp->base.base.dev;
1239 struct drm_i915_private *dev_priv = dev->dev_private;
1240 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1241 int i;
1242 uint8_t voltage;
1243 bool clock_recovery = false;
1244 int tries;
1245 u32 reg;
1246 uint32_t DP = intel_dp->DP;
1247
1248 /* Enable output, wait for it to become active */
1249 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1250 POSTING_READ(intel_dp->output_reg);
1251 intel_wait_for_vblank(dev, intel_crtc->pipe);
1252
1253 /* Write the link configuration data */
1254 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1255 intel_dp->link_configuration,
1256 DP_LINK_CONFIGURATION_SIZE);
1257
1258 DP |= DP_PORT_EN;
1259 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1260 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1261 else
1262 DP &= ~DP_LINK_TRAIN_MASK;
1263 memset(intel_dp->train_set, 0, 4);
1264 voltage = 0xff;
1265 tries = 0;
1266 clock_recovery = false;
1267 for (;;) {
1268 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1269 uint32_t signal_levels;
1270 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1271 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1272 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1273 } else {
1274 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1275 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1276 }
1277
1278 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1279 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1280 else
1281 reg = DP | DP_LINK_TRAIN_PAT_1;
1282
1283 if (!intel_dp_set_link_train(intel_dp, reg,
1284 DP_TRAINING_PATTERN_1))
1285 break;
1286 /* Set training pattern 1 */
1287
1288 udelay(100);
1289 if (!intel_dp_get_link_status(intel_dp))
1290 break;
1291
1292 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1293 clock_recovery = true;
1294 break;
1295 }
1296
1297 /* Check to see if we've tried the max voltage */
1298 for (i = 0; i < intel_dp->lane_count; i++)
1299 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1300 break;
1301 if (i == intel_dp->lane_count)
1302 break;
1303
1304 /* Check to see if we've tried the same voltage 5 times */
1305 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1306 ++tries;
1307 if (tries == 5)
1308 break;
1309 } else
1310 tries = 0;
1311 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1312
1313 /* Compute new intel_dp->train_set as requested by target */
1314 intel_get_adjust_train(intel_dp);
1315 }
1316
1317 intel_dp->DP = DP;
1318 }
1319
1320 static void
1321 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1322 {
1323 struct drm_device *dev = intel_dp->base.base.dev;
1324 struct drm_i915_private *dev_priv = dev->dev_private;
1325 bool channel_eq = false;
1326 int tries;
1327 u32 reg;
1328 uint32_t DP = intel_dp->DP;
1329
1330 /* channel equalization */
1331 tries = 0;
1332 channel_eq = false;
1333 for (;;) {
1334 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1335 uint32_t signal_levels;
1336
1337 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1338 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1339 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1340 } else {
1341 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1342 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1343 }
1344
1345 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1346 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1347 else
1348 reg = DP | DP_LINK_TRAIN_PAT_2;
1349
1350 /* channel eq pattern */
1351 if (!intel_dp_set_link_train(intel_dp, reg,
1352 DP_TRAINING_PATTERN_2))
1353 break;
1354
1355 udelay(400);
1356 if (!intel_dp_get_link_status(intel_dp))
1357 break;
1358
1359 if (intel_channel_eq_ok(intel_dp)) {
1360 channel_eq = true;
1361 break;
1362 }
1363
1364 /* Try 5 times */
1365 if (tries > 5)
1366 break;
1367
1368 /* Compute new intel_dp->train_set as requested by target */
1369 intel_get_adjust_train(intel_dp);
1370 ++tries;
1371 }
1372
1373 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1374 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1375 else
1376 reg = DP | DP_LINK_TRAIN_OFF;
1377
1378 I915_WRITE(intel_dp->output_reg, reg);
1379 POSTING_READ(intel_dp->output_reg);
1380 intel_dp_aux_native_write_1(intel_dp,
1381 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1382 }
1383
1384 static void
1385 intel_dp_link_down(struct intel_dp *intel_dp)
1386 {
1387 struct drm_device *dev = intel_dp->base.base.dev;
1388 struct drm_i915_private *dev_priv = dev->dev_private;
1389 uint32_t DP = intel_dp->DP;
1390
1391 DRM_DEBUG_KMS("\n");
1392
1393 if (is_edp(intel_dp)) {
1394 DP &= ~DP_PLL_ENABLE;
1395 I915_WRITE(intel_dp->output_reg, DP);
1396 POSTING_READ(intel_dp->output_reg);
1397 udelay(100);
1398 }
1399
1400 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1401 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1402 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1403 } else {
1404 DP &= ~DP_LINK_TRAIN_MASK;
1405 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1406 }
1407 POSTING_READ(intel_dp->output_reg);
1408
1409 msleep(17);
1410
1411 if (is_edp(intel_dp))
1412 DP |= DP_LINK_TRAIN_OFF;
1413 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1414 POSTING_READ(intel_dp->output_reg);
1415 }
1416
1417 /*
1418 * According to DP spec
1419 * 5.1.2:
1420 * 1. Read DPCD
1421 * 2. Configure link according to Receiver Capabilities
1422 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1423 * 4. Check link status on receipt of hot-plug interrupt
1424 */
1425
1426 static void
1427 intel_dp_check_link_status(struct intel_dp *intel_dp)
1428 {
1429 if (!intel_dp->base.base.crtc)
1430 return;
1431
1432 if (!intel_dp_get_link_status(intel_dp)) {
1433 intel_dp_link_down(intel_dp);
1434 return;
1435 }
1436
1437 if (!intel_channel_eq_ok(intel_dp)) {
1438 intel_dp_start_link_train(intel_dp);
1439 intel_dp_complete_link_train(intel_dp);
1440 }
1441 }
1442
1443 static enum drm_connector_status
1444 ironlake_dp_detect(struct drm_connector *connector)
1445 {
1446 struct intel_dp *intel_dp = intel_attached_dp(connector);
1447 enum drm_connector_status status;
1448
1449 /* Panel needs power for AUX to work */
1450 if (is_edp(intel_dp) || is_pch_edp(intel_dp))
1451 ironlake_edp_panel_vdd_on(connector->dev);
1452 status = connector_status_disconnected;
1453 if (intel_dp_aux_native_read(intel_dp,
1454 0x000, intel_dp->dpcd,
1455 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1456 {
1457 if (intel_dp->dpcd[0] != 0)
1458 status = connector_status_connected;
1459 }
1460 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1461 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1462 if (is_edp(intel_dp) || is_pch_edp(intel_dp))
1463 ironlake_edp_panel_vdd_off(connector->dev);
1464 return status;
1465 }
1466
1467 /**
1468 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1469 *
1470 * \return true if DP port is connected.
1471 * \return false if DP port is disconnected.
1472 */
1473 static enum drm_connector_status
1474 intel_dp_detect(struct drm_connector *connector, bool force)
1475 {
1476 struct intel_dp *intel_dp = intel_attached_dp(connector);
1477 struct drm_device *dev = intel_dp->base.base.dev;
1478 struct drm_i915_private *dev_priv = dev->dev_private;
1479 uint32_t temp, bit;
1480 enum drm_connector_status status;
1481
1482 intel_dp->has_audio = false;
1483
1484 if (HAS_PCH_SPLIT(dev))
1485 return ironlake_dp_detect(connector);
1486
1487 switch (intel_dp->output_reg) {
1488 case DP_B:
1489 bit = DPB_HOTPLUG_INT_STATUS;
1490 break;
1491 case DP_C:
1492 bit = DPC_HOTPLUG_INT_STATUS;
1493 break;
1494 case DP_D:
1495 bit = DPD_HOTPLUG_INT_STATUS;
1496 break;
1497 default:
1498 return connector_status_unknown;
1499 }
1500
1501 temp = I915_READ(PORT_HOTPLUG_STAT);
1502
1503 if ((temp & bit) == 0)
1504 return connector_status_disconnected;
1505
1506 status = connector_status_disconnected;
1507 if (intel_dp_aux_native_read(intel_dp,
1508 0x000, intel_dp->dpcd,
1509 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1510 {
1511 if (intel_dp->dpcd[0] != 0)
1512 status = connector_status_connected;
1513 }
1514 return status;
1515 }
1516
1517 static int intel_dp_get_modes(struct drm_connector *connector)
1518 {
1519 struct intel_dp *intel_dp = intel_attached_dp(connector);
1520 struct drm_device *dev = intel_dp->base.base.dev;
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522 int ret;
1523
1524 /* We should parse the EDID data and find out if it has an audio sink
1525 */
1526
1527 ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1528 if (ret) {
1529 if ((is_edp(intel_dp) || is_pch_edp(intel_dp)) &&
1530 !dev_priv->panel_fixed_mode) {
1531 struct drm_display_mode *newmode;
1532 list_for_each_entry(newmode, &connector->probed_modes,
1533 head) {
1534 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1535 dev_priv->panel_fixed_mode =
1536 drm_mode_duplicate(dev, newmode);
1537 break;
1538 }
1539 }
1540 }
1541
1542 return ret;
1543 }
1544
1545 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1546 if (is_edp(intel_dp) || is_pch_edp(intel_dp)) {
1547 if (dev_priv->panel_fixed_mode != NULL) {
1548 struct drm_display_mode *mode;
1549 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1550 drm_mode_probed_add(connector, mode);
1551 return 1;
1552 }
1553 }
1554 return 0;
1555 }
1556
1557 static void
1558 intel_dp_destroy (struct drm_connector *connector)
1559 {
1560 drm_sysfs_connector_remove(connector);
1561 drm_connector_cleanup(connector);
1562 kfree(connector);
1563 }
1564
1565 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1566 {
1567 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1568
1569 i2c_del_adapter(&intel_dp->adapter);
1570 drm_encoder_cleanup(encoder);
1571 kfree(intel_dp);
1572 }
1573
1574 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1575 .dpms = intel_dp_dpms,
1576 .mode_fixup = intel_dp_mode_fixup,
1577 .prepare = intel_dp_prepare,
1578 .mode_set = intel_dp_mode_set,
1579 .commit = intel_dp_commit,
1580 };
1581
1582 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1583 .dpms = drm_helper_connector_dpms,
1584 .detect = intel_dp_detect,
1585 .fill_modes = drm_helper_probe_single_connector_modes,
1586 .destroy = intel_dp_destroy,
1587 };
1588
1589 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1590 .get_modes = intel_dp_get_modes,
1591 .mode_valid = intel_dp_mode_valid,
1592 .best_encoder = intel_best_encoder,
1593 };
1594
1595 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1596 .destroy = intel_dp_encoder_destroy,
1597 };
1598
1599 static void
1600 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1601 {
1602 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1603
1604 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1605 intel_dp_check_link_status(intel_dp);
1606 }
1607
1608 /* Return which DP Port should be selected for Transcoder DP control */
1609 int
1610 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1611 {
1612 struct drm_device *dev = crtc->dev;
1613 struct drm_mode_config *mode_config = &dev->mode_config;
1614 struct drm_encoder *encoder;
1615
1616 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1617 struct intel_dp *intel_dp;
1618
1619 if (encoder->crtc != crtc)
1620 continue;
1621
1622 intel_dp = enc_to_intel_dp(encoder);
1623 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1624 return intel_dp->output_reg;
1625 }
1626
1627 return -1;
1628 }
1629
1630 /* check the VBT to see whether the eDP is on DP-D port */
1631 bool intel_dpd_is_edp(struct drm_device *dev)
1632 {
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 struct child_device_config *p_child;
1635 int i;
1636
1637 if (!dev_priv->child_dev_num)
1638 return false;
1639
1640 for (i = 0; i < dev_priv->child_dev_num; i++) {
1641 p_child = dev_priv->child_dev + i;
1642
1643 if (p_child->dvo_port == PORT_IDPD &&
1644 p_child->device_type == DEVICE_TYPE_eDP)
1645 return true;
1646 }
1647 return false;
1648 }
1649
1650 void
1651 intel_dp_init(struct drm_device *dev, int output_reg)
1652 {
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654 struct drm_connector *connector;
1655 struct intel_dp *intel_dp;
1656 struct intel_encoder *intel_encoder;
1657 struct intel_connector *intel_connector;
1658 const char *name = NULL;
1659 int type;
1660
1661 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1662 if (!intel_dp)
1663 return;
1664
1665 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1666 if (!intel_connector) {
1667 kfree(intel_dp);
1668 return;
1669 }
1670 intel_encoder = &intel_dp->base;
1671
1672 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1673 if (intel_dpd_is_edp(dev))
1674 intel_dp->is_pch_edp = true;
1675
1676 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1677 type = DRM_MODE_CONNECTOR_eDP;
1678 intel_encoder->type = INTEL_OUTPUT_EDP;
1679 } else {
1680 type = DRM_MODE_CONNECTOR_DisplayPort;
1681 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1682 }
1683
1684 connector = &intel_connector->base;
1685 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1686 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1687
1688 connector->polled = DRM_CONNECTOR_POLL_HPD;
1689
1690 if (output_reg == DP_B || output_reg == PCH_DP_B)
1691 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1692 else if (output_reg == DP_C || output_reg == PCH_DP_C)
1693 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1694 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1695 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1696
1697 if (is_edp(intel_dp))
1698 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1699
1700 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1701 connector->interlace_allowed = true;
1702 connector->doublescan_allowed = 0;
1703
1704 intel_dp->output_reg = output_reg;
1705 intel_dp->has_audio = false;
1706 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1707
1708 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1709 DRM_MODE_ENCODER_TMDS);
1710 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1711
1712 intel_connector_attach_encoder(intel_connector, intel_encoder);
1713 drm_sysfs_connector_add(connector);
1714
1715 /* Set up the DDC bus. */
1716 switch (output_reg) {
1717 case DP_A:
1718 name = "DPDDC-A";
1719 break;
1720 case DP_B:
1721 case PCH_DP_B:
1722 dev_priv->hotplug_supported_mask |=
1723 HDMIB_HOTPLUG_INT_STATUS;
1724 name = "DPDDC-B";
1725 break;
1726 case DP_C:
1727 case PCH_DP_C:
1728 dev_priv->hotplug_supported_mask |=
1729 HDMIC_HOTPLUG_INT_STATUS;
1730 name = "DPDDC-C";
1731 break;
1732 case DP_D:
1733 case PCH_DP_D:
1734 dev_priv->hotplug_supported_mask |=
1735 HDMID_HOTPLUG_INT_STATUS;
1736 name = "DPDDC-D";
1737 break;
1738 }
1739
1740 intel_dp_i2c_init(intel_dp, intel_connector, name);
1741
1742 intel_encoder->hot_plug = intel_dp_hot_plug;
1743
1744 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1745 /* initialize panel mode from VBT if available for eDP */
1746 if (dev_priv->lfp_lvds_vbt_mode) {
1747 dev_priv->panel_fixed_mode =
1748 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1749 if (dev_priv->panel_fixed_mode) {
1750 dev_priv->panel_fixed_mode->type |=
1751 DRM_MODE_TYPE_PREFERRED;
1752 }
1753 }
1754 }
1755
1756 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1757 * 0xd. Failure to do so will result in spurious interrupts being
1758 * generated on the port when a cable is not attached.
1759 */
1760 if (IS_G4X(dev) && !IS_GM45(dev)) {
1761 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1762 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1763 }
1764 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree