3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_address_map.h - Contains the register mapping for the ET1310
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
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22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
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26 * modifications, are permitted provided that the following conditions are met:
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33 * . Redistributions in binary form must reproduce the above copyright notice,
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58 #ifndef _ET1310_ADDRESS_MAP_H_
59 #define _ET1310_ADDRESS_MAP_H_
62 /* START OF GLOBAL REGISTER ADDRESS MAP */
67 * Tx queue start address reg in global address map at address 0x0000
68 * tx queue end address reg in global address map at address 0x0004
69 * rx queue start address reg in global address map at address 0x0008
70 * rx queue end address reg in global address map at address 0x000C
74 * structure for power management control status reg in global address map
75 * located at address 0x0010
76 * jagcore_rx_rdy bit 9
77 * jagcore_tx_rdy bit 8
88 #define ET_PM_PHY_SW_COMA 0x40
89 #define ET_PMCSR_INIT 0x38
92 * Interrupt status reg at address 0x0018
95 #define ET_INTR_TXDMA_ISR 0x00000008
96 #define ET_INTR_TXDMA_ERR 0x00000010
97 #define ET_INTR_RXDMA_XFR_DONE 0x00000020
98 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
99 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
100 #define ET_INTR_RXDMA_STAT_LOW 0x00000100
101 #define ET_INTR_RXDMA_ERR 0x00000200
102 #define ET_INTR_WATCHDOG 0x00004000
103 #define ET_INTR_WOL 0x00008000
104 #define ET_INTR_PHY 0x00010000
105 #define ET_INTR_TXMAC 0x00020000
106 #define ET_INTR_RXMAC 0x00040000
107 #define ET_INTR_MAC_STAT 0x00080000
108 #define ET_INTR_SLV_TIMEOUT 0x00100000
111 * Interrupt mask register at address 0x001C
112 * Interrupt alias clear mask reg at address 0x0020
113 * Interrupt status alias reg at address 0x0024
115 * Same masks as above
119 * Software reset reg at address 0x0028
125 * 5: mac_stat_sw_reset
131 * SLV Timer reg at address 0x002C (low 24 bits)
135 * MSI Configuration reg at address 0x0030
138 #define ET_MSI_VECTOR 0x0000001F
139 #define ET_MSI_TC 0x00070000
142 * Loopback reg located at address 0x0034
145 #define ET_LOOP_MAC 0x00000001
146 #define ET_LOOP_DMA 0x00000002
149 * GLOBAL Module of JAGCore Address Mapping
150 * Located at address 0x0000
152 typedef struct _GLOBAL_t
{ /* Location: */
153 u32 txq_start_addr
; /* 0x0000 */
154 u32 txq_end_addr
; /* 0x0004 */
155 u32 rxq_start_addr
; /* 0x0008 */
156 u32 rxq_end_addr
; /* 0x000C */
157 u32 pm_csr
; /* 0x0010 */
158 u32 unused
; /* 0x0014 */
159 u32 int_status
; /* 0x0018 */
160 u32 int_mask
; /* 0x001C */
161 u32 int_alias_clr_en
; /* 0x0020 */
162 u32 int_status_alias
; /* 0x0024 */
163 u32 sw_reset
; /* 0x0028 */
164 u32 slv_timer
; /* 0x002C */
165 u32 msi_config
; /* 0x0030 */
166 u32 loopback
; /* 0x0034 */
167 u32 watchdog_timer
; /* 0x0038 */
168 } GLOBAL_t
, *PGLOBAL_t
;
170 /* END OF GLOBAL REGISTER ADDRESS MAP */
173 /* START OF TXDMA REGISTER ADDRESS MAP */
176 * txdma control status reg at address 0x1000
179 #define ET_TXDMA_CSR_HALT 0x00000001
180 #define ET_TXDMA_DROP_TLP 0x00000002
181 #define ET_TXDMA_CACHE_THRS 0x000000F0
182 #define ET_TXDMA_CACHE_SHIFT 4
183 #define ET_TXDMA_SNGL_EPKT 0x00000100
184 #define ET_TXDMA_CLASS 0x00001E00
187 * structure for txdma packet ring base address hi reg in txdma address map
188 * located at address 0x1004
189 * Defined earlier (u32)
193 * structure for txdma packet ring base address low reg in txdma address map
194 * located at address 0x1008
195 * Defined earlier (u32)
199 * structure for txdma packet ring number of descriptor reg in txdma address
200 * map. Located at address 0x100C
206 #define ET_DMA10_MASK 0x3FF /* 10 bit mask for DMA10W types */
207 #define ET_DMA10_WRAP 0x400
208 #define ET_DMA4_MASK 0x00F /* 4 bit mask for DMA4W types */
209 #define ET_DMA4_WRAP 0x010
211 #define INDEX10(x) ((x) & ET_DMA10_MASK)
212 #define INDEX4(x) ((x) & ET_DMA4_MASK)
214 extern inline void add_10bit(u32
*v
, int n
)
216 *v
= INDEX10(*v
+ n
) | (*v
& ET_DMA10_WRAP
);
220 * 10bit DMA with wrap
221 * txdma tx queue write address reg in txdma address map at 0x1010
222 * txdma tx queue write address external reg in txdma address map at 0x1014
223 * txdma tx queue read address reg in txdma address map at 0x1018
226 * txdma status writeback address hi reg in txdma address map at0x101C
227 * txdma status writeback address lo reg in txdma address map at 0x1020
229 * 10bit DMA with wrap
230 * txdma service request reg in txdma address map at 0x1024
231 * structure for txdma service complete reg in txdma address map at 0x1028
234 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
235 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
237 * txdma error reg in txdma address map at address 0x1034
247 * Tx DMA Module of JAGCore Address Mapping
248 * Located at address 0x1000
250 typedef struct _TXDMA_t
{ /* Location: */
251 u32 csr
; /* 0x1000 */
252 u32 pr_base_hi
; /* 0x1004 */
253 u32 pr_base_lo
; /* 0x1008 */
254 u32 pr_num_des
; /* 0x100C */
255 u32 txq_wr_addr
; /* 0x1010 */
256 u32 txq_wr_addr_ext
; /* 0x1014 */
257 u32 txq_rd_addr
; /* 0x1018 */
258 u32 dma_wb_base_hi
; /* 0x101C */
259 u32 dma_wb_base_lo
; /* 0x1020 */
260 u32 service_request
; /* 0x1024 */
261 u32 service_complete
; /* 0x1028 */
262 u32 cache_rd_index
; /* 0x102C */
263 u32 cache_wr_index
; /* 0x1030 */
264 u32 TxDmaError
; /* 0x1034 */
265 u32 DescAbortCount
; /* 0x1038 */
266 u32 PayloadAbortCnt
; /* 0x103c */
267 u32 WriteBackAbortCnt
; /* 0x1040 */
268 u32 DescTimeoutCnt
; /* 0x1044 */
269 u32 PayloadTimeoutCnt
; /* 0x1048 */
270 u32 WriteBackTimeoutCnt
; /* 0x104c */
271 u32 DescErrorCount
; /* 0x1050 */
272 u32 PayloadErrorCnt
; /* 0x1054 */
273 u32 WriteBackErrorCnt
; /* 0x1058 */
274 u32 DroppedTLPCount
; /* 0x105c */
275 u32 NewServiceComplete
; /* 0x1060 */
276 u32 EthernetPacketCount
; /* 0x1064 */
277 } TXDMA_t
, *PTXDMA_t
;
279 /* END OF TXDMA REGISTER ADDRESS MAP */
282 /* START OF RXDMA REGISTER ADDRESS MAP */
285 * structure for control status reg in rxdma address map
286 * Located at address 0x2000
288 typedef union _RXDMA_CSR_t
{
291 #ifdef _BIT_FIELDS_HTOL
292 u32 unused2
:14; /* bits 18-31 */
293 u32 halt_status
:1; /* bit 17 */
294 u32 pkt_done_flush
:1; /* bit 16 */
295 u32 pkt_drop_disable
:1; /* bit 15 */
296 u32 unused1
:1; /* bit 14 */
297 u32 fbr1_enable
:1; /* bit 13 */
298 u32 fbr1_size
:2; /* bits 11-12 */
299 u32 fbr0_enable
:1; /* bit 10 */
300 u32 fbr0_size
:2; /* bits 8-9 */
301 u32 dma_big_endian
:1; /* bit 7 */
302 u32 pkt_big_endian
:1; /* bit 6 */
303 u32 psr_big_endian
:1; /* bit 5 */
304 u32 fbr_big_endian
:1; /* bit 4 */
305 u32 tc
:3; /* bits 1-3 */
306 u32 halt
:1; /* bit 0 */
308 u32 halt
:1; /* bit 0 */
309 u32 tc
:3; /* bits 1-3 */
310 u32 fbr_big_endian
:1; /* bit 4 */
311 u32 psr_big_endian
:1; /* bit 5 */
312 u32 pkt_big_endian
:1; /* bit 6 */
313 u32 dma_big_endian
:1; /* bit 7 */
314 u32 fbr0_size
:2; /* bits 8-9 */
315 u32 fbr0_enable
:1; /* bit 10 */
316 u32 fbr1_size
:2; /* bits 11-12 */
317 u32 fbr1_enable
:1; /* bit 13 */
318 u32 unused1
:1; /* bit 14 */
319 u32 pkt_drop_disable
:1; /* bit 15 */
320 u32 pkt_done_flush
:1; /* bit 16 */
321 u32 halt_status
:1; /* bit 17 */
322 u32 unused2
:14; /* bits 18-31 */
325 } RXDMA_CSR_t
, *PRXDMA_CSR_t
;
328 * structure for dma writeback lo reg in rxdma address map
329 * located at address 0x2004
330 * Defined earlier (u32)
334 * structure for dma writeback hi reg in rxdma address map
335 * located at address 0x2008
336 * Defined earlier (u32)
340 * structure for number of packets done reg in rxdma address map
341 * located at address 0x200C
343 typedef union _RXDMA_NUM_PKT_DONE_t
{
346 #ifdef _BIT_FIELDS_HTOL
347 u32 unused
:24; /* bits 8-31 */
348 u32 num_done
:8; /* bits 0-7 */
350 u32 num_done
:8; /* bits 0-7 */
351 u32 unused
:24; /* bits 8-31 */
354 } RXDMA_NUM_PKT_DONE_t
, *PRXDMA_NUM_PKT_DONE_t
;
357 * structure for max packet time reg in rxdma address map
358 * located at address 0x2010
360 typedef union _RXDMA_MAX_PKT_TIME_t
{
363 #ifdef _BIT_FIELDS_HTOL
364 u32 unused
:14; /* bits 18-31 */
365 u32 time_done
:18; /* bits 0-17 */
367 u32 time_done
:18; /* bits 0-17 */
368 u32 unused
:14; /* bits 18-31 */
371 } RXDMA_MAX_PKT_TIME_t
, *PRXDMA_MAX_PKT_TIME_t
;
374 * structure for rx queue read address reg in rxdma address map
375 * located at address 0x2014
376 * Defined earlier (u32)
380 * structure for rx queue read address external reg in rxdma address map
381 * located at address 0x2018
382 * Defined earlier (u32)
386 * structure for rx queue write address reg in rxdma address map
387 * located at address 0x201C
388 * Defined earlier (u32)
392 * structure for packet status ring base address lo reg in rxdma address map
393 * located at address 0x2020
394 * Defined earlier (u32)
398 * structure for packet status ring base address hi reg in rxdma address map
399 * located at address 0x2024
400 * Defined earlier (u32)
404 * structure for packet status ring number of descriptors reg in rxdma address
405 * map. Located at address 0x2028
407 typedef union _RXDMA_PSR_NUM_DES_t
{
410 #ifdef _BIT_FIELDS_HTOL
411 u32 unused
:20; /* bits 12-31 */
412 u32 psr_ndes
:12; /* bit 0-11 */
414 u32 psr_ndes
:12; /* bit 0-11 */
415 u32 unused
:20; /* bits 12-31 */
418 } RXDMA_PSR_NUM_DES_t
, *PRXDMA_PSR_NUM_DES_t
;
421 * structure for packet status ring available offset reg in rxdma address map
422 * located at address 0x202C
424 typedef union _RXDMA_PSR_AVAIL_OFFSET_t
{
427 #ifdef _BIT_FIELDS_HTOL
428 u32 unused
:19; /* bits 13-31 */
429 u32 psr_avail_wrap
:1; /* bit 12 */
430 u32 psr_avail
:12; /* bit 0-11 */
432 u32 psr_avail
:12; /* bit 0-11 */
433 u32 psr_avail_wrap
:1; /* bit 12 */
434 u32 unused
:19; /* bits 13-31 */
437 } RXDMA_PSR_AVAIL_OFFSET_t
, *PRXDMA_PSR_AVAIL_OFFSET_t
;
440 * structure for packet status ring full offset reg in rxdma address map
441 * located at address 0x2030
443 typedef union _RXDMA_PSR_FULL_OFFSET_t
{
446 #ifdef _BIT_FIELDS_HTOL
447 u32 unused
:19; /* bits 13-31 */
448 u32 psr_full_wrap
:1; /* bit 12 */
449 u32 psr_full
:12; /* bit 0-11 */
451 u32 psr_full
:12; /* bit 0-11 */
452 u32 psr_full_wrap
:1; /* bit 12 */
453 u32 unused
:19; /* bits 13-31 */
456 } RXDMA_PSR_FULL_OFFSET_t
, *PRXDMA_PSR_FULL_OFFSET_t
;
459 * structure for packet status ring access index reg in rxdma address map
460 * located at address 0x2034
462 typedef union _RXDMA_PSR_ACCESS_INDEX_t
{
465 #ifdef _BIT_FIELDS_HTOL
466 u32 unused
:27; /* bits 5-31 */
467 u32 psr_ai
:5; /* bits 0-4 */
469 u32 psr_ai
:5; /* bits 0-4 */
470 u32 unused
:27; /* bits 5-31 */
473 } RXDMA_PSR_ACCESS_INDEX_t
, *PRXDMA_PSR_ACCESS_INDEX_t
;
476 * structure for packet status ring minimum descriptors reg in rxdma address
477 * map. Located at address 0x2038
479 typedef union _RXDMA_PSR_MIN_DES_t
{
482 #ifdef _BIT_FIELDS_HTOL
483 u32 unused
:20; /* bits 12-31 */
484 u32 psr_min
:12; /* bits 0-11 */
486 u32 psr_min
:12; /* bits 0-11 */
487 u32 unused
:20; /* bits 12-31 */
490 } RXDMA_PSR_MIN_DES_t
, *PRXDMA_PSR_MIN_DES_t
;
493 * structure for free buffer ring base lo address reg in rxdma address map
494 * located at address 0x203C
495 * Defined earlier (u32)
499 * structure for free buffer ring base hi address reg in rxdma address map
500 * located at address 0x2040
501 * Defined earlier (u32)
505 * structure for free buffer ring number of descriptors reg in rxdma address
506 * map. Located at address 0x2044
508 typedef union _RXDMA_FBR_NUM_DES_t
{
511 #ifdef _BIT_FIELDS_HTOL
512 u32 unused
:22; /* bits 10-31 */
513 u32 fbr_ndesc
:10; /* bits 0-9 */
515 u32 fbr_ndesc
:10; /* bits 0-9 */
516 u32 unused
:22; /* bits 10-31 */
519 } RXDMA_FBR_NUM_DES_t
, *PRXDMA_FBR_NUM_DES_t
;
522 * structure for free buffer ring 0 available offset reg in rxdma address map
523 * located at address 0x2048
524 * Defined earlier (u32)
528 * structure for free buffer ring 0 full offset reg in rxdma address map
529 * located at address 0x204C
530 * Defined earlier (u32)
534 * structure for free buffer cache 0 full offset reg in rxdma address map
535 * located at address 0x2050
537 typedef union _RXDMA_FBC_RD_INDEX_t
{
540 #ifdef _BIT_FIELDS_HTOL
541 u32 unused
:27; /* bits 5-31 */
542 u32 fbc_rdi
:5; /* bit 0-4 */
544 u32 fbc_rdi
:5; /* bit 0-4 */
545 u32 unused
:27; /* bits 5-31 */
548 } RXDMA_FBC_RD_INDEX_t
, *PRXDMA_FBC_RD_INDEX_t
;
551 * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
552 * located at address 0x2054
554 typedef union _RXDMA_FBR_MIN_DES_t
{
557 #ifdef _BIT_FIELDS_HTOL
558 u32 unused
:22; /* bits 10-31 */
559 u32 fbr_min
:10; /* bits 0-9 */
561 u32 fbr_min
:10; /* bits 0-9 */
562 u32 unused
:22; /* bits 10-31 */
565 } RXDMA_FBR_MIN_DES_t
, *PRXDMA_FBR_MIN_DES_t
;
568 * structure for free buffer ring 1 base address lo reg in rxdma address map
569 * located at address 0x2058 - 0x205C
570 * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
574 * structure for free buffer ring 1 number of descriptors reg in rxdma address
575 * map. Located at address 0x2060
576 * Defined earlier (RXDMA_FBR_NUM_DES_t)
580 * structure for free buffer ring 1 available offset reg in rxdma address map
581 * located at address 0x2064
582 * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
586 * structure for free buffer ring 1 full offset reg in rxdma address map
587 * located at address 0x2068
588 * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
592 * structure for free buffer cache 1 read index reg in rxdma address map
593 * located at address 0x206C
594 * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
598 * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
599 * located at address 0x2070
600 * Defined Earlier (RXDMA_FBR_MIN_DES_t)
604 * Rx DMA Module of JAGCore Address Mapping
605 * Located at address 0x2000
607 typedef struct _RXDMA_t
{ /* Location: */
608 RXDMA_CSR_t csr
; /* 0x2000 */
609 u32 dma_wb_base_lo
; /* 0x2004 */
610 u32 dma_wb_base_hi
; /* 0x2008 */
611 RXDMA_NUM_PKT_DONE_t num_pkt_done
; /* 0x200C */
612 RXDMA_MAX_PKT_TIME_t max_pkt_time
; /* 0x2010 */
613 u32 rxq_rd_addr
; /* 0x2014 */
614 u32 rxq_rd_addr_ext
; /* 0x2018 */
615 u32 rxq_wr_addr
; /* 0x201C */
616 u32 psr_base_lo
; /* 0x2020 */
617 u32 psr_base_hi
; /* 0x2024 */
618 RXDMA_PSR_NUM_DES_t psr_num_des
; /* 0x2028 */
619 RXDMA_PSR_AVAIL_OFFSET_t psr_avail_offset
; /* 0x202C */
620 RXDMA_PSR_FULL_OFFSET_t psr_full_offset
; /* 0x2030 */
621 RXDMA_PSR_ACCESS_INDEX_t psr_access_index
; /* 0x2034 */
622 RXDMA_PSR_MIN_DES_t psr_min_des
; /* 0x2038 */
623 u32 fbr0_base_lo
; /* 0x203C */
624 u32 fbr0_base_hi
; /* 0x2040 */
625 RXDMA_FBR_NUM_DES_t fbr0_num_des
; /* 0x2044 */
626 u32 fbr0_avail_offset
; /* 0x2048 */
627 u32 fbr0_full_offset
; /* 0x204C */
628 RXDMA_FBC_RD_INDEX_t fbr0_rd_index
; /* 0x2050 */
629 RXDMA_FBR_MIN_DES_t fbr0_min_des
; /* 0x2054 */
630 u32 fbr1_base_lo
; /* 0x2058 */
631 u32 fbr1_base_hi
; /* 0x205C */
632 RXDMA_FBR_NUM_DES_t fbr1_num_des
; /* 0x2060 */
633 u32 fbr1_avail_offset
; /* 0x2064 */
634 u32 fbr1_full_offset
; /* 0x2068 */
635 RXDMA_FBC_RD_INDEX_t fbr1_rd_index
; /* 0x206C */
636 RXDMA_FBR_MIN_DES_t fbr1_min_des
; /* 0x2070 */
637 } RXDMA_t
, *PRXDMA_t
;
639 /* END OF RXDMA REGISTER ADDRESS MAP */
642 /* START OF TXMAC REGISTER ADDRESS MAP */
645 * structure for control reg in txmac address map
646 * located at address 0x3000
648 typedef union _TXMAC_CTL_t
{
651 #ifdef _BIT_FIELDS_HTOL
652 u32 unused
:24; /* bits 8-31 */
653 u32 cklseg_diable
:1; /* bit 7 */
654 u32 ckbcnt_disable
:1; /* bit 6 */
655 u32 cksegnum
:1; /* bit 5 */
656 u32 async_disable
:1; /* bit 4 */
657 u32 fc_disable
:1; /* bit 3 */
658 u32 mcif_disable
:1; /* bit 2 */
659 u32 mif_disable
:1; /* bit 1 */
660 u32 txmac_en
:1; /* bit 0 */
662 u32 txmac_en
:1; /* bit 0 */
663 u32 mif_disable
:1; /* bit 1 mac interface */
664 u32 mcif_disable
:1; /* bit 2 mem. contr. interface */
665 u32 fc_disable
:1; /* bit 3 */
666 u32 async_disable
:1; /* bit 4 */
667 u32 cksegnum
:1; /* bit 5 */
668 u32 ckbcnt_disable
:1; /* bit 6 */
669 u32 cklseg_diable
:1; /* bit 7 */
670 u32 unused
:24; /* bits 8-31 */
673 } TXMAC_CTL_t
, *PTXMAC_CTL_t
;
676 * structure for shadow pointer reg in txmac address map
677 * located at address 0x3004
679 typedef union _TXMAC_SHADOW_PTR_t
{
682 #ifdef _BIT_FIELDS_HTOL
683 u32 reserved2
:5; /* bits 27-31 */
684 u32 txq_rd_ptr
:11; /* bits 16-26 */
685 u32 reserved
:5; /* bits 11-15 */
686 u32 txq_wr_ptr
:11; /* bits 0-10 */
688 u32 txq_wr_ptr
:11; /* bits 0-10 */
689 u32 reserved
:5; /* bits 11-15 */
690 u32 txq_rd_ptr
:11; /* bits 16-26 */
691 u32 reserved2
:5; /* bits 27-31 */
694 } TXMAC_SHADOW_PTR_t
, *PTXMAC_SHADOW_PTR_t
;
697 * structure for error count reg in txmac address map
698 * located at address 0x3008
700 typedef union _TXMAC_ERR_CNT_t
{
703 #ifdef _BIT_FIELDS_HTOL
704 u32 unused
:20; /* bits 12-31 */
705 u32 reserved
:4; /* bits 8-11 */
706 u32 txq_underrun
:4; /* bits 4-7 */
707 u32 fifo_underrun
:4; /* bits 0-3 */
709 u32 fifo_underrun
:4; /* bits 0-3 */
710 u32 txq_underrun
:4; /* bits 4-7 */
711 u32 reserved
:4; /* bits 8-11 */
712 u32 unused
:20; /* bits 12-31 */
715 } TXMAC_ERR_CNT_t
, *PTXMAC_ERR_CNT_t
;
718 * structure for max fill reg in txmac address map
719 * located at address 0x300C
725 * structure for cf parameter reg in txmac address map
726 * located at address 0x3010
732 * structure for tx test reg in txmac address map
733 * located at address 0x3014
738 * 10-0: txq test pointer
742 * structure for error reg in txmac address map
743 * located at address 0x3018
745 typedef union _TXMAC_ERR_t
{
748 #ifdef _BIT_FIELDS_HTOL
749 u32 unused2
:23; /* bits 9-31 */
750 u32 fifo_underrun
:1; /* bit 8 */
751 u32 unused1
:2; /* bits 6-7 */
752 u32 ctrl2_err
:1; /* bit 5 */
753 u32 txq_underrun
:1; /* bit 4 */
754 u32 bcnt_err
:1; /* bit 3 */
755 u32 lseg_err
:1; /* bit 2 */
756 u32 segnum_err
:1; /* bit 1 */
757 u32 seg0_err
:1; /* bit 0 */
759 u32 seg0_err
:1; /* bit 0 */
760 u32 segnum_err
:1; /* bit 1 */
761 u32 lseg_err
:1; /* bit 2 */
762 u32 bcnt_err
:1; /* bit 3 */
763 u32 txq_underrun
:1; /* bit 4 */
764 u32 ctrl2_err
:1; /* bit 5 */
765 u32 unused1
:2; /* bits 6-7 */
766 u32 fifo_underrun
:1; /* bit 8 */
767 u32 unused2
:23; /* bits 9-31 */
770 } TXMAC_ERR_t
, *PTXMAC_ERR_t
;
773 * structure for error interrupt reg in txmac address map
774 * located at address 0x301C
776 typedef union _TXMAC_ERR_INT_t
{
779 #ifdef _BIT_FIELDS_HTOL
780 u32 unused2
:23; /* bits 9-31 */
781 u32 fifo_underrun
:1; /* bit 8 */
782 u32 unused1
:2; /* bits 6-7 */
783 u32 ctrl2_err
:1; /* bit 5 */
784 u32 txq_underrun
:1; /* bit 4 */
785 u32 bcnt_err
:1; /* bit 3 */
786 u32 lseg_err
:1; /* bit 2 */
787 u32 segnum_err
:1; /* bit 1 */
788 u32 seg0_err
:1; /* bit 0 */
790 u32 seg0_err
:1; /* bit 0 */
791 u32 segnum_err
:1; /* bit 1 */
792 u32 lseg_err
:1; /* bit 2 */
793 u32 bcnt_err
:1; /* bit 3 */
794 u32 txq_underrun
:1; /* bit 4 */
795 u32 ctrl2_err
:1; /* bit 5 */
796 u32 unused1
:2; /* bits 6-7 */
797 u32 fifo_underrun
:1; /* bit 8 */
798 u32 unused2
:23; /* bits 9-31 */
801 } TXMAC_ERR_INT_t
, *PTXMAC_ERR_INT_t
;
804 * structure for error interrupt reg in txmac address map
805 * located at address 0x3020
813 * Tx MAC Module of JAGCore Address Mapping
815 typedef struct _TXMAC_t
{ /* Location: */
816 TXMAC_CTL_t ctl
; /* 0x3000 */
817 TXMAC_SHADOW_PTR_t shadow_ptr
; /* 0x3004 */
818 TXMAC_ERR_CNT_t err_cnt
; /* 0x3008 */
819 u32 max_fill
; /* 0x300C */
820 u32 cf_param
; /* 0x3010 */
821 u32 tx_test
; /* 0x3014 */
822 TXMAC_ERR_t err
; /* 0x3018 */
823 TXMAC_ERR_INT_t err_int
; /* 0x301C */
824 u32 bp_ctrl
; /* 0x3020 */
825 } TXMAC_t
, *PTXMAC_t
;
827 /* END OF TXMAC REGISTER ADDRESS MAP */
829 /* START OF RXMAC REGISTER ADDRESS MAP */
832 * structure for rxmac control reg in rxmac address map
833 * located at address 0x4000
835 typedef union _RXMAC_CTRL_t
{
838 #ifdef _BIT_FIELDS_HTOL
839 u32 reserved
:25; /* bits 7-31 */
840 u32 rxmac_int_disable
:1; /* bit 6 */
841 u32 async_disable
:1; /* bit 5 */
842 u32 mif_disable
:1; /* bit 4 */
843 u32 wol_disable
:1; /* bit 3 */
844 u32 pkt_filter_disable
:1; /* bit 2 */
845 u32 mcif_disable
:1; /* bit 1 */
846 u32 rxmac_en
:1; /* bit 0 */
848 u32 rxmac_en
:1; /* bit 0 */
849 u32 mcif_disable
:1; /* bit 1 */
850 u32 pkt_filter_disable
:1; /* bit 2 */
851 u32 wol_disable
:1; /* bit 3 */
852 u32 mif_disable
:1; /* bit 4 */
853 u32 async_disable
:1; /* bit 5 */
854 u32 rxmac_int_disable
:1; /* bit 6 */
855 u32 reserved
:25; /* bits 7-31 */
858 } RXMAC_CTRL_t
, *PRXMAC_CTRL_t
;
861 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
862 * located at address 0x4004
864 typedef union _RXMAC_WOL_CTL_CRC0_t
{
867 #ifdef _BIT_FIELDS_HTOL
868 u32 crc0
:16; /* bits 16-31 */
869 u32 reserve
:4; /* bits 12-15 */
870 u32 ignore_pp
:1; /* bit 11 */
871 u32 ignore_mp
:1; /* bit 10 */
872 u32 clr_intr
:1; /* bit 9 */
873 u32 ignore_link_chg
:1; /* bit 8 */
874 u32 ignore_uni
:1; /* bit 7 */
875 u32 ignore_multi
:1; /* bit 6 */
876 u32 ignore_broad
:1; /* bit 5 */
877 u32 valid_crc4
:1; /* bit 4 */
878 u32 valid_crc3
:1; /* bit 3 */
879 u32 valid_crc2
:1; /* bit 2 */
880 u32 valid_crc1
:1; /* bit 1 */
881 u32 valid_crc0
:1; /* bit 0 */
883 u32 valid_crc0
:1; /* bit 0 */
884 u32 valid_crc1
:1; /* bit 1 */
885 u32 valid_crc2
:1; /* bit 2 */
886 u32 valid_crc3
:1; /* bit 3 */
887 u32 valid_crc4
:1; /* bit 4 */
888 u32 ignore_broad
:1; /* bit 5 */
889 u32 ignore_multi
:1; /* bit 6 */
890 u32 ignore_uni
:1; /* bit 7 */
891 u32 ignore_link_chg
:1; /* bit 8 */
892 u32 clr_intr
:1; /* bit 9 */
893 u32 ignore_mp
:1; /* bit 10 */
894 u32 ignore_pp
:1; /* bit 11 */
895 u32 reserve
:4; /* bits 12-15 */
896 u32 crc0
:16; /* bits 16-31 */
899 } RXMAC_WOL_CTL_CRC0_t
, *PRXMAC_WOL_CTL_CRC0_t
;
902 * structure for CRC 1 and CRC 2 reg in rxmac address map
903 * located at address 0x4008
905 typedef union _RXMAC_WOL_CRC12_t
{
908 #ifdef _BIT_FIELDS_HTOL
909 u32 crc2
:16; /* bits 16-31 */
910 u32 crc1
:16; /* bits 0-15 */
912 u32 crc1
:16; /* bits 0-15 */
913 u32 crc2
:16; /* bits 16-31 */
916 } RXMAC_WOL_CRC12_t
, *PRXMAC_WOL_CRC12_t
;
919 * structure for CRC 3 and CRC 4 reg in rxmac address map
920 * located at address 0x400C
922 typedef union _RXMAC_WOL_CRC34_t
{
925 #ifdef _BIT_FIELDS_HTOL
926 u32 crc4
:16; /* bits 16-31 */
927 u32 crc3
:16; /* bits 0-15 */
929 u32 crc3
:16; /* bits 0-15 */
930 u32 crc4
:16; /* bits 16-31 */
933 } RXMAC_WOL_CRC34_t
, *PRXMAC_WOL_CRC34_t
;
936 * structure for Wake On Lan Source Address Lo reg in rxmac address map
937 * located at address 0x4010
939 typedef union _RXMAC_WOL_SA_LO_t
{
942 #ifdef _BIT_FIELDS_HTOL
943 u32 sa3
:8; /* bits 24-31 */
944 u32 sa4
:8; /* bits 16-23 */
945 u32 sa5
:8; /* bits 8-15 */
946 u32 sa6
:8; /* bits 0-7 */
948 u32 sa6
:8; /* bits 0-7 */
949 u32 sa5
:8; /* bits 8-15 */
950 u32 sa4
:8; /* bits 16-23 */
951 u32 sa3
:8; /* bits 24-31 */
954 } RXMAC_WOL_SA_LO_t
, *PRXMAC_WOL_SA_LO_t
;
957 * structure for Wake On Lan Source Address Hi reg in rxmac address map
958 * located at address 0x4014
960 typedef union _RXMAC_WOL_SA_HI_t
{
963 #ifdef _BIT_FIELDS_HTOL
964 u32 reserved
:16; /* bits 16-31 */
965 u32 sa1
:8; /* bits 8-15 */
966 u32 sa2
:8; /* bits 0-7 */
968 u32 sa2
:8; /* bits 0-7 */
969 u32 sa1
:8; /* bits 8-15 */
970 u32 reserved
:16; /* bits 16-31 */
973 } RXMAC_WOL_SA_HI_t
, *PRXMAC_WOL_SA_HI_t
;
976 * structure for Wake On Lan mask reg in rxmac address map
977 * located at address 0x4018 - 0x4064
978 * Defined earlier (u32)
982 * structure for Unicast Paket Filter Address 1 reg in rxmac address map
983 * located at address 0x4068
985 typedef union _RXMAC_UNI_PF_ADDR1_t
{
988 #ifdef _BIT_FIELDS_HTOL
989 u32 addr1_3
:8; /* bits 24-31 */
990 u32 addr1_4
:8; /* bits 16-23 */
991 u32 addr1_5
:8; /* bits 8-15 */
992 u32 addr1_6
:8; /* bits 0-7 */
994 u32 addr1_6
:8; /* bits 0-7 */
995 u32 addr1_5
:8; /* bits 8-15 */
996 u32 addr1_4
:8; /* bits 16-23 */
997 u32 addr1_3
:8; /* bits 24-31 */
1000 } RXMAC_UNI_PF_ADDR1_t
, *PRXMAC_UNI_PF_ADDR1_t
;
1003 * structure for Unicast Paket Filter Address 2 reg in rxmac address map
1004 * located at address 0x406C
1006 typedef union _RXMAC_UNI_PF_ADDR2_t
{
1009 #ifdef _BIT_FIELDS_HTOL
1010 u32 addr2_3
:8; /* bits 24-31 */
1011 u32 addr2_4
:8; /* bits 16-23 */
1012 u32 addr2_5
:8; /* bits 8-15 */
1013 u32 addr2_6
:8; /* bits 0-7 */
1015 u32 addr2_6
:8; /* bits 0-7 */
1016 u32 addr2_5
:8; /* bits 8-15 */
1017 u32 addr2_4
:8; /* bits 16-23 */
1018 u32 addr2_3
:8; /* bits 24-31 */
1021 } RXMAC_UNI_PF_ADDR2_t
, *PRXMAC_UNI_PF_ADDR2_t
;
1024 * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
1025 * located at address 0x4070
1027 typedef union _RXMAC_UNI_PF_ADDR3_t
{
1030 #ifdef _BIT_FIELDS_HTOL
1031 u32 addr2_1
:8; /* bits 24-31 */
1032 u32 addr2_2
:8; /* bits 16-23 */
1033 u32 addr1_1
:8; /* bits 8-15 */
1034 u32 addr1_2
:8; /* bits 0-7 */
1036 u32 addr1_2
:8; /* bits 0-7 */
1037 u32 addr1_1
:8; /* bits 8-15 */
1038 u32 addr2_2
:8; /* bits 16-23 */
1039 u32 addr2_1
:8; /* bits 24-31 */
1042 } RXMAC_UNI_PF_ADDR3_t
, *PRXMAC_UNI_PF_ADDR3_t
;
1045 * structure for Multicast Hash reg in rxmac address map
1046 * located at address 0x4074 - 0x4080
1047 * Defined earlier (u32)
1051 * structure for Packet Filter Control reg in rxmac address map
1052 * located at address 0x4084
1054 typedef union _RXMAC_PF_CTRL_t
{
1057 #ifdef _BIT_FIELDS_HTOL
1058 u32 unused2
:9; /* bits 23-31 */
1059 u32 min_pkt_size
:7; /* bits 16-22 */
1060 u32 unused1
:12; /* bits 4-15 */
1061 u32 filter_frag_en
:1; /* bit 3 */
1062 u32 filter_uni_en
:1; /* bit 2 */
1063 u32 filter_multi_en
:1; /* bit 1 */
1064 u32 filter_broad_en
:1; /* bit 0 */
1066 u32 filter_broad_en
:1; /* bit 0 */
1067 u32 filter_multi_en
:1; /* bit 1 */
1068 u32 filter_uni_en
:1; /* bit 2 */
1069 u32 filter_frag_en
:1; /* bit 3 */
1070 u32 unused1
:12; /* bits 4-15 */
1071 u32 min_pkt_size
:7; /* bits 16-22 */
1072 u32 unused2
:9; /* bits 23-31 */
1075 } RXMAC_PF_CTRL_t
, *PRXMAC_PF_CTRL_t
;
1078 * structure for Memory Controller Interface Control Max Segment reg in rxmac
1079 * address map. Located at address 0x4088
1081 typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t
{
1084 #ifdef _BIT_FIELDS_HTOL
1085 u32 reserved
:22; /* bits 10-31 */
1086 u32 max_size
:8; /* bits 2-9 */
1087 u32 fc_en
:1; /* bit 1 */
1088 u32 seg_en
:1; /* bit 0 */
1090 u32 seg_en
:1; /* bit 0 */
1091 u32 fc_en
:1; /* bit 1 */
1092 u32 max_size
:8; /* bits 2-9 */
1093 u32 reserved
:22; /* bits 10-31 */
1096 } RXMAC_MCIF_CTRL_MAX_SEG_t
, *PRXMAC_MCIF_CTRL_MAX_SEG_t
;
1099 * structure for Memory Controller Interface Water Mark reg in rxmac address
1100 * map. Located at address 0x408C
1102 typedef union _RXMAC_MCIF_WATER_MARK_t
{
1105 #ifdef _BIT_FIELDS_HTOL
1106 u32 reserved2
:6; /* bits 26-31 */
1107 u32 mark_hi
:10; /* bits 16-25 */
1108 u32 reserved1
:6; /* bits 10-15 */
1109 u32 mark_lo
:10; /* bits 0-9 */
1111 u32 mark_lo
:10; /* bits 0-9 */
1112 u32 reserved1
:6; /* bits 10-15 */
1113 u32 mark_hi
:10; /* bits 16-25 */
1114 u32 reserved2
:6; /* bits 26-31 */
1117 } RXMAC_MCIF_WATER_MARK_t
, *PRXMAC_MCIF_WATER_MARK_t
;
1120 * structure for Rx Queue Dialog reg in rxmac address map.
1121 * located at address 0x4090
1123 typedef union _RXMAC_RXQ_DIAG_t
{
1126 #ifdef _BIT_FIELDS_HTOL
1127 u32 reserved2
:6; /* bits 26-31 */
1128 u32 rd_ptr
:10; /* bits 16-25 */
1129 u32 reserved1
:6; /* bits 10-15 */
1130 u32 wr_ptr
:10; /* bits 0-9 */
1132 u32 wr_ptr
:10; /* bits 0-9 */
1133 u32 reserved1
:6; /* bits 10-15 */
1134 u32 rd_ptr
:10; /* bits 16-25 */
1135 u32 reserved2
:6; /* bits 26-31 */
1138 } RXMAC_RXQ_DIAG_t
, *PRXMAC_RXQ_DIAG_t
;
1141 * structure for space availiable reg in rxmac address map.
1142 * located at address 0x4094
1144 typedef union _RXMAC_SPACE_AVAIL_t
{
1147 #ifdef _BIT_FIELDS_HTOL
1148 u32 reserved2
:15; /* bits 17-31 */
1149 u32 space_avail_en
:1; /* bit 16 */
1150 u32 reserved1
:6; /* bits 10-15 */
1151 u32 space_avail
:10; /* bits 0-9 */
1153 u32 space_avail
:10; /* bits 0-9 */
1154 u32 reserved1
:6; /* bits 10-15 */
1155 u32 space_avail_en
:1; /* bit 16 */
1156 u32 reserved2
:15; /* bits 17-31 */
1159 } RXMAC_SPACE_AVAIL_t
, *PRXMAC_SPACE_AVAIL_t
;
1162 * structure for management interface reg in rxmac address map.
1163 * located at address 0x4098
1165 typedef union _RXMAC_MIF_CTL_t
{
1168 #ifdef _BIT_FIELDS_HTOL
1169 u32 reserve
:14; /* bits 18-31 */
1170 u32 drop_pkt_en
:1; /* bit 17 */
1171 u32 drop_pkt_mask
:17; /* bits 0-16 */
1173 u32 drop_pkt_mask
:17; /* bits 0-16 */
1174 u32 drop_pkt_en
:1; /* bit 17 */
1175 u32 reserve
:14; /* bits 18-31 */
1178 } RXMAC_MIF_CTL_t
, *PRXMAC_MIF_CTL_t
;
1181 * structure for Error reg in rxmac address map.
1182 * located at address 0x409C
1184 typedef union _RXMAC_ERROR_REG_t
{
1187 #ifdef _BIT_FIELDS_HTOL
1188 u32 reserve
:28; /* bits 4-31 */
1189 u32 mif
:1; /* bit 3 */
1190 u32 async
:1; /* bit 2 */
1191 u32 pkt_filter
:1; /* bit 1 */
1192 u32 mcif
:1; /* bit 0 */
1194 u32 mcif
:1; /* bit 0 */
1195 u32 pkt_filter
:1; /* bit 1 */
1196 u32 async
:1; /* bit 2 */
1197 u32 mif
:1; /* bit 3 */
1198 u32 reserve
:28; /* bits 4-31 */
1201 } RXMAC_ERROR_REG_t
, *PRXMAC_ERROR_REG_t
;
1204 * Rx MAC Module of JAGCore Address Mapping
1206 typedef struct _RXMAC_t
{ /* Location: */
1207 RXMAC_CTRL_t ctrl
; /* 0x4000 */
1208 RXMAC_WOL_CTL_CRC0_t crc0
; /* 0x4004 */
1209 RXMAC_WOL_CRC12_t crc12
; /* 0x4008 */
1210 RXMAC_WOL_CRC34_t crc34
; /* 0x400C */
1211 RXMAC_WOL_SA_LO_t sa_lo
; /* 0x4010 */
1212 RXMAC_WOL_SA_HI_t sa_hi
; /* 0x4014 */
1213 u32 mask0_word0
; /* 0x4018 */
1214 u32 mask0_word1
; /* 0x401C */
1215 u32 mask0_word2
; /* 0x4020 */
1216 u32 mask0_word3
; /* 0x4024 */
1217 u32 mask1_word0
; /* 0x4028 */
1218 u32 mask1_word1
; /* 0x402C */
1219 u32 mask1_word2
; /* 0x4030 */
1220 u32 mask1_word3
; /* 0x4034 */
1221 u32 mask2_word0
; /* 0x4038 */
1222 u32 mask2_word1
; /* 0x403C */
1223 u32 mask2_word2
; /* 0x4040 */
1224 u32 mask2_word3
; /* 0x4044 */
1225 u32 mask3_word0
; /* 0x4048 */
1226 u32 mask3_word1
; /* 0x404C */
1227 u32 mask3_word2
; /* 0x4050 */
1228 u32 mask3_word3
; /* 0x4054 */
1229 u32 mask4_word0
; /* 0x4058 */
1230 u32 mask4_word1
; /* 0x405C */
1231 u32 mask4_word2
; /* 0x4060 */
1232 u32 mask4_word3
; /* 0x4064 */
1233 RXMAC_UNI_PF_ADDR1_t uni_pf_addr1
; /* 0x4068 */
1234 RXMAC_UNI_PF_ADDR2_t uni_pf_addr2
; /* 0x406C */
1235 RXMAC_UNI_PF_ADDR3_t uni_pf_addr3
; /* 0x4070 */
1236 u32 multi_hash1
; /* 0x4074 */
1237 u32 multi_hash2
; /* 0x4078 */
1238 u32 multi_hash3
; /* 0x407C */
1239 u32 multi_hash4
; /* 0x4080 */
1240 RXMAC_PF_CTRL_t pf_ctrl
; /* 0x4084 */
1241 RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg
; /* 0x4088 */
1242 RXMAC_MCIF_WATER_MARK_t mcif_water_mark
; /* 0x408C */
1243 RXMAC_RXQ_DIAG_t rxq_diag
; /* 0x4090 */
1244 RXMAC_SPACE_AVAIL_t space_avail
; /* 0x4094 */
1246 RXMAC_MIF_CTL_t mif_ctrl
; /* 0x4098 */
1247 RXMAC_ERROR_REG_t err_reg
; /* 0x409C */
1248 } RXMAC_t
, *PRXMAC_t
;
1250 /* END OF TXMAC REGISTER ADDRESS MAP */
1253 /* START OF MAC REGISTER ADDRESS MAP */
1256 * structure for configuration #1 reg in mac address map.
1257 * located at address 0x5000
1277 #define CFG1_LOOPBACK 0x00000100
1278 #define CFG1_RX_FLOW 0x00000020
1279 #define CFG1_TX_FLOW 0x00000010
1280 #define CFG1_RX_ENABLE 0x00000004
1281 #define CFG1_TX_ENABLE 0x00000001
1282 #define CFG1_WAIT 0x0000000A /* RX & TX syncd */
1285 * structure for configuration #2 reg in mac address map.
1286 * located at address 0x5004
1302 * structure for Interpacket gap reg in mac address map.
1303 * located at address 0x5008
1306 * 30-24: non B2B ipg 1
1308 * 22-16: non B2B ipg 2
1309 * 15-8: Min ifg enforce
1312 * structure for half duplex reg in mac address map.
1313 * located at address 0x500C
1315 * 23-20: Alt BEB trunc
1316 * 19: Alt BEB enable
1320 * 15-12: re-xmit max
1322 * 9-0: collision window
1326 * structure for Maximum Frame Length reg in mac address map.
1327 * located at address 0x5010: bits 0-15 hold the length.
1331 * structure for Reserve 1 reg in mac address map.
1332 * located at address 0x5014 - 0x5018
1333 * Defined earlier (u32)
1337 * structure for Test reg in mac address map.
1338 * located at address 0x501C
1339 * test: bits 0-2, rest unused
1343 * structure for MII Management Configuration reg in mac address map.
1344 * located at address 0x5020
1346 * 31: reset MII mgmt
1348 * 5: scan auto increment
1349 * 4: preamble supress
1351 * 2-0: mgmt clock reset
1355 * structure for MII Management Command reg in mac address map.
1356 * located at address 0x5024
1362 * structure for MII Management Address reg in mac address map.
1363 * located at address 0x5028
1370 #define MII_ADDR(phy,reg) ((phy) << 8 | (reg))
1373 * structure for MII Management Control reg in mac address map.
1374 * located at address 0x502C
1380 * structure for MII Management Status reg in mac address map.
1381 * located at address 0x5030
1387 * structure for MII Management Indicators reg in mac address map.
1388 * located at address 0x5034
1395 #define MGMT_BUSY 0x00000001 /* busy */
1396 #define MGMT_WAIT 0x00000005 /* busy | not valid */
1399 * structure for Interface Control reg in mac address map.
1400 * located at address 0x5038
1402 * 31: reset if module
1415 * 8: disable link fail
1418 * 0: enable jabber protection
1422 * structure for Interface Status reg in mac address map.
1423 * located at address 0x503C
1425 typedef union _MAC_IF_STAT_t
{
1428 #ifdef _BIT_FIELDS_HTOL
1429 u32 reserved
:22; /* bits 10-31 */
1430 u32 excess_defer
:1; /* bit 9 */
1431 u32 clash
:1; /* bit 8 */
1432 u32 phy_jabber
:1; /* bit 7 */
1433 u32 phy_link_ok
:1; /* bit 6 */
1434 u32 phy_full_duplex
:1; /* bit 5 */
1435 u32 phy_speed
:1; /* bit 4 */
1436 u32 pe100x_link_fail
:1; /* bit 3 */
1437 u32 pe10t_loss_carrie
:1; /* bit 2 */
1438 u32 pe10t_sqe_error
:1; /* bit 1 */
1439 u32 pe10t_jabber
:1; /* bit 0 */
1441 u32 pe10t_jabber
:1; /* bit 0 */
1442 u32 pe10t_sqe_error
:1; /* bit 1 */
1443 u32 pe10t_loss_carrie
:1; /* bit 2 */
1444 u32 pe100x_link_fail
:1; /* bit 3 */
1445 u32 phy_speed
:1; /* bit 4 */
1446 u32 phy_full_duplex
:1; /* bit 5 */
1447 u32 phy_link_ok
:1; /* bit 6 */
1448 u32 phy_jabber
:1; /* bit 7 */
1449 u32 clash
:1; /* bit 8 */
1450 u32 excess_defer
:1; /* bit 9 */
1451 u32 reserved
:22; /* bits 10-31 */
1454 } MAC_IF_STAT_t
, *PMAC_IF_STAT_t
;
1457 * structure for Mac Station Address, Part 1 reg in mac address map.
1458 * located at address 0x5040
1460 typedef union _MAC_STATION_ADDR1_t
{
1463 #ifdef _BIT_FIELDS_HTOL
1464 u32 Octet6
:8; /* bits 24-31 */
1465 u32 Octet5
:8; /* bits 16-23 */
1466 u32 Octet4
:8; /* bits 8-15 */
1467 u32 Octet3
:8; /* bits 0-7 */
1469 u32 Octet3
:8; /* bits 0-7 */
1470 u32 Octet4
:8; /* bits 8-15 */
1471 u32 Octet5
:8; /* bits 16-23 */
1472 u32 Octet6
:8; /* bits 24-31 */
1475 } MAC_STATION_ADDR1_t
, *PMAC_STATION_ADDR1_t
;
1478 * structure for Mac Station Address, Part 2 reg in mac address map.
1479 * located at address 0x5044
1481 typedef union _MAC_STATION_ADDR2_t
{
1484 #ifdef _BIT_FIELDS_HTOL
1485 u32 Octet2
:8; /* bits 24-31 */
1486 u32 Octet1
:8; /* bits 16-23 */
1487 u32 reserved
:16; /* bits 0-15 */
1489 u32 reserved
:16; /* bit 0-15 */
1490 u32 Octet1
:8; /* bits 16-23 */
1491 u32 Octet2
:8; /* bits 24-31 */
1494 } MAC_STATION_ADDR2_t
, *PMAC_STATION_ADDR2_t
;
1497 * MAC Module of JAGCore Address Mapping
1499 typedef struct _MAC_t
{ /* Location: */
1500 u32 cfg1
; /* 0x5000 */
1501 u32 cfg2
; /* 0x5004 */
1502 u32 ipg
; /* 0x5008 */
1503 u32 hfdp
; /* 0x500C */
1504 u32 max_fm_len
; /* 0x5010 */
1505 u32 rsv1
; /* 0x5014 */
1506 u32 rsv2
; /* 0x5018 */
1507 u32 mac_test
; /* 0x501C */
1508 u32 mii_mgmt_cfg
; /* 0x5020 */
1509 u32 mii_mgmt_cmd
; /* 0x5024 */
1510 u32 mii_mgmt_addr
; /* 0x5028 */
1511 u32 mii_mgmt_ctrl
; /* 0x502C */
1512 u32 mii_mgmt_stat
; /* 0x5030 */
1513 u32 mii_mgmt_indicator
; /* 0x5034 */
1514 u32 if_ctrl
; /* 0x5038 */
1515 MAC_IF_STAT_t if_stat
; /* 0x503C */
1516 MAC_STATION_ADDR1_t station_addr_1
; /* 0x5040 */
1517 MAC_STATION_ADDR2_t station_addr_2
; /* 0x5044 */
1520 /* END OF MAC REGISTER ADDRESS MAP */
1522 /* START OF MAC STAT REGISTER ADDRESS MAP */
1525 * structure for Carry Register One and it's Mask Register reg located in mac
1526 * stat address map address 0x6130 and 0x6138.
1556 * structure for Carry Register Two Mask Register reg in mac stat address map.
1557 * located at address 0x613C
1583 * MAC STATS Module of JAGCore Address Mapping
1585 typedef struct _MAC_STAT_t
{ /* Location: */
1586 u32 pad
[32]; /* 0x6000 - 607C */
1588 /* Tx/Rx 0-64 Byte Frame Counter */
1589 u32 TR64
; /* 0x6080 */
1591 /* Tx/Rx 65-127 Byte Frame Counter */
1592 u32 TR127
; /* 0x6084 */
1594 /* Tx/Rx 128-255 Byte Frame Counter */
1595 u32 TR255
; /* 0x6088 */
1597 /* Tx/Rx 256-511 Byte Frame Counter */
1598 u32 TR511
; /* 0x608C */
1600 /* Tx/Rx 512-1023 Byte Frame Counter */
1601 u32 TR1K
; /* 0x6090 */
1603 /* Tx/Rx 1024-1518 Byte Frame Counter */
1604 u32 TRMax
; /* 0x6094 */
1606 /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1607 u32 TRMgv
; /* 0x6098 */
1609 /* Rx Byte Counter */
1610 u32 RByt
; /* 0x609C */
1612 /* Rx Packet Counter */
1613 u32 RPkt
; /* 0x60A0 */
1615 /* Rx FCS Error Counter */
1616 u32 RFcs
; /* 0x60A4 */
1618 /* Rx Multicast Packet Counter */
1619 u32 RMca
; /* 0x60A8 */
1621 /* Rx Broadcast Packet Counter */
1622 u32 RBca
; /* 0x60AC */
1624 /* Rx Control Frame Packet Counter */
1625 u32 RxCf
; /* 0x60B0 */
1627 /* Rx Pause Frame Packet Counter */
1628 u32 RxPf
; /* 0x60B4 */
1630 /* Rx Unknown OP Code Counter */
1631 u32 RxUo
; /* 0x60B8 */
1633 /* Rx Alignment Error Counter */
1634 u32 RAln
; /* 0x60BC */
1636 /* Rx Frame Length Error Counter */
1637 u32 RFlr
; /* 0x60C0 */
1639 /* Rx Code Error Counter */
1640 u32 RCde
; /* 0x60C4 */
1642 /* Rx Carrier Sense Error Counter */
1643 u32 RCse
; /* 0x60C8 */
1645 /* Rx Undersize Packet Counter */
1646 u32 RUnd
; /* 0x60CC */
1648 /* Rx Oversize Packet Counter */
1649 u32 ROvr
; /* 0x60D0 */
1651 /* Rx Fragment Counter */
1652 u32 RFrg
; /* 0x60D4 */
1654 /* Rx Jabber Counter */
1655 u32 RJbr
; /* 0x60D8 */
1658 u32 RDrp
; /* 0x60DC */
1660 /* Tx Byte Counter */
1661 u32 TByt
; /* 0x60E0 */
1663 /* Tx Packet Counter */
1664 u32 TPkt
; /* 0x60E4 */
1666 /* Tx Multicast Packet Counter */
1667 u32 TMca
; /* 0x60E8 */
1669 /* Tx Broadcast Packet Counter */
1670 u32 TBca
; /* 0x60EC */
1672 /* Tx Pause Control Frame Counter */
1673 u32 TxPf
; /* 0x60F0 */
1675 /* Tx Deferral Packet Counter */
1676 u32 TDfr
; /* 0x60F4 */
1678 /* Tx Excessive Deferral Packet Counter */
1679 u32 TEdf
; /* 0x60F8 */
1681 /* Tx Single Collision Packet Counter */
1682 u32 TScl
; /* 0x60FC */
1684 /* Tx Multiple Collision Packet Counter */
1685 u32 TMcl
; /* 0x6100 */
1687 /* Tx Late Collision Packet Counter */
1688 u32 TLcl
; /* 0x6104 */
1690 /* Tx Excessive Collision Packet Counter */
1691 u32 TXcl
; /* 0x6108 */
1693 /* Tx Total Collision Packet Counter */
1694 u32 TNcl
; /* 0x610C */
1696 /* Tx Pause Frame Honored Counter */
1697 u32 TPfh
; /* 0x6110 */
1699 /* Tx Drop Frame Counter */
1700 u32 TDrp
; /* 0x6114 */
1702 /* Tx Jabber Frame Counter */
1703 u32 TJbr
; /* 0x6118 */
1705 /* Tx FCS Error Counter */
1706 u32 TFcs
; /* 0x611C */
1708 /* Tx Control Frame Counter */
1709 u32 TxCf
; /* 0x6120 */
1711 /* Tx Oversize Frame Counter */
1712 u32 TOvr
; /* 0x6124 */
1714 /* Tx Undersize Frame Counter */
1715 u32 TUnd
; /* 0x6128 */
1717 /* Tx Fragments Frame Counter */
1718 u32 TFrg
; /* 0x612C */
1720 /* Carry Register One Register */
1721 u32 Carry1
; /* 0x6130 */
1723 /* Carry Register Two Register */
1724 u32 Carry2
; /* 0x6134 */
1726 /* Carry Register One Mask Register */
1727 u32 Carry1M
; /* 0x6138 */
1729 /* Carry Register Two Mask Register */
1730 u32 Carry2M
; /* 0x613C */
1731 } MAC_STAT_t
, *PMAC_STAT_t
;
1733 /* END OF MAC STAT REGISTER ADDRESS MAP */
1736 /* START OF MMC REGISTER ADDRESS MAP */
1739 * Main Memory Controller Control reg in mmc address map.
1740 * located at address 0x7000
1743 #define ET_MMC_ENABLE 1
1744 #define ET_MMC_ARB_DISABLE 2
1745 #define ET_MMC_RXMAC_DISABLE 4
1746 #define ET_MMC_TXMAC_DISABLE 8
1747 #define ET_MMC_TXDMA_DISABLE 16
1748 #define ET_MMC_RXDMA_DISABLE 32
1749 #define ET_MMC_FORCE_CE 64
1752 * Main Memory Controller Host Memory Access Address reg in mmc
1753 * address map. Located at address 0x7004. Top 16 bits hold the address bits
1756 #define ET_SRAM_REQ_ACCESS 1
1757 #define ET_SRAM_WR_ACCESS 2
1758 #define ET_SRAM_IS_CTRL 4
1761 * structure for Main Memory Controller Host Memory Access Data reg in mmc
1762 * address map. Located at address 0x7008 - 0x7014
1763 * Defined earlier (u32)
1767 * Memory Control Module of JAGCore Address Mapping
1769 typedef struct _MMC_t
{ /* Location: */
1770 u32 mmc_ctrl
; /* 0x7000 */
1771 u32 sram_access
; /* 0x7004 */
1772 u32 sram_word1
; /* 0x7008 */
1773 u32 sram_word2
; /* 0x700C */
1774 u32 sram_word3
; /* 0x7010 */
1775 u32 sram_word4
; /* 0x7014 */
1778 /* END OF MMC REGISTER ADDRESS MAP */
1781 /* START OF EXP ROM REGISTER ADDRESS MAP */
1784 * Expansion ROM Module of JAGCore Address Mapping
1787 /* Take this out until it is not empty */
1789 typedef struct _EXP_ROM_t
{
1791 } EXP_ROM_t
, *PEXP_ROM_t
;
1794 /* END OF EXP ROM REGISTER ADDRESS MAP */
1798 * JAGCore Address Mapping
1800 typedef struct _ADDRESS_MAP_t
{
1802 /* unused section of global address map */
1803 u8 unused_global
[4096 - sizeof(GLOBAL_t
)];
1805 /* unused section of txdma address map */
1806 u8 unused_txdma
[4096 - sizeof(TXDMA_t
)];
1808 /* unused section of rxdma address map */
1809 u8 unused_rxdma
[4096 - sizeof(RXDMA_t
)];
1811 /* unused section of txmac address map */
1812 u8 unused_txmac
[4096 - sizeof(TXMAC_t
)];
1814 /* unused section of rxmac address map */
1815 u8 unused_rxmac
[4096 - sizeof(RXMAC_t
)];
1817 /* unused section of mac address map */
1818 u8 unused_mac
[4096 - sizeof(MAC_t
)];
1820 /* unused section of mac stat address map */
1821 u8 unused_mac_stat
[4096 - sizeof(MAC_STAT_t
)];
1823 /* unused section of mmc address map */
1824 u8 unused_mmc
[4096 - sizeof(MMC_t
)];
1825 /* unused section of address map */
1826 u8 unused_
[1015808];
1828 /* Take this out until it is not empty */
1833 u8 unused_exp_rom
[4096]; /* MGS-size TBD */
1834 u8 unused__
[524288]; /* unused section of address map */
1835 } ADDRESS_MAP_t
, *PADDRESS_MAP_t
;
1837 #endif /* _ET1310_ADDRESS_MAP_H_ */