drivers/net/wireless/ath/ath9k/debug.h

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef DEBUG_H
  18 #define DEBUG_H
  19
  20 #include "hw.h"
  21 #include "rc.h"
  22
  23 struct ath_txq;
  24 struct ath_buf;
  25
  26 #ifdef CONFIG_ATH9K_DEBUGFS
  27 #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
  28 #else
  29 #define TX_STAT_INC(q, c) do { } while (0)
  30 #endif
  31
  32 #ifdef CONFIG_ATH9K_DEBUGFS
  33
  34 /**
  35  * struct ath_interrupt_stats - Contains statistics about interrupts
  36  * @total: Total no. of interrupts generated so far
  37  * @rxok: RX with no errors
  38  * @rxlp: RX with low priority RX
  39  * @rxhp: RX with high priority, uapsd only
  40  * @rxeol: RX with no more RXDESC available
  41  * @rxorn: RX FIFO overrun
  42  * @txok: TX completed at the requested rate
  43  * @txurn: TX FIFO underrun
  44  * @mib: MIB regs reaching its threshold
  45  * @rxphyerr: RX with phy errors
  46  * @rx_keycache_miss: RX with key cache misses
  47  * @swba: Software Beacon Alert
  48  * @bmiss: Beacon Miss
  49  * @bnr: Beacon Not Ready
  50  * @cst: Carrier Sense TImeout
  51  * @gtt: Global TX Timeout
  52  * @tim: RX beacon TIM occurrence
  53  * @cabend: RX End of CAB traffic
  54  * @dtimsync: DTIM sync lossage
  55  * @dtim: RX Beacon with DTIM
  56  * @bb_watchdog: Baseband watchdog
  57  * @tsfoor: TSF out of range, indicates that the corrected TSF received
  58  * from a beacon differs from the PCU's internal TSF by more than a
  59  * (programmable) threshold
  60  */
  61 struct ath_interrupt_stats {
  62         u32 total;
  63         u32 rxok;
  64         u32 rxlp;
  65         u32 rxhp;
  66         u32 rxeol;
  67         u32 rxorn;
  68         u32 txok;
  69         u32 txeol;
  70         u32 txurn;
  71         u32 mib;
  72         u32 rxphyerr;
  73         u32 rx_keycache_miss;
  74         u32 swba;
  75         u32 bmiss;
  76         u32 bnr;
  77         u32 cst;
  78         u32 gtt;
  79         u32 tim;
  80         u32 cabend;
  81         u32 dtimsync;
  82         u32 dtim;
  83         u32 bb_watchdog;
  84         u32 tsfoor;
  85 };
  86
  87 /**
  88  * struct ath_tx_stats - Statistics about TX
  89  * @tx_pkts_all:  No. of total frames transmitted, including ones that
  90         may have had errors.
  91  * @tx_bytes_all:  No. of total bytes transmitted, including ones that
  92         may have had errors.
  93  * @queued: Total MPDUs (non-aggr) queued
  94  * @completed: Total MPDUs (non-aggr) completed
  95  * @a_aggr: Total no. of aggregates queued
  96  * @a_queued_hw: Total AMPDUs queued to hardware
  97  * @a_queued_sw: Total AMPDUs queued to software queues
  98  * @a_completed: Total AMPDUs completed
  99  * @a_retries: No. of AMPDUs retried (SW)
 100  * @a_xretries: No. of AMPDUs dropped due to xretries
 101  * @fifo_underrun: FIFO underrun occurrences
 102         Valid only for:
 103                 - non-aggregate condition.
 104                 - first packet of aggregate.
 105  * @xtxop: No. of frames filtered because of TXOP limit
 106  * @timer_exp: Transmit timer expiry
 107  * @desc_cfg_err: Descriptor configuration errors
 108  * @data_urn: TX data underrun errors
 109  * @delim_urn: TX delimiter underrun errors
 110  * @puttxbuf: Number of times hardware was given txbuf to write.
 111  * @txstart:  Number of times hardware was told to start tx.
 112  * @txprocdesc:  Number of times tx descriptor was processed
 113  */
 114 struct ath_tx_stats {
 115         u32 tx_pkts_all;
 116         u32 tx_bytes_all;
 117         u32 queued;
 118         u32 completed;
 119         u32 xretries;
 120         u32 a_aggr;
 121         u32 a_queued_hw;
 122         u32 a_queued_sw;
 123         u32 a_completed;
 124         u32 a_retries;
 125         u32 a_xretries;
 126         u32 fifo_underrun;
 127         u32 xtxop;
 128         u32 timer_exp;
 129         u32 desc_cfg_err;
 130         u32 data_underrun;
 131         u32 delim_underrun;
 132         u32 puttxbuf;
 133         u32 txstart;
 134         u32 txprocdesc;
 135 };
 136
 137 /**
 138  * struct ath_rx_stats - RX Statistics
 139  * @rx_pkts_all:  No. of total frames received, including ones that
 140         may have had errors.
 141  * @rx_bytes_all:  No. of total bytes received, including ones that
 142         may have had errors.
 143  * @crc_err: No. of frames with incorrect CRC value
 144  * @decrypt_crc_err: No. of frames whose CRC check failed after
 145         decryption process completed
 146  * @phy_err: No. of frames whose reception failed because the PHY
 147         encountered an error
 148  * @mic_err: No. of frames with incorrect TKIP MIC verification failure
 149  * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
 150  * @post_delim_crc_err: Post-Frame delimiter CRC error detections
 151  * @decrypt_busy_err: Decryption interruptions counter
 152  * @phy_err_stats: Individual PHY error statistics
 153  */
 154 struct ath_rx_stats {
 155         u32 rx_pkts_all;
 156         u32 rx_bytes_all;
 157         u32 crc_err;
 158         u32 decrypt_crc_err;
 159         u32 phy_err;
 160         u32 mic_err;
 161         u32 pre_delim_crc_err;
 162         u32 post_delim_crc_err;
 163         u32 decrypt_busy_err;
 164         u32 phy_err_stats[ATH9K_PHYERR_MAX];
 165         int8_t rs_rssi_ctl0;
 166         int8_t rs_rssi_ctl1;
 167         int8_t rs_rssi_ctl2;
 168         int8_t rs_rssi_ext0;
 169         int8_t rs_rssi_ext1;
 170         int8_t rs_rssi_ext2;
 171         u8 rs_antenna;
 172 };
 173
 174 struct ath_stats {
 175         struct ath_interrupt_stats istats;
 176         struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
 177         struct ath_rx_stats rxstats;
 178 };
 179
 180 #define ATH_DBG_MAX_SAMPLES     10
 181 struct ath_dbg_bb_mac_samp {
 182         u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS];
 183         u32 pcu_obs, pcu_cr, noise;
 184         struct {
 185                 u64 jiffies;
 186                 int8_t rssi_ctl0;
 187                 int8_t rssi_ctl1;
 188                 int8_t rssi_ctl2;
 189                 int8_t rssi_ext0;
 190                 int8_t rssi_ext1;
 191                 int8_t rssi_ext2;
 192                 int8_t rssi;
 193                 bool isok;
 194                 u8 rts_fail_cnt;
 195                 u8 data_fail_cnt;
 196                 u8 rateindex;
 197                 u8 qid;
 198                 u8 tid;
 199         } ts[ATH_DBG_MAX_SAMPLES];
 200         struct {
 201                 u64 jiffies;
 202                 int8_t rssi_ctl0;
 203                 int8_t rssi_ctl1;
 204                 int8_t rssi_ctl2;
 205                 int8_t rssi_ext0;
 206                 int8_t rssi_ext1;
 207                 int8_t rssi_ext2;
 208                 int8_t rssi;
 209                 bool is_mybeacon;
 210                 u8 antenna;
 211                 u8 rate;
 212         } rs[ATH_DBG_MAX_SAMPLES];
 213         struct ath_cycle_counters cc;
 214         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 215 };
 216
 217 struct ath9k_debug {
 218         struct dentry *debugfs_phy;
 219         u32 regidx;
 220         struct ath_stats stats;
 221         spinlock_t samp_lock;
 222         struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES];
 223         u8 sampidx;
 224         u8 tsidx;
 225         u8 rsidx;
 226 };
 227
 228 int ath9k_init_debug(struct ath_hw *ah);
 229
 230 void ath9k_debug_samp_bb_mac(struct ath_softc *sc);
 231 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
 232 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
 233                        struct ath_tx_status *ts, struct ath_txq *txq);
 234 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
 235
 236 #else
 237
 238 static inline int ath9k_init_debug(struct ath_hw *ah)
 239 {
 240         return 0;
 241 }
 242
 243 static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc)
 244 {
 245 }
 246
 247 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
 248                                             enum ath9k_int status)
 249 {
 250 }
 251
 252 static inline void ath_debug_stat_tx(struct ath_softc *sc,
 253                                      struct ath_buf *bf,
 254                                      struct ath_tx_status *ts,
 255                                      struct ath_txq *txq)
 256 {
 257 }
 258
 259 static inline void ath_debug_stat_rx(struct ath_softc *sc,
 260                                      struct ath_rx_status *rs)
 261 {
 262 }
 263
 264 #endif /* CONFIG_ATH9K_DEBUGFS */
 265
 266 #endif /* DEBUG_H */