arch/arm/mach-spear6xx/clock.c

   1 /*
   2  * arch/arm/mach-spear6xx/clock.c
   3  *
   4  * SPEAr6xx machines clock framework source file
   5  *
   6  * Copyright (C) 2009 ST Microelectronics
   7  * Viresh Kumar<viresh.kumar@st.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <mach/misc_regs.h>
  17 #include <plat/clock.h>
  18
  19 /* root clks */
  20 /* 32 KHz oscillator clock */
  21 static struct clk osc_32k_clk = {
  22         .flags = ALWAYS_ENABLED,
  23         .rate = 32000,
  24 };
  25
  26 /* 30 MHz oscillator clock */
  27 static struct clk osc_30m_clk = {
  28         .flags = ALWAYS_ENABLED,
  29         .rate = 30000000,
  30 };
  31
  32 /* clock derived from 32 KHz osc clk */
  33 /* rtc clock */
  34 static struct clk rtc_clk = {
  35         .pclk = &osc_32k_clk,
  36         .en_reg = PERIP1_CLK_ENB,
  37         .en_reg_bit = RTC_CLK_ENB,
  38         .recalc = &follow_parent,
  39 };
  40
  41 /* clock derived from 30 MHz osc clk */
  42 /* pll masks structure */
  43 static struct pll_clk_masks pll1_masks = {
  44         .mode_mask = PLL_MODE_MASK,
  45         .mode_shift = PLL_MODE_SHIFT,
  46         .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
  47         .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
  48         .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
  49         .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
  50         .div_p_mask = PLL_DIV_P_MASK,
  51         .div_p_shift = PLL_DIV_P_SHIFT,
  52         .div_n_mask = PLL_DIV_N_MASK,
  53         .div_n_shift = PLL_DIV_N_SHIFT,
  54 };
  55
  56 /* pll1 configuration structure */
  57 static struct pll_clk_config pll1_config = {
  58         .mode_reg = PLL1_CTR,
  59         .cfg_reg = PLL1_FRQ,
  60         .masks = &pll1_masks,
  61 };
  62
  63 /* PLL1 clock */
  64 static struct clk pll1_clk = {
  65         .pclk = &osc_30m_clk,
  66         .en_reg = PLL1_CTR,
  67         .en_reg_bit = PLL_ENABLE,
  68         .recalc = &pll_clk_recalc,
  69         .private_data = &pll1_config,
  70 };
  71
  72 /* PLL3 48 MHz clock */
  73 static struct clk pll3_48m_clk = {
  74         .flags = ALWAYS_ENABLED,
  75         .pclk = &osc_30m_clk,
  76         .rate = 48000000,
  77 };
  78
  79 /* watch dog timer clock */
  80 static struct clk wdt_clk = {
  81         .flags = ALWAYS_ENABLED,
  82         .pclk = &osc_30m_clk,
  83         .recalc = &follow_parent,
  84 };
  85
  86 /* clock derived from pll1 clk */
  87 /* cpu clock */
  88 static struct clk cpu_clk = {
  89         .flags = ALWAYS_ENABLED,
  90         .pclk = &pll1_clk,
  91         .recalc = &follow_parent,
  92 };
  93
  94 /* ahb masks structure */
  95 static struct bus_clk_masks ahb_masks = {
  96         .mask = PLL_HCLK_RATIO_MASK,
  97         .shift = PLL_HCLK_RATIO_SHIFT,
  98 };
  99
 100 /* ahb configuration structure */
 101 static struct bus_clk_config ahb_config = {
 102         .reg = CORE_CLK_CFG,
 103         .masks = &ahb_masks,
 104 };
 105
 106 /* ahb clock */
 107 static struct clk ahb_clk = {
 108         .flags = ALWAYS_ENABLED,
 109         .pclk = &pll1_clk,
 110         .recalc = &bus_clk_recalc,
 111         .private_data = &ahb_config,
 112 };
 113
 114 /* uart parents */
 115 static struct pclk_info uart_pclk_info[] = {
 116         {
 117                 .pclk = &pll1_clk,
 118                 .pclk_mask = AUX_CLK_PLL1_MASK,
 119                 .scalable = 1,
 120         }, {
 121                 .pclk = &pll3_48m_clk,
 122                 .pclk_mask = AUX_CLK_PLL3_MASK,
 123                 .scalable = 0,
 124         },
 125 };
 126
 127 /* uart parent select structure */
 128 static struct pclk_sel uart_pclk_sel = {
 129         .pclk_info = uart_pclk_info,
 130         .pclk_count = ARRAY_SIZE(uart_pclk_info),
 131         .pclk_sel_reg = PERIP_CLK_CFG,
 132         .pclk_sel_mask = UART_CLK_MASK,
 133 };
 134
 135 /* auxiliary synthesizers masks */
 136 static struct aux_clk_masks aux_masks = {
 137         .eq_sel_mask = AUX_EQ_SEL_MASK,
 138         .eq_sel_shift = AUX_EQ_SEL_SHIFT,
 139         .eq1_mask = AUX_EQ1_SEL,
 140         .eq2_mask = AUX_EQ2_SEL,
 141         .xscale_sel_mask = AUX_XSCALE_MASK,
 142         .xscale_sel_shift = AUX_XSCALE_SHIFT,
 143         .yscale_sel_mask = AUX_YSCALE_MASK,
 144         .yscale_sel_shift = AUX_YSCALE_SHIFT,
 145 };
 146
 147 /* uart configurations */
 148 static struct aux_clk_config uart_config = {
 149         .synth_reg = UART_CLK_SYNT,
 150         .masks = &aux_masks,
 151 };
 152
 153 /* uart0 clock */
 154 static struct clk uart0_clk = {
 155         .en_reg = PERIP1_CLK_ENB,
 156         .en_reg_bit = UART0_CLK_ENB,
 157         .pclk_sel = &uart_pclk_sel,
 158         .pclk_sel_shift = UART_CLK_SHIFT,
 159         .recalc = &aux_clk_recalc,
 160         .private_data = &uart_config,
 161 };
 162
 163 /* uart1 clock */
 164 static struct clk uart1_clk = {
 165         .en_reg = PERIP1_CLK_ENB,
 166         .en_reg_bit = UART1_CLK_ENB,
 167         .pclk_sel = &uart_pclk_sel,
 168         .pclk_sel_shift = UART_CLK_SHIFT,
 169         .recalc = &aux_clk_recalc,
 170         .private_data = &uart_config,
 171 };
 172
 173 /* firda configurations */
 174 static struct aux_clk_config firda_config = {
 175         .synth_reg = FIRDA_CLK_SYNT,
 176         .masks = &aux_masks,
 177 };
 178
 179 /* firda parents */
 180 static struct pclk_info firda_pclk_info[] = {
 181         {
 182                 .pclk = &pll1_clk,
 183                 .pclk_mask = AUX_CLK_PLL1_MASK,
 184                 .scalable = 1,
 185         }, {
 186                 .pclk = &pll3_48m_clk,
 187                 .pclk_mask = AUX_CLK_PLL3_MASK,
 188                 .scalable = 0,
 189         },
 190 };
 191
 192 /* firda parent select structure */
 193 static struct pclk_sel firda_pclk_sel = {
 194         .pclk_info = firda_pclk_info,
 195         .pclk_count = ARRAY_SIZE(firda_pclk_info),
 196         .pclk_sel_reg = PERIP_CLK_CFG,
 197         .pclk_sel_mask = FIRDA_CLK_MASK,
 198 };
 199
 200 /* firda clock */
 201 static struct clk firda_clk = {
 202         .en_reg = PERIP1_CLK_ENB,
 203         .en_reg_bit = FIRDA_CLK_ENB,
 204         .pclk_sel = &firda_pclk_sel,
 205         .pclk_sel_shift = FIRDA_CLK_SHIFT,
 206         .recalc = &aux_clk_recalc,
 207         .private_data = &firda_config,
 208 };
 209
 210 /* clcd configurations */
 211 static struct aux_clk_config clcd_config = {
 212         .synth_reg = CLCD_CLK_SYNT,
 213         .masks = &aux_masks,
 214 };
 215
 216 /* clcd parents */
 217 static struct pclk_info clcd_pclk_info[] = {
 218         {
 219                 .pclk = &pll1_clk,
 220                 .pclk_mask = AUX_CLK_PLL1_MASK,
 221                 .scalable = 1,
 222         }, {
 223                 .pclk = &pll3_48m_clk,
 224                 .pclk_mask = AUX_CLK_PLL3_MASK,
 225                 .scalable = 0,
 226         },
 227 };
 228
 229 /* clcd parent select structure */
 230 static struct pclk_sel clcd_pclk_sel = {
 231         .pclk_info = clcd_pclk_info,
 232         .pclk_count = ARRAY_SIZE(clcd_pclk_info),
 233         .pclk_sel_reg = PERIP_CLK_CFG,
 234         .pclk_sel_mask = CLCD_CLK_MASK,
 235 };
 236
 237 /* clcd clock */
 238 static struct clk clcd_clk = {
 239         .en_reg = PERIP1_CLK_ENB,
 240         .en_reg_bit = CLCD_CLK_ENB,
 241         .pclk_sel = &clcd_pclk_sel,
 242         .pclk_sel_shift = CLCD_CLK_SHIFT,
 243         .recalc = &aux_clk_recalc,
 244         .private_data = &clcd_config,
 245 };
 246
 247 /* gpt parents */
 248 static struct pclk_info gpt_pclk_info[] = {
 249         {
 250                 .pclk = &pll1_clk,
 251                 .pclk_mask = AUX_CLK_PLL1_MASK,
 252                 .scalable = 1,
 253         }, {
 254                 .pclk = &pll3_48m_clk,
 255                 .pclk_mask = AUX_CLK_PLL3_MASK,
 256                 .scalable = 0,
 257         },
 258 };
 259
 260 /* gpt parent select structure */
 261 static struct pclk_sel gpt_pclk_sel = {
 262         .pclk_info = gpt_pclk_info,
 263         .pclk_count = ARRAY_SIZE(gpt_pclk_info),
 264         .pclk_sel_reg = PERIP_CLK_CFG,
 265         .pclk_sel_mask = GPT_CLK_MASK,
 266 };
 267
 268 /* gpt synthesizer masks */
 269 static struct gpt_clk_masks gpt_masks = {
 270         .mscale_sel_mask = GPT_MSCALE_MASK,
 271         .mscale_sel_shift = GPT_MSCALE_SHIFT,
 272         .nscale_sel_mask = GPT_NSCALE_MASK,
 273         .nscale_sel_shift = GPT_NSCALE_SHIFT,
 274 };
 275
 276 /* gpt0_1 configurations */
 277 static struct gpt_clk_config gpt0_1_config = {
 278         .synth_reg = PRSC1_CLK_CFG,
 279         .masks = &gpt_masks,
 280 };
 281
 282 /* gpt0 ARM1 subsystem timer clock */
 283 static struct clk gpt0_clk = {
 284         .flags = ALWAYS_ENABLED,
 285         .pclk_sel = &gpt_pclk_sel,
 286         .pclk_sel_shift = GPT0_CLK_SHIFT,
 287         .recalc = &gpt_clk_recalc,
 288         .private_data = &gpt0_1_config,
 289 };
 290
 291 /* gpt1 timer clock */
 292 static struct clk gpt1_clk = {
 293         .flags = ALWAYS_ENABLED,
 294         .pclk_sel = &gpt_pclk_sel,
 295         .pclk_sel_shift = GPT1_CLK_SHIFT,
 296         .recalc = &gpt_clk_recalc,
 297         .private_data = &gpt0_1_config,
 298 };
 299
 300 /* gpt2 configurations */
 301 static struct gpt_clk_config gpt2_config = {
 302         .synth_reg = PRSC2_CLK_CFG,
 303         .masks = &gpt_masks,
 304 };
 305
 306 /* gpt2 timer clock */
 307 static struct clk gpt2_clk = {
 308         .en_reg = PERIP1_CLK_ENB,
 309         .en_reg_bit = GPT2_CLK_ENB,
 310         .pclk_sel = &gpt_pclk_sel,
 311         .pclk_sel_shift = GPT2_CLK_SHIFT,
 312         .recalc = &gpt_clk_recalc,
 313         .private_data = &gpt2_config,
 314 };
 315
 316 /* gpt3 configurations */
 317 static struct gpt_clk_config gpt3_config = {
 318         .synth_reg = PRSC3_CLK_CFG,
 319         .masks = &gpt_masks,
 320 };
 321
 322 /* gpt3 timer clock */
 323 static struct clk gpt3_clk = {
 324         .en_reg = PERIP1_CLK_ENB,
 325         .en_reg_bit = GPT3_CLK_ENB,
 326         .pclk_sel = &gpt_pclk_sel,
 327         .pclk_sel_shift = GPT3_CLK_SHIFT,
 328         .recalc = &gpt_clk_recalc,
 329         .private_data = &gpt3_config,
 330 };
 331
 332 /* clock derived from pll3 clk */
 333 /* usbh0 clock */
 334 static struct clk usbh0_clk = {
 335         .pclk = &pll3_48m_clk,
 336         .en_reg = PERIP1_CLK_ENB,
 337         .en_reg_bit = USBH0_CLK_ENB,
 338         .recalc = &follow_parent,
 339 };
 340
 341 /* usbh1 clock */
 342 static struct clk usbh1_clk = {
 343         .pclk = &pll3_48m_clk,
 344         .en_reg = PERIP1_CLK_ENB,
 345         .en_reg_bit = USBH1_CLK_ENB,
 346         .recalc = &follow_parent,
 347 };
 348
 349 /* usbd clock */
 350 static struct clk usbd_clk = {
 351         .pclk = &pll3_48m_clk,
 352         .en_reg = PERIP1_CLK_ENB,
 353         .en_reg_bit = USBD_CLK_ENB,
 354         .recalc = &follow_parent,
 355 };
 356
 357 /* clock derived from ahb clk */
 358 /* apb masks structure */
 359 static struct bus_clk_masks apb_masks = {
 360         .mask = HCLK_PCLK_RATIO_MASK,
 361         .shift = HCLK_PCLK_RATIO_SHIFT,
 362 };
 363
 364 /* apb configuration structure */
 365 static struct bus_clk_config apb_config = {
 366         .reg = CORE_CLK_CFG,
 367         .masks = &apb_masks,
 368 };
 369
 370 /* apb clock */
 371 static struct clk apb_clk = {
 372         .flags = ALWAYS_ENABLED,
 373         .pclk = &ahb_clk,
 374         .recalc = &bus_clk_recalc,
 375         .private_data = &apb_config,
 376 };
 377
 378 /* i2c clock */
 379 static struct clk i2c_clk = {
 380         .pclk = &ahb_clk,
 381         .en_reg = PERIP1_CLK_ENB,
 382         .en_reg_bit = I2C_CLK_ENB,
 383         .recalc = &follow_parent,
 384 };
 385
 386 /* dma clock */
 387 static struct clk dma_clk = {
 388         .pclk = &ahb_clk,
 389         .en_reg = PERIP1_CLK_ENB,
 390         .en_reg_bit = DMA_CLK_ENB,
 391         .recalc = &follow_parent,
 392 };
 393
 394 /* jpeg clock */
 395 static struct clk jpeg_clk = {
 396         .pclk = &ahb_clk,
 397         .en_reg = PERIP1_CLK_ENB,
 398         .en_reg_bit = JPEG_CLK_ENB,
 399         .recalc = &follow_parent,
 400 };
 401
 402 /* gmac clock */
 403 static struct clk gmac_clk = {
 404         .pclk = &ahb_clk,
 405         .en_reg = PERIP1_CLK_ENB,
 406         .en_reg_bit = GMAC_CLK_ENB,
 407         .recalc = &follow_parent,
 408 };
 409
 410 /* smi clock */
 411 static struct clk smi_clk = {
 412         .pclk = &ahb_clk,
 413         .en_reg = PERIP1_CLK_ENB,
 414         .en_reg_bit = SMI_CLK_ENB,
 415         .recalc = &follow_parent,
 416 };
 417
 418 /* fsmc clock */
 419 static struct clk fsmc_clk = {
 420         .pclk = &ahb_clk,
 421         .en_reg = PERIP1_CLK_ENB,
 422         .en_reg_bit = FSMC_CLK_ENB,
 423         .recalc = &follow_parent,
 424 };
 425
 426 /* clock derived from apb clk */
 427 /* adc clock */
 428 static struct clk adc_clk = {
 429         .pclk = &apb_clk,
 430         .en_reg = PERIP1_CLK_ENB,
 431         .en_reg_bit = ADC_CLK_ENB,
 432         .recalc = &follow_parent,
 433 };
 434
 435 /* ssp0 clock */
 436 static struct clk ssp0_clk = {
 437         .pclk = &apb_clk,
 438         .en_reg = PERIP1_CLK_ENB,
 439         .en_reg_bit = SSP0_CLK_ENB,
 440         .recalc = &follow_parent,
 441 };
 442
 443 /* ssp1 clock */
 444 static struct clk ssp1_clk = {
 445         .pclk = &apb_clk,
 446         .en_reg = PERIP1_CLK_ENB,
 447         .en_reg_bit = SSP1_CLK_ENB,
 448         .recalc = &follow_parent,
 449 };
 450
 451 /* ssp2 clock */
 452 static struct clk ssp2_clk = {
 453         .pclk = &apb_clk,
 454         .en_reg = PERIP1_CLK_ENB,
 455         .en_reg_bit = SSP2_CLK_ENB,
 456         .recalc = &follow_parent,
 457 };
 458
 459 /* gpio0 ARM subsystem clock */
 460 static struct clk gpio0_clk = {
 461         .flags = ALWAYS_ENABLED,
 462         .pclk = &apb_clk,
 463         .recalc = &follow_parent,
 464 };
 465
 466 /* gpio1 clock */
 467 static struct clk gpio1_clk = {
 468         .pclk = &apb_clk,
 469         .en_reg = PERIP1_CLK_ENB,
 470         .en_reg_bit = GPIO1_CLK_ENB,
 471         .recalc = &follow_parent,
 472 };
 473
 474 /* gpio2 clock */
 475 static struct clk gpio2_clk = {
 476         .pclk = &apb_clk,
 477         .en_reg = PERIP1_CLK_ENB,
 478         .en_reg_bit = GPIO2_CLK_ENB,
 479         .recalc = &follow_parent,
 480 };
 481
 482 static struct clk dummy_apb_pclk;
 483
 484 /* array of all spear 6xx clock lookups */
 485 static struct clk_lookup spear_clk_lookups[] = {
 486         { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
 487         /* root clks */
 488         { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
 489         { .con_id = "osc_30m_clk",      .clk = &osc_30m_clk},
 490         /* clock derived from 32 KHz os          clk */
 491         { .dev_id = "rtc",              .clk = &rtc_clk},
 492         /* clock derived from 30 MHz os          clk */
 493         { .con_id = "pll1_clk",         .clk = &pll1_clk},
 494         { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
 495         { .dev_id = "wdt",              .clk = &wdt_clk},
 496         /* clock derived from pll1 clk */
 497         { .con_id = "cpu_clk",          .clk = &cpu_clk},
 498         { .con_id = "ahb_clk",          .clk = &ahb_clk},
 499         { .dev_id = "uart0",            .clk = &uart0_clk},
 500         { .dev_id = "uart1",            .clk = &uart1_clk},
 501         { .dev_id = "firda",            .clk = &firda_clk},
 502         { .dev_id = "clcd",             .clk = &clcd_clk},
 503         { .dev_id = "gpt0",             .clk = &gpt0_clk},
 504         { .dev_id = "gpt1",             .clk = &gpt1_clk},
 505         { .dev_id = "gpt2",             .clk = &gpt2_clk},
 506         { .dev_id = "gpt3",             .clk = &gpt3_clk},
 507         /* clock derived from pll3 clk */
 508         { .dev_id = "usbh0",            .clk = &usbh0_clk},
 509         { .dev_id = "usbh1",            .clk = &usbh1_clk},
 510         { .dev_id = "usbd",             .clk = &usbd_clk},
 511         /* clock derived from ahb clk */
 512         { .con_id = "apb_clk",          .clk = &apb_clk},
 513         { .dev_id = "i2c",              .clk = &i2c_clk},
 514         { .dev_id = "dma",              .clk = &dma_clk},
 515         { .dev_id = "jpeg",             .clk = &jpeg_clk},
 516         { .dev_id = "gmac",             .clk = &gmac_clk},
 517         { .dev_id = "smi",              .clk = &smi_clk},
 518         { .dev_id = "fsmc",             .clk = &fsmc_clk},
 519         /* clock derived from apb clk */
 520         { .dev_id = "adc",              .clk = &adc_clk},
 521         { .dev_id = "ssp0",             .clk = &ssp0_clk},
 522         { .dev_id = "ssp1",             .clk = &ssp1_clk},
 523         { .dev_id = "ssp2",             .clk = &ssp2_clk},
 524         { .dev_id = "gpio0",            .clk = &gpio0_clk},
 525         { .dev_id = "gpio1",            .clk = &gpio1_clk},
 526         { .dev_id = "gpio2",            .clk = &gpio2_clk},
 527 };
 528
 529 void __init clk_init(void)
 530 {
 531         int i;
 532
 533         for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
 534                 clk_register(&spear_clk_lookups[i]);
 535
 536         recalc_root_clocks();
 537 }