2 * ngene.h: nGene PCIe bridge driver
4 * Copyright (C) 2005-2007 Micronas
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
27 #include <linux/types.h>
28 #include <linux/sched.h>
29 #include <linux/interrupt.h>
30 #include <linux/i2c.h>
32 #include <asm/scatterlist.h>
34 #include <linux/dvb/frontend.h>
38 #include "dvb_demux.h"
39 #include "dvb_frontend.h"
40 #include "dvb_ringbuffer.h"
42 #define NGENE_VID 0x18c3
43 #define NGENE_PID 0x0720
46 #define VIDEO_CAP_AVC 128
47 #define VIDEO_CAP_H264 128
48 #define VIDEO_CAP_VC1 256
49 #define VIDEO_CAP_WMV9 256
50 #define VIDEO_CAP_MPEG4 512
54 STREAM_VIDEOIN1
= 0, /* ITU656 or TS Input */
56 STREAM_AUDIOIN1
, /* I2S or SPI Input */
63 SMODE_AUDIO_SPDIF
= 0x20,
65 SMODE_TRANSPORT_STREAM
= 0x08,
66 SMODE_AUDIO_CAPTURE
= 0x04,
67 SMODE_VBI_CAPTURE
= 0x02,
68 SMODE_VIDEO_CAPTURE
= 0x01
71 enum STREAM_FLAG_BITS
{
72 SFLAG_CHROMA_FORMAT_2COMP
= 0x01, /* Chroma Format : 2's complement */
73 SFLAG_CHROMA_FORMAT_OFFSET
= 0x00, /* Chroma Format : Binary offset */
74 SFLAG_ORDER_LUMA_CHROMA
= 0x02, /* Byte order: Y,Cb,Y,Cr */
75 SFLAG_ORDER_CHROMA_LUMA
= 0x00, /* Byte order: Cb,Y,Cr,Y */
76 SFLAG_COLORBAR
= 0x04, /* Select colorbar */
79 #define PROGRAM_ROM 0x0000
80 #define PROGRAM_SRAM 0x1000
81 #define PERIPHERALS0 0x8000
82 #define PERIPHERALS1 0x9000
83 #define SHARED_BUFFER 0xC000
85 #define HOST_TO_NGENE (SHARED_BUFFER+0x0000)
86 #define NGENE_TO_HOST (SHARED_BUFFER+0x0100)
87 #define NGENE_COMMAND (SHARED_BUFFER+0x0200)
88 #define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204)
89 #define NGENE_STATUS (SHARED_BUFFER+0x0208)
90 #define NGENE_STATUS_HI (SHARED_BUFFER+0x020C)
91 #define NGENE_EVENT (SHARED_BUFFER+0x0210)
92 #define NGENE_EVENT_HI (SHARED_BUFFER+0x0214)
93 #define VARIABLES (SHARED_BUFFER+0x0210)
95 #define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260)
96 #define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264)
97 #define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268)
99 #define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800)
100 #define BUFFER_GP_RECV (SHARED_BUFFER+0x0900)
101 #define EEPROM_AREA (SHARED_BUFFER+0x0A00)
103 #define SG_V_IN_1 (SHARED_BUFFER+0x0A80)
104 #define SG_VBI_1 (SHARED_BUFFER+0x0B00)
105 #define SG_A_IN_1 (SHARED_BUFFER+0x0B80)
106 #define SG_V_IN_2 (SHARED_BUFFER+0x0C00)
107 #define SG_VBI_2 (SHARED_BUFFER+0x0C80)
108 #define SG_A_IN_2 (SHARED_BUFFER+0x0D00)
109 #define SG_V_OUT (SHARED_BUFFER+0x0D80)
110 #define SG_A_OUT2 (SHARED_BUFFER+0x0E00)
112 #define DATA_A_IN_1 (SHARED_BUFFER+0x0E80)
113 #define DATA_A_IN_2 (SHARED_BUFFER+0x0F00)
114 #define DATA_A_OUT (SHARED_BUFFER+0x0F80)
115 #define DATA_V_IN_1 (SHARED_BUFFER+0x1000)
116 #define DATA_V_IN_2 (SHARED_BUFFER+0x2000)
117 #define DATA_V_OUT (SHARED_BUFFER+0x3000)
119 #define DATA_FIFO_AREA (SHARED_BUFFER+0x1000)
121 #define TIMESTAMPS 0xA000
122 #define SCRATCHPAD 0xA080
123 #define FORCE_INT 0xA088
124 #define FORCE_NMI 0xA090
125 #define INT_STATUS 0xA0A0
127 #define DEV_VER 0x9004
129 #define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF)
137 } __attribute__ ((__packed__
));
139 struct SHARED_MEMORY
{
152 u8 pad1
[0xc260 - 0xc218];
159 u8 pad2
[0xd000 - 0xc268];
161 } __attribute__ ((__packed__
));
163 struct BUFFER_STREAM_RESULTS
{
164 u32 Clock
; /* Stream time in 100ns units */
165 u16 RemainingLines
; /* Remaining lines in this field.
166 0 for complete field */
167 u8 FieldCount
; /* Video field number */
168 u8 Flags
; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow,
170 u16 BlockCount
; /* Audio block count (unused) */
173 } __attribute__ ((__packed__
));
175 struct HW_SCATTER_GATHER_ELEMENT
{
179 } __attribute__ ((__packed__
));
181 struct BUFFER_HEADER
{
183 struct BUFFER_STREAM_RESULTS SR
;
185 u32 Number_of_entries_1
;
187 u64 Address_of_first_entry_1
;
189 u32 Number_of_entries_2
;
191 u64 Address_of_first_entry_2
;
192 } __attribute__ ((__packed__
));
194 struct EVENT_BUFFER
{
201 } __attribute__ ((__packed__
));
203 typedef struct EVENT_BUFFER
*PEVENT_BUFFER
;
205 /* Firmware commands. */
209 CMD_FWLOAD_PREPARE
= 0x01,
210 CMD_FWLOAD_FINISH
= 0x02,
212 CMD_I2C_WRITE
= 0x04,
214 CMD_I2C_WRITE_NOSTOP
= 0x05,
215 CMD_I2C_CONTINUE_WRITE
= 0x06,
216 CMD_I2C_CONTINUE_WRITE_NOSTOP
= 0x07,
218 CMD_DEBUG_OUTPUT
= 0x09,
221 CMD_CONFIGURE_BUFFER
= 0x11,
222 CMD_CONFIGURE_FREE_BUFFER
= 0x12,
225 CMD_SPI_WRITE
= 0x14,
228 CMD_MEM_WRITE
= 0x21,
230 CMD_SFR_WRITE
= 0x23,
231 CMD_IRAM_READ
= 0x24,
232 CMD_IRAM_WRITE
= 0x25,
233 CMD_SET_GPIO_PIN
= 0x26,
234 CMD_SET_GPIO_INT
= 0x27,
235 CMD_CONFIGURE_UART
= 0x28,
236 CMD_WRITE_UART
= 0x29,
248 } __attribute__ ((__packed__
));
250 struct FW_I2C_WRITE
{
251 struct FW_HEADER hdr
;
254 } __attribute__ ((__packed__
));
256 struct FW_I2C_CONTINUE_WRITE
{
257 struct FW_HEADER hdr
;
259 } __attribute__ ((__packed__
));
262 struct FW_HEADER hdr
;
264 u8 Data
[252]; /* followed by two bytes of read data count */
265 } __attribute__ ((__packed__
));
267 struct FW_SPI_WRITE
{
268 struct FW_HEADER hdr
;
271 } __attribute__ ((__packed__
));
274 struct FW_HEADER hdr
;
276 u8 Data
[252]; /* followed by two bytes of read data count */
277 } __attribute__ ((__packed__
));
279 struct FW_FWLOAD_PREPARE
{
280 struct FW_HEADER hdr
;
281 } __attribute__ ((__packed__
));
283 struct FW_FWLOAD_FINISH
{
284 struct FW_HEADER hdr
;
285 u16 Address
; /* address of final block */
287 } __attribute__ ((__packed__
));
290 * Meaning of FW_STREAM_CONTROL::Mode bits:
291 * Bit 7: Loopback PEXin to PEXout using TVOut channel
293 * Bit 5: Audio select; 0=I2S, 1=SPDIF
295 * Bit 3: Enable transport stream
296 * Bit 2: Enable audio capture
297 * Bit 1: Enable ITU-Video VBI capture
298 * Bit 0: Enable ITU-Video capture
300 * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL)
301 * Bit 7: continuous capture
302 * Bit 6: capture one field
303 * Bit 5: capture one frame
305 * Bit 3: starting field; 0=odd, 1=even
306 * Bit 2: sample size; 0=8-bit, 1=10-bit
307 * Bit 1: data format; 0=UYVY, 1=YUY2
308 * Bit 0: resets buffer pointers
312 SMODE_LOOPBACK
= 0x80,
314 _SMODE_AUDIO_SPDIF
= 0x20,
315 _SMODE_AVSYNC
= 0x10,
316 _SMODE_TRANSPORT_STREAM
= 0x08,
317 _SMODE_AUDIO_CAPTURE
= 0x04,
318 _SMODE_VBI_CAPTURE
= 0x02,
319 _SMODE_VIDEO_CAPTURE
= 0x01
323 /* Meaning of FW_STREAM_CONTROL::Stream bits:
324 * Bit 3: Audio sample count: 0 = relative, 1 = absolute
325 * Bit 2: color bar select; 1=color bars, 0=CV3 decoder
326 * Bits 1-0: stream select, UVI1, UVI2, TVOUT
329 struct FW_STREAM_CONTROL
{
330 struct FW_HEADER hdr
;
331 u8 Stream
; /* Stream number (UVI1, UVI2, TVOUT) */
332 u8 Control
; /* Value written to UVI1_CTL */
333 u8 Mode
; /* Controls clock source */
334 u8 SetupDataLen
; /* Length of setup data, MSB=1 write
336 u16 CaptureBlockCount
; /* Blocks (a 256 Bytes) to capture per buffer
338 u64 Buffer_Address
; /* Address of first buffer header */
339 u16 BytesPerVideoLine
;
340 u16 MaxLinesPerField
;
341 u16 MinLinesPerField
;
344 u16 MaxVBILinesPerField
;
345 u16 MinVBILinesPerField
;
346 u16 SetupDataAddr
; /* ngene relative address of setup data */
347 u8 SetupData
[32]; /* setup data */
348 } __attribute__((__packed__
));
350 #define AUDIO_BLOCK_SIZE 256
351 #define TS_BLOCK_SIZE 256
354 struct FW_HEADER hdr
;
356 } __attribute__ ((__packed__
));
358 struct FW_MEM_WRITE
{
359 struct FW_HEADER hdr
;
362 } __attribute__ ((__packed__
));
364 struct FW_SFR_IRAM_READ
{
365 struct FW_HEADER hdr
;
367 } __attribute__ ((__packed__
));
369 struct FW_SFR_IRAM_WRITE
{
370 struct FW_HEADER hdr
;
373 } __attribute__ ((__packed__
));
375 struct FW_SET_GPIO_PIN
{
376 struct FW_HEADER hdr
;
378 } __attribute__ ((__packed__
));
380 struct FW_SET_GPIO_INT
{
381 struct FW_HEADER hdr
;
383 } __attribute__ ((__packed__
));
385 struct FW_SET_DEBUGMODE
{
386 struct FW_HEADER hdr
;
388 } __attribute__ ((__packed__
));
390 struct FW_CONFIGURE_BUFFERS
{
391 struct FW_HEADER hdr
;
393 } __attribute__ ((__packed__
));
395 enum _BUFFER_CONFIGS
{
396 /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */
397 BUFFER_CONFIG_4422
= 0,
398 /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */
399 BUFFER_CONFIG_3333
= 1,
400 /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */
401 BUFFER_CONFIG_8022
= 2,
402 BUFFER_CONFIG_FW17
= 255, /* Use new FW 17 command */
405 struct FW_CONFIGURE_FREE_BUFFERS
{
406 struct FW_HEADER hdr
;
407 u8 UVI1_BufferLength
;
408 u8 UVI2_BufferLength
;
410 u8 AUD1_BufferLength
;
411 u8 AUD2_BufferLength
;
413 } __attribute__ ((__packed__
));
415 struct FW_CONFIGURE_UART
{
416 struct FW_HEADER hdr
;
418 } __attribute__ ((__packed__
));
421 _UART_BAUDRATE_19200
= 0,
422 _UART_BAUDRATE_9600
= 1,
423 _UART_BAUDRATE_4800
= 2,
424 _UART_BAUDRATE_2400
= 3,
425 _UART_RX_ENABLE
= 0x40,
426 _UART_TX_ENABLE
= 0x80,
429 struct FW_WRITE_UART
{
430 struct FW_HEADER hdr
;
432 } __attribute__ ((__packed__
));
435 struct ngene_command
{
441 struct FW_HEADER hdr
;
442 struct FW_I2C_WRITE I2CWrite
;
443 struct FW_I2C_CONTINUE_WRITE I2CContinueWrite
;
444 struct FW_I2C_READ I2CRead
;
445 struct FW_STREAM_CONTROL StreamControl
;
446 struct FW_FWLOAD_PREPARE FWLoadPrepare
;
447 struct FW_FWLOAD_FINISH FWLoadFinish
;
448 struct FW_MEM_READ MemoryRead
;
449 struct FW_MEM_WRITE MemoryWrite
;
450 struct FW_SFR_IRAM_READ SfrIramRead
;
451 struct FW_SFR_IRAM_WRITE SfrIramWrite
;
452 struct FW_SPI_WRITE SPIWrite
;
453 struct FW_SPI_READ SPIRead
;
454 struct FW_SET_GPIO_PIN SetGpioPin
;
455 struct FW_SET_GPIO_INT SetGpioInt
;
456 struct FW_SET_DEBUGMODE SetDebugMode
;
457 struct FW_CONFIGURE_BUFFERS ConfigureBuffers
;
458 struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers
;
459 struct FW_CONFIGURE_UART ConfigureUart
;
460 struct FW_WRITE_UART WriteUart
;
462 } __attribute__ ((__packed__
));
464 #define NGENE_INTERFACE_VERSION 0x103
465 #define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */
466 #define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */
467 #define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */
468 #define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */
469 #define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page
470 Max: (1920x1080i60) */
472 #define OVERFLOW_BUFFER_SIZE (8192)
474 #define RING_SIZE_VIDEO 4
475 #define RING_SIZE_AUDIO 8
476 #define RING_SIZE_TS 8
478 #define NUM_SCATTER_GATHER_ENTRIES 8
480 #define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \
481 RING_SIZE_VIDEO * 2) + \
482 (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \
483 (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \
484 (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \
485 (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \
486 (RING_SIZE_TS * PAGE_SIZE * 4) + \
487 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE)
489 #define EVENT_QUEUE_SIZE 16
491 typedef struct HW_SCATTER_GATHER_ELEMENT
*PHW_SCATTER_GATHER_ELEMENT
;
492 typedef struct FWRB
*PFWRB
;
494 /* Gathers the current state of a single channel. */
496 struct SBufferHeader
{
497 struct BUFFER_HEADER ngeneBuffer
; /* Physical descriptor */
498 struct SBufferHeader
*Next
;
500 PHW_SCATTER_GATHER_ELEMENT scList1
;
502 PHW_SCATTER_GATHER_ELEMENT scList2
;
505 /* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */
506 #define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63)
522 struct SRingBufferDescriptor
{
523 struct SBufferHeader
*Head
; /* Points to first buffer in ring buffer
525 u64 PAHead
; /* Physical address of first buffer */
526 u32 MemSize
; /* Memory size of allocated ring buffers
527 (needed for freeing) */
528 u32 NumBuffers
; /* Number of buffers in the ring */
529 u32 Buffer1Length
; /* Allocated length of Buffer 1 */
530 u32 Buffer2Length
; /* Allocated length of Buffer 2 */
531 void *SCListMem
; /* Memory to hold scatter gather lists for this
533 u64 PASCListMem
; /* Physical address .. */
534 u32 SCListMemSize
; /* Size of this memory */
537 enum STREAMMODEFLAGS
{
538 StreamMode_NONE
= 0, /* Stream not used */
539 StreamMode_ANALOG
= 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */
540 StreamMode_TSIN
= 2, /* Transport stream input (all) */
541 StreamMode_HDTV
= 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60
543 StreamMode_TSOUT
= 8, /* Transport stream output (only stream 3) */
547 enum BufferExchangeFlags
{
548 BEF_EVEN_FIELD
= 0x00000001,
549 BEF_CONTINUATION
= 0x00000002,
550 BEF_MORE_DATA
= 0x00000004,
551 BEF_OVERFLOW
= 0x00000008,
552 DF_SWAP32
= 0x00010000,
555 typedef void *(IBufferExchange
)(void *, void *, u32
, u32
, u32
);
558 IBufferExchange
*pExchange
;
559 IBufferExchange
*pExchangeVBI
; /* Secondary (VBI, ancillary) */
565 u16 nBytesPerLineVideo
;
567 u16 nBytesPerLineVBI
;
568 u32 CaptureLength
; /* Used for audio and transport stream */
569 } MICI_STREAMINFO
, *PMICI_STREAMINFO
;
571 /****************************************************************************/
572 /* STRUCTS ******************************************************************/
573 /****************************************************************************/
575 /* sound hardware definition */
576 #define MIXER_ADDR_TVTUNER 0
577 #define MIXER_ADDR_LAST 0
579 struct ngene_channel
;
581 /*struct sound chip*/
584 struct ngene_channel
*chan
;
585 struct snd_card
*card
;
587 struct snd_pcm_substream
*substream
;
591 spinlock_t mixer_lock
;
593 int mixer_volume
[MIXER_ADDR_LAST
+ 1][2];
594 int capture_source
[MIXER_ADDR_LAST
+ 1][2];
598 struct ngene_overlay
{
601 enum v4l2_field field
;
602 struct v4l2_clip
*clips
;
607 struct ngene_tvnorm
{
610 u16 swidth
, sheight
; /* scaled standard width, height */
616 struct ngene_channel
*ch
;
617 enum v4l2_priority prio
;
621 struct videobuf_queue vbuf_q
;
622 struct videobuf_queue vbi
;
626 enum v4l2_buf_type type
;
627 const struct ngene_format
*fmt
;
629 const struct ngene_format
*ovfmt
;
630 struct ngene_overlay ov
;
634 struct ngene_channel
{
635 struct device device
;
636 struct i2c_adapter i2c_adapter
;
643 struct dvb_frontend
*fe
;
644 struct dmxdev dmxdev
;
645 struct dvb_demux demux
;
646 struct dmx_frontend hw_frontend
;
647 struct dmx_frontend mem_frontend
;
649 struct video_device
*v4l_dev
;
650 struct tasklet_struct demux_tasklet
;
652 struct SBufferHeader
*nextBuffer
;
654 enum HWSTATE HWState
;
658 IBufferExchange
*pBufferExchange
;
659 IBufferExchange
*pBufferExchange2
;
661 spinlock_t state_lock
;
665 u16 nBytesPerVBILine
;
669 struct SRingBufferDescriptor RingBuffer
;
670 struct SRingBufferDescriptor TSRingBuffer
;
671 struct SRingBufferDescriptor TSIdleBuffer
;
678 int (*set_tone
)(struct dvb_frontend
*, fe_sec_tone_mode_t
);
681 /* stuff from analog driver */
684 struct mychip
*mychip
;
685 struct snd_card
*soundcard
;
690 int soundbuffisallocated
;
697 struct ngene_tvnorm
*tvnorms
;
703 struct v4l2_prio_state prio
;
704 struct ngene_vopen init
;
706 struct v4l2_framebuffer fbuf
;
707 struct ngene_buffer
*screen
; /* overlay */
708 struct list_head capture
; /* video capture queue */
710 struct semaphore reslock
;
718 typedef void (rx_cb_t
)(struct ngene
*, u32
, u8
);
719 typedef void (tx_cb_t
)(struct ngene
*, u32
);
723 struct pci_dev
*pci_dev
;
724 unsigned char *iomem
;
726 /*struct i2c_adapter i2c_adapter;*/
729 u32 fw_interface_version
;
734 void *OverflowBuffer
;
735 dma_addr_t PAOverflowBuffer
;
736 void *FWInterfaceBuffer
;
737 dma_addr_t PAFWInterfaceBuffer
;
741 struct EVENT_BUFFER EventQueue
[EVENT_QUEUE_SIZE
];
742 int EventQueueOverflowCount
;
743 int EventQueueOverflowFlag
;
744 struct tasklet_struct event_tasklet
;
745 struct EVENT_BUFFER
*EventBuffer
;
746 int EventQueueWriteIndex
;
747 int EventQueueReadIndex
;
749 wait_queue_head_t cmd_wq
;
751 struct semaphore cmd_mutex
;
752 struct semaphore stream_mutex
;
753 struct semaphore pll_mutex
;
754 struct semaphore i2c_switch_mutex
;
755 int i2c_current_channel
;
759 struct dvb_adapter adapter
[MAX_STREAM
];
760 struct ngene_channel channel
[MAX_STREAM
];
762 struct ngene_info
*card_info
;
764 tx_cb_t
*TxEventNotify
;
765 rx_cb_t
*RxEventNotify
;
767 wait_queue_head_t tx_wq
;
768 wait_queue_head_t rx_wq
;
769 #define UART_RBUF_LEN 4096
770 u8 uart_rbuf
[UART_RBUF_LEN
];
771 int uart_rp
, uart_wp
;
774 #define TSOUT_BUF_SIZE (512*188*8)
775 struct dvb_ringbuffer tsout_rbuf
;
778 #define AIN_BUF_SIZE (128*1024)
779 struct dvb_ringbuffer ain_rbuf
;
783 #define VIN_BUF_SIZE (4*1920*1080)
784 struct dvb_ringbuffer vin_rbuf
;
786 unsigned long exp_val
;
793 #define NGENE_TERRATEC 1
794 #define NGENE_SIDEWINDER 2
795 #define NGENE_RACER 3
796 #define NGENE_VIPER 4
797 #define NGENE_PYTHON 5
798 #define NGENE_VBOX_V1 6
799 #define NGENE_VBOX_V2 7
804 int io_type
[MAX_STREAM
];
805 #define NGENE_IO_NONE 0
806 #define NGENE_IO_TV 1
807 #define NGENE_IO_HDTV 2
808 #define NGENE_IO_TSIN 4
809 #define NGENE_IO_TSOUT 8
810 #define NGENE_IO_AIN 16
813 void *tuner_config
[4];
815 int (*demod_attach
[4])(struct ngene_channel
*);
816 int (*tuner_attach
[4])(struct ngene_channel
*);
827 int (*gate_ctrl
)(struct dvb_frontend
*, int);
828 int (*switch_ctrl
)(struct ngene_channel
*, int, int);
834 int fourcc
; /* video4linux 2 */
835 int btformat
; /* BT848_COLOR_FMT_* */
837 int btswap
; /* BT848_COLOR_CTL_* */
838 int depth
; /* bit/pixel */
840 int hshift
, vshift
; /* for planar modes */
844 #define RESOURCE_OVERLAY 1
845 #define RESOURCE_VIDEO 2
846 #define RESOURCE_VBI 4
848 struct ngene_buffer
{
849 /* common v4l buffer stuff -- must be first */
850 struct videobuf_buffer vb
;
853 const struct ngene_format
*fmt
;
860 int ngene_command_stream_control(struct ngene
*dev
,
861 u8 stream
, u8 control
, u8 mode
, u8 flags
);
862 int ngene_command_nop(struct ngene
*dev
);
863 int ngene_command_i2c_read(struct ngene
*dev
, u8 adr
,
864 u8
*out
, u8 outlen
, u8
*in
, u8 inlen
, int flag
);
865 int ngene_command_i2c_write(struct ngene
*dev
, u8 adr
, u8
*out
, u8 outlen
);
866 int ngene_command_imem_read(struct ngene
*dev
, u8 adr
, u8
*data
, int type
);
867 int ngene_command_imem_write(struct ngene
*dev
, u8 adr
, u8 data
, int type
);
868 int ngene_stream_control(struct ngene
*dev
, u8 stream
, u8 control
, u8 mode
,
869 u16 lines
, u16 bpl
, u16 vblines
, u16 vbibpl
);