drivers/media/dvb/ngene/ngene.h

   1 /*
   2  * ngene.h: nGene PCIe bridge driver
   3  *
   4  * Copyright (C) 2005-2007 Micronas
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 only, as published by the Free Software Foundation.
   9  *
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301, USA
  21  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  22  */
  23
  24 #ifndef _NGENE_H_
  25 #define _NGENE_H_
  26
  27 #include <linux/types.h>
  28 #include <linux/sched.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/i2c.h>
  31 #include <asm/dma.h>
  32 #include <asm/scatterlist.h>
  33
  34 #include <linux/dvb/frontend.h>
  35
  36 #include "dmxdev.h"
  37 #include "dvbdev.h"
  38 #include "dvb_demux.h"
  39 #include "dvb_frontend.h"
  40 #include "dvb_ringbuffer.h"
  41
  42 #define NGENE_VID       0x18c3
  43 #define NGENE_PID       0x0720
  44
  45 #ifndef VIDEO_CAP_VC1
  46 #define VIDEO_CAP_AVC   128
  47 #define VIDEO_CAP_H264  128
  48 #define VIDEO_CAP_VC1   256
  49 #define VIDEO_CAP_WMV9  256
  50 #define VIDEO_CAP_MPEG4 512
  51 #endif
  52
  53 enum STREAM {
  54         STREAM_VIDEOIN1 = 0,        /* ITU656 or TS Input */
  55         STREAM_VIDEOIN2,
  56         STREAM_AUDIOIN1,            /* I2S or SPI Input */
  57         STREAM_AUDIOIN2,
  58         STREAM_AUDIOOUT,
  59         MAX_STREAM
  60 };
  61
  62 enum SMODE_BITS {
  63         SMODE_AUDIO_SPDIF = 0x20,
  64         SMODE_AVSYNC = 0x10,
  65         SMODE_TRANSPORT_STREAM = 0x08,
  66         SMODE_AUDIO_CAPTURE = 0x04,
  67         SMODE_VBI_CAPTURE = 0x02,
  68         SMODE_VIDEO_CAPTURE = 0x01
  69 };
  70
  71 enum STREAM_FLAG_BITS {
  72         SFLAG_CHROMA_FORMAT_2COMP  = 0x01, /* Chroma Format : 2's complement */
  73         SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */
  74         SFLAG_ORDER_LUMA_CHROMA    = 0x02, /* Byte order: Y,Cb,Y,Cr */
  75         SFLAG_ORDER_CHROMA_LUMA    = 0x00, /* Byte order: Cb,Y,Cr,Y */
  76         SFLAG_COLORBAR             = 0x04, /* Select colorbar */
  77 };
  78
  79 #define PROGRAM_ROM     0x0000
  80 #define PROGRAM_SRAM    0x1000
  81 #define PERIPHERALS0    0x8000
  82 #define PERIPHERALS1    0x9000
  83 #define SHARED_BUFFER   0xC000
  84
  85 #define HOST_TO_NGENE    (SHARED_BUFFER+0x0000)
  86 #define NGENE_TO_HOST    (SHARED_BUFFER+0x0100)
  87 #define NGENE_COMMAND    (SHARED_BUFFER+0x0200)
  88 #define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204)
  89 #define NGENE_STATUS     (SHARED_BUFFER+0x0208)
  90 #define NGENE_STATUS_HI  (SHARED_BUFFER+0x020C)
  91 #define NGENE_EVENT      (SHARED_BUFFER+0x0210)
  92 #define NGENE_EVENT_HI   (SHARED_BUFFER+0x0214)
  93 #define VARIABLES        (SHARED_BUFFER+0x0210)
  94
  95 #define NGENE_INT_COUNTS       (SHARED_BUFFER+0x0260)
  96 #define NGENE_INT_ENABLE       (SHARED_BUFFER+0x0264)
  97 #define NGENE_VBI_LINE_COUNT   (SHARED_BUFFER+0x0268)
  98
  99 #define BUFFER_GP_XMIT  (SHARED_BUFFER+0x0800)
 100 #define BUFFER_GP_RECV  (SHARED_BUFFER+0x0900)
 101 #define EEPROM_AREA     (SHARED_BUFFER+0x0A00)
 102
 103 #define SG_V_IN_1       (SHARED_BUFFER+0x0A80)
 104 #define SG_VBI_1        (SHARED_BUFFER+0x0B00)
 105 #define SG_A_IN_1       (SHARED_BUFFER+0x0B80)
 106 #define SG_V_IN_2       (SHARED_BUFFER+0x0C00)
 107 #define SG_VBI_2        (SHARED_BUFFER+0x0C80)
 108 #define SG_A_IN_2       (SHARED_BUFFER+0x0D00)
 109 #define SG_V_OUT        (SHARED_BUFFER+0x0D80)
 110 #define SG_A_OUT2       (SHARED_BUFFER+0x0E00)
 111
 112 #define DATA_A_IN_1     (SHARED_BUFFER+0x0E80)
 113 #define DATA_A_IN_2     (SHARED_BUFFER+0x0F00)
 114 #define DATA_A_OUT      (SHARED_BUFFER+0x0F80)
 115 #define DATA_V_IN_1     (SHARED_BUFFER+0x1000)
 116 #define DATA_V_IN_2     (SHARED_BUFFER+0x2000)
 117 #define DATA_V_OUT      (SHARED_BUFFER+0x3000)
 118
 119 #define DATA_FIFO_AREA  (SHARED_BUFFER+0x1000)
 120
 121 #define TIMESTAMPS      0xA000
 122 #define SCRATCHPAD      0xA080
 123 #define FORCE_INT       0xA088
 124 #define FORCE_NMI       0xA090
 125 #define INT_STATUS      0xA0A0
 126
 127 #define DEV_VER         0x9004
 128
 129 #define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF)
 130
 131 struct SG_ADDR {
 132         u64 start;
 133         u64 curr;
 134         u16 curr_ptr;
 135         u16 elements;
 136         u32 pad[3];
 137 } __attribute__ ((__packed__));
 138
 139 struct SHARED_MEMORY {
 140         /* C000 */
 141         u32 HostToNgene[64];
 142
 143         /* C100 */
 144         u32 NgeneToHost[64];
 145
 146         /* C200 */
 147         u64 NgeneCommand;
 148         u64 NgeneStatus;
 149         u64 NgeneEvent;
 150
 151         /* C210 */
 152         u8 pad1[0xc260 - 0xc218];
 153
 154         /* C260 */
 155         u32 IntCounts;
 156         u32 IntEnable;
 157
 158         /* C268 */
 159         u8 pad2[0xd000 - 0xc268];
 160
 161 } __attribute__ ((__packed__));
 162
 163 struct BUFFER_STREAM_RESULTS {
 164         u32 Clock;           /* Stream time in 100ns units */
 165         u16 RemainingLines;  /* Remaining lines in this field.
 166                                 0 for complete field */
 167         u8  FieldCount;      /* Video field number */
 168         u8  Flags;           /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow,
 169                                 Bit 0 = FieldID */
 170         u16 BlockCount;      /* Audio block count (unused) */
 171         u8  Reserved[2];
 172         u32 DTOUpdate;
 173 } __attribute__ ((__packed__));
 174
 175 struct HW_SCATTER_GATHER_ELEMENT {
 176         u64 Address;
 177         u32 Length;
 178         u32 Reserved;
 179 } __attribute__ ((__packed__));
 180
 181 struct BUFFER_HEADER {
 182         u64    Next;
 183         struct BUFFER_STREAM_RESULTS SR;
 184
 185         u32    Number_of_entries_1;
 186         u32    Reserved5;
 187         u64    Address_of_first_entry_1;
 188
 189         u32    Number_of_entries_2;
 190         u32    Reserved7;
 191         u64    Address_of_first_entry_2;
 192 } __attribute__ ((__packed__));
 193
 194 struct EVENT_BUFFER {
 195         u32    TimeStamp;
 196         u8     GPIOStatus;
 197         u8     UARTStatus;
 198         u8     RXCharacter;
 199         u8     EventStatus;
 200         u32    Reserved[2];
 201 } __attribute__ ((__packed__));
 202
 203 typedef struct EVENT_BUFFER *PEVENT_BUFFER;
 204
 205 /* Firmware commands. */
 206
 207 enum OPCODES {
 208         CMD_NOP = 0,
 209         CMD_FWLOAD_PREPARE  = 0x01,
 210         CMD_FWLOAD_FINISH   = 0x02,
 211         CMD_I2C_READ        = 0x03,
 212         CMD_I2C_WRITE       = 0x04,
 213
 214         CMD_I2C_WRITE_NOSTOP = 0x05,
 215         CMD_I2C_CONTINUE_WRITE = 0x06,
 216         CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07,
 217
 218         CMD_DEBUG_OUTPUT    = 0x09,
 219
 220         CMD_CONTROL         = 0x10,
 221         CMD_CONFIGURE_BUFFER = 0x11,
 222         CMD_CONFIGURE_FREE_BUFFER = 0x12,
 223
 224         CMD_SPI_READ        = 0x13,
 225         CMD_SPI_WRITE       = 0x14,
 226
 227         CMD_MEM_READ        = 0x20,
 228         CMD_MEM_WRITE       = 0x21,
 229         CMD_SFR_READ        = 0x22,
 230         CMD_SFR_WRITE       = 0x23,
 231         CMD_IRAM_READ       = 0x24,
 232         CMD_IRAM_WRITE      = 0x25,
 233         CMD_SET_GPIO_PIN    = 0x26,
 234         CMD_SET_GPIO_INT    = 0x27,
 235         CMD_CONFIGURE_UART  = 0x28,
 236         CMD_WRITE_UART      = 0x29,
 237         MAX_CMD
 238 };
 239
 240 enum RESPONSES {
 241         OK = 0,
 242         ERROR = 1
 243 };
 244
 245 struct FW_HEADER {
 246         u8 Opcode;
 247         u8 Length;
 248 } __attribute__ ((__packed__));
 249
 250 struct FW_I2C_WRITE {
 251         struct FW_HEADER hdr;
 252         u8 Device;
 253         u8 Data[250];
 254 } __attribute__ ((__packed__));
 255
 256 struct FW_I2C_CONTINUE_WRITE {
 257         struct FW_HEADER hdr;
 258         u8 Data[250];
 259 } __attribute__ ((__packed__));
 260
 261 struct FW_I2C_READ {
 262         struct FW_HEADER hdr;
 263         u8 Device;
 264         u8 Data[252];    /* followed by two bytes of read data count */
 265 } __attribute__ ((__packed__));
 266
 267 struct FW_SPI_WRITE {
 268         struct FW_HEADER hdr;
 269         u8 ModeSelect;
 270         u8 Data[250];
 271 } __attribute__ ((__packed__));
 272
 273 struct FW_SPI_READ {
 274         struct FW_HEADER hdr;
 275         u8 ModeSelect;
 276         u8 Data[252];    /* followed by two bytes of read data count */
 277 } __attribute__ ((__packed__));
 278
 279 struct FW_FWLOAD_PREPARE {
 280         struct FW_HEADER hdr;
 281 } __attribute__ ((__packed__));
 282
 283 struct FW_FWLOAD_FINISH {
 284         struct FW_HEADER hdr;
 285         u16 Address;     /* address of final block */
 286         u16 Length;
 287 } __attribute__ ((__packed__));
 288
 289 /*
 290  * Meaning of FW_STREAM_CONTROL::Mode bits:
 291  *  Bit 7: Loopback PEXin to PEXout using TVOut channel
 292  *  Bit 6: AVLOOP
 293  *  Bit 5: Audio select; 0=I2S, 1=SPDIF
 294  *  Bit 4: AVSYNC
 295  *  Bit 3: Enable transport stream
 296  *  Bit 2: Enable audio capture
 297  *  Bit 1: Enable ITU-Video VBI capture
 298  *  Bit 0: Enable ITU-Video capture
 299  *
 300  * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL)
 301  *  Bit 7: continuous capture
 302  *  Bit 6: capture one field
 303  *  Bit 5: capture one frame
 304  *  Bit 4: unused
 305  *  Bit 3: starting field; 0=odd, 1=even
 306  *  Bit 2: sample size; 0=8-bit, 1=10-bit
 307  *  Bit 1: data format; 0=UYVY, 1=YUY2
 308  *  Bit 0: resets buffer pointers
 309 */
 310
 311 enum FSC_MODE_BITS {
 312         SMODE_LOOPBACK          = 0x80,
 313         SMODE_AVLOOP            = 0x40,
 314         _SMODE_AUDIO_SPDIF      = 0x20,
 315         _SMODE_AVSYNC           = 0x10,
 316         _SMODE_TRANSPORT_STREAM = 0x08,
 317         _SMODE_AUDIO_CAPTURE    = 0x04,
 318         _SMODE_VBI_CAPTURE      = 0x02,
 319         _SMODE_VIDEO_CAPTURE    = 0x01
 320 };
 321
 322
 323 /* Meaning of FW_STREAM_CONTROL::Stream bits:
 324  * Bit 3: Audio sample count:  0 = relative, 1 = absolute
 325  * Bit 2: color bar select; 1=color bars, 0=CV3 decoder
 326  * Bits 1-0: stream select, UVI1, UVI2, TVOUT
 327  */
 328
 329 struct FW_STREAM_CONTROL {
 330         struct FW_HEADER hdr;
 331         u8     Stream;             /* Stream number (UVI1, UVI2, TVOUT) */
 332         u8     Control;            /* Value written to UVI1_CTL */
 333         u8     Mode;               /* Controls clock source */
 334         u8     SetupDataLen;       /* Length of setup data, MSB=1 write
 335                                       backwards */
 336         u16    CaptureBlockCount;  /* Blocks (a 256 Bytes) to capture per buffer
 337                                       for TS and Audio */
 338         u64    Buffer_Address;     /* Address of first buffer header */
 339         u16    BytesPerVideoLine;
 340         u16    MaxLinesPerField;
 341         u16    MinLinesPerField;
 342         u16    Reserved_1;
 343         u16    BytesPerVBILine;
 344         u16    MaxVBILinesPerField;
 345         u16    MinVBILinesPerField;
 346         u16    SetupDataAddr;      /* ngene relative address of setup data */
 347         u8     SetupData[32];      /* setup data */
 348 } __attribute__((__packed__));
 349
 350 #define AUDIO_BLOCK_SIZE    256
 351 #define TS_BLOCK_SIZE       256
 352
 353 struct FW_MEM_READ {
 354         struct FW_HEADER hdr;
 355         u16   address;
 356 } __attribute__ ((__packed__));
 357
 358 struct FW_MEM_WRITE {
 359         struct FW_HEADER hdr;
 360         u16   address;
 361         u8    data;
 362 } __attribute__ ((__packed__));
 363
 364 struct FW_SFR_IRAM_READ {
 365         struct FW_HEADER hdr;
 366         u8    address;
 367 } __attribute__ ((__packed__));
 368
 369 struct FW_SFR_IRAM_WRITE {
 370         struct FW_HEADER hdr;
 371         u8    address;
 372         u8    data;
 373 } __attribute__ ((__packed__));
 374
 375 struct FW_SET_GPIO_PIN {
 376         struct FW_HEADER hdr;
 377         u8    select;
 378 } __attribute__ ((__packed__));
 379
 380 struct FW_SET_GPIO_INT {
 381         struct FW_HEADER hdr;
 382         u8    select;
 383 } __attribute__ ((__packed__));
 384
 385 struct FW_SET_DEBUGMODE {
 386         struct FW_HEADER hdr;
 387         u8   debug_flags;
 388 } __attribute__ ((__packed__));
 389
 390 struct FW_CONFIGURE_BUFFERS {
 391         struct FW_HEADER hdr;
 392         u8   config;
 393 } __attribute__ ((__packed__));
 394
 395 enum _BUFFER_CONFIGS {
 396         /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2  (standard usage) */
 397         BUFFER_CONFIG_4422 = 0,
 398         /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2  (4x TS input usage) */
 399         BUFFER_CONFIG_3333 = 1,
 400         /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut  (HDTV decoder usage) */
 401         BUFFER_CONFIG_8022 = 2,
 402         BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */
 403 };
 404
 405 struct FW_CONFIGURE_FREE_BUFFERS {
 406         struct FW_HEADER hdr;
 407         u8   UVI1_BufferLength;
 408         u8   UVI2_BufferLength;
 409         u8   TVO_BufferLength;
 410         u8   AUD1_BufferLength;
 411         u8   AUD2_BufferLength;
 412         u8   TVA_BufferLength;
 413 } __attribute__ ((__packed__));
 414
 415 struct FW_CONFIGURE_UART {
 416         struct FW_HEADER hdr;
 417         u8 UartControl;
 418 } __attribute__ ((__packed__));
 419
 420 enum _UART_CONFIG {
 421         _UART_BAUDRATE_19200 = 0,
 422         _UART_BAUDRATE_9600  = 1,
 423         _UART_BAUDRATE_4800  = 2,
 424         _UART_BAUDRATE_2400  = 3,
 425         _UART_RX_ENABLE      = 0x40,
 426         _UART_TX_ENABLE      = 0x80,
 427 };
 428
 429 struct FW_WRITE_UART {
 430         struct FW_HEADER hdr;
 431         u8 Data[252];
 432 } __attribute__ ((__packed__));
 433
 434
 435 struct ngene_command {
 436         u32 in_len;
 437         u32 out_len;
 438         union {
 439                 u32                              raw[64];
 440                 u8                               raw8[256];
 441                 struct FW_HEADER                 hdr;
 442                 struct FW_I2C_WRITE              I2CWrite;
 443                 struct FW_I2C_CONTINUE_WRITE     I2CContinueWrite;
 444                 struct FW_I2C_READ               I2CRead;
 445                 struct FW_STREAM_CONTROL         StreamControl;
 446                 struct FW_FWLOAD_PREPARE         FWLoadPrepare;
 447                 struct FW_FWLOAD_FINISH          FWLoadFinish;
 448                 struct FW_MEM_READ               MemoryRead;
 449                 struct FW_MEM_WRITE              MemoryWrite;
 450                 struct FW_SFR_IRAM_READ          SfrIramRead;
 451                 struct FW_SFR_IRAM_WRITE         SfrIramWrite;
 452                 struct FW_SPI_WRITE              SPIWrite;
 453                 struct FW_SPI_READ               SPIRead;
 454                 struct FW_SET_GPIO_PIN           SetGpioPin;
 455                 struct FW_SET_GPIO_INT           SetGpioInt;
 456                 struct FW_SET_DEBUGMODE          SetDebugMode;
 457                 struct FW_CONFIGURE_BUFFERS      ConfigureBuffers;
 458                 struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers;
 459                 struct FW_CONFIGURE_UART         ConfigureUart;
 460                 struct FW_WRITE_UART             WriteUart;
 461         } cmd;
 462 } __attribute__ ((__packed__));
 463
 464 #define NGENE_INTERFACE_VERSION 0x103
 465 #define MAX_VIDEO_BUFFER_SIZE   (417792) /* 288*1440 rounded up to next page */
 466 #define MAX_AUDIO_BUFFER_SIZE     (8192) /* Gives room for about 23msec@48KHz */
 467 #define MAX_VBI_BUFFER_SIZE      (28672) /* 1144*18 rounded up to next page */
 468 #define MAX_TS_BUFFER_SIZE       (98304) /* 512*188 rounded up to next page */
 469 #define MAX_HDTV_BUFFER_SIZE   (2080768) /* 541*1920*2 rounded up to next page
 470                                             Max: (1920x1080i60) */
 471
 472 #define OVERFLOW_BUFFER_SIZE    (8192)
 473
 474 #define RING_SIZE_VIDEO     4
 475 #define RING_SIZE_AUDIO     8
 476 #define RING_SIZE_TS        8
 477
 478 #define NUM_SCATTER_GATHER_ENTRIES  8
 479
 480 #define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \
 481                         RING_SIZE_VIDEO * 2) + \
 482                         (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \
 483                         (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \
 484                         (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \
 485                         (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \
 486                         (RING_SIZE_TS    * PAGE_SIZE * 4) + \
 487                          8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE)
 488
 489 #define EVENT_QUEUE_SIZE    16
 490
 491 typedef struct HW_SCATTER_GATHER_ELEMENT *PHW_SCATTER_GATHER_ELEMENT;
 492 typedef struct FWRB *PFWRB;
 493
 494 /* Gathers the current state of a single channel. */
 495
 496 struct SBufferHeader {
 497         struct BUFFER_HEADER   ngeneBuffer; /* Physical descriptor */
 498         struct SBufferHeader  *Next;
 499         void                  *Buffer1;
 500         PHW_SCATTER_GATHER_ELEMENT scList1;
 501         void                  *Buffer2;
 502         PHW_SCATTER_GATHER_ELEMENT scList2;
 503 };
 504
 505 /* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */
 506 #define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63)
 507
 508 enum HWSTATE {
 509         HWSTATE_STOP,
 510         HWSTATE_STARTUP,
 511         HWSTATE_RUN,
 512         HWSTATE_PAUSE,
 513 };
 514
 515 enum KSSTATE {
 516         KSSTATE_STOP,
 517         KSSTATE_ACQUIRE,
 518         KSSTATE_PAUSE,
 519         KSSTATE_RUN,
 520 };
 521
 522 struct SRingBufferDescriptor {
 523         struct SBufferHeader *Head; /* Points to first buffer in ring buffer
 524                                        structure*/
 525         u64   PAHead;         /* Physical address of first buffer */
 526         u32   MemSize;        /* Memory size of allocated ring buffers
 527                                  (needed for freeing) */
 528         u32   NumBuffers;     /* Number of buffers in the ring */
 529         u32   Buffer1Length;  /* Allocated length of Buffer 1 */
 530         u32   Buffer2Length;  /* Allocated length of Buffer 2 */
 531         void *SCListMem;      /* Memory to hold scatter gather lists for this
 532                                  ring */
 533         u64   PASCListMem;    /* Physical address  .. */
 534         u32   SCListMemSize;  /* Size of this memory */
 535 };
 536
 537 enum STREAMMODEFLAGS {
 538         StreamMode_NONE   = 0, /* Stream not used */
 539         StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */
 540         StreamMode_TSIN   = 2, /* Transport stream input (all) */
 541         StreamMode_HDTV   = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60
 542                                   (only stream 0) */
 543         StreamMode_TSOUT  = 8, /* Transport stream output (only stream 3) */
 544 };
 545
 546
 547 enum BufferExchangeFlags {
 548         BEF_EVEN_FIELD   = 0x00000001,
 549         BEF_CONTINUATION = 0x00000002,
 550         BEF_MORE_DATA    = 0x00000004,
 551         BEF_OVERFLOW     = 0x00000008,
 552         DF_SWAP32        = 0x00010000,
 553 };
 554
 555 typedef void *(IBufferExchange)(void *, void *, u32, u32, u32);
 556
 557 typedef struct {
 558         IBufferExchange    *pExchange;
 559         IBufferExchange    *pExchangeVBI;     /* Secondary (VBI, ancillary) */
 560         u8  Stream;
 561         u8  Flags;
 562         u8  Mode;
 563         u8  Reserved;
 564         u16 nLinesVideo;
 565         u16 nBytesPerLineVideo;
 566         u16 nLinesVBI;
 567         u16 nBytesPerLineVBI;
 568         u32 CaptureLength;    /* Used for audio and transport stream */
 569 } MICI_STREAMINFO, *PMICI_STREAMINFO;
 570
 571 /****************************************************************************/
 572 /* STRUCTS ******************************************************************/
 573 /****************************************************************************/
 574
 575 /* sound hardware definition */
 576 #define MIXER_ADDR_TVTUNER      0
 577 #define MIXER_ADDR_LAST         0
 578
 579 struct ngene_channel;
 580
 581 /*struct sound chip*/
 582
 583 struct mychip {
 584         struct ngene_channel *chan;
 585         struct snd_card *card;
 586         struct pci_dev *pci;
 587         struct snd_pcm_substream *substream;
 588         struct snd_pcm *pcm;
 589         unsigned long port;
 590         int irq;
 591         spinlock_t mixer_lock;
 592         spinlock_t lock;
 593         int mixer_volume[MIXER_ADDR_LAST + 1][2];
 594         int capture_source[MIXER_ADDR_LAST + 1][2];
 595 };
 596
 597 #ifdef NGENE_V4L
 598 struct ngene_overlay {
 599         int                    tvnorm;
 600         struct v4l2_rect       w;
 601         enum v4l2_field        field;
 602         struct v4l2_clip       *clips;
 603         int                    nclips;
 604         int                    setup_ok;
 605 };
 606
 607 struct ngene_tvnorm {
 608         int   v4l2_id;
 609         char  *name;
 610         u16   swidth, sheight; /* scaled standard width, height */
 611         int   tuner_norm;
 612         int   soundstd;
 613 };
 614
 615 struct ngene_vopen {
 616         struct ngene_channel      *ch;
 617         enum v4l2_priority         prio;
 618         int                        width;
 619         int                        height;
 620         int                        depth;
 621         struct videobuf_queue      vbuf_q;
 622         struct videobuf_queue      vbi;
 623         int                        fourcc;
 624         int                        picxcount;
 625         int                        resources;
 626         enum v4l2_buf_type         type;
 627         const struct ngene_format *fmt;
 628
 629         const struct ngene_format *ovfmt;
 630         struct ngene_overlay       ov;
 631 };
 632 #endif
 633
 634 struct ngene_channel {
 635         struct device         device;
 636         struct i2c_adapter    i2c_adapter;
 637
 638         struct ngene         *dev;
 639         int                   number;
 640         int                   type;
 641         int                   mode;
 642
 643         struct dvb_frontend  *fe;
 644         struct dmxdev         dmxdev;
 645         struct dvb_demux      demux;
 646         struct dmx_frontend   hw_frontend;
 647         struct dmx_frontend   mem_frontend;
 648         int                   users;
 649         struct video_device  *v4l_dev;
 650         struct tasklet_struct demux_tasklet;
 651
 652         struct SBufferHeader *nextBuffer;
 653         enum KSSTATE          State;
 654         enum HWSTATE          HWState;
 655         u8                    Stream;
 656         u8                    Flags;
 657         u8                    Mode;
 658         IBufferExchange      *pBufferExchange;
 659         IBufferExchange      *pBufferExchange2;
 660
 661         spinlock_t            state_lock;
 662         u16                   nLines;
 663         u16                   nBytesPerLine;
 664         u16                   nVBILines;
 665         u16                   nBytesPerVBILine;
 666         u16                   itumode;
 667         u32                   Capture1Length;
 668         u32                   Capture2Length;
 669         struct SRingBufferDescriptor RingBuffer;
 670         struct SRingBufferDescriptor TSRingBuffer;
 671         struct SRingBufferDescriptor TSIdleBuffer;
 672
 673         u32                   DataFormatFlags;
 674
 675         int                   AudioDTOUpdated;
 676         u32                   AudioDTOValue;
 677
 678         int (*set_tone)(struct dvb_frontend *, fe_sec_tone_mode_t);
 679         u8 lnbh;
 680
 681         /* stuff from analog driver */
 682
 683         int minor;
 684         struct mychip        *mychip;
 685         struct snd_card      *soundcard;
 686         u8                   *evenbuffer;
 687         u8                    dma_on;
 688         int                   soundstreamon;
 689         int                   audiomute;
 690         int                   soundbuffisallocated;
 691         int                   sndbuffflag;
 692         int                   tun_rdy;
 693         int                   dec_rdy;
 694         int                   tun_dec_rdy;
 695         int                   lastbufferflag;
 696
 697         struct ngene_tvnorm  *tvnorms;
 698         int                   tvnorm_num;
 699         int                   tvnorm;
 700
 701 #ifdef NGENE_V4L
 702         int                   videousers;
 703         struct v4l2_prio_state prio;
 704         struct ngene_vopen    init;
 705         int                   resources;
 706         struct v4l2_framebuffer fbuf;
 707         struct ngene_buffer  *screen;     /* overlay             */
 708         struct list_head      capture;    /* video capture queue */
 709         spinlock_t s_lock;
 710         struct semaphore reslock;
 711 #endif
 712
 713         int running;
 714 };
 715
 716 struct ngene;
 717
 718 typedef void (rx_cb_t)(struct ngene *, u32, u8);
 719 typedef void (tx_cb_t)(struct ngene *, u32);
 720
 721 struct ngene {
 722         int                   nr;
 723         struct pci_dev       *pci_dev;
 724         unsigned char        *iomem;
 725
 726         /*struct i2c_adapter  i2c_adapter;*/
 727
 728         u32                   device_version;
 729         u32                   fw_interface_version;
 730         u32                   icounts;
 731
 732         u8                   *CmdDoneByte;
 733         int                   BootFirmware;
 734         void                 *OverflowBuffer;
 735         dma_addr_t            PAOverflowBuffer;
 736         void                 *FWInterfaceBuffer;
 737         dma_addr_t            PAFWInterfaceBuffer;
 738         u8                   *ngenetohost;
 739         u8                   *hosttongene;
 740
 741         struct EVENT_BUFFER   EventQueue[EVENT_QUEUE_SIZE];
 742         int                   EventQueueOverflowCount;
 743         int                   EventQueueOverflowFlag;
 744         struct tasklet_struct event_tasklet;
 745         struct EVENT_BUFFER  *EventBuffer;
 746         int                   EventQueueWriteIndex;
 747         int                   EventQueueReadIndex;
 748
 749         wait_queue_head_t     cmd_wq;
 750         int                   cmd_done;
 751         struct semaphore      cmd_mutex;
 752         struct semaphore      stream_mutex;
 753         struct semaphore      pll_mutex;
 754         struct semaphore      i2c_switch_mutex;
 755         int                   i2c_current_channel;
 756         int                   i2c_current_bus;
 757         spinlock_t            cmd_lock;
 758
 759         struct dvb_adapter    adapter[MAX_STREAM];
 760         struct ngene_channel  channel[MAX_STREAM];
 761
 762         struct ngene_info    *card_info;
 763
 764         tx_cb_t              *TxEventNotify;
 765         rx_cb_t              *RxEventNotify;
 766         int                   tx_busy;
 767         wait_queue_head_t     tx_wq;
 768         wait_queue_head_t     rx_wq;
 769 #define UART_RBUF_LEN 4096
 770         u8                    uart_rbuf[UART_RBUF_LEN];
 771         int                   uart_rp, uart_wp;
 772
 773         u8                   *tsout_buf;
 774 #define TSOUT_BUF_SIZE (512*188*8)
 775         struct dvb_ringbuffer tsout_rbuf;
 776
 777         u8                   *ain_buf;
 778 #define AIN_BUF_SIZE (128*1024)
 779         struct dvb_ringbuffer ain_rbuf;
 780
 781
 782         u8                   *vin_buf;
 783 #define VIN_BUF_SIZE (4*1920*1080)
 784         struct dvb_ringbuffer vin_rbuf;
 785
 786         unsigned long         exp_val;
 787         int prev_cmd;
 788 };
 789
 790 struct ngene_info {
 791         int   type;
 792 #define NGENE_APP        0
 793 #define NGENE_TERRATEC   1
 794 #define NGENE_SIDEWINDER 2
 795 #define NGENE_RACER      3
 796 #define NGENE_VIPER      4
 797 #define NGENE_PYTHON     5
 798 #define NGENE_VBOX_V1    6
 799 #define NGENE_VBOX_V2    7
 800
 801         int   fw_version;
 802         char *name;
 803
 804         int   io_type[MAX_STREAM];
 805 #define NGENE_IO_NONE    0
 806 #define NGENE_IO_TV      1
 807 #define NGENE_IO_HDTV    2
 808 #define NGENE_IO_TSIN    4
 809 #define NGENE_IO_TSOUT   8
 810 #define NGENE_IO_AIN     16
 811
 812         void *fe_config[4];
 813         void *tuner_config[4];
 814
 815         int (*demod_attach[4])(struct ngene_channel *);
 816         int (*tuner_attach[4])(struct ngene_channel *);
 817
 818         u8    avf[4];
 819         u8    msp[4];
 820         u8    demoda[4];
 821         u8    lnb[4];
 822         int   i2c_access;
 823         u8    ntsc;
 824         u8    tsf[4];
 825         u8    i2s[4];
 826
 827         int (*gate_ctrl)(struct dvb_frontend *, int);
 828         int (*switch_ctrl)(struct ngene_channel *, int, int);
 829 };
 830
 831 #ifdef NGENE_V4L
 832 struct ngene_format{
 833         char *name;
 834         int   fourcc;          /* video4linux 2      */
 835         int   btformat;        /* BT848_COLOR_FMT_*  */
 836         int   format;
 837         int   btswap;          /* BT848_COLOR_CTL_*  */
 838         int   depth;           /* bit/pixel          */
 839         int   flags;
 840         int   hshift, vshift;  /* for planar modes   */
 841         int   palette;
 842 };
 843
 844 #define RESOURCE_OVERLAY       1
 845 #define RESOURCE_VIDEO         2
 846 #define RESOURCE_VBI           4
 847
 848 struct ngene_buffer {
 849         /* common v4l buffer stuff -- must be first */
 850         struct videobuf_buffer     vb;
 851
 852         /* ngene specific */
 853         const struct ngene_format *fmt;
 854         int                        tvnorm;
 855         int                        btformat;
 856         int                        btswap;
 857 };
 858 #endif
 859
 860 int ngene_command_stream_control(struct ngene *dev,
 861                                  u8 stream, u8 control, u8 mode, u8 flags);
 862 int ngene_command_nop(struct ngene *dev);
 863 int ngene_command_i2c_read(struct ngene *dev, u8 adr,
 864                            u8 *out, u8 outlen, u8 *in, u8 inlen, int flag);
 865 int ngene_command_i2c_write(struct ngene *dev, u8 adr, u8 *out, u8 outlen);
 866 int ngene_command_imem_read(struct ngene *dev, u8 adr, u8 *data, int type);
 867 int ngene_command_imem_write(struct ngene *dev, u8 adr, u8 data, int type);
 868 int ngene_stream_control(struct ngene *dev, u8 stream, u8 control, u8 mode,
 869                          u16 lines, u16 bpl, u16 vblines, u16 vbibpl);
 870
 871
 872 #endif
 873
 874 /*  LocalWords:  Endif
 875  */