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ath9k: Update copyright in all the files
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath9k / main.c
blob7d27eed78af48914dba3422e6730665d2486f20c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19
20 #define ATH_PCI_VERSION "0.1"
21
22 static char *dev_info = "ath9k";
23
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
28
29 static int modparam_nohwcrypt;
30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
33 /* We use the hw_value as an index into our private channel structure */
34
35 #define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 30, \
39 }
40
41 #define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 30, \
46 }
47
48 /* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67 };
68
69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102 };
103
104 static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
106 {
107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
118 else
119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
135 break;
136 default:
137 BUG_ON(1);
138 break;
139 }
140 }
141
142 static void ath_update_txpow(struct ath_softc *sc)
143 {
144 struct ath_hw *ah = sc->sc_ah;
145 u32 txpow;
146
147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
151 sc->curtxpow = txpow;
152 }
153 }
154
155 static u8 parse_mpdudensity(u8 mpdudensity)
156 {
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188 }
189
190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191 {
192 struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
227 sband->n_bitrates++;
228
229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
231 }
232 }
233
234 /*
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
238 */
239 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
240 struct ath9k_channel *hchan)
241 {
242 struct ath_hw *ah = sc->sc_ah;
243 bool fastcc = true, stopped;
244 struct ieee80211_channel *channel = hw->conf.channel;
245 int r;
246
247 if (sc->sc_flags & SC_OP_INVALID)
248 return -EIO;
249
250 ath9k_ps_wakeup(sc);
251
252 /*
253 * This is only performed if the channel settings have
254 * actually changed.
255 *
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
260 */
261 ath9k_hw_set_interrupts(ah, 0);
262 ath_drain_all_txq(sc, false);
263 stopped = ath_stoprecv(sc);
264
265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
268
269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270 fastcc = false;
271
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
274 sc->sc_ah->curchan->channel,
275 channel->center_freq, sc->tx_chan_width);
276
277 spin_lock_bh(&sc->sc_resetlock);
278
279 r = ath9k_hw_reset(ah, hchan, fastcc);
280 if (r) {
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
283 "reset status %u\n",
284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
286 return r;
287 }
288 spin_unlock_bh(&sc->sc_resetlock);
289
290 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
291 sc->sc_flags &= ~SC_OP_FULL_RESET;
292
293 if (ath_startrecv(sc) != 0) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to restart recv logic\n");
296 return -EIO;
297 }
298
299 ath_cache_conf_rate(sc, &hw->conf);
300 ath_update_txpow(sc);
301 ath9k_hw_set_interrupts(ah, sc->imask);
302 ath9k_ps_restore(sc);
303 return 0;
304 }
305
306 /*
307 * This routine performs the periodic noise floor calibration function
308 * that is used to adjust and optimize the chip performance. This
309 * takes environmental changes (location, temperature) into account.
310 * When the task is complete, it reschedules itself depending on the
311 * appropriate interval that was calculated.
312 */
313 static void ath_ani_calibrate(unsigned long data)
314 {
315 struct ath_softc *sc = (struct ath_softc *)data;
316 struct ath_hw *ah = sc->sc_ah;
317 bool longcal = false;
318 bool shortcal = false;
319 bool aniflag = false;
320 unsigned int timestamp = jiffies_to_msecs(jiffies);
321 u32 cal_interval, short_cal_interval;
322
323 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
324 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
325
326 /*
327 * don't calibrate when we're scanning.
328 * we are most likely not on our home channel.
329 */
330 if (sc->sc_flags & SC_OP_SCANNING)
331 goto set_timer;
332
333 /* Long calibration runs independently of short calibration. */
334 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
335 longcal = true;
336 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
337 sc->ani.longcal_timer = timestamp;
338 }
339
340 /* Short calibration applies only while caldone is false */
341 if (!sc->ani.caldone) {
342 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
343 shortcal = true;
344 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
345 sc->ani.shortcal_timer = timestamp;
346 sc->ani.resetcal_timer = timestamp;
347 }
348 } else {
349 if ((timestamp - sc->ani.resetcal_timer) >=
350 ATH_RESTART_CALINTERVAL) {
351 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
352 if (sc->ani.caldone)
353 sc->ani.resetcal_timer = timestamp;
354 }
355 }
356
357 /* Verify whether we must check ANI */
358 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
359 aniflag = true;
360 sc->ani.checkani_timer = timestamp;
361 }
362
363 /* Skip all processing if there's nothing to do. */
364 if (longcal || shortcal || aniflag) {
365 /* Call ANI routine if necessary */
366 if (aniflag)
367 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
368
369 /* Perform calibration if necessary */
370 if (longcal || shortcal) {
371 bool iscaldone = false;
372
373 if (ath9k_hw_calibrate(ah, ah->curchan,
374 sc->rx_chainmask, longcal,
375 &iscaldone)) {
376 if (longcal)
377 sc->ani.noise_floor =
378 ath9k_hw_getchan_noise(ah,
379 ah->curchan);
380
381 DPRINTF(sc, ATH_DBG_ANI,
382 "calibrate chan %u/%x nf: %d\n",
383 ah->curchan->channel,
384 ah->curchan->channelFlags,
385 sc->ani.noise_floor);
386 } else {
387 DPRINTF(sc, ATH_DBG_ANY,
388 "calibrate chan %u/%x failed\n",
389 ah->curchan->channel,
390 ah->curchan->channelFlags);
391 }
392 sc->ani.caldone = iscaldone;
393 }
394 }
395
396 set_timer:
397 /*
398 * Set timer interval based on previous results.
399 * The interval must be the shortest necessary to satisfy ANI,
400 * short calibration and long calibration.
401 */
402 cal_interval = ATH_LONG_CALINTERVAL;
403 if (sc->sc_ah->config.enable_ani)
404 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
405 if (!sc->ani.caldone)
406 cal_interval = min(cal_interval, (u32)short_cal_interval);
407
408 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
409 }
410
411 /*
412 * Update tx/rx chainmask. For legacy association,
413 * hard code chainmask to 1x1, for 11n association, use
414 * the chainmask configuration, for bt coexistence, use
415 * the chainmask configuration even in legacy mode.
416 */
417 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
418 {
419 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
420 if (is_ht ||
421 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
422 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
423 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
424 } else {
425 sc->tx_chainmask = 1;
426 sc->rx_chainmask = 1;
427 }
428
429 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
430 sc->tx_chainmask, sc->rx_chainmask);
431 }
432
433 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
434 {
435 struct ath_node *an;
436
437 an = (struct ath_node *)sta->drv_priv;
438
439 if (sc->sc_flags & SC_OP_TXAGGR)
440 ath_tx_node_init(sc, an);
441
442 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
443 sta->ht_cap.ampdu_factor);
444 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
445 }
446
447 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
448 {
449 struct ath_node *an = (struct ath_node *)sta->drv_priv;
450
451 if (sc->sc_flags & SC_OP_TXAGGR)
452 ath_tx_node_cleanup(sc, an);
453 }
454
455 static void ath9k_tasklet(unsigned long data)
456 {
457 struct ath_softc *sc = (struct ath_softc *)data;
458 u32 status = sc->intrstatus;
459
460 if (status & ATH9K_INT_FATAL) {
461 /* need a chip reset */
462 ath_reset(sc, false);
463 return;
464 } else {
465
466 if (status &
467 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
468 spin_lock_bh(&sc->rx.rxflushlock);
469 ath_rx_tasklet(sc, 0);
470 spin_unlock_bh(&sc->rx.rxflushlock);
471 }
472 /* XXX: optimize this */
473 if (status & ATH9K_INT_TX)
474 ath_tx_tasklet(sc);
475 }
476
477 /* re-enable hardware interrupt */
478 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
479 }
480
481 irqreturn_t ath_isr(int irq, void *dev)
482 {
483 struct ath_softc *sc = dev;
484 struct ath_hw *ah = sc->sc_ah;
485 enum ath9k_int status;
486 bool sched = false;
487
488 do {
489 if (sc->sc_flags & SC_OP_INVALID) {
490 /*
491 * The hardware is not ready/present, don't
492 * touch anything. Note this can happen early
493 * on if the IRQ is shared.
494 */
495 return IRQ_NONE;
496 }
497 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
498 return IRQ_NONE;
499 }
500
501 /*
502 * Figure out the reason(s) for the interrupt. Note
503 * that the hal returns a pseudo-ISR that may include
504 * bits we haven't explicitly enabled so we mask the
505 * value to insure we only process bits we requested.
506 */
507 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
508
509 status &= sc->imask; /* discard unasked-for bits */
510
511 /*
512 * If there are no status bits set, then this interrupt was not
513 * for me (should have been caught above).
514 */
515 if (!status)
516 return IRQ_NONE;
517
518 sc->intrstatus = status;
519 ath9k_ps_wakeup(sc);
520
521 if (status & ATH9K_INT_FATAL) {
522 /* need a chip reset */
523 sched = true;
524 } else if (status & ATH9K_INT_RXORN) {
525 /* need a chip reset */
526 sched = true;
527 } else {
528 if (status & ATH9K_INT_SWBA) {
529 /* schedule a tasklet for beacon handling */
530 tasklet_schedule(&sc->bcon_tasklet);
531 }
532 if (status & ATH9K_INT_RXEOL) {
533 /*
534 * NB: the hardware should re-read the link when
535 * RXE bit is written, but it doesn't work
536 * at least on older hardware revs.
537 */
538 sched = true;
539 }
540
541 if (status & ATH9K_INT_TXURN)
542 /* bump tx trigger level */
543 ath9k_hw_updatetxtriglevel(ah, true);
544 /* XXX: optimize this */
545 if (status & ATH9K_INT_RX)
546 sched = true;
547 if (status & ATH9K_INT_TX)
548 sched = true;
549 if (status & ATH9K_INT_BMISS)
550 sched = true;
551 /* carrier sense timeout */
552 if (status & ATH9K_INT_CST)
553 sched = true;
554 if (status & ATH9K_INT_MIB) {
555 /*
556 * Disable interrupts until we service the MIB
557 * interrupt; otherwise it will continue to
558 * fire.
559 */
560 ath9k_hw_set_interrupts(ah, 0);
561 /*
562 * Let the hal handle the event. We assume
563 * it will clear whatever condition caused
564 * the interrupt.
565 */
566 ath9k_hw_procmibevent(ah, &sc->nodestats);
567 ath9k_hw_set_interrupts(ah, sc->imask);
568 }
569 if (status & ATH9K_INT_TIM_TIMER) {
570 if (!(ah->caps.hw_caps &
571 ATH9K_HW_CAP_AUTOSLEEP)) {
572 /* Clear RxAbort bit so that we can
573 * receive frames */
574 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
575 ath9k_hw_setrxabort(ah, 0);
576 sched = true;
577 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
578 }
579 }
580 if (status & ATH9K_INT_TSFOOR) {
581 /* FIXME: Handle this interrupt for power save */
582 sched = true;
583 }
584 }
585 ath9k_ps_restore(sc);
586 } while (0);
587
588 ath_debug_stat_interrupt(sc, status);
589
590 if (sched) {
591 /* turn off every interrupt except SWBA */
592 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
593 tasklet_schedule(&sc->intr_tq);
594 }
595
596 return IRQ_HANDLED;
597 }
598
599 static u32 ath_get_extchanmode(struct ath_softc *sc,
600 struct ieee80211_channel *chan,
601 enum nl80211_channel_type channel_type)
602 {
603 u32 chanmode = 0;
604
605 switch (chan->band) {
606 case IEEE80211_BAND_2GHZ:
607 switch(channel_type) {
608 case NL80211_CHAN_NO_HT:
609 case NL80211_CHAN_HT20:
610 chanmode = CHANNEL_G_HT20;
611 break;
612 case NL80211_CHAN_HT40PLUS:
613 chanmode = CHANNEL_G_HT40PLUS;
614 break;
615 case NL80211_CHAN_HT40MINUS:
616 chanmode = CHANNEL_G_HT40MINUS;
617 break;
618 }
619 break;
620 case IEEE80211_BAND_5GHZ:
621 switch(channel_type) {
622 case NL80211_CHAN_NO_HT:
623 case NL80211_CHAN_HT20:
624 chanmode = CHANNEL_A_HT20;
625 break;
626 case NL80211_CHAN_HT40PLUS:
627 chanmode = CHANNEL_A_HT40PLUS;
628 break;
629 case NL80211_CHAN_HT40MINUS:
630 chanmode = CHANNEL_A_HT40MINUS;
631 break;
632 }
633 break;
634 default:
635 break;
636 }
637
638 return chanmode;
639 }
640
641 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
642 struct ath9k_keyval *hk, const u8 *addr,
643 bool authenticator)
644 {
645 const u8 *key_rxmic;
646 const u8 *key_txmic;
647
648 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
649 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
650
651 if (addr == NULL) {
652 /*
653 * Group key installation - only two key cache entries are used
654 * regardless of splitmic capability since group key is only
655 * used either for TX or RX.
656 */
657 if (authenticator) {
658 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
659 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
660 } else {
661 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
662 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
663 }
664 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
665 }
666 if (!sc->splitmic) {
667 /* TX and RX keys share the same key cache entry. */
668 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
669 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
670 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
671 }
672
673 /* Separate key cache entries for TX and RX */
674
675 /* TX key goes at first index, RX key at +32. */
676 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
677 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
678 /* TX MIC entry failed. No need to proceed further */
679 DPRINTF(sc, ATH_DBG_KEYCACHE,
680 "Setting TX MIC Key Failed\n");
681 return 0;
682 }
683
684 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
685 /* XXX delete tx key on failure? */
686 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
687 }
688
689 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
690 {
691 int i;
692
693 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
694 if (test_bit(i, sc->keymap) ||
695 test_bit(i + 64, sc->keymap))
696 continue; /* At least one part of TKIP key allocated */
697 if (sc->splitmic &&
698 (test_bit(i + 32, sc->keymap) ||
699 test_bit(i + 64 + 32, sc->keymap)))
700 continue; /* At least one part of TKIP key allocated */
701
702 /* Found a free slot for a TKIP key */
703 return i;
704 }
705 return -1;
706 }
707
708 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
709 {
710 int i;
711
712 /* First, try to find slots that would not be available for TKIP. */
713 if (sc->splitmic) {
714 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
715 if (!test_bit(i, sc->keymap) &&
716 (test_bit(i + 32, sc->keymap) ||
717 test_bit(i + 64, sc->keymap) ||
718 test_bit(i + 64 + 32, sc->keymap)))
719 return i;
720 if (!test_bit(i + 32, sc->keymap) &&
721 (test_bit(i, sc->keymap) ||
722 test_bit(i + 64, sc->keymap) ||
723 test_bit(i + 64 + 32, sc->keymap)))
724 return i + 32;
725 if (!test_bit(i + 64, sc->keymap) &&
726 (test_bit(i , sc->keymap) ||
727 test_bit(i + 32, sc->keymap) ||
728 test_bit(i + 64 + 32, sc->keymap)))
729 return i + 64;
730 if (!test_bit(i + 64 + 32, sc->keymap) &&
731 (test_bit(i, sc->keymap) ||
732 test_bit(i + 32, sc->keymap) ||
733 test_bit(i + 64, sc->keymap)))
734 return i + 64 + 32;
735 }
736 } else {
737 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
738 if (!test_bit(i, sc->keymap) &&
739 test_bit(i + 64, sc->keymap))
740 return i;
741 if (test_bit(i, sc->keymap) &&
742 !test_bit(i + 64, sc->keymap))
743 return i + 64;
744 }
745 }
746
747 /* No partially used TKIP slots, pick any available slot */
748 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
749 /* Do not allow slots that could be needed for TKIP group keys
750 * to be used. This limitation could be removed if we know that
751 * TKIP will not be used. */
752 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
753 continue;
754 if (sc->splitmic) {
755 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
756 continue;
757 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
758 continue;
759 }
760
761 if (!test_bit(i, sc->keymap))
762 return i; /* Found a free slot for a key */
763 }
764
765 /* No free slot found */
766 return -1;
767 }
768
769 static int ath_key_config(struct ath_softc *sc,
770 struct ieee80211_vif *vif,
771 struct ieee80211_sta *sta,
772 struct ieee80211_key_conf *key)
773 {
774 struct ath9k_keyval hk;
775 const u8 *mac = NULL;
776 int ret = 0;
777 int idx;
778
779 memset(&hk, 0, sizeof(hk));
780
781 switch (key->alg) {
782 case ALG_WEP:
783 hk.kv_type = ATH9K_CIPHER_WEP;
784 break;
785 case ALG_TKIP:
786 hk.kv_type = ATH9K_CIPHER_TKIP;
787 break;
788 case ALG_CCMP:
789 hk.kv_type = ATH9K_CIPHER_AES_CCM;
790 break;
791 default:
792 return -EOPNOTSUPP;
793 }
794
795 hk.kv_len = key->keylen;
796 memcpy(hk.kv_val, key->key, key->keylen);
797
798 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
799 /* For now, use the default keys for broadcast keys. This may
800 * need to change with virtual interfaces. */
801 idx = key->keyidx;
802 } else if (key->keyidx) {
803 if (WARN_ON(!sta))
804 return -EOPNOTSUPP;
805 mac = sta->addr;
806
807 if (vif->type != NL80211_IFTYPE_AP) {
808 /* Only keyidx 0 should be used with unicast key, but
809 * allow this for client mode for now. */
810 idx = key->keyidx;
811 } else
812 return -EIO;
813 } else {
814 if (WARN_ON(!sta))
815 return -EOPNOTSUPP;
816 mac = sta->addr;
817
818 if (key->alg == ALG_TKIP)
819 idx = ath_reserve_key_cache_slot_tkip(sc);
820 else
821 idx = ath_reserve_key_cache_slot(sc);
822 if (idx < 0)
823 return -ENOSPC; /* no free key cache entries */
824 }
825
826 if (key->alg == ALG_TKIP)
827 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
828 vif->type == NL80211_IFTYPE_AP);
829 else
830 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
831
832 if (!ret)
833 return -EIO;
834
835 set_bit(idx, sc->keymap);
836 if (key->alg == ALG_TKIP) {
837 set_bit(idx + 64, sc->keymap);
838 if (sc->splitmic) {
839 set_bit(idx + 32, sc->keymap);
840 set_bit(idx + 64 + 32, sc->keymap);
841 }
842 }
843
844 return idx;
845 }
846
847 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
848 {
849 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
850 if (key->hw_key_idx < IEEE80211_WEP_NKID)
851 return;
852
853 clear_bit(key->hw_key_idx, sc->keymap);
854 if (key->alg != ALG_TKIP)
855 return;
856
857 clear_bit(key->hw_key_idx + 64, sc->keymap);
858 if (sc->splitmic) {
859 clear_bit(key->hw_key_idx + 32, sc->keymap);
860 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
861 }
862 }
863
864 static void setup_ht_cap(struct ath_softc *sc,
865 struct ieee80211_sta_ht_cap *ht_info)
866 {
867 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
868 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
869
870 ht_info->ht_supported = true;
871 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
872 IEEE80211_HT_CAP_SM_PS |
873 IEEE80211_HT_CAP_SGI_40 |
874 IEEE80211_HT_CAP_DSSSCCK40;
875
876 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
877 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
878
879 /* set up supported mcs set */
880 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
881
882 switch(sc->rx_chainmask) {
883 case 1:
884 ht_info->mcs.rx_mask[0] = 0xff;
885 break;
886 case 3:
887 case 5:
888 case 7:
889 default:
890 ht_info->mcs.rx_mask[0] = 0xff;
891 ht_info->mcs.rx_mask[1] = 0xff;
892 break;
893 }
894
895 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
896 }
897
898 static void ath9k_bss_assoc_info(struct ath_softc *sc,
899 struct ieee80211_vif *vif,
900 struct ieee80211_bss_conf *bss_conf)
901 {
902 struct ath_vif *avp = (void *)vif->drv_priv;
903
904 if (bss_conf->assoc) {
905 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
906 bss_conf->aid, sc->curbssid);
907
908 /* New association, store aid */
909 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
910 sc->curaid = bss_conf->aid;
911 ath9k_hw_write_associd(sc);
912 }
913
914 /* Configure the beacon */
915 ath_beacon_config(sc, vif);
916
917 /* Reset rssi stats */
918 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
919 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
920 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
921 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
922
923 /* Start ANI */
924 mod_timer(&sc->ani.timer,
925 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
926 } else {
927 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
928 sc->curaid = 0;
929 }
930 }
931
932 /********************************/
933 /* LED functions */
934 /********************************/
935
936 static void ath_led_blink_work(struct work_struct *work)
937 {
938 struct ath_softc *sc = container_of(work, struct ath_softc,
939 ath_led_blink_work.work);
940
941 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
942 return;
943 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
944 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
945
946 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
947 (sc->sc_flags & SC_OP_LED_ON) ?
948 msecs_to_jiffies(sc->led_off_duration) :
949 msecs_to_jiffies(sc->led_on_duration));
950
951 sc->led_on_duration =
952 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
953 sc->led_off_duration =
954 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
955 sc->led_on_cnt = sc->led_off_cnt = 0;
956 if (sc->sc_flags & SC_OP_LED_ON)
957 sc->sc_flags &= ~SC_OP_LED_ON;
958 else
959 sc->sc_flags |= SC_OP_LED_ON;
960 }
961
962 static void ath_led_brightness(struct led_classdev *led_cdev,
963 enum led_brightness brightness)
964 {
965 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
966 struct ath_softc *sc = led->sc;
967
968 switch (brightness) {
969 case LED_OFF:
970 if (led->led_type == ATH_LED_ASSOC ||
971 led->led_type == ATH_LED_RADIO) {
972 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
973 (led->led_type == ATH_LED_RADIO));
974 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
975 if (led->led_type == ATH_LED_RADIO)
976 sc->sc_flags &= ~SC_OP_LED_ON;
977 } else {
978 sc->led_off_cnt++;
979 }
980 break;
981 case LED_FULL:
982 if (led->led_type == ATH_LED_ASSOC) {
983 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
984 queue_delayed_work(sc->hw->workqueue,
985 &sc->ath_led_blink_work, 0);
986 } else if (led->led_type == ATH_LED_RADIO) {
987 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
988 sc->sc_flags |= SC_OP_LED_ON;
989 } else {
990 sc->led_on_cnt++;
991 }
992 break;
993 default:
994 break;
995 }
996 }
997
998 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
999 char *trigger)
1000 {
1001 int ret;
1002
1003 led->sc = sc;
1004 led->led_cdev.name = led->name;
1005 led->led_cdev.default_trigger = trigger;
1006 led->led_cdev.brightness_set = ath_led_brightness;
1007
1008 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1009 if (ret)
1010 DPRINTF(sc, ATH_DBG_FATAL,
1011 "Failed to register led:%s", led->name);
1012 else
1013 led->registered = 1;
1014 return ret;
1015 }
1016
1017 static void ath_unregister_led(struct ath_led *led)
1018 {
1019 if (led->registered) {
1020 led_classdev_unregister(&led->led_cdev);
1021 led->registered = 0;
1022 }
1023 }
1024
1025 static void ath_deinit_leds(struct ath_softc *sc)
1026 {
1027 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1028 ath_unregister_led(&sc->assoc_led);
1029 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1030 ath_unregister_led(&sc->tx_led);
1031 ath_unregister_led(&sc->rx_led);
1032 ath_unregister_led(&sc->radio_led);
1033 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1034 }
1035
1036 static void ath_init_leds(struct ath_softc *sc)
1037 {
1038 char *trigger;
1039 int ret;
1040
1041 /* Configure gpio 1 for output */
1042 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1043 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1044 /* LED off, active low */
1045 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1046
1047 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1048
1049 trigger = ieee80211_get_radio_led_name(sc->hw);
1050 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1051 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1052 ret = ath_register_led(sc, &sc->radio_led, trigger);
1053 sc->radio_led.led_type = ATH_LED_RADIO;
1054 if (ret)
1055 goto fail;
1056
1057 trigger = ieee80211_get_assoc_led_name(sc->hw);
1058 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1059 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1060 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1061 sc->assoc_led.led_type = ATH_LED_ASSOC;
1062 if (ret)
1063 goto fail;
1064
1065 trigger = ieee80211_get_tx_led_name(sc->hw);
1066 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1067 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1068 ret = ath_register_led(sc, &sc->tx_led, trigger);
1069 sc->tx_led.led_type = ATH_LED_TX;
1070 if (ret)
1071 goto fail;
1072
1073 trigger = ieee80211_get_rx_led_name(sc->hw);
1074 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1075 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1076 ret = ath_register_led(sc, &sc->rx_led, trigger);
1077 sc->rx_led.led_type = ATH_LED_RX;
1078 if (ret)
1079 goto fail;
1080
1081 return;
1082
1083 fail:
1084 ath_deinit_leds(sc);
1085 }
1086
1087 void ath_radio_enable(struct ath_softc *sc)
1088 {
1089 struct ath_hw *ah = sc->sc_ah;
1090 struct ieee80211_channel *channel = sc->hw->conf.channel;
1091 int r;
1092
1093 ath9k_ps_wakeup(sc);
1094 spin_lock_bh(&sc->sc_resetlock);
1095
1096 r = ath9k_hw_reset(ah, ah->curchan, false);
1097
1098 if (r) {
1099 DPRINTF(sc, ATH_DBG_FATAL,
1100 "Unable to reset channel %u (%uMhz) ",
1101 "reset status %u\n",
1102 channel->center_freq, r);
1103 }
1104 spin_unlock_bh(&sc->sc_resetlock);
1105
1106 ath_update_txpow(sc);
1107 if (ath_startrecv(sc) != 0) {
1108 DPRINTF(sc, ATH_DBG_FATAL,
1109 "Unable to restart recv logic\n");
1110 return;
1111 }
1112
1113 if (sc->sc_flags & SC_OP_BEACONS)
1114 ath_beacon_config(sc, NULL); /* restart beacons */
1115
1116 /* Re-Enable interrupts */
1117 ath9k_hw_set_interrupts(ah, sc->imask);
1118
1119 /* Enable LED */
1120 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1121 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1122 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1123
1124 ieee80211_wake_queues(sc->hw);
1125 ath9k_ps_restore(sc);
1126 }
1127
1128 void ath_radio_disable(struct ath_softc *sc)
1129 {
1130 struct ath_hw *ah = sc->sc_ah;
1131 struct ieee80211_channel *channel = sc->hw->conf.channel;
1132 int r;
1133
1134 ath9k_ps_wakeup(sc);
1135 ieee80211_stop_queues(sc->hw);
1136
1137 /* Disable LED */
1138 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1139 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1140
1141 /* Disable interrupts */
1142 ath9k_hw_set_interrupts(ah, 0);
1143
1144 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1145 ath_stoprecv(sc); /* turn off frame recv */
1146 ath_flushrecv(sc); /* flush recv queue */
1147
1148 spin_lock_bh(&sc->sc_resetlock);
1149 r = ath9k_hw_reset(ah, ah->curchan, false);
1150 if (r) {
1151 DPRINTF(sc, ATH_DBG_FATAL,
1152 "Unable to reset channel %u (%uMhz) "
1153 "reset status %u\n",
1154 channel->center_freq, r);
1155 }
1156 spin_unlock_bh(&sc->sc_resetlock);
1157
1158 ath9k_hw_phy_disable(ah);
1159 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1160 ath9k_ps_restore(sc);
1161 }
1162
1163 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1164
1165 /*******************/
1166 /* Rfkill */
1167 /*******************/
1168
1169 static bool ath_is_rfkill_set(struct ath_softc *sc)
1170 {
1171 struct ath_hw *ah = sc->sc_ah;
1172
1173 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1174 ah->rfkill_polarity;
1175 }
1176
1177 /* h/w rfkill poll function */
1178 static void ath_rfkill_poll(struct work_struct *work)
1179 {
1180 struct ath_softc *sc = container_of(work, struct ath_softc,
1181 rf_kill.rfkill_poll.work);
1182 bool radio_on;
1183
1184 if (sc->sc_flags & SC_OP_INVALID)
1185 return;
1186
1187 radio_on = !ath_is_rfkill_set(sc);
1188
1189 /*
1190 * enable/disable radio only when there is a
1191 * state change in RF switch
1192 */
1193 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1194 enum rfkill_state state;
1195
1196 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1197 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1198 : RFKILL_STATE_HARD_BLOCKED;
1199 } else if (radio_on) {
1200 ath_radio_enable(sc);
1201 state = RFKILL_STATE_UNBLOCKED;
1202 } else {
1203 ath_radio_disable(sc);
1204 state = RFKILL_STATE_HARD_BLOCKED;
1205 }
1206
1207 if (state == RFKILL_STATE_HARD_BLOCKED)
1208 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1209 else
1210 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1211
1212 rfkill_force_state(sc->rf_kill.rfkill, state);
1213 }
1214
1215 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1216 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1217 }
1218
1219 /* s/w rfkill handler */
1220 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1221 {
1222 struct ath_softc *sc = data;
1223
1224 switch (state) {
1225 case RFKILL_STATE_SOFT_BLOCKED:
1226 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1227 SC_OP_RFKILL_SW_BLOCKED)))
1228 ath_radio_disable(sc);
1229 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1230 return 0;
1231 case RFKILL_STATE_UNBLOCKED:
1232 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1233 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1234 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1235 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1236 "radio as it is disabled by h/w\n");
1237 return -EPERM;
1238 }
1239 ath_radio_enable(sc);
1240 }
1241 return 0;
1242 default:
1243 return -EINVAL;
1244 }
1245 }
1246
1247 /* Init s/w rfkill */
1248 static int ath_init_sw_rfkill(struct ath_softc *sc)
1249 {
1250 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1251 RFKILL_TYPE_WLAN);
1252 if (!sc->rf_kill.rfkill) {
1253 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1254 return -ENOMEM;
1255 }
1256
1257 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1258 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1259 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1260 sc->rf_kill.rfkill->data = sc;
1261 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1262 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1263 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1264
1265 return 0;
1266 }
1267
1268 /* Deinitialize rfkill */
1269 static void ath_deinit_rfkill(struct ath_softc *sc)
1270 {
1271 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1272 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1273
1274 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1275 rfkill_unregister(sc->rf_kill.rfkill);
1276 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1277 sc->rf_kill.rfkill = NULL;
1278 }
1279 }
1280
1281 static int ath_start_rfkill_poll(struct ath_softc *sc)
1282 {
1283 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1284 queue_delayed_work(sc->hw->workqueue,
1285 &sc->rf_kill.rfkill_poll, 0);
1286
1287 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1288 if (rfkill_register(sc->rf_kill.rfkill)) {
1289 DPRINTF(sc, ATH_DBG_FATAL,
1290 "Unable to register rfkill\n");
1291 rfkill_free(sc->rf_kill.rfkill);
1292
1293 /* Deinitialize the device */
1294 ath_cleanup(sc);
1295 return -EIO;
1296 } else {
1297 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1298 }
1299 }
1300
1301 return 0;
1302 }
1303 #endif /* CONFIG_RFKILL */
1304
1305 void ath_cleanup(struct ath_softc *sc)
1306 {
1307 ath_detach(sc);
1308 free_irq(sc->irq, sc);
1309 ath_bus_cleanup(sc);
1310 kfree(sc->sec_wiphy);
1311 ieee80211_free_hw(sc->hw);
1312 }
1313
1314 void ath_detach(struct ath_softc *sc)
1315 {
1316 struct ieee80211_hw *hw = sc->hw;
1317 int i = 0;
1318
1319 ath9k_ps_wakeup(sc);
1320
1321 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1322
1323 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1324 ath_deinit_rfkill(sc);
1325 #endif
1326 ath_deinit_leds(sc);
1327 cancel_work_sync(&sc->chan_work);
1328 cancel_delayed_work_sync(&sc->wiphy_work);
1329
1330 for (i = 0; i < sc->num_sec_wiphy; i++) {
1331 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1332 if (aphy == NULL)
1333 continue;
1334 sc->sec_wiphy[i] = NULL;
1335 ieee80211_unregister_hw(aphy->hw);
1336 ieee80211_free_hw(aphy->hw);
1337 }
1338 ieee80211_unregister_hw(hw);
1339 ath_rx_cleanup(sc);
1340 ath_tx_cleanup(sc);
1341
1342 tasklet_kill(&sc->intr_tq);
1343 tasklet_kill(&sc->bcon_tasklet);
1344
1345 if (!(sc->sc_flags & SC_OP_INVALID))
1346 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1347
1348 /* cleanup tx queues */
1349 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1350 if (ATH_TXQ_SETUP(sc, i))
1351 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1352
1353 ath9k_hw_detach(sc->sc_ah);
1354 ath9k_exit_debug(sc);
1355 ath9k_ps_restore(sc);
1356 }
1357
1358 static int ath_init(u16 devid, struct ath_softc *sc)
1359 {
1360 struct ath_hw *ah = NULL;
1361 int status;
1362 int error = 0, i;
1363 int csz = 0;
1364
1365 /* XXX: hardware will not be ready until ath_open() being called */
1366 sc->sc_flags |= SC_OP_INVALID;
1367
1368 if (ath9k_init_debug(sc) < 0)
1369 printk(KERN_ERR "Unable to create debugfs files\n");
1370
1371 spin_lock_init(&sc->wiphy_lock);
1372 spin_lock_init(&sc->sc_resetlock);
1373 spin_lock_init(&sc->sc_serial_rw);
1374 mutex_init(&sc->mutex);
1375 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1376 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1377 (unsigned long)sc);
1378
1379 /*
1380 * Cache line size is used to size and align various
1381 * structures used to communicate with the hardware.
1382 */
1383 ath_read_cachesize(sc, &csz);
1384 /* XXX assert csz is non-zero */
1385 sc->cachelsz = csz << 2; /* convert to bytes */
1386
1387 ah = ath9k_hw_attach(devid, sc, &status);
1388 if (ah == NULL) {
1389 DPRINTF(sc, ATH_DBG_FATAL,
1390 "Unable to attach hardware; HAL status %d\n", status);
1391 error = -ENXIO;
1392 goto bad;
1393 }
1394 sc->sc_ah = ah;
1395
1396 /* Get the hardware key cache size. */
1397 sc->keymax = ah->caps.keycache_size;
1398 if (sc->keymax > ATH_KEYMAX) {
1399 DPRINTF(sc, ATH_DBG_KEYCACHE,
1400 "Warning, using only %u entries in %u key cache\n",
1401 ATH_KEYMAX, sc->keymax);
1402 sc->keymax = ATH_KEYMAX;
1403 }
1404
1405 /*
1406 * Reset the key cache since some parts do not
1407 * reset the contents on initial power up.
1408 */
1409 for (i = 0; i < sc->keymax; i++)
1410 ath9k_hw_keyreset(ah, (u16) i);
1411
1412 if (ath9k_regd_init(sc->sc_ah))
1413 goto bad;
1414
1415 /* default to MONITOR mode */
1416 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1417
1418 /* Setup rate tables */
1419
1420 ath_rate_attach(sc);
1421 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1422 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1423
1424 /*
1425 * Allocate hardware transmit queues: one queue for
1426 * beacon frames and one data queue for each QoS
1427 * priority. Note that the hal handles reseting
1428 * these queues at the needed time.
1429 */
1430 sc->beacon.beaconq = ath_beaconq_setup(ah);
1431 if (sc->beacon.beaconq == -1) {
1432 DPRINTF(sc, ATH_DBG_FATAL,
1433 "Unable to setup a beacon xmit queue\n");
1434 error = -EIO;
1435 goto bad2;
1436 }
1437 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1438 if (sc->beacon.cabq == NULL) {
1439 DPRINTF(sc, ATH_DBG_FATAL,
1440 "Unable to setup CAB xmit queue\n");
1441 error = -EIO;
1442 goto bad2;
1443 }
1444
1445 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1446 ath_cabq_update(sc);
1447
1448 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1449 sc->tx.hwq_map[i] = -1;
1450
1451 /* Setup data queues */
1452 /* NB: ensure BK queue is the lowest priority h/w queue */
1453 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1454 DPRINTF(sc, ATH_DBG_FATAL,
1455 "Unable to setup xmit queue for BK traffic\n");
1456 error = -EIO;
1457 goto bad2;
1458 }
1459
1460 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1461 DPRINTF(sc, ATH_DBG_FATAL,
1462 "Unable to setup xmit queue for BE traffic\n");
1463 error = -EIO;
1464 goto bad2;
1465 }
1466 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1467 DPRINTF(sc, ATH_DBG_FATAL,
1468 "Unable to setup xmit queue for VI traffic\n");
1469 error = -EIO;
1470 goto bad2;
1471 }
1472 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1473 DPRINTF(sc, ATH_DBG_FATAL,
1474 "Unable to setup xmit queue for VO traffic\n");
1475 error = -EIO;
1476 goto bad2;
1477 }
1478
1479 /* Initializes the noise floor to a reasonable default value.
1480 * Later on this will be updated during ANI processing. */
1481
1482 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1483 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1484
1485 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1486 ATH9K_CIPHER_TKIP, NULL)) {
1487 /*
1488 * Whether we should enable h/w TKIP MIC.
1489 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1490 * report WMM capable, so it's always safe to turn on
1491 * TKIP MIC in this case.
1492 */
1493 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1494 0, 1, NULL);
1495 }
1496
1497 /*
1498 * Check whether the separate key cache entries
1499 * are required to handle both tx+rx MIC keys.
1500 * With split mic keys the number of stations is limited
1501 * to 27 otherwise 59.
1502 */
1503 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1504 ATH9K_CIPHER_TKIP, NULL)
1505 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1506 ATH9K_CIPHER_MIC, NULL)
1507 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1508 0, NULL))
1509 sc->splitmic = 1;
1510
1511 /* turn on mcast key search if possible */
1512 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1513 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1514 1, NULL);
1515
1516 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1517
1518 /* 11n Capabilities */
1519 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1520 sc->sc_flags |= SC_OP_TXAGGR;
1521 sc->sc_flags |= SC_OP_RXAGGR;
1522 }
1523
1524 sc->tx_chainmask = ah->caps.tx_chainmask;
1525 sc->rx_chainmask = ah->caps.rx_chainmask;
1526
1527 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1528 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1529
1530 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1531 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1532
1533 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1534
1535 /* initialize beacon slots */
1536 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1537 sc->beacon.bslot[i] = NULL;
1538 sc->beacon.bslot_aphy[i] = NULL;
1539 }
1540
1541 /* save MISC configurations */
1542 sc->config.swBeaconProcess = 1;
1543
1544 /* setup channels and rates */
1545
1546 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1547 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1548 sc->rates[IEEE80211_BAND_2GHZ];
1549 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1550 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1551 ARRAY_SIZE(ath9k_2ghz_chantable);
1552
1553 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1554 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1555 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1556 sc->rates[IEEE80211_BAND_5GHZ];
1557 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1558 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1559 ARRAY_SIZE(ath9k_5ghz_chantable);
1560 }
1561
1562 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1563 ath9k_hw_btcoex_enable(sc->sc_ah);
1564
1565 return 0;
1566 bad2:
1567 /* cleanup tx queues */
1568 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1569 if (ATH_TXQ_SETUP(sc, i))
1570 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1571 bad:
1572 if (ah)
1573 ath9k_hw_detach(ah);
1574 ath9k_exit_debug(sc);
1575
1576 return error;
1577 }
1578
1579 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1580 {
1581 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1582 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1583 IEEE80211_HW_SIGNAL_DBM |
1584 IEEE80211_HW_AMPDU_AGGREGATION |
1585 IEEE80211_HW_SUPPORTS_PS |
1586 IEEE80211_HW_PS_NULLFUNC_STACK |
1587 IEEE80211_HW_SPECTRUM_MGMT;
1588
1589 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1590 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1591
1592 hw->wiphy->interface_modes =
1593 BIT(NL80211_IFTYPE_AP) |
1594 BIT(NL80211_IFTYPE_STATION) |
1595 BIT(NL80211_IFTYPE_ADHOC);
1596
1597 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1598 hw->wiphy->strict_regulatory = true;
1599
1600 hw->queues = 4;
1601 hw->max_rates = 4;
1602 hw->channel_change_time = 5000;
1603 hw->max_listen_interval = 10;
1604 hw->max_rate_tries = ATH_11N_TXMAXTRY;
1605 hw->sta_data_size = sizeof(struct ath_node);
1606 hw->vif_data_size = sizeof(struct ath_vif);
1607
1608 hw->rate_control_algorithm = "ath9k_rate_control";
1609
1610 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1611 &sc->sbands[IEEE80211_BAND_2GHZ];
1612 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1613 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1614 &sc->sbands[IEEE80211_BAND_5GHZ];
1615 }
1616
1617 int ath_attach(u16 devid, struct ath_softc *sc)
1618 {
1619 struct ieee80211_hw *hw = sc->hw;
1620 const struct ieee80211_regdomain *regd;
1621 int error = 0, i;
1622
1623 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1624
1625 error = ath_init(devid, sc);
1626 if (error != 0)
1627 return error;
1628
1629 /* get mac address from hardware and set in mac80211 */
1630
1631 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1632
1633 ath_set_hw_capab(sc, hw);
1634
1635 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1636 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1637 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1638 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1639 }
1640
1641 /* initialize tx/rx engine */
1642 error = ath_tx_init(sc, ATH_TXBUF);
1643 if (error != 0)
1644 goto error_attach;
1645
1646 error = ath_rx_init(sc, ATH_RXBUF);
1647 if (error != 0)
1648 goto error_attach;
1649
1650 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1651 /* Initialze h/w Rfkill */
1652 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1653 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1654
1655 /* Initialize s/w rfkill */
1656 error = ath_init_sw_rfkill(sc);
1657 if (error)
1658 goto error_attach;
1659 #endif
1660
1661 if (ath9k_is_world_regd(sc->sc_ah)) {
1662 /* Anything applied here (prior to wiphy registration) gets
1663 * saved on the wiphy orig_* parameters */
1664 regd = ath9k_world_regdomain(sc->sc_ah);
1665 hw->wiphy->custom_regulatory = true;
1666 hw->wiphy->strict_regulatory = false;
1667 } else {
1668 /* This gets applied in the case of the absense of CRDA,
1669 * it's our own custom world regulatory domain, similar to
1670 * cfg80211's but we enable passive scanning */
1671 regd = ath9k_default_world_regdomain();
1672 }
1673 wiphy_apply_custom_regulatory(hw->wiphy, regd);
1674 ath9k_reg_apply_radar_flags(hw->wiphy);
1675 ath9k_reg_apply_world_flags(hw->wiphy, NL80211_REGDOM_SET_BY_DRIVER);
1676
1677 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1678 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1679 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1680
1681 error = ieee80211_register_hw(hw);
1682
1683 if (!ath9k_is_world_regd(sc->sc_ah)) {
1684 error = regulatory_hint(hw->wiphy,
1685 sc->sc_ah->regulatory.alpha2);
1686 if (error)
1687 goto error_attach;
1688 }
1689
1690 /* Initialize LED control */
1691 ath_init_leds(sc);
1692
1693
1694 return 0;
1695
1696 error_attach:
1697 /* cleanup tx queues */
1698 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1699 if (ATH_TXQ_SETUP(sc, i))
1700 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1701
1702 ath9k_hw_detach(sc->sc_ah);
1703 ath9k_exit_debug(sc);
1704
1705 return error;
1706 }
1707
1708 int ath_reset(struct ath_softc *sc, bool retry_tx)
1709 {
1710 struct ath_hw *ah = sc->sc_ah;
1711 struct ieee80211_hw *hw = sc->hw;
1712 int r;
1713
1714 ath9k_hw_set_interrupts(ah, 0);
1715 ath_drain_all_txq(sc, retry_tx);
1716 ath_stoprecv(sc);
1717 ath_flushrecv(sc);
1718
1719 spin_lock_bh(&sc->sc_resetlock);
1720 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1721 if (r)
1722 DPRINTF(sc, ATH_DBG_FATAL,
1723 "Unable to reset hardware; reset status %u\n", r);
1724 spin_unlock_bh(&sc->sc_resetlock);
1725
1726 if (ath_startrecv(sc) != 0)
1727 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1728
1729 /*
1730 * We may be doing a reset in response to a request
1731 * that changes the channel so update any state that
1732 * might change as a result.
1733 */
1734 ath_cache_conf_rate(sc, &hw->conf);
1735
1736 ath_update_txpow(sc);
1737
1738 if (sc->sc_flags & SC_OP_BEACONS)
1739 ath_beacon_config(sc, NULL); /* restart beacons */
1740
1741 ath9k_hw_set_interrupts(ah, sc->imask);
1742
1743 if (retry_tx) {
1744 int i;
1745 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1746 if (ATH_TXQ_SETUP(sc, i)) {
1747 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1748 ath_txq_schedule(sc, &sc->tx.txq[i]);
1749 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1750 }
1751 }
1752 }
1753
1754 return r;
1755 }
1756
1757 /*
1758 * This function will allocate both the DMA descriptor structure, and the
1759 * buffers it contains. These are used to contain the descriptors used
1760 * by the system.
1761 */
1762 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1763 struct list_head *head, const char *name,
1764 int nbuf, int ndesc)
1765 {
1766 #define DS2PHYS(_dd, _ds) \
1767 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1768 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1769 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1770
1771 struct ath_desc *ds;
1772 struct ath_buf *bf;
1773 int i, bsize, error;
1774
1775 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1776 name, nbuf, ndesc);
1777
1778 INIT_LIST_HEAD(head);
1779 /* ath_desc must be a multiple of DWORDs */
1780 if ((sizeof(struct ath_desc) % 4) != 0) {
1781 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1782 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1783 error = -ENOMEM;
1784 goto fail;
1785 }
1786
1787 dd->dd_name = name;
1788 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1789
1790 /*
1791 * Need additional DMA memory because we can't use
1792 * descriptors that cross the 4K page boundary. Assume
1793 * one skipped descriptor per 4K page.
1794 */
1795 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1796 u32 ndesc_skipped =
1797 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1798 u32 dma_len;
1799
1800 while (ndesc_skipped) {
1801 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1802 dd->dd_desc_len += dma_len;
1803
1804 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1805 };
1806 }
1807
1808 /* allocate descriptors */
1809 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1810 &dd->dd_desc_paddr, GFP_KERNEL);
1811 if (dd->dd_desc == NULL) {
1812 error = -ENOMEM;
1813 goto fail;
1814 }
1815 ds = dd->dd_desc;
1816 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1817 dd->dd_name, ds, (u32) dd->dd_desc_len,
1818 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1819
1820 /* allocate buffers */
1821 bsize = sizeof(struct ath_buf) * nbuf;
1822 bf = kzalloc(bsize, GFP_KERNEL);
1823 if (bf == NULL) {
1824 error = -ENOMEM;
1825 goto fail2;
1826 }
1827 dd->dd_bufptr = bf;
1828
1829 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1830 bf->bf_desc = ds;
1831 bf->bf_daddr = DS2PHYS(dd, ds);
1832
1833 if (!(sc->sc_ah->caps.hw_caps &
1834 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1835 /*
1836 * Skip descriptor addresses which can cause 4KB
1837 * boundary crossing (addr + length) with a 32 dword
1838 * descriptor fetch.
1839 */
1840 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1841 ASSERT((caddr_t) bf->bf_desc <
1842 ((caddr_t) dd->dd_desc +
1843 dd->dd_desc_len));
1844
1845 ds += ndesc;
1846 bf->bf_desc = ds;
1847 bf->bf_daddr = DS2PHYS(dd, ds);
1848 }
1849 }
1850 list_add_tail(&bf->list, head);
1851 }
1852 return 0;
1853 fail2:
1854 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1855 dd->dd_desc_paddr);
1856 fail:
1857 memset(dd, 0, sizeof(*dd));
1858 return error;
1859 #undef ATH_DESC_4KB_BOUND_CHECK
1860 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1861 #undef DS2PHYS
1862 }
1863
1864 void ath_descdma_cleanup(struct ath_softc *sc,
1865 struct ath_descdma *dd,
1866 struct list_head *head)
1867 {
1868 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1869 dd->dd_desc_paddr);
1870
1871 INIT_LIST_HEAD(head);
1872 kfree(dd->dd_bufptr);
1873 memset(dd, 0, sizeof(*dd));
1874 }
1875
1876 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1877 {
1878 int qnum;
1879
1880 switch (queue) {
1881 case 0:
1882 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1883 break;
1884 case 1:
1885 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1886 break;
1887 case 2:
1888 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1889 break;
1890 case 3:
1891 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1892 break;
1893 default:
1894 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1895 break;
1896 }
1897
1898 return qnum;
1899 }
1900
1901 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1902 {
1903 int qnum;
1904
1905 switch (queue) {
1906 case ATH9K_WME_AC_VO:
1907 qnum = 0;
1908 break;
1909 case ATH9K_WME_AC_VI:
1910 qnum = 1;
1911 break;
1912 case ATH9K_WME_AC_BE:
1913 qnum = 2;
1914 break;
1915 case ATH9K_WME_AC_BK:
1916 qnum = 3;
1917 break;
1918 default:
1919 qnum = -1;
1920 break;
1921 }
1922
1923 return qnum;
1924 }
1925
1926 /* XXX: Remove me once we don't depend on ath9k_channel for all
1927 * this redundant data */
1928 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1929 struct ath9k_channel *ichan)
1930 {
1931 struct ieee80211_channel *chan = hw->conf.channel;
1932 struct ieee80211_conf *conf = &hw->conf;
1933
1934 ichan->channel = chan->center_freq;
1935 ichan->chan = chan;
1936
1937 if (chan->band == IEEE80211_BAND_2GHZ) {
1938 ichan->chanmode = CHANNEL_G;
1939 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1940 } else {
1941 ichan->chanmode = CHANNEL_A;
1942 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1943 }
1944
1945 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1946
1947 if (conf_is_ht(conf)) {
1948 if (conf_is_ht40(conf))
1949 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1950
1951 ichan->chanmode = ath_get_extchanmode(sc, chan,
1952 conf->channel_type);
1953 }
1954 }
1955
1956 /**********************/
1957 /* mac80211 callbacks */
1958 /**********************/
1959
1960 static int ath9k_start(struct ieee80211_hw *hw)
1961 {
1962 struct ath_wiphy *aphy = hw->priv;
1963 struct ath_softc *sc = aphy->sc;
1964 struct ieee80211_channel *curchan = hw->conf.channel;
1965 struct ath9k_channel *init_channel;
1966 int r, pos;
1967
1968 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1969 "initial channel: %d MHz\n", curchan->center_freq);
1970
1971 mutex_lock(&sc->mutex);
1972
1973 if (ath9k_wiphy_started(sc)) {
1974 if (sc->chan_idx == curchan->hw_value) {
1975 /*
1976 * Already on the operational channel, the new wiphy
1977 * can be marked active.
1978 */
1979 aphy->state = ATH_WIPHY_ACTIVE;
1980 ieee80211_wake_queues(hw);
1981 } else {
1982 /*
1983 * Another wiphy is on another channel, start the new
1984 * wiphy in paused state.
1985 */
1986 aphy->state = ATH_WIPHY_PAUSED;
1987 ieee80211_stop_queues(hw);
1988 }
1989 mutex_unlock(&sc->mutex);
1990 return 0;
1991 }
1992 aphy->state = ATH_WIPHY_ACTIVE;
1993
1994 /* setup initial channel */
1995
1996 pos = curchan->hw_value;
1997
1998 sc->chan_idx = pos;
1999 init_channel = &sc->sc_ah->channels[pos];
2000 ath9k_update_ichannel(sc, hw, init_channel);
2001
2002 /* Reset SERDES registers */
2003 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
2004
2005 /*
2006 * The basic interface to setting the hardware in a good
2007 * state is ``reset''. On return the hardware is known to
2008 * be powered up and with interrupts disabled. This must
2009 * be followed by initialization of the appropriate bits
2010 * and then setup of the interrupt mask.
2011 */
2012 spin_lock_bh(&sc->sc_resetlock);
2013 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2014 if (r) {
2015 DPRINTF(sc, ATH_DBG_FATAL,
2016 "Unable to reset hardware; reset status %u "
2017 "(freq %u MHz)\n", r,
2018 curchan->center_freq);
2019 spin_unlock_bh(&sc->sc_resetlock);
2020 goto mutex_unlock;
2021 }
2022 spin_unlock_bh(&sc->sc_resetlock);
2023
2024 /*
2025 * This is needed only to setup initial state
2026 * but it's best done after a reset.
2027 */
2028 ath_update_txpow(sc);
2029
2030 /*
2031 * Setup the hardware after reset:
2032 * The receive engine is set going.
2033 * Frame transmit is handled entirely
2034 * in the frame output path; there's nothing to do
2035 * here except setup the interrupt mask.
2036 */
2037 if (ath_startrecv(sc) != 0) {
2038 DPRINTF(sc, ATH_DBG_FATAL,
2039 "Unable to start recv logic\n");
2040 r = -EIO;
2041 goto mutex_unlock;
2042 }
2043
2044 /* Setup our intr mask. */
2045 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2046 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2047 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2048
2049 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2050 sc->imask |= ATH9K_INT_GTT;
2051
2052 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2053 sc->imask |= ATH9K_INT_CST;
2054
2055 ath_cache_conf_rate(sc, &hw->conf);
2056
2057 sc->sc_flags &= ~SC_OP_INVALID;
2058
2059 /* Disable BMISS interrupt when we're not associated */
2060 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2061 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2062
2063 ieee80211_wake_queues(hw);
2064
2065 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2066 r = ath_start_rfkill_poll(sc);
2067 #endif
2068
2069 mutex_unlock:
2070 mutex_unlock(&sc->mutex);
2071
2072 return r;
2073 }
2074
2075 static int ath9k_tx(struct ieee80211_hw *hw,
2076 struct sk_buff *skb)
2077 {
2078 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2079 struct ath_wiphy *aphy = hw->priv;
2080 struct ath_softc *sc = aphy->sc;
2081 struct ath_tx_control txctl;
2082 int hdrlen, padsize;
2083
2084 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2085 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2086 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2087 goto exit;
2088 }
2089
2090 memset(&txctl, 0, sizeof(struct ath_tx_control));
2091
2092 /*
2093 * As a temporary workaround, assign seq# here; this will likely need
2094 * to be cleaned up to work better with Beacon transmission and virtual
2095 * BSSes.
2096 */
2097 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2098 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2099 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2100 sc->tx.seq_no += 0x10;
2101 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2102 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2103 }
2104
2105 /* Add the padding after the header if this is not already done */
2106 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2107 if (hdrlen & 3) {
2108 padsize = hdrlen % 4;
2109 if (skb_headroom(skb) < padsize)
2110 return -1;
2111 skb_push(skb, padsize);
2112 memmove(skb->data, skb->data + padsize, hdrlen);
2113 }
2114
2115 /* Check if a tx queue is available */
2116
2117 txctl.txq = ath_test_get_txq(sc, skb);
2118 if (!txctl.txq)
2119 goto exit;
2120
2121 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2122
2123 if (ath_tx_start(hw, skb, &txctl) != 0) {
2124 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2125 goto exit;
2126 }
2127
2128 return 0;
2129 exit:
2130 dev_kfree_skb_any(skb);
2131 return 0;
2132 }
2133
2134 static void ath9k_stop(struct ieee80211_hw *hw)
2135 {
2136 struct ath_wiphy *aphy = hw->priv;
2137 struct ath_softc *sc = aphy->sc;
2138
2139 aphy->state = ATH_WIPHY_INACTIVE;
2140
2141 if (sc->sc_flags & SC_OP_INVALID) {
2142 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2143 return;
2144 }
2145
2146 mutex_lock(&sc->mutex);
2147
2148 ieee80211_stop_queues(hw);
2149
2150 if (ath9k_wiphy_started(sc)) {
2151 mutex_unlock(&sc->mutex);
2152 return; /* another wiphy still in use */
2153 }
2154
2155 /* make sure h/w will not generate any interrupt
2156 * before setting the invalid flag. */
2157 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2158
2159 if (!(sc->sc_flags & SC_OP_INVALID)) {
2160 ath_drain_all_txq(sc, false);
2161 ath_stoprecv(sc);
2162 ath9k_hw_phy_disable(sc->sc_ah);
2163 } else
2164 sc->rx.rxlink = NULL;
2165
2166 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2167 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2168 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2169 #endif
2170 /* disable HAL and put h/w to sleep */
2171 ath9k_hw_disable(sc->sc_ah);
2172 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2173
2174 sc->sc_flags |= SC_OP_INVALID;
2175
2176 mutex_unlock(&sc->mutex);
2177
2178 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2179 }
2180
2181 static int ath9k_add_interface(struct ieee80211_hw *hw,
2182 struct ieee80211_if_init_conf *conf)
2183 {
2184 struct ath_wiphy *aphy = hw->priv;
2185 struct ath_softc *sc = aphy->sc;
2186 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2187 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2188 int ret = 0;
2189
2190 mutex_lock(&sc->mutex);
2191
2192 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2193 sc->nvifs > 0) {
2194 ret = -ENOBUFS;
2195 goto out;
2196 }
2197
2198 switch (conf->type) {
2199 case NL80211_IFTYPE_STATION:
2200 ic_opmode = NL80211_IFTYPE_STATION;
2201 break;
2202 case NL80211_IFTYPE_ADHOC:
2203 if (sc->nbcnvifs >= ATH_BCBUF) {
2204 ret = -ENOBUFS;
2205 goto out;
2206 }
2207 ic_opmode = NL80211_IFTYPE_ADHOC;
2208 break;
2209 case NL80211_IFTYPE_AP:
2210 if (sc->nbcnvifs >= ATH_BCBUF) {
2211 ret = -ENOBUFS;
2212 goto out;
2213 }
2214 ic_opmode = NL80211_IFTYPE_AP;
2215 break;
2216 default:
2217 DPRINTF(sc, ATH_DBG_FATAL,
2218 "Interface type %d not yet supported\n", conf->type);
2219 ret = -EOPNOTSUPP;
2220 goto out;
2221 }
2222
2223 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2224
2225 /* Set the VIF opmode */
2226 avp->av_opmode = ic_opmode;
2227 avp->av_bslot = -1;
2228
2229 sc->nvifs++;
2230
2231 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2232 ath9k_set_bssid_mask(hw);
2233
2234 if (sc->nvifs > 1)
2235 goto out; /* skip global settings for secondary vif */
2236
2237 if (ic_opmode == NL80211_IFTYPE_AP) {
2238 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2239 sc->sc_flags |= SC_OP_TSF_RESET;
2240 }
2241
2242 /* Set the device opmode */
2243 sc->sc_ah->opmode = ic_opmode;
2244
2245 /*
2246 * Enable MIB interrupts when there are hardware phy counters.
2247 * Note we only do this (at the moment) for station mode.
2248 */
2249 if ((conf->type == NL80211_IFTYPE_STATION) ||
2250 (conf->type == NL80211_IFTYPE_ADHOC)) {
2251 if (ath9k_hw_phycounters(sc->sc_ah))
2252 sc->imask |= ATH9K_INT_MIB;
2253 sc->imask |= ATH9K_INT_TSFOOR;
2254 }
2255
2256 /*
2257 * Some hardware processes the TIM IE and fires an
2258 * interrupt when the TIM bit is set. For hardware
2259 * that does, if not overridden by configuration,
2260 * enable the TIM interrupt when operating as station.
2261 */
2262 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2263 (conf->type == NL80211_IFTYPE_STATION) &&
2264 !sc->config.swBeaconProcess)
2265 sc->imask |= ATH9K_INT_TIM;
2266
2267 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2268
2269 if (conf->type == NL80211_IFTYPE_AP) {
2270 /* TODO: is this a suitable place to start ANI for AP mode? */
2271 /* Start ANI */
2272 mod_timer(&sc->ani.timer,
2273 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2274 }
2275
2276 out:
2277 mutex_unlock(&sc->mutex);
2278 return ret;
2279 }
2280
2281 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2282 struct ieee80211_if_init_conf *conf)
2283 {
2284 struct ath_wiphy *aphy = hw->priv;
2285 struct ath_softc *sc = aphy->sc;
2286 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2287 int i;
2288
2289 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2290
2291 mutex_lock(&sc->mutex);
2292
2293 /* Stop ANI */
2294 del_timer_sync(&sc->ani.timer);
2295
2296 /* Reclaim beacon resources */
2297 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2298 sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
2299 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2300 ath_beacon_return(sc, avp);
2301 }
2302
2303 sc->sc_flags &= ~SC_OP_BEACONS;
2304
2305 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2306 if (sc->beacon.bslot[i] == conf->vif) {
2307 printk(KERN_DEBUG "%s: vif had allocated beacon "
2308 "slot\n", __func__);
2309 sc->beacon.bslot[i] = NULL;
2310 sc->beacon.bslot_aphy[i] = NULL;
2311 }
2312 }
2313
2314 sc->nvifs--;
2315
2316 mutex_unlock(&sc->mutex);
2317 }
2318
2319 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2320 {
2321 struct ath_wiphy *aphy = hw->priv;
2322 struct ath_softc *sc = aphy->sc;
2323 struct ieee80211_conf *conf = &hw->conf;
2324
2325 mutex_lock(&sc->mutex);
2326
2327 if (changed & IEEE80211_CONF_CHANGE_PS) {
2328 if (conf->flags & IEEE80211_CONF_PS) {
2329 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2330 sc->imask |= ATH9K_INT_TIM_TIMER;
2331 ath9k_hw_set_interrupts(sc->sc_ah,
2332 sc->imask);
2333 }
2334 ath9k_hw_setrxabort(sc->sc_ah, 1);
2335 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2336 } else {
2337 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2338 ath9k_hw_setrxabort(sc->sc_ah, 0);
2339 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2340 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2341 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2342 ath9k_hw_set_interrupts(sc->sc_ah,
2343 sc->imask);
2344 }
2345 }
2346 }
2347
2348 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2349 struct ieee80211_channel *curchan = hw->conf.channel;
2350 int pos = curchan->hw_value;
2351
2352 aphy->chan_idx = pos;
2353 aphy->chan_is_ht = conf_is_ht(conf);
2354
2355 if (aphy->state == ATH_WIPHY_SCAN ||
2356 aphy->state == ATH_WIPHY_ACTIVE)
2357 ath9k_wiphy_pause_all_forced(sc, aphy);
2358 else {
2359 /*
2360 * Do not change operational channel based on a paused
2361 * wiphy changes.
2362 */
2363 goto skip_chan_change;
2364 }
2365
2366 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2367 curchan->center_freq);
2368
2369 /* XXX: remove me eventualy */
2370 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2371
2372 ath_update_chainmask(sc, conf_is_ht(conf));
2373
2374 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2375 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2376 mutex_unlock(&sc->mutex);
2377 return -EINVAL;
2378 }
2379 }
2380
2381 skip_chan_change:
2382 if (changed & IEEE80211_CONF_CHANGE_POWER)
2383 sc->config.txpowlimit = 2 * conf->power_level;
2384
2385 /*
2386 * The HW TSF has to be reset when the beacon interval changes.
2387 * We set the flag here, and ath_beacon_config_ap() would take this
2388 * into account when it gets called through the subsequent
2389 * config_interface() call - with IFCC_BEACON in the changed field.
2390 */
2391
2392 if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2393 sc->sc_flags |= SC_OP_TSF_RESET;
2394
2395 mutex_unlock(&sc->mutex);
2396
2397 return 0;
2398 }
2399
2400 static int ath9k_config_interface(struct ieee80211_hw *hw,
2401 struct ieee80211_vif *vif,
2402 struct ieee80211_if_conf *conf)
2403 {
2404 struct ath_wiphy *aphy = hw->priv;
2405 struct ath_softc *sc = aphy->sc;
2406 struct ath_hw *ah = sc->sc_ah;
2407 struct ath_vif *avp = (void *)vif->drv_priv;
2408 u32 rfilt = 0;
2409 int error, i;
2410
2411 mutex_lock(&sc->mutex);
2412
2413 /* TODO: Need to decide which hw opmode to use for multi-interface
2414 * cases */
2415 if (vif->type == NL80211_IFTYPE_AP &&
2416 ah->opmode != NL80211_IFTYPE_AP) {
2417 ah->opmode = NL80211_IFTYPE_STATION;
2418 ath9k_hw_setopmode(ah);
2419 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2420 sc->curaid = 0;
2421 ath9k_hw_write_associd(sc);
2422 /* Request full reset to get hw opmode changed properly */
2423 sc->sc_flags |= SC_OP_FULL_RESET;
2424 }
2425
2426 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2427 !is_zero_ether_addr(conf->bssid)) {
2428 switch (vif->type) {
2429 case NL80211_IFTYPE_STATION:
2430 case NL80211_IFTYPE_ADHOC:
2431 /* Set BSSID */
2432 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2433 memcpy(avp->bssid, conf->bssid, ETH_ALEN);
2434 sc->curaid = 0;
2435 ath9k_hw_write_associd(sc);
2436
2437 /* Set aggregation protection mode parameters */
2438 sc->config.ath_aggr_prot = 0;
2439
2440 DPRINTF(sc, ATH_DBG_CONFIG,
2441 "RX filter 0x%x bssid %pM aid 0x%x\n",
2442 rfilt, sc->curbssid, sc->curaid);
2443
2444 /* need to reconfigure the beacon */
2445 sc->sc_flags &= ~SC_OP_BEACONS ;
2446
2447 break;
2448 default:
2449 break;
2450 }
2451 }
2452
2453 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2454 (vif->type == NL80211_IFTYPE_AP)) {
2455 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2456 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2457 conf->enable_beacon)) {
2458 /*
2459 * Allocate and setup the beacon frame.
2460 *
2461 * Stop any previous beacon DMA. This may be
2462 * necessary, for example, when an ibss merge
2463 * causes reconfiguration; we may be called
2464 * with beacon transmission active.
2465 */
2466 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2467
2468 error = ath_beacon_alloc(aphy, vif);
2469 if (error != 0) {
2470 mutex_unlock(&sc->mutex);
2471 return error;
2472 }
2473
2474 ath_beacon_config(sc, vif);
2475 }
2476 }
2477
2478 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2479 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2480 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2481 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2482 ath9k_hw_keysetmac(sc->sc_ah,
2483 (u16)i,
2484 sc->curbssid);
2485 }
2486
2487 /* Only legacy IBSS for now */
2488 if (vif->type == NL80211_IFTYPE_ADHOC)
2489 ath_update_chainmask(sc, 0);
2490
2491 mutex_unlock(&sc->mutex);
2492
2493 return 0;
2494 }
2495
2496 #define SUPPORTED_FILTERS \
2497 (FIF_PROMISC_IN_BSS | \
2498 FIF_ALLMULTI | \
2499 FIF_CONTROL | \
2500 FIF_OTHER_BSS | \
2501 FIF_BCN_PRBRESP_PROMISC | \
2502 FIF_FCSFAIL)
2503
2504 /* FIXME: sc->sc_full_reset ? */
2505 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2506 unsigned int changed_flags,
2507 unsigned int *total_flags,
2508 int mc_count,
2509 struct dev_mc_list *mclist)
2510 {
2511 struct ath_wiphy *aphy = hw->priv;
2512 struct ath_softc *sc = aphy->sc;
2513 u32 rfilt;
2514
2515 changed_flags &= SUPPORTED_FILTERS;
2516 *total_flags &= SUPPORTED_FILTERS;
2517
2518 sc->rx.rxfilter = *total_flags;
2519 rfilt = ath_calcrxfilter(sc);
2520 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2521
2522 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2523 }
2524
2525 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2526 struct ieee80211_vif *vif,
2527 enum sta_notify_cmd cmd,
2528 struct ieee80211_sta *sta)
2529 {
2530 struct ath_wiphy *aphy = hw->priv;
2531 struct ath_softc *sc = aphy->sc;
2532
2533 switch (cmd) {
2534 case STA_NOTIFY_ADD:
2535 ath_node_attach(sc, sta);
2536 break;
2537 case STA_NOTIFY_REMOVE:
2538 ath_node_detach(sc, sta);
2539 break;
2540 default:
2541 break;
2542 }
2543 }
2544
2545 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2546 const struct ieee80211_tx_queue_params *params)
2547 {
2548 struct ath_wiphy *aphy = hw->priv;
2549 struct ath_softc *sc = aphy->sc;
2550 struct ath9k_tx_queue_info qi;
2551 int ret = 0, qnum;
2552
2553 if (queue >= WME_NUM_AC)
2554 return 0;
2555
2556 mutex_lock(&sc->mutex);
2557
2558 qi.tqi_aifs = params->aifs;
2559 qi.tqi_cwmin = params->cw_min;
2560 qi.tqi_cwmax = params->cw_max;
2561 qi.tqi_burstTime = params->txop;
2562 qnum = ath_get_hal_qnum(queue, sc);
2563
2564 DPRINTF(sc, ATH_DBG_CONFIG,
2565 "Configure tx [queue/halq] [%d/%d], "
2566 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2567 queue, qnum, params->aifs, params->cw_min,
2568 params->cw_max, params->txop);
2569
2570 ret = ath_txq_update(sc, qnum, &qi);
2571 if (ret)
2572 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2573
2574 mutex_unlock(&sc->mutex);
2575
2576 return ret;
2577 }
2578
2579 static int ath9k_set_key(struct ieee80211_hw *hw,
2580 enum set_key_cmd cmd,
2581 struct ieee80211_vif *vif,
2582 struct ieee80211_sta *sta,
2583 struct ieee80211_key_conf *key)
2584 {
2585 struct ath_wiphy *aphy = hw->priv;
2586 struct ath_softc *sc = aphy->sc;
2587 int ret = 0;
2588
2589 if (modparam_nohwcrypt)
2590 return -ENOSPC;
2591
2592 mutex_lock(&sc->mutex);
2593 ath9k_ps_wakeup(sc);
2594 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2595
2596 switch (cmd) {
2597 case SET_KEY:
2598 ret = ath_key_config(sc, vif, sta, key);
2599 if (ret >= 0) {
2600 key->hw_key_idx = ret;
2601 /* push IV and Michael MIC generation to stack */
2602 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2603 if (key->alg == ALG_TKIP)
2604 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2605 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2606 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2607 ret = 0;
2608 }
2609 break;
2610 case DISABLE_KEY:
2611 ath_key_delete(sc, key);
2612 break;
2613 default:
2614 ret = -EINVAL;
2615 }
2616
2617 ath9k_ps_restore(sc);
2618 mutex_unlock(&sc->mutex);
2619
2620 return ret;
2621 }
2622
2623 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2624 struct ieee80211_vif *vif,
2625 struct ieee80211_bss_conf *bss_conf,
2626 u32 changed)
2627 {
2628 struct ath_wiphy *aphy = hw->priv;
2629 struct ath_softc *sc = aphy->sc;
2630
2631 mutex_lock(&sc->mutex);
2632
2633 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2634 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2635 bss_conf->use_short_preamble);
2636 if (bss_conf->use_short_preamble)
2637 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2638 else
2639 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2640 }
2641
2642 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2643 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2644 bss_conf->use_cts_prot);
2645 if (bss_conf->use_cts_prot &&
2646 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2647 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2648 else
2649 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2650 }
2651
2652 if (changed & BSS_CHANGED_ASSOC) {
2653 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2654 bss_conf->assoc);
2655 ath9k_bss_assoc_info(sc, vif, bss_conf);
2656 }
2657
2658 mutex_unlock(&sc->mutex);
2659 }
2660
2661 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2662 {
2663 u64 tsf;
2664 struct ath_wiphy *aphy = hw->priv;
2665 struct ath_softc *sc = aphy->sc;
2666
2667 mutex_lock(&sc->mutex);
2668 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2669 mutex_unlock(&sc->mutex);
2670
2671 return tsf;
2672 }
2673
2674 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2675 {
2676 struct ath_wiphy *aphy = hw->priv;
2677 struct ath_softc *sc = aphy->sc;
2678
2679 mutex_lock(&sc->mutex);
2680 ath9k_hw_settsf64(sc->sc_ah, tsf);
2681 mutex_unlock(&sc->mutex);
2682 }
2683
2684 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2685 {
2686 struct ath_wiphy *aphy = hw->priv;
2687 struct ath_softc *sc = aphy->sc;
2688
2689 mutex_lock(&sc->mutex);
2690 ath9k_hw_reset_tsf(sc->sc_ah);
2691 mutex_unlock(&sc->mutex);
2692 }
2693
2694 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2695 enum ieee80211_ampdu_mlme_action action,
2696 struct ieee80211_sta *sta,
2697 u16 tid, u16 *ssn)
2698 {
2699 struct ath_wiphy *aphy = hw->priv;
2700 struct ath_softc *sc = aphy->sc;
2701 int ret = 0;
2702
2703 switch (action) {
2704 case IEEE80211_AMPDU_RX_START:
2705 if (!(sc->sc_flags & SC_OP_RXAGGR))
2706 ret = -ENOTSUPP;
2707 break;
2708 case IEEE80211_AMPDU_RX_STOP:
2709 break;
2710 case IEEE80211_AMPDU_TX_START:
2711 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2712 if (ret < 0)
2713 DPRINTF(sc, ATH_DBG_FATAL,
2714 "Unable to start TX aggregation\n");
2715 else
2716 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2717 break;
2718 case IEEE80211_AMPDU_TX_STOP:
2719 ret = ath_tx_aggr_stop(sc, sta, tid);
2720 if (ret < 0)
2721 DPRINTF(sc, ATH_DBG_FATAL,
2722 "Unable to stop TX aggregation\n");
2723
2724 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2725 break;
2726 case IEEE80211_AMPDU_TX_RESUME:
2727 ath_tx_aggr_resume(sc, sta, tid);
2728 break;
2729 default:
2730 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2731 }
2732
2733 return ret;
2734 }
2735
2736 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2737 {
2738 struct ath_wiphy *aphy = hw->priv;
2739 struct ath_softc *sc = aphy->sc;
2740
2741 if (ath9k_wiphy_scanning(sc)) {
2742 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2743 "same time\n");
2744 /*
2745 * Do not allow the concurrent scanning state for now. This
2746 * could be improved with scanning control moved into ath9k.
2747 */
2748 return;
2749 }
2750
2751 aphy->state = ATH_WIPHY_SCAN;
2752 ath9k_wiphy_pause_all_forced(sc, aphy);
2753
2754 mutex_lock(&sc->mutex);
2755 sc->sc_flags |= SC_OP_SCANNING;
2756 mutex_unlock(&sc->mutex);
2757 }
2758
2759 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2760 {
2761 struct ath_wiphy *aphy = hw->priv;
2762 struct ath_softc *sc = aphy->sc;
2763
2764 mutex_lock(&sc->mutex);
2765 aphy->state = ATH_WIPHY_ACTIVE;
2766 sc->sc_flags &= ~SC_OP_SCANNING;
2767 mutex_unlock(&sc->mutex);
2768 }
2769
2770 struct ieee80211_ops ath9k_ops = {
2771 .tx = ath9k_tx,
2772 .start = ath9k_start,
2773 .stop = ath9k_stop,
2774 .add_interface = ath9k_add_interface,
2775 .remove_interface = ath9k_remove_interface,
2776 .config = ath9k_config,
2777 .config_interface = ath9k_config_interface,
2778 .configure_filter = ath9k_configure_filter,
2779 .sta_notify = ath9k_sta_notify,
2780 .conf_tx = ath9k_conf_tx,
2781 .bss_info_changed = ath9k_bss_info_changed,
2782 .set_key = ath9k_set_key,
2783 .get_tsf = ath9k_get_tsf,
2784 .set_tsf = ath9k_set_tsf,
2785 .reset_tsf = ath9k_reset_tsf,
2786 .ampdu_action = ath9k_ampdu_action,
2787 .sw_scan_start = ath9k_sw_scan_start,
2788 .sw_scan_complete = ath9k_sw_scan_complete,
2789 };
2790
2791 static struct {
2792 u32 version;
2793 const char * name;
2794 } ath_mac_bb_names[] = {
2795 { AR_SREV_VERSION_5416_PCI, "5416" },
2796 { AR_SREV_VERSION_5416_PCIE, "5418" },
2797 { AR_SREV_VERSION_9100, "9100" },
2798 { AR_SREV_VERSION_9160, "9160" },
2799 { AR_SREV_VERSION_9280, "9280" },
2800 { AR_SREV_VERSION_9285, "9285" }
2801 };
2802
2803 static struct {
2804 u16 version;
2805 const char * name;
2806 } ath_rf_names[] = {
2807 { 0, "5133" },
2808 { AR_RAD5133_SREV_MAJOR, "5133" },
2809 { AR_RAD5122_SREV_MAJOR, "5122" },
2810 { AR_RAD2133_SREV_MAJOR, "2133" },
2811 { AR_RAD2122_SREV_MAJOR, "2122" }
2812 };
2813
2814 /*
2815 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2816 */
2817 const char *
2818 ath_mac_bb_name(u32 mac_bb_version)
2819 {
2820 int i;
2821
2822 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2823 if (ath_mac_bb_names[i].version == mac_bb_version) {
2824 return ath_mac_bb_names[i].name;
2825 }
2826 }
2827
2828 return "????";
2829 }
2830
2831 /*
2832 * Return the RF name. "????" is returned if the RF is unknown.
2833 */
2834 const char *
2835 ath_rf_name(u16 rf_version)
2836 {
2837 int i;
2838
2839 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2840 if (ath_rf_names[i].version == rf_version) {
2841 return ath_rf_names[i].name;
2842 }
2843 }
2844
2845 return "????";
2846 }
2847
2848 static int __init ath9k_init(void)
2849 {
2850 int error;
2851
2852 /* Register rate control algorithm */
2853 error = ath_rate_control_register();
2854 if (error != 0) {
2855 printk(KERN_ERR
2856 "ath9k: Unable to register rate control "
2857 "algorithm: %d\n",
2858 error);
2859 goto err_out;
2860 }
2861
2862 error = ath9k_debug_create_root();
2863 if (error) {
2864 printk(KERN_ERR
2865 "ath9k: Unable to create debugfs root: %d\n",
2866 error);
2867 goto err_rate_unregister;
2868 }
2869
2870 error = ath_pci_init();
2871 if (error < 0) {
2872 printk(KERN_ERR
2873 "ath9k: No PCI devices found, driver not installed.\n");
2874 error = -ENODEV;
2875 goto err_remove_root;
2876 }
2877
2878 error = ath_ahb_init();
2879 if (error < 0) {
2880 error = -ENODEV;
2881 goto err_pci_exit;
2882 }
2883
2884 return 0;
2885
2886 err_pci_exit:
2887 ath_pci_exit();
2888
2889 err_remove_root:
2890 ath9k_debug_remove_root();
2891 err_rate_unregister:
2892 ath_rate_control_unregister();
2893 err_out:
2894 return error;
2895 }
2896 module_init(ath9k_init);
2897
2898 static void __exit ath9k_exit(void)
2899 {
2900 ath_ahb_exit();
2901 ath_pci_exit();
2902 ath9k_debug_remove_root();
2903 ath_rate_control_unregister();
2904 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2905 }
2906 module_exit(ath9k_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree