drivers/dma/coh901318.c

   1 /*
   2  * driver/dma/coh901318.c
   3  *
   4  * Copyright (C) 2007-2009 ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  * DMA driver for COH 901 318
   7  * Author: Per Friden <per.friden@stericsson.com>
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/module.h>
  12 #include <linux/kernel.h> /* printk() */
  13 #include <linux/fs.h> /* everything... */
  14 #include <linux/slab.h> /* kmalloc() */
  15 #include <linux/dmaengine.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/device.h>
  18 #include <linux/irqreturn.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/uaccess.h>
  22 #include <linux/debugfs.h>
  23 #include <mach/coh901318.h>
  24
  25 #include "coh901318_lli.h"
  26
  27 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
  28
  29 #ifdef VERBOSE_DEBUG
  30 #define COH_DBG(x) ({ if (1) x; 0; })
  31 #else
  32 #define COH_DBG(x) ({ if (0) x; 0; })
  33 #endif
  34
  35 struct coh901318_desc {
  36         struct dma_async_tx_descriptor desc;
  37         struct list_head node;
  38         struct scatterlist *sg;
  39         unsigned int sg_len;
  40         struct coh901318_lli *lli;
  41         enum dma_data_direction dir;
  42         unsigned long flags;
  43 };
  44
  45 struct coh901318_base {
  46         struct device *dev;
  47         void __iomem *virtbase;
  48         struct coh901318_pool pool;
  49         struct powersave pm;
  50         struct dma_device dma_slave;
  51         struct dma_device dma_memcpy;
  52         struct coh901318_chan *chans;
  53         struct coh901318_platform *platform;
  54 };
  55
  56 struct coh901318_chan {
  57         spinlock_t lock;
  58         int allocated;
  59         int completed;
  60         int id;
  61         int stopped;
  62
  63         struct work_struct free_work;
  64         struct dma_chan chan;
  65
  66         struct tasklet_struct tasklet;
  67
  68         struct list_head active;
  69         struct list_head queue;
  70         struct list_head free;
  71
  72         unsigned long nbr_active_done;
  73         unsigned long busy;
  74
  75         struct coh901318_base *base;
  76 };
  77
  78 static void coh901318_list_print(struct coh901318_chan *cohc,
  79                                  struct coh901318_lli *lli)
  80 {
  81         struct coh901318_lli *l = lli;
  82         int i = 0;
  83
  84         while (l) {
  85                 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
  86                          ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
  87                          i, l, l->control, l->src_addr, l->dst_addr,
  88                          l->link_addr, l->virt_link_addr);
  89                 i++;
  90                 l = l->virt_link_addr;
  91         }
  92 }
  93
  94 #ifdef CONFIG_DEBUG_FS
  95
  96 #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
  97
  98 static struct coh901318_base *debugfs_dma_base;
  99 static struct dentry *dma_dentry;
 100
 101 static int coh901318_debugfs_open(struct inode *inode, struct file *file)
 102 {
 103
 104         file->private_data = inode->i_private;
 105         return 0;
 106 }
 107
 108 static int coh901318_debugfs_read(struct file *file, char __user *buf,
 109                                   size_t count, loff_t *f_pos)
 110 {
 111         u64 started_channels = debugfs_dma_base->pm.started_channels;
 112         int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
 113         int i;
 114         int ret = 0;
 115         char *dev_buf;
 116         char *tmp;
 117         int dev_size;
 118
 119         dev_buf = kmalloc(4*1024, GFP_KERNEL);
 120         if (dev_buf == NULL)
 121                 goto err_kmalloc;
 122         tmp = dev_buf;
 123
 124         tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
 125
 126         for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
 127                 if (started_channels & (1 << i))
 128                         tmp += sprintf(tmp, "channel %d\n", i);
 129
 130         tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
 131         dev_size = tmp  - dev_buf;
 132
 133         /* No more to read if offset != 0 */
 134         if (*f_pos > dev_size)
 135                 goto out;
 136
 137         if (count > dev_size - *f_pos)
 138                 count = dev_size - *f_pos;
 139
 140         if (copy_to_user(buf, dev_buf + *f_pos, count))
 141                 ret = -EINVAL;
 142         ret = count;
 143         *f_pos += count;
 144
 145  out:
 146         kfree(dev_buf);
 147         return ret;
 148
 149  err_kmalloc:
 150         return 0;
 151 }
 152
 153 static const struct file_operations coh901318_debugfs_status_operations = {
 154         .owner          = THIS_MODULE,
 155         .open           = coh901318_debugfs_open,
 156         .read           = coh901318_debugfs_read,
 157 };
 158
 159
 160 static int __init init_coh901318_debugfs(void)
 161 {
 162
 163         dma_dentry = debugfs_create_dir("dma", NULL);
 164
 165         (void) debugfs_create_file("status",
 166                                    S_IFREG | S_IRUGO,
 167                                    dma_dentry, NULL,
 168                                    &coh901318_debugfs_status_operations);
 169         return 0;
 170 }
 171
 172 static void __exit exit_coh901318_debugfs(void)
 173 {
 174         debugfs_remove_recursive(dma_dentry);
 175 }
 176
 177 module_init(init_coh901318_debugfs);
 178 module_exit(exit_coh901318_debugfs);
 179 #else
 180
 181 #define COH901318_DEBUGFS_ASSIGN(x, y)
 182
 183 #endif /* CONFIG_DEBUG_FS */
 184
 185 static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
 186 {
 187         return container_of(chan, struct coh901318_chan, chan);
 188 }
 189
 190 static inline dma_addr_t
 191 cohc_dev_addr(struct coh901318_chan *cohc)
 192 {
 193         return cohc->base->platform->chan_conf[cohc->id].dev_addr;
 194 }
 195
 196 static inline const struct coh901318_params *
 197 cohc_chan_param(struct coh901318_chan *cohc)
 198 {
 199         return &cohc->base->platform->chan_conf[cohc->id].param;
 200 }
 201
 202 static inline const struct coh_dma_channel *
 203 cohc_chan_conf(struct coh901318_chan *cohc)
 204 {
 205         return &cohc->base->platform->chan_conf[cohc->id];
 206 }
 207
 208 static void enable_powersave(struct coh901318_chan *cohc)
 209 {
 210         unsigned long flags;
 211         struct powersave *pm = &cohc->base->pm;
 212
 213         spin_lock_irqsave(&pm->lock, flags);
 214
 215         pm->started_channels &= ~(1ULL << cohc->id);
 216
 217         if (!pm->started_channels) {
 218                 /* DMA no longer intends to access memory */
 219                 cohc->base->platform->access_memory_state(cohc->base->dev,
 220                                                           false);
 221         }
 222
 223         spin_unlock_irqrestore(&pm->lock, flags);
 224 }
 225 static void disable_powersave(struct coh901318_chan *cohc)
 226 {
 227         unsigned long flags;
 228         struct powersave *pm = &cohc->base->pm;
 229
 230         spin_lock_irqsave(&pm->lock, flags);
 231
 232         if (!pm->started_channels) {
 233                 /* DMA intends to access memory */
 234                 cohc->base->platform->access_memory_state(cohc->base->dev,
 235                                                           true);
 236         }
 237
 238         pm->started_channels |= (1ULL << cohc->id);
 239
 240         spin_unlock_irqrestore(&pm->lock, flags);
 241 }
 242
 243 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
 244 {
 245         int channel = cohc->id;
 246         void __iomem *virtbase = cohc->base->virtbase;
 247
 248         writel(control,
 249                virtbase + COH901318_CX_CTRL +
 250                COH901318_CX_CTRL_SPACING * channel);
 251         return 0;
 252 }
 253
 254 static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
 255 {
 256         int channel = cohc->id;
 257         void __iomem *virtbase = cohc->base->virtbase;
 258
 259         writel(conf,
 260                virtbase + COH901318_CX_CFG +
 261                COH901318_CX_CFG_SPACING*channel);
 262         return 0;
 263 }
 264
 265
 266 static int coh901318_start(struct coh901318_chan *cohc)
 267 {
 268         u32 val;
 269         int channel = cohc->id;
 270         void __iomem *virtbase = cohc->base->virtbase;
 271
 272         disable_powersave(cohc);
 273
 274         val = readl(virtbase + COH901318_CX_CFG +
 275                     COH901318_CX_CFG_SPACING * channel);
 276
 277         /* Enable channel */
 278         val |= COH901318_CX_CFG_CH_ENABLE;
 279         writel(val, virtbase + COH901318_CX_CFG +
 280                COH901318_CX_CFG_SPACING * channel);
 281
 282         return 0;
 283 }
 284
 285 static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
 286                                       struct coh901318_lli *lli)
 287 {
 288         int channel = cohc->id;
 289         void __iomem *virtbase = cohc->base->virtbase;
 290
 291         BUG_ON(readl(virtbase + COH901318_CX_STAT +
 292                      COH901318_CX_STAT_SPACING*channel) &
 293                COH901318_CX_STAT_ACTIVE);
 294
 295         writel(lli->src_addr,
 296                virtbase + COH901318_CX_SRC_ADDR +
 297                COH901318_CX_SRC_ADDR_SPACING * channel);
 298
 299         writel(lli->dst_addr, virtbase +
 300                COH901318_CX_DST_ADDR +
 301                COH901318_CX_DST_ADDR_SPACING * channel);
 302
 303         writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
 304                COH901318_CX_LNK_ADDR_SPACING * channel);
 305
 306         writel(lli->control, virtbase + COH901318_CX_CTRL +
 307                COH901318_CX_CTRL_SPACING * channel);
 308
 309         return 0;
 310 }
 311 static dma_cookie_t
 312 coh901318_assign_cookie(struct coh901318_chan *cohc,
 313                         struct coh901318_desc *cohd)
 314 {
 315         dma_cookie_t cookie = cohc->chan.cookie;
 316
 317         if (++cookie < 0)
 318                 cookie = 1;
 319
 320         cohc->chan.cookie = cookie;
 321         cohd->desc.cookie = cookie;
 322
 323         return cookie;
 324 }
 325
 326 static struct coh901318_desc *
 327 coh901318_desc_get(struct coh901318_chan *cohc)
 328 {
 329         struct coh901318_desc *desc;
 330
 331         if (list_empty(&cohc->free)) {
 332                 /* alloc new desc because we're out of used ones
 333                  * TODO: alloc a pile of descs instead of just one,
 334                  * avoid many small allocations.
 335                  */
 336                 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
 337                 if (desc == NULL)
 338                         goto out;
 339                 INIT_LIST_HEAD(&desc->node);
 340                 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
 341         } else {
 342                 /* Reuse an old desc. */
 343                 desc = list_first_entry(&cohc->free,
 344                                         struct coh901318_desc,
 345                                         node);
 346                 list_del(&desc->node);
 347                 /* Initialize it a bit so it's not insane */
 348                 desc->sg = NULL;
 349                 desc->sg_len = 0;
 350                 desc->desc.callback = NULL;
 351                 desc->desc.callback_param = NULL;
 352         }
 353
 354  out:
 355         return desc;
 356 }
 357
 358 static void
 359 coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
 360 {
 361         list_add_tail(&cohd->node, &cohc->free);
 362 }
 363
 364 /* call with irq lock held */
 365 static void
 366 coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
 367 {
 368         list_add_tail(&desc->node, &cohc->active);
 369 }
 370
 371 static struct coh901318_desc *
 372 coh901318_first_active_get(struct coh901318_chan *cohc)
 373 {
 374         struct coh901318_desc *d;
 375
 376         if (list_empty(&cohc->active))
 377                 return NULL;
 378
 379         d = list_first_entry(&cohc->active,
 380                              struct coh901318_desc,
 381                              node);
 382         return d;
 383 }
 384
 385 static void
 386 coh901318_desc_remove(struct coh901318_desc *cohd)
 387 {
 388         list_del(&cohd->node);
 389 }
 390
 391 static void
 392 coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
 393 {
 394         list_add_tail(&desc->node, &cohc->queue);
 395 }
 396
 397 static struct coh901318_desc *
 398 coh901318_first_queued(struct coh901318_chan *cohc)
 399 {
 400         struct coh901318_desc *d;
 401
 402         if (list_empty(&cohc->queue))
 403                 return NULL;
 404
 405         d = list_first_entry(&cohc->queue,
 406                              struct coh901318_desc,
 407                              node);
 408         return d;
 409 }
 410
 411 /*
 412  * DMA start/stop controls
 413  */
 414 u32 coh901318_get_bytes_left(struct dma_chan *chan)
 415 {
 416         unsigned long flags;
 417         u32 ret;
 418         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 419
 420         spin_lock_irqsave(&cohc->lock, flags);
 421
 422         /* Read transfer count value */
 423         ret = readl(cohc->base->virtbase +
 424                     COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
 425                     cohc->id) & COH901318_CX_CTRL_TC_VALUE_MASK;
 426
 427         spin_unlock_irqrestore(&cohc->lock, flags);
 428
 429         return ret;
 430 }
 431 EXPORT_SYMBOL(coh901318_get_bytes_left);
 432
 433
 434 /* Stops a transfer without losing data. Enables power save.
 435    Use this function in conjunction with coh901318_continue(..)
 436 */
 437 void coh901318_stop(struct dma_chan *chan)
 438 {
 439         u32 val;
 440         unsigned long flags;
 441         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 442         int channel = cohc->id;
 443         void __iomem *virtbase = cohc->base->virtbase;
 444
 445         spin_lock_irqsave(&cohc->lock, flags);
 446
 447         /* Disable channel in HW */
 448         val = readl(virtbase + COH901318_CX_CFG +
 449                     COH901318_CX_CFG_SPACING * channel);
 450
 451         /* Stopping infinit transfer */
 452         if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
 453             (val & COH901318_CX_CFG_CH_ENABLE))
 454                 cohc->stopped = 1;
 455
 456
 457         val &= ~COH901318_CX_CFG_CH_ENABLE;
 458         /* Enable twice, HW bug work around */
 459         writel(val, virtbase + COH901318_CX_CFG +
 460                COH901318_CX_CFG_SPACING * channel);
 461         writel(val, virtbase + COH901318_CX_CFG +
 462                COH901318_CX_CFG_SPACING * channel);
 463
 464         /* Spin-wait for it to actually go inactive */
 465         while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
 466                      channel) & COH901318_CX_STAT_ACTIVE)
 467                 cpu_relax();
 468
 469         /* Check if we stopped an active job */
 470         if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
 471                    channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
 472                 cohc->stopped = 1;
 473
 474         enable_powersave(cohc);
 475
 476         spin_unlock_irqrestore(&cohc->lock, flags);
 477 }
 478 EXPORT_SYMBOL(coh901318_stop);
 479
 480 /* Continues a transfer that has been stopped via 300_dma_stop(..).
 481    Power save is handled.
 482 */
 483 void coh901318_continue(struct dma_chan *chan)
 484 {
 485         u32 val;
 486         unsigned long flags;
 487         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 488         int channel = cohc->id;
 489
 490         spin_lock_irqsave(&cohc->lock, flags);
 491
 492         disable_powersave(cohc);
 493
 494         if (cohc->stopped) {
 495                 /* Enable channel in HW */
 496                 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
 497                             COH901318_CX_CFG_SPACING * channel);
 498
 499                 val |= COH901318_CX_CFG_CH_ENABLE;
 500
 501                 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
 502                        COH901318_CX_CFG_SPACING*channel);
 503
 504                 cohc->stopped = 0;
 505         }
 506
 507         spin_unlock_irqrestore(&cohc->lock, flags);
 508 }
 509 EXPORT_SYMBOL(coh901318_continue);
 510
 511 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
 512 {
 513         unsigned int ch_nr = (unsigned int) chan_id;
 514
 515         if (ch_nr == to_coh901318_chan(chan)->id)
 516                 return true;
 517
 518         return false;
 519 }
 520 EXPORT_SYMBOL(coh901318_filter_id);
 521
 522 /*
 523  * DMA channel allocation
 524  */
 525 static int coh901318_config(struct coh901318_chan *cohc,
 526                             struct coh901318_params *param)
 527 {
 528         unsigned long flags;
 529         const struct coh901318_params *p;
 530         int channel = cohc->id;
 531         void __iomem *virtbase = cohc->base->virtbase;
 532
 533         spin_lock_irqsave(&cohc->lock, flags);
 534
 535         if (param)
 536                 p = param;
 537         else
 538                 p = &cohc->base->platform->chan_conf[channel].param;
 539
 540         /* Clear any pending BE or TC interrupt */
 541         if (channel < 32) {
 542                 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
 543                 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
 544         } else {
 545                 writel(1 << (channel - 32), virtbase +
 546                        COH901318_BE_INT_CLEAR2);
 547                 writel(1 << (channel - 32), virtbase +
 548                        COH901318_TC_INT_CLEAR2);
 549         }
 550
 551         coh901318_set_conf(cohc, p->config);
 552         coh901318_set_ctrl(cohc, p->ctrl_lli_last);
 553
 554         spin_unlock_irqrestore(&cohc->lock, flags);
 555
 556         return 0;
 557 }
 558
 559 /* must lock when calling this function
 560  * start queued jobs, if any
 561  * TODO: start all queued jobs in one go
 562  *
 563  * Returns descriptor if queued job is started otherwise NULL.
 564  * If the queue is empty NULL is returned.
 565  */
 566 static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
 567 {
 568         struct coh901318_desc *cohd;
 569
 570         /*
 571          * start queued jobs, if any
 572          * TODO: transmit all queued jobs in one go
 573          */
 574         cohd = coh901318_first_queued(cohc);
 575
 576         if (cohd != NULL) {
 577                 /* Remove from queue */
 578                 coh901318_desc_remove(cohd);
 579                 /* initiate DMA job */
 580                 cohc->busy = 1;
 581
 582                 coh901318_desc_submit(cohc, cohd);
 583
 584                 coh901318_prep_linked_list(cohc, cohd->lli);
 585
 586                 /* start dma job on this channel */
 587                 coh901318_start(cohc);
 588
 589         }
 590
 591         return cohd;
 592 }
 593
 594 /*
 595  * This tasklet is called from the interrupt handler to
 596  * handle each descriptor (DMA job) that is sent to a channel.
 597  */
 598 static void dma_tasklet(unsigned long data)
 599 {
 600         struct coh901318_chan *cohc = (struct coh901318_chan *) data;
 601         struct coh901318_desc *cohd_fin;
 602         unsigned long flags;
 603         dma_async_tx_callback callback;
 604         void *callback_param;
 605
 606         dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
 607                  " nbr_active_done %ld\n", __func__,
 608                  cohc->id, cohc->nbr_active_done);
 609
 610         spin_lock_irqsave(&cohc->lock, flags);
 611
 612         /* get first active descriptor entry from list */
 613         cohd_fin = coh901318_first_active_get(cohc);
 614
 615         if (cohd_fin == NULL)
 616                 goto err;
 617
 618         /* locate callback to client */
 619         callback = cohd_fin->desc.callback;
 620         callback_param = cohd_fin->desc.callback_param;
 621
 622         /* sign this job as completed on the channel */
 623         cohc->completed = cohd_fin->desc.cookie;
 624
 625         /* release the lli allocation and remove the descriptor */
 626         coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
 627
 628         /* return desc to free-list */
 629         coh901318_desc_remove(cohd_fin);
 630         coh901318_desc_free(cohc, cohd_fin);
 631
 632         spin_unlock_irqrestore(&cohc->lock, flags);
 633
 634         /* Call the callback when we're done */
 635         if (callback)
 636                 callback(callback_param);
 637
 638         spin_lock_irqsave(&cohc->lock, flags);
 639
 640         /*
 641          * If another interrupt fired while the tasklet was scheduling,
 642          * we don't get called twice, so we have this number of active
 643          * counter that keep track of the number of IRQs expected to
 644          * be handled for this channel. If there happen to be more than
 645          * one IRQ to be ack:ed, we simply schedule this tasklet again.
 646          */
 647         cohc->nbr_active_done--;
 648         if (cohc->nbr_active_done) {
 649                 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
 650                         "came in while we were scheduling this tasklet\n");
 651                 if (cohc_chan_conf(cohc)->priority_high)
 652                         tasklet_hi_schedule(&cohc->tasklet);
 653                 else
 654                         tasklet_schedule(&cohc->tasklet);
 655         }
 656
 657         spin_unlock_irqrestore(&cohc->lock, flags);
 658
 659         return;
 660
 661  err:
 662         spin_unlock_irqrestore(&cohc->lock, flags);
 663         dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
 664 }
 665
 666
 667 /* called from interrupt context */
 668 static void dma_tc_handle(struct coh901318_chan *cohc)
 669 {
 670         /*
 671          * If the channel is not allocated, then we shouldn't have
 672          * any TC interrupts on it.
 673          */
 674         if (!cohc->allocated) {
 675                 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
 676                         "unallocated channel\n");
 677                 return;
 678         }
 679
 680         spin_lock(&cohc->lock);
 681
 682         /*
 683          * When we reach this point, at least one queue item
 684          * should have been moved over from cohc->queue to
 685          * cohc->active and run to completion, that is why we're
 686          * getting a terminal count interrupt is it not?
 687          * If you get this BUG() the most probable cause is that
 688          * the individual nodes in the lli chain have IRQ enabled,
 689          * so check your platform config for lli chain ctrl.
 690          */
 691         BUG_ON(list_empty(&cohc->active));
 692
 693         cohc->nbr_active_done++;
 694
 695         /*
 696          * This attempt to take a job from cohc->queue, put it
 697          * into cohc->active and start it.
 698          */
 699         if (coh901318_queue_start(cohc) == NULL)
 700                 cohc->busy = 0;
 701
 702         spin_unlock(&cohc->lock);
 703
 704         /*
 705          * This tasklet will remove items from cohc->active
 706          * and thus terminates them.
 707          */
 708         if (cohc_chan_conf(cohc)->priority_high)
 709                 tasklet_hi_schedule(&cohc->tasklet);
 710         else
 711                 tasklet_schedule(&cohc->tasklet);
 712 }
 713
 714
 715 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 716 {
 717         u32 status1;
 718         u32 status2;
 719         int i;
 720         int ch;
 721         struct coh901318_base *base  = dev_id;
 722         struct coh901318_chan *cohc;
 723         void __iomem *virtbase = base->virtbase;
 724
 725         status1 = readl(virtbase + COH901318_INT_STATUS1);
 726         status2 = readl(virtbase + COH901318_INT_STATUS2);
 727
 728         if (unlikely(status1 == 0 && status2 == 0)) {
 729                 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
 730                 return IRQ_HANDLED;
 731         }
 732
 733         /* TODO: consider handle IRQ in tasklet here to
 734          *       minimize interrupt latency */
 735
 736         /* Check the first 32 DMA channels for IRQ */
 737         while (status1) {
 738                 /* Find first bit set, return as a number. */
 739                 i = ffs(status1) - 1;
 740                 ch = i;
 741
 742                 cohc = &base->chans[ch];
 743                 spin_lock(&cohc->lock);
 744
 745                 /* Mask off this bit */
 746                 status1 &= ~(1 << i);
 747                 /* Check the individual channel bits */
 748                 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
 749                         dev_crit(COHC_2_DEV(cohc),
 750                                  "DMA bus error on channel %d!\n", ch);
 751                         BUG_ON(1);
 752                         /* Clear BE interrupt */
 753                         __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
 754                 } else {
 755                         /* Caused by TC, really? */
 756                         if (unlikely(!test_bit(i, virtbase +
 757                                                COH901318_TC_INT_STATUS1))) {
 758                                 dev_warn(COHC_2_DEV(cohc),
 759                                          "ignoring interrupt not caused by terminal count on channel %d\n", ch);
 760                                 /* Clear TC interrupt */
 761                                 BUG_ON(1);
 762                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
 763                         } else {
 764                                 /* Enable powersave if transfer has finished */
 765                                 if (!(readl(virtbase + COH901318_CX_STAT +
 766                                             COH901318_CX_STAT_SPACING*ch) &
 767                                       COH901318_CX_STAT_ENABLED)) {
 768                                         enable_powersave(cohc);
 769                                 }
 770
 771                                 /* Must clear TC interrupt before calling
 772                                  * dma_tc_handle
 773                                  * in case tc_handle initate a new dma job
 774                                  */
 775                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
 776
 777                                 dma_tc_handle(cohc);
 778                         }
 779                 }
 780                 spin_unlock(&cohc->lock);
 781         }
 782
 783         /* Check the remaining 32 DMA channels for IRQ */
 784         while (status2) {
 785                 /* Find first bit set, return as a number. */
 786                 i = ffs(status2) - 1;
 787                 ch = i + 32;
 788                 cohc = &base->chans[ch];
 789                 spin_lock(&cohc->lock);
 790
 791                 /* Mask off this bit */
 792                 status2 &= ~(1 << i);
 793                 /* Check the individual channel bits */
 794                 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
 795                         dev_crit(COHC_2_DEV(cohc),
 796                                  "DMA bus error on channel %d!\n", ch);
 797                         /* Clear BE interrupt */
 798                         BUG_ON(1);
 799                         __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
 800                 } else {
 801                         /* Caused by TC, really? */
 802                         if (unlikely(!test_bit(i, virtbase +
 803                                                COH901318_TC_INT_STATUS2))) {
 804                                 dev_warn(COHC_2_DEV(cohc),
 805                                          "ignoring interrupt not caused by terminal count on channel %d\n", ch);
 806                                 /* Clear TC interrupt */
 807                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
 808                                 BUG_ON(1);
 809                         } else {
 810                                 /* Enable powersave if transfer has finished */
 811                                 if (!(readl(virtbase + COH901318_CX_STAT +
 812                                             COH901318_CX_STAT_SPACING*ch) &
 813                                       COH901318_CX_STAT_ENABLED)) {
 814                                         enable_powersave(cohc);
 815                                 }
 816                                 /* Must clear TC interrupt before calling
 817                                  * dma_tc_handle
 818                                  * in case tc_handle initate a new dma job
 819                                  */
 820                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
 821
 822                                 dma_tc_handle(cohc);
 823                         }
 824                 }
 825                 spin_unlock(&cohc->lock);
 826         }
 827
 828         return IRQ_HANDLED;
 829 }
 830
 831 static int coh901318_alloc_chan_resources(struct dma_chan *chan)
 832 {
 833         struct coh901318_chan   *cohc = to_coh901318_chan(chan);
 834
 835         dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
 836                  __func__, cohc->id);
 837
 838         if (chan->client_count > 1)
 839                 return -EBUSY;
 840
 841         coh901318_config(cohc, NULL);
 842
 843         cohc->allocated = 1;
 844         cohc->completed = chan->cookie = 1;
 845
 846         return 1;
 847 }
 848
 849 static void
 850 coh901318_free_chan_resources(struct dma_chan *chan)
 851 {
 852         struct coh901318_chan   *cohc = to_coh901318_chan(chan);
 853         int channel = cohc->id;
 854         unsigned long flags;
 855
 856         spin_lock_irqsave(&cohc->lock, flags);
 857
 858         /* Disable HW */
 859         writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
 860                COH901318_CX_CFG_SPACING*channel);
 861         writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
 862                COH901318_CX_CTRL_SPACING*channel);
 863
 864         cohc->allocated = 0;
 865
 866         spin_unlock_irqrestore(&cohc->lock, flags);
 867
 868         chan->device->device_terminate_all(chan);
 869 }
 870
 871
 872 static dma_cookie_t
 873 coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
 874 {
 875         struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
 876                                                    desc);
 877         struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
 878         unsigned long flags;
 879
 880         spin_lock_irqsave(&cohc->lock, flags);
 881
 882         tx->cookie = coh901318_assign_cookie(cohc, cohd);
 883
 884         coh901318_desc_queue(cohc, cohd);
 885
 886         spin_unlock_irqrestore(&cohc->lock, flags);
 887
 888         return tx->cookie;
 889 }
 890
 891 static struct dma_async_tx_descriptor *
 892 coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 893                       size_t size, unsigned long flags)
 894 {
 895         struct coh901318_lli *lli;
 896         struct coh901318_desc *cohd;
 897         unsigned long flg;
 898         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 899         int lli_len;
 900         u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
 901         int ret;
 902
 903         spin_lock_irqsave(&cohc->lock, flg);
 904
 905         dev_vdbg(COHC_2_DEV(cohc),
 906                  "[%s] channel %d src 0x%x dest 0x%x size %d\n",
 907                  __func__, cohc->id, src, dest, size);
 908
 909         if (flags & DMA_PREP_INTERRUPT)
 910                 /* Trigger interrupt after last lli */
 911                 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
 912
 913         lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
 914         if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
 915                 lli_len++;
 916
 917         lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
 918
 919         if (lli == NULL)
 920                 goto err;
 921
 922         ret = coh901318_lli_fill_memcpy(
 923                 &cohc->base->pool, lli, src, size, dest,
 924                 cohc_chan_param(cohc)->ctrl_lli_chained,
 925                 ctrl_last);
 926         if (ret)
 927                 goto err;
 928
 929         COH_DBG(coh901318_list_print(cohc, lli));
 930
 931         /* Pick a descriptor to handle this transfer */
 932         cohd = coh901318_desc_get(cohc);
 933         cohd->lli = lli;
 934         cohd->flags = flags;
 935         cohd->desc.tx_submit = coh901318_tx_submit;
 936
 937         spin_unlock_irqrestore(&cohc->lock, flg);
 938
 939         return &cohd->desc;
 940  err:
 941         spin_unlock_irqrestore(&cohc->lock, flg);
 942         return NULL;
 943 }
 944
 945 static struct dma_async_tx_descriptor *
 946 coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 947                         unsigned int sg_len, enum dma_data_direction direction,
 948                         unsigned long flags)
 949 {
 950         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 951         struct coh901318_lli *lli;
 952         struct coh901318_desc *cohd;
 953         const struct coh901318_params *params;
 954         struct scatterlist *sg;
 955         int len = 0;
 956         int size;
 957         int i;
 958         u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
 959         u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
 960         u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
 961         u32 config;
 962         unsigned long flg;
 963         int ret;
 964
 965         if (!sgl)
 966                 goto out;
 967         if (sgl->length == 0)
 968                 goto out;
 969
 970         spin_lock_irqsave(&cohc->lock, flg);
 971
 972         dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
 973                  __func__, sg_len, direction);
 974
 975         if (flags & DMA_PREP_INTERRUPT)
 976                 /* Trigger interrupt after last lli */
 977                 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
 978
 979         params = cohc_chan_param(cohc);
 980         config = params->config;
 981
 982         if (direction == DMA_TO_DEVICE) {
 983                 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
 984                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
 985
 986                 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
 987                 ctrl_chained |= tx_flags;
 988                 ctrl_last |= tx_flags;
 989                 ctrl |= tx_flags;
 990         } else if (direction == DMA_FROM_DEVICE) {
 991                 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
 992                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
 993
 994                 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
 995                 ctrl_chained |= rx_flags;
 996                 ctrl_last |= rx_flags;
 997                 ctrl |= rx_flags;
 998         } else
 999                 goto err_direction;
1000
1001         coh901318_set_conf(cohc, config);
1002
1003         /* The dma only supports transmitting packages up to
1004          * MAX_DMA_PACKET_SIZE. Calculate to total number of
1005          * dma elemts required to send the entire sg list
1006          */
1007         for_each_sg(sgl, sg, sg_len, i) {
1008                 unsigned int factor;
1009                 size = sg_dma_len(sg);
1010
1011                 if (size <= MAX_DMA_PACKET_SIZE) {
1012                         len++;
1013                         continue;
1014                 }
1015
1016                 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
1017                 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1018                         factor++;
1019
1020                 len += factor;
1021         }
1022
1023         pr_debug("Allocate %d lli:s for this transfer\n", len);
1024         lli = coh901318_lli_alloc(&cohc->base->pool, len);
1025
1026         if (lli == NULL)
1027                 goto err_dma_alloc;
1028
1029         /* initiate allocated lli list */
1030         ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
1031                                     cohc_dev_addr(cohc),
1032                                     ctrl_chained,
1033                                     ctrl,
1034                                     ctrl_last,
1035                                     direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
1036         if (ret)
1037                 goto err_lli_fill;
1038
1039         COH_DBG(coh901318_list_print(cohc, lli));
1040
1041         /* Pick a descriptor to handle this transfer */
1042         cohd = coh901318_desc_get(cohc);
1043         cohd->dir = direction;
1044         cohd->flags = flags;
1045         cohd->desc.tx_submit = coh901318_tx_submit;
1046         cohd->lli = lli;
1047
1048         spin_unlock_irqrestore(&cohc->lock, flg);
1049
1050         return &cohd->desc;
1051  err_lli_fill:
1052  err_dma_alloc:
1053  err_direction:
1054         spin_unlock_irqrestore(&cohc->lock, flg);
1055  out:
1056         return NULL;
1057 }
1058
1059 static enum dma_status
1060 coh901318_is_tx_complete(struct dma_chan *chan,
1061                          dma_cookie_t cookie, dma_cookie_t *done,
1062                          dma_cookie_t *used)
1063 {
1064         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1065         dma_cookie_t last_used;
1066         dma_cookie_t last_complete;
1067         int ret;
1068
1069         last_complete = cohc->completed;
1070         last_used = chan->cookie;
1071
1072         ret = dma_async_is_complete(cookie, last_complete, last_used);
1073
1074         if (done)
1075                 *done = last_complete;
1076         if (used)
1077                 *used = last_used;
1078
1079         return ret;
1080 }
1081
1082 static void
1083 coh901318_issue_pending(struct dma_chan *chan)
1084 {
1085         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1086         unsigned long flags;
1087
1088         spin_lock_irqsave(&cohc->lock, flags);
1089
1090         /*
1091          * Busy means that pending jobs are already being processed,
1092          * and then there is no point in starting the queue: the
1093          * terminal count interrupt on the channel will take the next
1094          * job on the queue and execute it anyway.
1095          */
1096         if (!cohc->busy)
1097                 coh901318_queue_start(cohc);
1098
1099         spin_unlock_irqrestore(&cohc->lock, flags);
1100 }
1101
1102 static void
1103 coh901318_terminate_all(struct dma_chan *chan)
1104 {
1105         unsigned long flags;
1106         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1107         struct coh901318_desc *cohd;
1108         void __iomem *virtbase = cohc->base->virtbase;
1109
1110         coh901318_stop(chan);
1111
1112         spin_lock_irqsave(&cohc->lock, flags);
1113
1114         /* Clear any pending BE or TC interrupt */
1115         if (cohc->id < 32) {
1116                 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
1117                 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
1118         } else {
1119                 writel(1 << (cohc->id - 32), virtbase +
1120                        COH901318_BE_INT_CLEAR2);
1121                 writel(1 << (cohc->id - 32), virtbase +
1122                        COH901318_TC_INT_CLEAR2);
1123         }
1124
1125         enable_powersave(cohc);
1126
1127         while ((cohd = coh901318_first_active_get(cohc))) {
1128                 /* release the lli allocation*/
1129                 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1130
1131                 /* return desc to free-list */
1132                 coh901318_desc_remove(cohd);
1133                 coh901318_desc_free(cohc, cohd);
1134         }
1135
1136         while ((cohd = coh901318_first_queued(cohc))) {
1137                 /* release the lli allocation*/
1138                 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1139
1140                 /* return desc to free-list */
1141                 coh901318_desc_remove(cohd);
1142                 coh901318_desc_free(cohc, cohd);
1143         }
1144
1145
1146         cohc->nbr_active_done = 0;
1147         cohc->busy = 0;
1148
1149         spin_unlock_irqrestore(&cohc->lock, flags);
1150 }
1151 void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
1152                          struct coh901318_base *base)
1153 {
1154         int chans_i;
1155         int i = 0;
1156         struct coh901318_chan *cohc;
1157
1158         INIT_LIST_HEAD(&dma->channels);
1159
1160         for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
1161                 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
1162                         cohc = &base->chans[i];
1163
1164                         cohc->base = base;
1165                         cohc->chan.device = dma;
1166                         cohc->id = i;
1167
1168                         /* TODO: do we really need this lock if only one
1169                          * client is connected to each channel?
1170                          */
1171
1172                         spin_lock_init(&cohc->lock);
1173
1174                         cohc->nbr_active_done = 0;
1175                         cohc->busy = 0;
1176                         INIT_LIST_HEAD(&cohc->free);
1177                         INIT_LIST_HEAD(&cohc->active);
1178                         INIT_LIST_HEAD(&cohc->queue);
1179
1180                         tasklet_init(&cohc->tasklet, dma_tasklet,
1181                                      (unsigned long) cohc);
1182
1183                         list_add_tail(&cohc->chan.device_node,
1184                                       &dma->channels);
1185                 }
1186         }
1187 }
1188
1189 static int __init coh901318_probe(struct platform_device *pdev)
1190 {
1191         int err = 0;
1192         struct coh901318_platform *pdata;
1193         struct coh901318_base *base;
1194         int irq;
1195         struct resource *io;
1196
1197         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1198         if (!io)
1199                 goto err_get_resource;
1200
1201         /* Map DMA controller registers to virtual memory */
1202         if (request_mem_region(io->start,
1203                                resource_size(io),
1204                                pdev->dev.driver->name) == NULL) {
1205                 err = -EBUSY;
1206                 goto err_request_mem;
1207         }
1208
1209         pdata = pdev->dev.platform_data;
1210         if (!pdata)
1211                 goto err_no_platformdata;
1212
1213         base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) +
1214                        pdata->max_channels *
1215                        sizeof(struct coh901318_chan),
1216                        GFP_KERNEL);
1217         if (!base)
1218                 goto err_alloc_coh_dma_channels;
1219
1220         base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
1221
1222         base->virtbase = ioremap(io->start, resource_size(io));
1223         if (!base->virtbase) {
1224                 err = -ENOMEM;
1225                 goto err_no_ioremap;
1226         }
1227
1228         base->dev = &pdev->dev;
1229         base->platform = pdata;
1230         spin_lock_init(&base->pm.lock);
1231         base->pm.started_channels = 0;
1232
1233         COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
1234
1235         platform_set_drvdata(pdev, base);
1236
1237         irq = platform_get_irq(pdev, 0);
1238         if (irq < 0)
1239                 goto err_no_irq;
1240
1241         err = request_irq(irq, dma_irq_handler, IRQF_DISABLED,
1242                           "coh901318", base);
1243         if (err) {
1244                 dev_crit(&pdev->dev,
1245                          "Cannot allocate IRQ for DMA controller!\n");
1246                 goto err_request_irq;
1247         }
1248
1249         err = coh901318_pool_create(&base->pool, &pdev->dev,
1250                                     sizeof(struct coh901318_lli),
1251                                     32);
1252         if (err)
1253                 goto err_pool_create;
1254
1255         /* init channels for device transfers */
1256         coh901318_base_init(&base->dma_slave,  base->platform->chans_slave,
1257                             base);
1258
1259         dma_cap_zero(base->dma_slave.cap_mask);
1260         dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
1261
1262         base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1263         base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
1264         base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
1265         base->dma_slave.device_is_tx_complete = coh901318_is_tx_complete;
1266         base->dma_slave.device_issue_pending = coh901318_issue_pending;
1267         base->dma_slave.device_terminate_all = coh901318_terminate_all;
1268         base->dma_slave.dev = &pdev->dev;
1269
1270         err = dma_async_device_register(&base->dma_slave);
1271
1272         if (err)
1273                 goto err_register_slave;
1274
1275         /* init channels for memcpy */
1276         coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
1277                             base);
1278
1279         dma_cap_zero(base->dma_memcpy.cap_mask);
1280         dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
1281
1282         base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1283         base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
1284         base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
1285         base->dma_memcpy.device_is_tx_complete = coh901318_is_tx_complete;
1286         base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
1287         base->dma_memcpy.device_terminate_all = coh901318_terminate_all;
1288         base->dma_memcpy.dev = &pdev->dev;
1289         /*
1290          * This controller can only access address at even 32bit boundaries,
1291          * i.e. 2^2
1292          */
1293         base->dma_memcpy.copy_align = 2;
1294         err = dma_async_device_register(&base->dma_memcpy);
1295
1296         if (err)
1297                 goto err_register_memcpy;
1298
1299         dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
1300                 (u32) base->virtbase);
1301
1302         return err;
1303
1304  err_register_memcpy:
1305         dma_async_device_unregister(&base->dma_slave);
1306  err_register_slave:
1307         coh901318_pool_destroy(&base->pool);
1308  err_pool_create:
1309         free_irq(platform_get_irq(pdev, 0), base);
1310  err_request_irq:
1311  err_no_irq:
1312         iounmap(base->virtbase);
1313  err_no_ioremap:
1314         kfree(base);
1315  err_alloc_coh_dma_channels:
1316  err_no_platformdata:
1317         release_mem_region(pdev->resource->start,
1318                            resource_size(pdev->resource));
1319  err_request_mem:
1320  err_get_resource:
1321         return err;
1322 }
1323
1324 static int __exit coh901318_remove(struct platform_device *pdev)
1325 {
1326         struct coh901318_base *base = platform_get_drvdata(pdev);
1327
1328         dma_async_device_unregister(&base->dma_memcpy);
1329         dma_async_device_unregister(&base->dma_slave);
1330         coh901318_pool_destroy(&base->pool);
1331         free_irq(platform_get_irq(pdev, 0), base);
1332         iounmap(base->virtbase);
1333         kfree(base);
1334         release_mem_region(pdev->resource->start,
1335                            resource_size(pdev->resource));
1336         return 0;
1337 }
1338
1339
1340 static struct platform_driver coh901318_driver = {
1341         .remove = __exit_p(coh901318_remove),
1342         .driver = {
1343                 .name   = "coh901318",
1344         },
1345 };
1346
1347 int __init coh901318_init(void)
1348 {
1349         return platform_driver_probe(&coh901318_driver, coh901318_probe);
1350 }
1351 subsys_initcall(coh901318_init);
1352
1353 void __exit coh901318_exit(void)
1354 {
1355         platform_driver_unregister(&coh901318_driver);
1356 }
1357 module_exit(coh901318_exit);
1358
1359 MODULE_LICENSE("GPL");
1360 MODULE_AUTHOR("Per Friden");