drivers/gpio/gpio-s5pc100.c

   1 /*
   2  * S5PC100 - GPIOlib support
   3  *
   4  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  *  Copyright 2009 Samsung Electronics Co
   8  *  Kyungmin Park <kyungmin.park@samsung.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/irq.h>
  17 #include <linux/io.h>
  18 #include <linux/gpio.h>
  19
  20 #include <mach/map.h>
  21 #include <mach/regs-gpio.h>
  22
  23 #include <plat/gpio-core.h>
  24 #include <plat/gpio-cfg.h>
  25 #include <plat/gpio-cfg-helpers.h>
  26
  27 /* S5PC100 GPIO bank summary:
  28  *
  29  * Bank GPIOs   Style   INT Type
  30  * A0   8       4Bit    GPIO_INT0
  31  * A1   5       4Bit    GPIO_INT1
  32  * B    8       4Bit    GPIO_INT2
  33  * C    5       4Bit    GPIO_INT3
  34  * D    7       4Bit    GPIO_INT4
  35  * E0   8       4Bit    GPIO_INT5
  36  * E1   6       4Bit    GPIO_INT6
  37  * F0   8       4Bit    GPIO_INT7
  38  * F1   8       4Bit    GPIO_INT8
  39  * F2   8       4Bit    GPIO_INT9
  40  * F3   4       4Bit    GPIO_INT10
  41  * G0   8       4Bit    GPIO_INT11
  42  * G1   3       4Bit    GPIO_INT12
  43  * G2   7       4Bit    GPIO_INT13
  44  * G3   7       4Bit    GPIO_INT14
  45  * H0   8       4Bit    WKUP_INT
  46  * H1   8       4Bit    WKUP_INT
  47  * H2   8       4Bit    WKUP_INT
  48  * H3   8       4Bit    WKUP_INT
  49  * I    8       4Bit    GPIO_INT15
  50  * J0   8       4Bit    GPIO_INT16
  51  * J1   5       4Bit    GPIO_INT17
  52  * J2   8       4Bit    GPIO_INT18
  53  * J3   8       4Bit    GPIO_INT19
  54  * J4   4       4Bit    GPIO_INT20
  55  * K0   8       4Bit    None
  56  * K1   6       4Bit    None
  57  * K2   8       4Bit    None
  58  * K3   8       4Bit    None
  59  * L0   8       4Bit    None
  60  * L1   8       4Bit    None
  61  * L2   8       4Bit    None
  62  * L3   8       4Bit    None
  63  */
  64
  65 static struct s3c_gpio_cfg gpio_cfg = {
  66         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
  67         .set_pull       = s3c_gpio_setpull_updown,
  68         .get_pull       = s3c_gpio_getpull_updown,
  69 };
  70
  71 static struct s3c_gpio_cfg gpio_cfg_eint = {
  72         .cfg_eint       = 0xf,
  73         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
  74         .set_pull       = s3c_gpio_setpull_updown,
  75         .get_pull       = s3c_gpio_getpull_updown,
  76 };
  77
  78 static struct s3c_gpio_cfg gpio_cfg_noint = {
  79         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
  80         .set_pull       = s3c_gpio_setpull_updown,
  81         .get_pull       = s3c_gpio_getpull_updown,
  82 };
  83
  84 /*
  85  * GPIO bank's base address given the index of the bank in the
  86  * list of all gpio banks.
  87  */
  88 #define S5PC100_BANK_BASE(bank_nr)      (S5P_VA_GPIO + ((bank_nr) * 0x20))
  89
  90 /*
  91  * Following are the gpio banks in S5PC100.
  92  *
  93  * The 'config' member when left to NULL, is initialized to the default
  94  * structure gpio_cfg in the init function below.
  95  *
  96  * The 'base' member is also initialized in the init function below.
  97  * Note: The initialization of 'base' member of s3c_gpio_chip structure
  98  * uses the above macro and depends on the banks being listed in order here.
  99  */
 100 static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 101         {
 102                 .chip   = {
 103                         .base   = S5PC100_GPA0(0),
 104                         .ngpio  = S5PC100_GPIO_A0_NR,
 105                         .label  = "GPA0",
 106                 },
 107         }, {
 108                 .chip   = {
 109                         .base   = S5PC100_GPA1(0),
 110                         .ngpio  = S5PC100_GPIO_A1_NR,
 111                         .label  = "GPA1",
 112                 },
 113         }, {
 114                 .chip   = {
 115                         .base   = S5PC100_GPB(0),
 116                         .ngpio  = S5PC100_GPIO_B_NR,
 117                         .label  = "GPB",
 118                 },
 119         }, {
 120                 .chip   = {
 121                         .base   = S5PC100_GPC(0),
 122                         .ngpio  = S5PC100_GPIO_C_NR,
 123                         .label  = "GPC",
 124                 },
 125         }, {
 126                 .chip   = {
 127                         .base   = S5PC100_GPD(0),
 128                         .ngpio  = S5PC100_GPIO_D_NR,
 129                         .label  = "GPD",
 130                 },
 131         }, {
 132                 .chip   = {
 133                         .base   = S5PC100_GPE0(0),
 134                         .ngpio  = S5PC100_GPIO_E0_NR,
 135                         .label  = "GPE0",
 136                 },
 137         }, {
 138                 .chip   = {
 139                         .base   = S5PC100_GPE1(0),
 140                         .ngpio  = S5PC100_GPIO_E1_NR,
 141                         .label  = "GPE1",
 142                 },
 143         }, {
 144                 .chip   = {
 145                         .base   = S5PC100_GPF0(0),
 146                         .ngpio  = S5PC100_GPIO_F0_NR,
 147                         .label  = "GPF0",
 148                 },
 149         }, {
 150                 .chip   = {
 151                         .base   = S5PC100_GPF1(0),
 152                         .ngpio  = S5PC100_GPIO_F1_NR,
 153                         .label  = "GPF1",
 154                 },
 155         }, {
 156                 .chip   = {
 157                         .base   = S5PC100_GPF2(0),
 158                         .ngpio  = S5PC100_GPIO_F2_NR,
 159                         .label  = "GPF2",
 160                 },
 161         }, {
 162                 .chip   = {
 163                         .base   = S5PC100_GPF3(0),
 164                         .ngpio  = S5PC100_GPIO_F3_NR,
 165                         .label  = "GPF3",
 166                 },
 167         }, {
 168                 .chip   = {
 169                         .base   = S5PC100_GPG0(0),
 170                         .ngpio  = S5PC100_GPIO_G0_NR,
 171                         .label  = "GPG0",
 172                 },
 173         }, {
 174                 .chip   = {
 175                         .base   = S5PC100_GPG1(0),
 176                         .ngpio  = S5PC100_GPIO_G1_NR,
 177                         .label  = "GPG1",
 178                 },
 179         }, {
 180                 .chip   = {
 181                         .base   = S5PC100_GPG2(0),
 182                         .ngpio  = S5PC100_GPIO_G2_NR,
 183                         .label  = "GPG2",
 184                 },
 185         }, {
 186                 .chip   = {
 187                         .base   = S5PC100_GPG3(0),
 188                         .ngpio  = S5PC100_GPIO_G3_NR,
 189                         .label  = "GPG3",
 190                 },
 191         }, {
 192                 .chip   = {
 193                         .base   = S5PC100_GPI(0),
 194                         .ngpio  = S5PC100_GPIO_I_NR,
 195                         .label  = "GPI",
 196                 },
 197         }, {
 198                 .chip   = {
 199                         .base   = S5PC100_GPJ0(0),
 200                         .ngpio  = S5PC100_GPIO_J0_NR,
 201                         .label  = "GPJ0",
 202                 },
 203         }, {
 204                 .chip   = {
 205                         .base   = S5PC100_GPJ1(0),
 206                         .ngpio  = S5PC100_GPIO_J1_NR,
 207                         .label  = "GPJ1",
 208                 },
 209         }, {
 210                 .chip   = {
 211                         .base   = S5PC100_GPJ2(0),
 212                         .ngpio  = S5PC100_GPIO_J2_NR,
 213                         .label  = "GPJ2",
 214                 },
 215         }, {
 216                 .chip   = {
 217                         .base   = S5PC100_GPJ3(0),
 218                         .ngpio  = S5PC100_GPIO_J3_NR,
 219                         .label  = "GPJ3",
 220                 },
 221         }, {
 222                 .chip   = {
 223                         .base   = S5PC100_GPJ4(0),
 224                         .ngpio  = S5PC100_GPIO_J4_NR,
 225                         .label  = "GPJ4",
 226                 },
 227         }, {
 228                 .config = &gpio_cfg_noint,
 229                 .chip   = {
 230                         .base   = S5PC100_GPK0(0),
 231                         .ngpio  = S5PC100_GPIO_K0_NR,
 232                         .label  = "GPK0",
 233                 },
 234         }, {
 235                 .config = &gpio_cfg_noint,
 236                 .chip   = {
 237                         .base   = S5PC100_GPK1(0),
 238                         .ngpio  = S5PC100_GPIO_K1_NR,
 239                         .label  = "GPK1",
 240                 },
 241         }, {
 242                 .config = &gpio_cfg_noint,
 243                 .chip   = {
 244                         .base   = S5PC100_GPK2(0),
 245                         .ngpio  = S5PC100_GPIO_K2_NR,
 246                         .label  = "GPK2",
 247                 },
 248         }, {
 249                 .config = &gpio_cfg_noint,
 250                 .chip   = {
 251                         .base   = S5PC100_GPK3(0),
 252                         .ngpio  = S5PC100_GPIO_K3_NR,
 253                         .label  = "GPK3",
 254                 },
 255         }, {
 256                 .config = &gpio_cfg_noint,
 257                 .chip   = {
 258                         .base   = S5PC100_GPL0(0),
 259                         .ngpio  = S5PC100_GPIO_L0_NR,
 260                         .label  = "GPL0",
 261                 },
 262         }, {
 263                 .config = &gpio_cfg_noint,
 264                 .chip   = {
 265                         .base   = S5PC100_GPL1(0),
 266                         .ngpio  = S5PC100_GPIO_L1_NR,
 267                         .label  = "GPL1",
 268                 },
 269         }, {
 270                 .config = &gpio_cfg_noint,
 271                 .chip   = {
 272                         .base   = S5PC100_GPL2(0),
 273                         .ngpio  = S5PC100_GPIO_L2_NR,
 274                         .label  = "GPL2",
 275                 },
 276         }, {
 277                 .config = &gpio_cfg_noint,
 278                 .chip   = {
 279                         .base   = S5PC100_GPL3(0),
 280                         .ngpio  = S5PC100_GPIO_L3_NR,
 281                         .label  = "GPL3",
 282                 },
 283         }, {
 284                 .config = &gpio_cfg_noint,
 285                 .chip   = {
 286                         .base   = S5PC100_GPL4(0),
 287                         .ngpio  = S5PC100_GPIO_L4_NR,
 288                         .label  = "GPL4",
 289                 },
 290         }, {
 291                 .base   = (S5P_VA_GPIO + 0xC00),
 292                 .config = &gpio_cfg_eint,
 293                 .irq_base = IRQ_EINT(0),
 294                 .chip   = {
 295                         .base   = S5PC100_GPH0(0),
 296                         .ngpio  = S5PC100_GPIO_H0_NR,
 297                         .label  = "GPH0",
 298                         .to_irq = samsung_gpiolib_to_irq,
 299                 },
 300         }, {
 301                 .base   = (S5P_VA_GPIO + 0xC20),
 302                 .config = &gpio_cfg_eint,
 303                 .irq_base = IRQ_EINT(8),
 304                 .chip   = {
 305                         .base   = S5PC100_GPH1(0),
 306                         .ngpio  = S5PC100_GPIO_H1_NR,
 307                         .label  = "GPH1",
 308                         .to_irq = samsung_gpiolib_to_irq,
 309                 },
 310         }, {
 311                 .base   = (S5P_VA_GPIO + 0xC40),
 312                 .config = &gpio_cfg_eint,
 313                 .irq_base = IRQ_EINT(16),
 314                 .chip   = {
 315                         .base   = S5PC100_GPH2(0),
 316                         .ngpio  = S5PC100_GPIO_H2_NR,
 317                         .label  = "GPH2",
 318                         .to_irq = samsung_gpiolib_to_irq,
 319                 },
 320         }, {
 321                 .base   = (S5P_VA_GPIO + 0xC60),
 322                 .config = &gpio_cfg_eint,
 323                 .irq_base = IRQ_EINT(24),
 324                 .chip   = {
 325                         .base   = S5PC100_GPH3(0),
 326                         .ngpio  = S5PC100_GPIO_H3_NR,
 327                         .label  = "GPH3",
 328                         .to_irq = samsung_gpiolib_to_irq,
 329                 },
 330         },
 331 };
 332
 333 static __init int s5pc100_gpiolib_init(void)
 334 {
 335         struct s3c_gpio_chip *chip = s5pc100_gpio_chips;
 336         int nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
 337         int gpioint_group = 0;
 338         int i;
 339
 340         for (i = 0; i < nr_chips; i++, chip++) {
 341                 if (chip->config == NULL) {
 342                         chip->config = &gpio_cfg;
 343                         chip->group = gpioint_group++;
 344                 }
 345                 if (chip->base == NULL)
 346                         chip->base = S5PC100_BANK_BASE(i);
 347         }
 348
 349         samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips);
 350         s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
 351
 352         return 0;
 353 }
 354 core_initcall(s5pc100_gpiolib_init);