arch/m68k/mac/macints.c

   1 /*
   2  *      Macintosh interrupts
   3  *
   4  * General design:
   5  * In contrary to the Amiga and Atari platforms, the Mac hardware seems to
   6  * exclusively use the autovector interrupts (the 'generic level0-level7'
   7  * interrupts with exception vectors 0x19-0x1f). The following interrupt levels
   8  * are used:
   9  *      1       - VIA1
  10  *                - slot 0: one second interrupt (CA2)
  11  *                - slot 1: VBlank (CA1)
  12  *                - slot 2: ADB data ready (SR full)
  13  *                - slot 3: ADB data  (CB2)
  14  *                - slot 4: ADB clock (CB1)
  15  *                - slot 5: timer 2
  16  *                - slot 6: timer 1
  17  *                - slot 7: status of IRQ; signals 'any enabled int.'
  18  *
  19  *      2       - VIA2 or RBV
  20  *                - slot 0: SCSI DRQ (CA2)
  21  *                - slot 1: NUBUS IRQ (CA1) need to read port A to find which
  22  *                - slot 2: /EXP IRQ (only on IIci)
  23  *                - slot 3: SCSI IRQ (CB2)
  24  *                - slot 4: ASC IRQ (CB1)
  25  *                - slot 5: timer 2 (not on IIci)
  26  *                - slot 6: timer 1 (not on IIci)
  27  *                - slot 7: status of IRQ; signals 'any enabled int.'
  28  *
  29  *      2       - OSS (IIfx only?)
  30  *                - slot 0: SCSI interrupt
  31  *                - slot 1: Sound interrupt
  32  *
  33  * Levels 3-6 vary by machine type. For VIA or RBV Macintoshes:
  34  *
  35  *      3       - unused (?)
  36  *
  37  *      4       - SCC (slot number determined by reading RR3 on the SSC itself)
  38  *                - slot 1: SCC channel A
  39  *                - slot 2: SCC channel B
  40  *
  41  *      5       - unused (?)
  42  *                [serial errors or special conditions seem to raise level 6
  43  *                interrupts on some models (LC4xx?)]
  44  *
  45  *      6       - off switch (?)
  46  *
  47  * For OSS Macintoshes (IIfx only at this point):
  48  *
  49  *      3       - Nubus interrupt
  50  *                - slot 0: Slot $9
  51  *                - slot 1: Slot $A
  52  *                - slot 2: Slot $B
  53  *                - slot 3: Slot $C
  54  *                - slot 4: Slot $D
  55  *                - slot 5: Slot $E
  56  *
  57  *      4       - SCC IOP
  58  *                - slot 1: SCC channel A
  59  *                - slot 2: SCC channel B
  60  *
  61  *      5       - ISM IOP (ADB?)
  62  *
  63  *      6       - unused
  64  *
  65  * For PSC Macintoshes (660AV, 840AV):
  66  *
  67  *      3       - PSC level 3
  68  *                - slot 0: MACE
  69  *
  70  *      4       - PSC level 4
  71  *                - slot 1: SCC channel A interrupt
  72  *                - slot 2: SCC channel B interrupt
  73  *                - slot 3: MACE DMA
  74  *
  75  *      5       - PSC level 5
  76  *
  77  *      6       - PSC level 6
  78  *
  79  * Finally we have good 'ole level 7, the non-maskable interrupt:
  80  *
  81  *      7       - NMI (programmer's switch on the back of some Macs)
  82  *                Also RAM parity error on models which support it (IIc, IIfx?)
  83  *
  84  * The current interrupt logic looks something like this:
  85  *
  86  * - We install dispatchers for the autovector interrupts (1-7). These
  87  *   dispatchers are responsible for querying the hardware (the
  88  *   VIA/RBV/OSS/PSC chips) to determine the actual interrupt source. Using
  89  *   this information a machspec interrupt number is generated by placing the
  90  *   index of the interrupt hardware into the low three bits and the original
  91  *   autovector interrupt number in the upper 5 bits. The handlers for the
  92  *   resulting machspec interrupt are then called.
  93  *
  94  * - Nubus is a special case because its interrupts are hidden behind two
  95  *   layers of hardware. Nubus interrupts come in as index 1 on VIA #2,
  96  *   which translates to IRQ number 17. In this spot we install _another_
  97  *   dispatcher. This dispatcher finds the interrupting slot number (9-F) and
  98  *   then forms a new machspec interrupt number as above with the slot number
  99  *   minus 9 in the low three bits and the pseudo-level 7 in the upper five
 100  *   bits.  The handlers for this new machspec interrupt number are then
 101  *   called. This puts Nubus interrupts into the range 56-62.
 102  *
 103  * - The Baboon interrupts (used on some PowerBooks) are an even more special
 104  *   case. They're hidden behind the Nubus slot $C interrupt thus adding a
 105  *   third layer of indirection. Why oh why did the Apple engineers do that?
 106  *
 107  * - We support "fast" and "slow" handlers, just like the Amiga port. The
 108  *   fast handlers are called first and with all interrupts disabled. They
 109  *   are expected to execute quickly (hence the name). The slow handlers are
 110  *   called last with interrupts enabled and the interrupt level restored.
 111  *   They must therefore be reentrant.
 112  *
 113  *   TODO:
 114  *
 115  */
 116
 117 #include <linux/module.h>
 118 #include <linux/types.h>
 119 #include <linux/kernel.h>
 120 #include <linux/sched.h>
 121 #include <linux/kernel_stat.h>
 122 #include <linux/interrupt.h> /* for intr_count */
 123 #include <linux/delay.h>
 124 #include <linux/seq_file.h>
 125
 126 #include <asm/system.h>
 127 #include <asm/irq.h>
 128 #include <asm/traps.h>
 129 #include <asm/bootinfo.h>
 130 #include <asm/macintosh.h>
 131 #include <asm/mac_via.h>
 132 #include <asm/mac_psc.h>
 133 #include <asm/hwtest.h>
 134 #include <asm/errno.h>
 135 #include <asm/macints.h>
 136 #include <asm/irq_regs.h>
 137 #include <asm/mac_oss.h>
 138
 139 #define DEBUG_SPURIOUS
 140 #define SHUTUP_SONIC
 141
 142 /* SCC interrupt mask */
 143
 144 static int scc_mask;
 145
 146 /*
 147  * VIA/RBV hooks
 148  */
 149
 150 extern void via_register_interrupts(void);
 151 extern void via_irq_enable(int);
 152 extern void via_irq_disable(int);
 153 extern void via_irq_clear(int);
 154 extern int  via_irq_pending(int);
 155
 156 /*
 157  * OSS hooks
 158  */
 159
 160 extern void oss_register_interrupts(void);
 161 extern void oss_irq_enable(int);
 162 extern void oss_irq_disable(int);
 163 extern void oss_irq_clear(int);
 164 extern int  oss_irq_pending(int);
 165
 166 /*
 167  * PSC hooks
 168  */
 169
 170 extern void psc_register_interrupts(void);
 171 extern void psc_irq_enable(int);
 172 extern void psc_irq_disable(int);
 173 extern void psc_irq_clear(int);
 174 extern int  psc_irq_pending(int);
 175
 176 /*
 177  * IOP hooks
 178  */
 179
 180 extern void iop_register_interrupts(void);
 181
 182 /*
 183  * Baboon hooks
 184  */
 185
 186 extern int baboon_present;
 187
 188 extern void baboon_register_interrupts(void);
 189 extern void baboon_irq_enable(int);
 190 extern void baboon_irq_disable(int);
 191 extern void baboon_irq_clear(int);
 192
 193 /*
 194  * SCC interrupt routines
 195  */
 196
 197 static void scc_irq_enable(unsigned int);
 198 static void scc_irq_disable(unsigned int);
 199
 200 /*
 201  * console_loglevel determines NMI handler function
 202  */
 203
 204 irqreturn_t mac_nmi_handler(int, void *);
 205 irqreturn_t mac_debug_handler(int, void *);
 206
 207 /* #define DEBUG_MACINTS */
 208
 209 void mac_enable_irq(unsigned int irq);
 210 void mac_disable_irq(unsigned int irq);
 211
 212 static struct irq_controller mac_irq_controller = {
 213         .name           = "mac",
 214         .lock           = __SPIN_LOCK_UNLOCKED(mac_irq_controller.lock),
 215         .enable         = mac_enable_irq,
 216         .disable        = mac_disable_irq,
 217 };
 218
 219 void __init mac_init_IRQ(void)
 220 {
 221 #ifdef DEBUG_MACINTS
 222         printk("mac_init_IRQ(): Setting things up...\n");
 223 #endif
 224         scc_mask = 0;
 225
 226         m68k_setup_irq_controller(&mac_irq_controller, IRQ_USER,
 227                                   NUM_MAC_SOURCES - IRQ_USER);
 228         /* Make sure the SONIC interrupt is cleared or things get ugly */
 229 #ifdef SHUTUP_SONIC
 230         printk("Killing onboard sonic... ");
 231         /* This address should hopefully be mapped already */
 232         if (hwreg_present((void*)(0x50f0a000))) {
 233                 *(long *)(0x50f0a014) = 0x7fffL;
 234                 *(long *)(0x50f0a010) = 0L;
 235         }
 236         printk("Done.\n");
 237 #endif /* SHUTUP_SONIC */
 238
 239         /*
 240          * Now register the handlers for the master IRQ handlers
 241          * at levels 1-7. Most of the work is done elsewhere.
 242          */
 243
 244         if (oss_present)
 245                 oss_register_interrupts();
 246         else
 247                 via_register_interrupts();
 248         if (psc_present)
 249                 psc_register_interrupts();
 250         if (baboon_present)
 251                 baboon_register_interrupts();
 252         iop_register_interrupts();
 253         if (request_irq(IRQ_AUTO_7, mac_nmi_handler, 0, "NMI",
 254                         mac_nmi_handler))
 255                 pr_err("Couldn't register NMI\n");
 256 #ifdef DEBUG_MACINTS
 257         printk("mac_init_IRQ(): Done!\n");
 258 #endif
 259 }
 260
 261 /*
 262  *  mac_enable_irq - enable an interrupt source
 263  * mac_disable_irq - disable an interrupt source
 264  *   mac_clear_irq - clears a pending interrupt
 265  * mac_pending_irq - Returns the pending status of an IRQ (nonzero = pending)
 266  *
 267  * These routines are just dispatchers to the VIA/OSS/PSC routines.
 268  */
 269
 270 void mac_enable_irq(unsigned int irq)
 271 {
 272         int irq_src = IRQ_SRC(irq);
 273
 274         switch(irq_src) {
 275         case 1:
 276                 via_irq_enable(irq);
 277                 break;
 278         case 2:
 279         case 7:
 280                 if (oss_present)
 281                         oss_irq_enable(irq);
 282                 else
 283                         via_irq_enable(irq);
 284                 break;
 285         case 3:
 286         case 4:
 287         case 5:
 288         case 6:
 289                 if (psc_present)
 290                         psc_irq_enable(irq);
 291                 else if (oss_present)
 292                         oss_irq_enable(irq);
 293                 else if (irq_src == 4)
 294                         scc_irq_enable(irq);
 295                 break;
 296         case 8:
 297                 if (baboon_present)
 298                         baboon_irq_enable(irq);
 299                 break;
 300         }
 301 }
 302
 303 void mac_disable_irq(unsigned int irq)
 304 {
 305         int irq_src = IRQ_SRC(irq);
 306
 307         switch(irq_src) {
 308         case 1:
 309                 via_irq_disable(irq);
 310                 break;
 311         case 2:
 312         case 7:
 313                 if (oss_present)
 314                         oss_irq_disable(irq);
 315                 else
 316                         via_irq_disable(irq);
 317                 break;
 318         case 3:
 319         case 4:
 320         case 5:
 321         case 6:
 322                 if (psc_present)
 323                         psc_irq_disable(irq);
 324                 else if (oss_present)
 325                         oss_irq_disable(irq);
 326                 else if (irq_src == 4)
 327                         scc_irq_disable(irq);
 328                 break;
 329         case 8:
 330                 if (baboon_present)
 331                         baboon_irq_disable(irq);
 332                 break;
 333         }
 334 }
 335
 336 void mac_clear_irq(unsigned int irq)
 337 {
 338         switch(IRQ_SRC(irq)) {
 339         case 1:
 340                 via_irq_clear(irq);
 341                 break;
 342         case 2:
 343         case 7:
 344                 if (oss_present)
 345                         oss_irq_clear(irq);
 346                 else
 347                         via_irq_clear(irq);
 348                 break;
 349         case 3:
 350         case 4:
 351         case 5:
 352         case 6:
 353                 if (psc_present)
 354                         psc_irq_clear(irq);
 355                 else if (oss_present)
 356                         oss_irq_clear(irq);
 357                 break;
 358         case 8:
 359                 if (baboon_present)
 360                         baboon_irq_clear(irq);
 361                 break;
 362         }
 363 }
 364
 365 int mac_irq_pending(unsigned int irq)
 366 {
 367         switch(IRQ_SRC(irq)) {
 368         case 1:
 369                 return via_irq_pending(irq);
 370         case 2:
 371         case 7:
 372                 if (oss_present)
 373                         return oss_irq_pending(irq);
 374                 else
 375                         return via_irq_pending(irq);
 376         case 3:
 377         case 4:
 378         case 5:
 379         case 6:
 380                 if (psc_present)
 381                         return psc_irq_pending(irq);
 382                 else if (oss_present)
 383                         return oss_irq_pending(irq);
 384         }
 385         return 0;
 386 }
 387 EXPORT_SYMBOL(mac_irq_pending);
 388
 389 static int num_debug[8];
 390
 391 irqreturn_t mac_debug_handler(int irq, void *dev_id)
 392 {
 393         if (num_debug[irq] < 10) {
 394                 printk("DEBUG: Unexpected IRQ %d\n", irq);
 395                 num_debug[irq]++;
 396         }
 397         return IRQ_HANDLED;
 398 }
 399
 400 static int in_nmi;
 401 static volatile int nmi_hold;
 402
 403 irqreturn_t mac_nmi_handler(int irq, void *dev_id)
 404 {
 405         int i;
 406         /*
 407          * generate debug output on NMI switch if 'debug' kernel option given
 408          * (only works with Penguin!)
 409          */
 410
 411         in_nmi++;
 412         for (i=0; i<100; i++)
 413                 udelay(1000);
 414
 415         if (in_nmi == 1) {
 416                 nmi_hold = 1;
 417                 printk("... pausing, press NMI to resume ...");
 418         } else {
 419                 printk(" ok!\n");
 420                 nmi_hold = 0;
 421         }
 422
 423         barrier();
 424
 425         while (nmi_hold == 1)
 426                 udelay(1000);
 427
 428         if (console_loglevel >= 8) {
 429 #if 0
 430                 struct pt_regs *fp = get_irq_regs();
 431                 show_state();
 432                 printk("PC: %08lx\nSR: %04x  SP: %p\n", fp->pc, fp->sr, fp);
 433                 printk("d0: %08lx    d1: %08lx    d2: %08lx    d3: %08lx\n",
 434                        fp->d0, fp->d1, fp->d2, fp->d3);
 435                 printk("d4: %08lx    d5: %08lx    a0: %08lx    a1: %08lx\n",
 436                        fp->d4, fp->d5, fp->a0, fp->a1);
 437
 438                 if (STACK_MAGIC != *(unsigned long *)current->kernel_stack_page)
 439                         printk("Corrupted stack page\n");
 440                 printk("Process %s (pid: %d, stackpage=%08lx)\n",
 441                         current->comm, current->pid, current->kernel_stack_page);
 442                 if (intr_count == 1)
 443                         dump_stack((struct frame *)fp);
 444 #else
 445                 /* printk("NMI "); */
 446 #endif
 447         }
 448         in_nmi--;
 449         return IRQ_HANDLED;
 450 }
 451
 452 /*
 453  * Simple routines for masking and unmasking
 454  * SCC interrupts in cases where this can't be
 455  * done in hardware (only the PSC can do that.)
 456  */
 457
 458 static void scc_irq_enable(unsigned int irq)
 459 {
 460         int irq_idx = IRQ_IDX(irq);
 461
 462         scc_mask |= (1 << irq_idx);
 463 }
 464
 465 static void scc_irq_disable(unsigned int irq)
 466 {
 467         int irq_idx = IRQ_IDX(irq);
 468
 469         scc_mask &= ~(1 << irq_idx);
 470 }
 471
 472 /*
 473  * SCC master interrupt handler. We have to do a bit of magic here
 474  * to figure out what channel gave us the interrupt; putting this
 475  * here is cleaner than hacking it into drivers/char/macserial.c.
 476  */
 477
 478 void mac_scc_dispatch(int irq, void *dev_id)
 479 {
 480         volatile unsigned char *scc = (unsigned char *) mac_bi_data.sccbase + 2;
 481         unsigned char reg;
 482         unsigned long flags;
 483
 484         /* Read RR3 from the chip. Always do this on channel A */
 485         /* This must be an atomic operation so disable irqs.   */
 486
 487         local_irq_save(flags);
 488         *scc = 3;
 489         reg = *scc;
 490         local_irq_restore(flags);
 491
 492         /* Now dispatch. Bits 0-2 are for channel B and */
 493         /* bits 3-5 are for channel A. We can safely    */
 494         /* ignore the remaining bits here.              */
 495         /*                                              */
 496         /* Note that we're ignoring scc_mask for now.   */
 497         /* If we actually mask the ints then we tend to */
 498         /* get hammered by very persistent SCC irqs,    */
 499         /* and since they're autovector interrupts they */
 500         /* pretty much kill the system.                 */
 501
 502         if (reg & 0x38)
 503                 m68k_handle_int(IRQ_SCCA);
 504         if (reg & 0x07)
 505                 m68k_handle_int(IRQ_SCCB);
 506 }