drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  44 {
  45         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  46         BUG_ON(1);
  47         return 0;
  48 }
  49
  50 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  51 {
  52         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  53                   reg, v);
  54         BUG_ON(1);
  55 }
  56
  57 static void radeon_register_accessor_init(struct radeon_device *rdev)
  58 {
  59         rdev->mc_rreg = &radeon_invalid_rreg;
  60         rdev->mc_wreg = &radeon_invalid_wreg;
  61         rdev->pll_rreg = &radeon_invalid_rreg;
  62         rdev->pll_wreg = &radeon_invalid_wreg;
  63         rdev->pciep_rreg = &radeon_invalid_rreg;
  64         rdev->pciep_wreg = &radeon_invalid_wreg;
  65
  66         /* Don't change order as we are overridding accessor. */
  67         if (rdev->family < CHIP_RV515) {
  68                 rdev->pcie_reg_mask = 0xff;
  69         } else {
  70                 rdev->pcie_reg_mask = 0x7ff;
  71         }
  72         /* FIXME: not sure here */
  73         if (rdev->family <= CHIP_R580) {
  74                 rdev->pll_rreg = &r100_pll_rreg;
  75                 rdev->pll_wreg = &r100_pll_wreg;
  76         }
  77         if (rdev->family >= CHIP_R420) {
  78                 rdev->mc_rreg = &r420_mc_rreg;
  79                 rdev->mc_wreg = &r420_mc_wreg;
  80         }
  81         if (rdev->family >= CHIP_RV515) {
  82                 rdev->mc_rreg = &rv515_mc_rreg;
  83                 rdev->mc_wreg = &rv515_mc_wreg;
  84         }
  85         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  86                 rdev->mc_rreg = &rs400_mc_rreg;
  87                 rdev->mc_wreg = &rs400_mc_wreg;
  88         }
  89         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  90                 rdev->mc_rreg = &rs690_mc_rreg;
  91                 rdev->mc_wreg = &rs690_mc_wreg;
  92         }
  93         if (rdev->family == CHIP_RS600) {
  94                 rdev->mc_rreg = &rs600_mc_rreg;
  95                 rdev->mc_wreg = &rs600_mc_wreg;
  96         }
  97         if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
  98                 rdev->pciep_rreg = &r600_pciep_rreg;
  99                 rdev->pciep_wreg = &r600_pciep_wreg;
 100         }
 101 }
 102
 103
 104 /* helper to disable agp */
 105 void radeon_agp_disable(struct radeon_device *rdev)
 106 {
 107         rdev->flags &= ~RADEON_IS_AGP;
 108         if (rdev->family >= CHIP_R600) {
 109                 DRM_INFO("Forcing AGP to PCIE mode\n");
 110                 rdev->flags |= RADEON_IS_PCIE;
 111         } else if (rdev->family >= CHIP_RV515 ||
 112                         rdev->family == CHIP_RV380 ||
 113                         rdev->family == CHIP_RV410 ||
 114                         rdev->family == CHIP_R423) {
 115                 DRM_INFO("Forcing AGP to PCIE mode\n");
 116                 rdev->flags |= RADEON_IS_PCIE;
 117                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 118                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 119         } else {
 120                 DRM_INFO("Forcing AGP to PCI mode\n");
 121                 rdev->flags |= RADEON_IS_PCI;
 122                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 123                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 124         }
 125         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 126 }
 127
 128 /*
 129  * ASIC
 130  */
 131 static struct radeon_asic r100_asic = {
 132         .init = &r100_init,
 133         .fini = &r100_fini,
 134         .suspend = &r100_suspend,
 135         .resume = &r100_resume,
 136         .vga_set_state = &r100_vga_set_state,
 137         .gpu_is_lockup = &r100_gpu_is_lockup,
 138         .asic_reset = &r100_asic_reset,
 139         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 140         .gart_set_page = &r100_pci_gart_set_page,
 141         .cp_commit = &r100_cp_commit,
 142         .ring_start = &r100_ring_start,
 143         .ring_test = &r100_ring_test,
 144         .ring_ib_execute = &r100_ring_ib_execute,
 145         .irq_set = &r100_irq_set,
 146         .irq_process = &r100_irq_process,
 147         .get_vblank_counter = &r100_get_vblank_counter,
 148         .fence_ring_emit = &r100_fence_ring_emit,
 149         .cs_parse = &r100_cs_parse,
 150         .copy_blit = &r100_copy_blit,
 151         .copy_dma = NULL,
 152         .copy = &r100_copy_blit,
 153         .get_engine_clock = &radeon_legacy_get_engine_clock,
 154         .set_engine_clock = &radeon_legacy_set_engine_clock,
 155         .get_memory_clock = &radeon_legacy_get_memory_clock,
 156         .set_memory_clock = NULL,
 157         .get_pcie_lanes = NULL,
 158         .set_pcie_lanes = NULL,
 159         .set_clock_gating = &radeon_legacy_set_clock_gating,
 160         .set_surface_reg = r100_set_surface_reg,
 161         .clear_surface_reg = r100_clear_surface_reg,
 162         .bandwidth_update = &r100_bandwidth_update,
 163         .hpd_init = &r100_hpd_init,
 164         .hpd_fini = &r100_hpd_fini,
 165         .hpd_sense = &r100_hpd_sense,
 166         .hpd_set_polarity = &r100_hpd_set_polarity,
 167         .ioctl_wait_idle = NULL,
 168         .gui_idle = &r100_gui_idle,
 169         .pm_misc = &r100_pm_misc,
 170         .pm_prepare = &r100_pm_prepare,
 171         .pm_finish = &r100_pm_finish,
 172         .pm_init_profile = &r100_pm_init_profile,
 173         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 174 };
 175
 176 static struct radeon_asic r200_asic = {
 177         .init = &r100_init,
 178         .fini = &r100_fini,
 179         .suspend = &r100_suspend,
 180         .resume = &r100_resume,
 181         .vga_set_state = &r100_vga_set_state,
 182         .gpu_is_lockup = &r100_gpu_is_lockup,
 183         .asic_reset = &r100_asic_reset,
 184         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 185         .gart_set_page = &r100_pci_gart_set_page,
 186         .cp_commit = &r100_cp_commit,
 187         .ring_start = &r100_ring_start,
 188         .ring_test = &r100_ring_test,
 189         .ring_ib_execute = &r100_ring_ib_execute,
 190         .irq_set = &r100_irq_set,
 191         .irq_process = &r100_irq_process,
 192         .get_vblank_counter = &r100_get_vblank_counter,
 193         .fence_ring_emit = &r100_fence_ring_emit,
 194         .cs_parse = &r100_cs_parse,
 195         .copy_blit = &r100_copy_blit,
 196         .copy_dma = &r200_copy_dma,
 197         .copy = &r100_copy_blit,
 198         .get_engine_clock = &radeon_legacy_get_engine_clock,
 199         .set_engine_clock = &radeon_legacy_set_engine_clock,
 200         .get_memory_clock = &radeon_legacy_get_memory_clock,
 201         .set_memory_clock = NULL,
 202         .set_pcie_lanes = NULL,
 203         .set_clock_gating = &radeon_legacy_set_clock_gating,
 204         .set_surface_reg = r100_set_surface_reg,
 205         .clear_surface_reg = r100_clear_surface_reg,
 206         .bandwidth_update = &r100_bandwidth_update,
 207         .hpd_init = &r100_hpd_init,
 208         .hpd_fini = &r100_hpd_fini,
 209         .hpd_sense = &r100_hpd_sense,
 210         .hpd_set_polarity = &r100_hpd_set_polarity,
 211         .ioctl_wait_idle = NULL,
 212         .gui_idle = &r100_gui_idle,
 213         .pm_misc = &r100_pm_misc,
 214         .pm_prepare = &r100_pm_prepare,
 215         .pm_finish = &r100_pm_finish,
 216         .pm_init_profile = &r100_pm_init_profile,
 217         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 218 };
 219
 220 static struct radeon_asic r300_asic = {
 221         .init = &r300_init,
 222         .fini = &r300_fini,
 223         .suspend = &r300_suspend,
 224         .resume = &r300_resume,
 225         .vga_set_state = &r100_vga_set_state,
 226         .gpu_is_lockup = &r300_gpu_is_lockup,
 227         .asic_reset = &r300_asic_reset,
 228         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 229         .gart_set_page = &r100_pci_gart_set_page,
 230         .cp_commit = &r100_cp_commit,
 231         .ring_start = &r300_ring_start,
 232         .ring_test = &r100_ring_test,
 233         .ring_ib_execute = &r100_ring_ib_execute,
 234         .irq_set = &r100_irq_set,
 235         .irq_process = &r100_irq_process,
 236         .get_vblank_counter = &r100_get_vblank_counter,
 237         .fence_ring_emit = &r300_fence_ring_emit,
 238         .cs_parse = &r300_cs_parse,
 239         .copy_blit = &r100_copy_blit,
 240         .copy_dma = &r200_copy_dma,
 241         .copy = &r100_copy_blit,
 242         .get_engine_clock = &radeon_legacy_get_engine_clock,
 243         .set_engine_clock = &radeon_legacy_set_engine_clock,
 244         .get_memory_clock = &radeon_legacy_get_memory_clock,
 245         .set_memory_clock = NULL,
 246         .get_pcie_lanes = &rv370_get_pcie_lanes,
 247         .set_pcie_lanes = &rv370_set_pcie_lanes,
 248         .set_clock_gating = &radeon_legacy_set_clock_gating,
 249         .set_surface_reg = r100_set_surface_reg,
 250         .clear_surface_reg = r100_clear_surface_reg,
 251         .bandwidth_update = &r100_bandwidth_update,
 252         .hpd_init = &r100_hpd_init,
 253         .hpd_fini = &r100_hpd_fini,
 254         .hpd_sense = &r100_hpd_sense,
 255         .hpd_set_polarity = &r100_hpd_set_polarity,
 256         .ioctl_wait_idle = NULL,
 257         .gui_idle = &r100_gui_idle,
 258         .pm_misc = &r100_pm_misc,
 259         .pm_prepare = &r100_pm_prepare,
 260         .pm_finish = &r100_pm_finish,
 261         .pm_init_profile = &r100_pm_init_profile,
 262         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 263 };
 264
 265 static struct radeon_asic r300_asic_pcie = {
 266         .init = &r300_init,
 267         .fini = &r300_fini,
 268         .suspend = &r300_suspend,
 269         .resume = &r300_resume,
 270         .vga_set_state = &r100_vga_set_state,
 271         .gpu_is_lockup = &r300_gpu_is_lockup,
 272         .asic_reset = &r300_asic_reset,
 273         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 274         .gart_set_page = &rv370_pcie_gart_set_page,
 275         .cp_commit = &r100_cp_commit,
 276         .ring_start = &r300_ring_start,
 277         .ring_test = &r100_ring_test,
 278         .ring_ib_execute = &r100_ring_ib_execute,
 279         .irq_set = &r100_irq_set,
 280         .irq_process = &r100_irq_process,
 281         .get_vblank_counter = &r100_get_vblank_counter,
 282         .fence_ring_emit = &r300_fence_ring_emit,
 283         .cs_parse = &r300_cs_parse,
 284         .copy_blit = &r100_copy_blit,
 285         .copy_dma = &r200_copy_dma,
 286         .copy = &r100_copy_blit,
 287         .get_engine_clock = &radeon_legacy_get_engine_clock,
 288         .set_engine_clock = &radeon_legacy_set_engine_clock,
 289         .get_memory_clock = &radeon_legacy_get_memory_clock,
 290         .set_memory_clock = NULL,
 291         .set_pcie_lanes = &rv370_set_pcie_lanes,
 292         .set_clock_gating = &radeon_legacy_set_clock_gating,
 293         .set_surface_reg = r100_set_surface_reg,
 294         .clear_surface_reg = r100_clear_surface_reg,
 295         .bandwidth_update = &r100_bandwidth_update,
 296         .hpd_init = &r100_hpd_init,
 297         .hpd_fini = &r100_hpd_fini,
 298         .hpd_sense = &r100_hpd_sense,
 299         .hpd_set_polarity = &r100_hpd_set_polarity,
 300         .ioctl_wait_idle = NULL,
 301         .gui_idle = &r100_gui_idle,
 302         .pm_misc = &r100_pm_misc,
 303         .pm_prepare = &r100_pm_prepare,
 304         .pm_finish = &r100_pm_finish,
 305         .pm_init_profile = &r100_pm_init_profile,
 306         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 307 };
 308
 309 static struct radeon_asic r420_asic = {
 310         .init = &r420_init,
 311         .fini = &r420_fini,
 312         .suspend = &r420_suspend,
 313         .resume = &r420_resume,
 314         .vga_set_state = &r100_vga_set_state,
 315         .gpu_is_lockup = &r300_gpu_is_lockup,
 316         .asic_reset = &r300_asic_reset,
 317         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 318         .gart_set_page = &rv370_pcie_gart_set_page,
 319         .cp_commit = &r100_cp_commit,
 320         .ring_start = &r300_ring_start,
 321         .ring_test = &r100_ring_test,
 322         .ring_ib_execute = &r100_ring_ib_execute,
 323         .irq_set = &r100_irq_set,
 324         .irq_process = &r100_irq_process,
 325         .get_vblank_counter = &r100_get_vblank_counter,
 326         .fence_ring_emit = &r300_fence_ring_emit,
 327         .cs_parse = &r300_cs_parse,
 328         .copy_blit = &r100_copy_blit,
 329         .copy_dma = &r200_copy_dma,
 330         .copy = &r100_copy_blit,
 331         .get_engine_clock = &radeon_atom_get_engine_clock,
 332         .set_engine_clock = &radeon_atom_set_engine_clock,
 333         .get_memory_clock = &radeon_atom_get_memory_clock,
 334         .set_memory_clock = &radeon_atom_set_memory_clock,
 335         .get_pcie_lanes = &rv370_get_pcie_lanes,
 336         .set_pcie_lanes = &rv370_set_pcie_lanes,
 337         .set_clock_gating = &radeon_atom_set_clock_gating,
 338         .set_surface_reg = r100_set_surface_reg,
 339         .clear_surface_reg = r100_clear_surface_reg,
 340         .bandwidth_update = &r100_bandwidth_update,
 341         .hpd_init = &r100_hpd_init,
 342         .hpd_fini = &r100_hpd_fini,
 343         .hpd_sense = &r100_hpd_sense,
 344         .hpd_set_polarity = &r100_hpd_set_polarity,
 345         .ioctl_wait_idle = NULL,
 346         .gui_idle = &r100_gui_idle,
 347         .pm_misc = &r100_pm_misc,
 348         .pm_prepare = &r100_pm_prepare,
 349         .pm_finish = &r100_pm_finish,
 350         .pm_init_profile = &r420_pm_init_profile,
 351         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 352 };
 353
 354 static struct radeon_asic rs400_asic = {
 355         .init = &rs400_init,
 356         .fini = &rs400_fini,
 357         .suspend = &rs400_suspend,
 358         .resume = &rs400_resume,
 359         .vga_set_state = &r100_vga_set_state,
 360         .gpu_is_lockup = &r300_gpu_is_lockup,
 361         .asic_reset = &r300_asic_reset,
 362         .gart_tlb_flush = &rs400_gart_tlb_flush,
 363         .gart_set_page = &rs400_gart_set_page,
 364         .cp_commit = &r100_cp_commit,
 365         .ring_start = &r300_ring_start,
 366         .ring_test = &r100_ring_test,
 367         .ring_ib_execute = &r100_ring_ib_execute,
 368         .irq_set = &r100_irq_set,
 369         .irq_process = &r100_irq_process,
 370         .get_vblank_counter = &r100_get_vblank_counter,
 371         .fence_ring_emit = &r300_fence_ring_emit,
 372         .cs_parse = &r300_cs_parse,
 373         .copy_blit = &r100_copy_blit,
 374         .copy_dma = &r200_copy_dma,
 375         .copy = &r100_copy_blit,
 376         .get_engine_clock = &radeon_legacy_get_engine_clock,
 377         .set_engine_clock = &radeon_legacy_set_engine_clock,
 378         .get_memory_clock = &radeon_legacy_get_memory_clock,
 379         .set_memory_clock = NULL,
 380         .get_pcie_lanes = NULL,
 381         .set_pcie_lanes = NULL,
 382         .set_clock_gating = &radeon_legacy_set_clock_gating,
 383         .set_surface_reg = r100_set_surface_reg,
 384         .clear_surface_reg = r100_clear_surface_reg,
 385         .bandwidth_update = &r100_bandwidth_update,
 386         .hpd_init = &r100_hpd_init,
 387         .hpd_fini = &r100_hpd_fini,
 388         .hpd_sense = &r100_hpd_sense,
 389         .hpd_set_polarity = &r100_hpd_set_polarity,
 390         .ioctl_wait_idle = NULL,
 391         .gui_idle = &r100_gui_idle,
 392         .pm_misc = &r100_pm_misc,
 393         .pm_prepare = &r100_pm_prepare,
 394         .pm_finish = &r100_pm_finish,
 395         .pm_init_profile = &r100_pm_init_profile,
 396         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 397 };
 398
 399 static struct radeon_asic rs600_asic = {
 400         .init = &rs600_init,
 401         .fini = &rs600_fini,
 402         .suspend = &rs600_suspend,
 403         .resume = &rs600_resume,
 404         .vga_set_state = &r100_vga_set_state,
 405         .gpu_is_lockup = &r300_gpu_is_lockup,
 406         .asic_reset = &rs600_asic_reset,
 407         .gart_tlb_flush = &rs600_gart_tlb_flush,
 408         .gart_set_page = &rs600_gart_set_page,
 409         .cp_commit = &r100_cp_commit,
 410         .ring_start = &r300_ring_start,
 411         .ring_test = &r100_ring_test,
 412         .ring_ib_execute = &r100_ring_ib_execute,
 413         .irq_set = &rs600_irq_set,
 414         .irq_process = &rs600_irq_process,
 415         .get_vblank_counter = &rs600_get_vblank_counter,
 416         .fence_ring_emit = &r300_fence_ring_emit,
 417         .cs_parse = &r300_cs_parse,
 418         .copy_blit = &r100_copy_blit,
 419         .copy_dma = &r200_copy_dma,
 420         .copy = &r100_copy_blit,
 421         .get_engine_clock = &radeon_atom_get_engine_clock,
 422         .set_engine_clock = &radeon_atom_set_engine_clock,
 423         .get_memory_clock = &radeon_atom_get_memory_clock,
 424         .set_memory_clock = &radeon_atom_set_memory_clock,
 425         .get_pcie_lanes = NULL,
 426         .set_pcie_lanes = NULL,
 427         .set_clock_gating = &radeon_atom_set_clock_gating,
 428         .set_surface_reg = r100_set_surface_reg,
 429         .clear_surface_reg = r100_clear_surface_reg,
 430         .bandwidth_update = &rs600_bandwidth_update,
 431         .hpd_init = &rs600_hpd_init,
 432         .hpd_fini = &rs600_hpd_fini,
 433         .hpd_sense = &rs600_hpd_sense,
 434         .hpd_set_polarity = &rs600_hpd_set_polarity,
 435         .ioctl_wait_idle = NULL,
 436         .gui_idle = &r100_gui_idle,
 437         .pm_misc = &rs600_pm_misc,
 438         .pm_prepare = &rs600_pm_prepare,
 439         .pm_finish = &rs600_pm_finish,
 440         .pm_init_profile = &r420_pm_init_profile,
 441         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 442 };
 443
 444 static struct radeon_asic rs690_asic = {
 445         .init = &rs690_init,
 446         .fini = &rs690_fini,
 447         .suspend = &rs690_suspend,
 448         .resume = &rs690_resume,
 449         .vga_set_state = &r100_vga_set_state,
 450         .gpu_is_lockup = &r300_gpu_is_lockup,
 451         .asic_reset = &rs600_asic_reset,
 452         .gart_tlb_flush = &rs400_gart_tlb_flush,
 453         .gart_set_page = &rs400_gart_set_page,
 454         .cp_commit = &r100_cp_commit,
 455         .ring_start = &r300_ring_start,
 456         .ring_test = &r100_ring_test,
 457         .ring_ib_execute = &r100_ring_ib_execute,
 458         .irq_set = &rs600_irq_set,
 459         .irq_process = &rs600_irq_process,
 460         .get_vblank_counter = &rs600_get_vblank_counter,
 461         .fence_ring_emit = &r300_fence_ring_emit,
 462         .cs_parse = &r300_cs_parse,
 463         .copy_blit = &r100_copy_blit,
 464         .copy_dma = &r200_copy_dma,
 465         .copy = &r200_copy_dma,
 466         .get_engine_clock = &radeon_atom_get_engine_clock,
 467         .set_engine_clock = &radeon_atom_set_engine_clock,
 468         .get_memory_clock = &radeon_atom_get_memory_clock,
 469         .set_memory_clock = &radeon_atom_set_memory_clock,
 470         .get_pcie_lanes = NULL,
 471         .set_pcie_lanes = NULL,
 472         .set_clock_gating = &radeon_atom_set_clock_gating,
 473         .set_surface_reg = r100_set_surface_reg,
 474         .clear_surface_reg = r100_clear_surface_reg,
 475         .bandwidth_update = &rs690_bandwidth_update,
 476         .hpd_init = &rs600_hpd_init,
 477         .hpd_fini = &rs600_hpd_fini,
 478         .hpd_sense = &rs600_hpd_sense,
 479         .hpd_set_polarity = &rs600_hpd_set_polarity,
 480         .ioctl_wait_idle = NULL,
 481         .gui_idle = &r100_gui_idle,
 482         .pm_misc = &rs600_pm_misc,
 483         .pm_prepare = &rs600_pm_prepare,
 484         .pm_finish = &rs600_pm_finish,
 485         .pm_init_profile = &r420_pm_init_profile,
 486         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 487 };
 488
 489 static struct radeon_asic rv515_asic = {
 490         .init = &rv515_init,
 491         .fini = &rv515_fini,
 492         .suspend = &rv515_suspend,
 493         .resume = &rv515_resume,
 494         .vga_set_state = &r100_vga_set_state,
 495         .gpu_is_lockup = &r300_gpu_is_lockup,
 496         .asic_reset = &rs600_asic_reset,
 497         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 498         .gart_set_page = &rv370_pcie_gart_set_page,
 499         .cp_commit = &r100_cp_commit,
 500         .ring_start = &rv515_ring_start,
 501         .ring_test = &r100_ring_test,
 502         .ring_ib_execute = &r100_ring_ib_execute,
 503         .irq_set = &rs600_irq_set,
 504         .irq_process = &rs600_irq_process,
 505         .get_vblank_counter = &rs600_get_vblank_counter,
 506         .fence_ring_emit = &r300_fence_ring_emit,
 507         .cs_parse = &r300_cs_parse,
 508         .copy_blit = &r100_copy_blit,
 509         .copy_dma = &r200_copy_dma,
 510         .copy = &r100_copy_blit,
 511         .get_engine_clock = &radeon_atom_get_engine_clock,
 512         .set_engine_clock = &radeon_atom_set_engine_clock,
 513         .get_memory_clock = &radeon_atom_get_memory_clock,
 514         .set_memory_clock = &radeon_atom_set_memory_clock,
 515         .get_pcie_lanes = &rv370_get_pcie_lanes,
 516         .set_pcie_lanes = &rv370_set_pcie_lanes,
 517         .set_clock_gating = &radeon_atom_set_clock_gating,
 518         .set_surface_reg = r100_set_surface_reg,
 519         .clear_surface_reg = r100_clear_surface_reg,
 520         .bandwidth_update = &rv515_bandwidth_update,
 521         .hpd_init = &rs600_hpd_init,
 522         .hpd_fini = &rs600_hpd_fini,
 523         .hpd_sense = &rs600_hpd_sense,
 524         .hpd_set_polarity = &rs600_hpd_set_polarity,
 525         .ioctl_wait_idle = NULL,
 526         .gui_idle = &r100_gui_idle,
 527         .pm_misc = &rs600_pm_misc,
 528         .pm_prepare = &rs600_pm_prepare,
 529         .pm_finish = &rs600_pm_finish,
 530         .pm_init_profile = &r420_pm_init_profile,
 531         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 532 };
 533
 534 static struct radeon_asic r520_asic = {
 535         .init = &r520_init,
 536         .fini = &rv515_fini,
 537         .suspend = &rv515_suspend,
 538         .resume = &r520_resume,
 539         .vga_set_state = &r100_vga_set_state,
 540         .gpu_is_lockup = &r300_gpu_is_lockup,
 541         .asic_reset = &rs600_asic_reset,
 542         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 543         .gart_set_page = &rv370_pcie_gart_set_page,
 544         .cp_commit = &r100_cp_commit,
 545         .ring_start = &rv515_ring_start,
 546         .ring_test = &r100_ring_test,
 547         .ring_ib_execute = &r100_ring_ib_execute,
 548         .irq_set = &rs600_irq_set,
 549         .irq_process = &rs600_irq_process,
 550         .get_vblank_counter = &rs600_get_vblank_counter,
 551         .fence_ring_emit = &r300_fence_ring_emit,
 552         .cs_parse = &r300_cs_parse,
 553         .copy_blit = &r100_copy_blit,
 554         .copy_dma = &r200_copy_dma,
 555         .copy = &r100_copy_blit,
 556         .get_engine_clock = &radeon_atom_get_engine_clock,
 557         .set_engine_clock = &radeon_atom_set_engine_clock,
 558         .get_memory_clock = &radeon_atom_get_memory_clock,
 559         .set_memory_clock = &radeon_atom_set_memory_clock,
 560         .get_pcie_lanes = &rv370_get_pcie_lanes,
 561         .set_pcie_lanes = &rv370_set_pcie_lanes,
 562         .set_clock_gating = &radeon_atom_set_clock_gating,
 563         .set_surface_reg = r100_set_surface_reg,
 564         .clear_surface_reg = r100_clear_surface_reg,
 565         .bandwidth_update = &rv515_bandwidth_update,
 566         .hpd_init = &rs600_hpd_init,
 567         .hpd_fini = &rs600_hpd_fini,
 568         .hpd_sense = &rs600_hpd_sense,
 569         .hpd_set_polarity = &rs600_hpd_set_polarity,
 570         .ioctl_wait_idle = NULL,
 571         .gui_idle = &r100_gui_idle,
 572         .pm_misc = &rs600_pm_misc,
 573         .pm_prepare = &rs600_pm_prepare,
 574         .pm_finish = &rs600_pm_finish,
 575         .pm_init_profile = &r420_pm_init_profile,
 576         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 577 };
 578
 579 static struct radeon_asic r600_asic = {
 580         .init = &r600_init,
 581         .fini = &r600_fini,
 582         .suspend = &r600_suspend,
 583         .resume = &r600_resume,
 584         .cp_commit = &r600_cp_commit,
 585         .vga_set_state = &r600_vga_set_state,
 586         .gpu_is_lockup = &r600_gpu_is_lockup,
 587         .asic_reset = &r600_asic_reset,
 588         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 589         .gart_set_page = &rs600_gart_set_page,
 590         .ring_test = &r600_ring_test,
 591         .ring_ib_execute = &r600_ring_ib_execute,
 592         .irq_set = &r600_irq_set,
 593         .irq_process = &r600_irq_process,
 594         .get_vblank_counter = &rs600_get_vblank_counter,
 595         .fence_ring_emit = &r600_fence_ring_emit,
 596         .cs_parse = &r600_cs_parse,
 597         .copy_blit = &r600_copy_blit,
 598         .copy_dma = &r600_copy_blit,
 599         .copy = &r600_copy_blit,
 600         .get_engine_clock = &radeon_atom_get_engine_clock,
 601         .set_engine_clock = &radeon_atom_set_engine_clock,
 602         .get_memory_clock = &radeon_atom_get_memory_clock,
 603         .set_memory_clock = &radeon_atom_set_memory_clock,
 604         .get_pcie_lanes = &rv370_get_pcie_lanes,
 605         .set_pcie_lanes = NULL,
 606         .set_clock_gating = NULL,
 607         .set_surface_reg = r600_set_surface_reg,
 608         .clear_surface_reg = r600_clear_surface_reg,
 609         .bandwidth_update = &rv515_bandwidth_update,
 610         .hpd_init = &r600_hpd_init,
 611         .hpd_fini = &r600_hpd_fini,
 612         .hpd_sense = &r600_hpd_sense,
 613         .hpd_set_polarity = &r600_hpd_set_polarity,
 614         .ioctl_wait_idle = r600_ioctl_wait_idle,
 615         .gui_idle = &r600_gui_idle,
 616         .pm_misc = &r600_pm_misc,
 617         .pm_prepare = &rs600_pm_prepare,
 618         .pm_finish = &rs600_pm_finish,
 619         .pm_init_profile = &r600_pm_init_profile,
 620         .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 621 };
 622
 623 static struct radeon_asic rs780_asic = {
 624         .init = &r600_init,
 625         .fini = &r600_fini,
 626         .suspend = &r600_suspend,
 627         .resume = &r600_resume,
 628         .cp_commit = &r600_cp_commit,
 629         .gpu_is_lockup = &r600_gpu_is_lockup,
 630         .vga_set_state = &r600_vga_set_state,
 631         .asic_reset = &r600_asic_reset,
 632         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 633         .gart_set_page = &rs600_gart_set_page,
 634         .ring_test = &r600_ring_test,
 635         .ring_ib_execute = &r600_ring_ib_execute,
 636         .irq_set = &r600_irq_set,
 637         .irq_process = &r600_irq_process,
 638         .get_vblank_counter = &rs600_get_vblank_counter,
 639         .fence_ring_emit = &r600_fence_ring_emit,
 640         .cs_parse = &r600_cs_parse,
 641         .copy_blit = &r600_copy_blit,
 642         .copy_dma = &r600_copy_blit,
 643         .copy = &r600_copy_blit,
 644         .get_engine_clock = &radeon_atom_get_engine_clock,
 645         .set_engine_clock = &radeon_atom_set_engine_clock,
 646         .get_memory_clock = NULL,
 647         .set_memory_clock = NULL,
 648         .get_pcie_lanes = NULL,
 649         .set_pcie_lanes = NULL,
 650         .set_clock_gating = NULL,
 651         .set_surface_reg = r600_set_surface_reg,
 652         .clear_surface_reg = r600_clear_surface_reg,
 653         .bandwidth_update = &rs690_bandwidth_update,
 654         .hpd_init = &r600_hpd_init,
 655         .hpd_fini = &r600_hpd_fini,
 656         .hpd_sense = &r600_hpd_sense,
 657         .hpd_set_polarity = &r600_hpd_set_polarity,
 658         .ioctl_wait_idle = r600_ioctl_wait_idle,
 659         .gui_idle = &r600_gui_idle,
 660         .pm_misc = &r600_pm_misc,
 661         .pm_prepare = &rs600_pm_prepare,
 662         .pm_finish = &rs600_pm_finish,
 663         .pm_init_profile = &rs780_pm_init_profile,
 664         .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 665 };
 666
 667 static struct radeon_asic rv770_asic = {
 668         .init = &rv770_init,
 669         .fini = &rv770_fini,
 670         .suspend = &rv770_suspend,
 671         .resume = &rv770_resume,
 672         .cp_commit = &r600_cp_commit,
 673         .asic_reset = &r600_asic_reset,
 674         .gpu_is_lockup = &r600_gpu_is_lockup,
 675         .vga_set_state = &r600_vga_set_state,
 676         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 677         .gart_set_page = &rs600_gart_set_page,
 678         .ring_test = &r600_ring_test,
 679         .ring_ib_execute = &r600_ring_ib_execute,
 680         .irq_set = &r600_irq_set,
 681         .irq_process = &r600_irq_process,
 682         .get_vblank_counter = &rs600_get_vblank_counter,
 683         .fence_ring_emit = &r600_fence_ring_emit,
 684         .cs_parse = &r600_cs_parse,
 685         .copy_blit = &r600_copy_blit,
 686         .copy_dma = &r600_copy_blit,
 687         .copy = &r600_copy_blit,
 688         .get_engine_clock = &radeon_atom_get_engine_clock,
 689         .set_engine_clock = &radeon_atom_set_engine_clock,
 690         .get_memory_clock = &radeon_atom_get_memory_clock,
 691         .set_memory_clock = &radeon_atom_set_memory_clock,
 692         .get_pcie_lanes = &rv370_get_pcie_lanes,
 693         .set_pcie_lanes = NULL,
 694         .set_clock_gating = &radeon_atom_set_clock_gating,
 695         .set_surface_reg = r600_set_surface_reg,
 696         .clear_surface_reg = r600_clear_surface_reg,
 697         .bandwidth_update = &rv515_bandwidth_update,
 698         .hpd_init = &r600_hpd_init,
 699         .hpd_fini = &r600_hpd_fini,
 700         .hpd_sense = &r600_hpd_sense,
 701         .hpd_set_polarity = &r600_hpd_set_polarity,
 702         .ioctl_wait_idle = r600_ioctl_wait_idle,
 703         .gui_idle = &r600_gui_idle,
 704         .pm_misc = &rv770_pm_misc,
 705         .pm_prepare = &rs600_pm_prepare,
 706         .pm_finish = &rs600_pm_finish,
 707         .pm_init_profile = &r600_pm_init_profile,
 708         .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 709 };
 710
 711 static struct radeon_asic evergreen_asic = {
 712         .init = &evergreen_init,
 713         .fini = &evergreen_fini,
 714         .suspend = &evergreen_suspend,
 715         .resume = &evergreen_resume,
 716         .cp_commit = &r600_cp_commit,
 717         .gpu_is_lockup = &evergreen_gpu_is_lockup,
 718         .asic_reset = &evergreen_asic_reset,
 719         .vga_set_state = &r600_vga_set_state,
 720         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
 721         .gart_set_page = &rs600_gart_set_page,
 722         .ring_test = &r600_ring_test,
 723         .ring_ib_execute = &r600_ring_ib_execute,
 724         .irq_set = &evergreen_irq_set,
 725         .irq_process = &evergreen_irq_process,
 726         .get_vblank_counter = &evergreen_get_vblank_counter,
 727         .fence_ring_emit = NULL,
 728         .cs_parse = NULL,
 729         .copy_blit = NULL,
 730         .copy_dma = NULL,
 731         .copy = NULL,
 732         .get_engine_clock = &radeon_atom_get_engine_clock,
 733         .set_engine_clock = &radeon_atom_set_engine_clock,
 734         .get_memory_clock = &radeon_atom_get_memory_clock,
 735         .set_memory_clock = &radeon_atom_set_memory_clock,
 736         .set_pcie_lanes = NULL,
 737         .set_clock_gating = NULL,
 738         .set_surface_reg = r600_set_surface_reg,
 739         .clear_surface_reg = r600_clear_surface_reg,
 740         .bandwidth_update = &evergreen_bandwidth_update,
 741         .hpd_init = &evergreen_hpd_init,
 742         .hpd_fini = &evergreen_hpd_fini,
 743         .hpd_sense = &evergreen_hpd_sense,
 744         .hpd_set_polarity = &evergreen_hpd_set_polarity,
 745         .gui_idle = &r600_gui_idle,
 746         .pm_misc = &evergreen_pm_misc,
 747         .pm_prepare = &evergreen_pm_prepare,
 748         .pm_finish = &evergreen_pm_finish,
 749         .pm_init_profile = &r600_pm_init_profile,
 750         .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 751 };
 752
 753 int radeon_asic_init(struct radeon_device *rdev)
 754 {
 755         radeon_register_accessor_init(rdev);
 756         switch (rdev->family) {
 757         case CHIP_R100:
 758         case CHIP_RV100:
 759         case CHIP_RS100:
 760         case CHIP_RV200:
 761         case CHIP_RS200:
 762                 rdev->asic = &r100_asic;
 763                 break;
 764         case CHIP_R200:
 765         case CHIP_RV250:
 766         case CHIP_RS300:
 767         case CHIP_RV280:
 768                 rdev->asic = &r200_asic;
 769                 break;
 770         case CHIP_R300:
 771         case CHIP_R350:
 772         case CHIP_RV350:
 773         case CHIP_RV380:
 774                 if (rdev->flags & RADEON_IS_PCIE)
 775                         rdev->asic = &r300_asic_pcie;
 776                 else
 777                         rdev->asic = &r300_asic;
 778                 break;
 779         case CHIP_R420:
 780         case CHIP_R423:
 781         case CHIP_RV410:
 782                 rdev->asic = &r420_asic;
 783                 break;
 784         case CHIP_RS400:
 785         case CHIP_RS480:
 786                 rdev->asic = &rs400_asic;
 787                 break;
 788         case CHIP_RS600:
 789                 rdev->asic = &rs600_asic;
 790                 break;
 791         case CHIP_RS690:
 792         case CHIP_RS740:
 793                 rdev->asic = &rs690_asic;
 794                 break;
 795         case CHIP_RV515:
 796                 rdev->asic = &rv515_asic;
 797                 break;
 798         case CHIP_R520:
 799         case CHIP_RV530:
 800         case CHIP_RV560:
 801         case CHIP_RV570:
 802         case CHIP_R580:
 803                 rdev->asic = &r520_asic;
 804                 break;
 805         case CHIP_R600:
 806         case CHIP_RV610:
 807         case CHIP_RV630:
 808         case CHIP_RV620:
 809         case CHIP_RV635:
 810         case CHIP_RV670:
 811                 rdev->asic = &r600_asic;
 812                 break;
 813         case CHIP_RS780:
 814         case CHIP_RS880:
 815                 rdev->asic = &rs780_asic;
 816                 break;
 817         case CHIP_RV770:
 818         case CHIP_RV730:
 819         case CHIP_RV710:
 820         case CHIP_RV740:
 821                 rdev->asic = &rv770_asic;
 822                 break;
 823         case CHIP_CEDAR:
 824         case CHIP_REDWOOD:
 825         case CHIP_JUNIPER:
 826         case CHIP_CYPRESS:
 827         case CHIP_HEMLOCK:
 828                 rdev->asic = &evergreen_asic;
 829                 break;
 830         default:
 831                 /* FIXME: not supported yet */
 832                 return -EINVAL;
 833         }
 834
 835         if (rdev->flags & RADEON_IS_IGP) {
 836                 rdev->asic->get_memory_clock = NULL;
 837                 rdev->asic->set_memory_clock = NULL;
 838         }
 839
 840         /* set the number of crtcs */
 841         if (rdev->flags & RADEON_SINGLE_CRTC)
 842                 rdev->num_crtc = 1;
 843         else {
 844                 if (ASIC_IS_DCE4(rdev))
 845                         rdev->num_crtc = 6;
 846                 else
 847                         rdev->num_crtc = 2;
 848         }
 849
 850         return 0;
 851 }
 852
 853 /*
 854  * Wrapper around modesetting bits. Move to radeon_clocks.c?
 855  */
 856 int radeon_clocks_init(struct radeon_device *rdev)
 857 {
 858         int r;
 859
 860         r = radeon_static_clocks_init(rdev->ddev);
 861         if (r) {
 862                 return r;
 863         }
 864         DRM_INFO("Clocks initialized !\n");
 865         return 0;
 866 }
 867
 868 void radeon_clocks_fini(struct radeon_device *rdev)
 869 {
 870 }