[PATCH] swsusp: add architecture special saveable pages support
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / include / asm-i386 / apic.h
blob1d8362cb2c5da98e28551297eddb26fd11b9a448
1 #ifndef __ASM_APIC_H
2 #define __ASM_APIC_H
4 #include <linux/pm.h>
5 #include <asm/fixmap.h>
6 #include <asm/apicdef.h>
7 #include <asm/processor.h>
8 #include <asm/system.h>
10 #define Dprintk(x...)
13 * Debugging macros
15 #define APIC_QUIET 0
16 #define APIC_VERBOSE 1
17 #define APIC_DEBUG 2
19 extern int enable_local_apic;
20 extern int apic_verbosity;
22 static inline void lapic_disable(void)
24 enable_local_apic = -1;
25 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
28 static inline void lapic_enable(void)
30 enable_local_apic = 1;
34 * Define the default level of output to be very little
35 * This can be turned up by using apic=verbose for more
36 * information and apic=debug for _lots_ of information.
37 * apic_verbosity is defined in apic.c
39 #define apic_printk(v, s, a...) do { \
40 if ((v) <= apic_verbosity) \
41 printk(s, ##a); \
42 } while (0)
45 #ifdef CONFIG_X86_LOCAL_APIC
48 * Basic functions accessing APICs.
51 static __inline void apic_write(unsigned long reg, unsigned long v)
53 *((volatile unsigned long *)(APIC_BASE+reg)) = v;
56 static __inline void apic_write_atomic(unsigned long reg, unsigned long v)
58 xchg((volatile unsigned long *)(APIC_BASE+reg), v);
61 static __inline unsigned long apic_read(unsigned long reg)
63 return *((volatile unsigned long *)(APIC_BASE+reg));
66 static __inline__ void apic_wait_icr_idle(void)
68 while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY )
69 cpu_relax();
72 int get_physical_broadcast(void);
74 #ifdef CONFIG_X86_GOOD_APIC
75 # define FORCE_READ_AROUND_WRITE 0
76 # define apic_read_around(x)
77 # define apic_write_around(x,y) apic_write((x),(y))
78 #else
79 # define FORCE_READ_AROUND_WRITE 1
80 # define apic_read_around(x) apic_read(x)
81 # define apic_write_around(x,y) apic_write_atomic((x),(y))
82 #endif
84 static inline void ack_APIC_irq(void)
87 * ack_APIC_irq() actually gets compiled as a single instruction:
88 * - a single rmw on Pentium/82489DX
89 * - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
90 * ... yummie.
93 /* Docs say use 0 for future compatibility */
94 apic_write_around(APIC_EOI, 0);
97 extern void (*wait_timer_tick)(void);
99 extern int get_maxlvt(void);
100 extern void clear_local_APIC(void);
101 extern void connect_bsp_APIC (void);
102 extern void disconnect_bsp_APIC (int virt_wire_setup);
103 extern void disable_local_APIC (void);
104 extern void lapic_shutdown (void);
105 extern int verify_local_APIC (void);
106 extern void cache_APIC_registers (void);
107 extern void sync_Arb_IDs (void);
108 extern void init_bsp_APIC (void);
109 extern void setup_local_APIC (void);
110 extern void init_apic_mappings (void);
111 extern void smp_local_timer_interrupt (struct pt_regs * regs);
112 extern void setup_boot_APIC_clock (void);
113 extern void setup_secondary_APIC_clock (void);
114 extern void setup_apic_nmi_watchdog (void);
115 extern int reserve_lapic_nmi(void);
116 extern void release_lapic_nmi(void);
117 extern void disable_timer_nmi_watchdog(void);
118 extern void enable_timer_nmi_watchdog(void);
119 extern void nmi_watchdog_tick (struct pt_regs * regs);
120 extern int APIC_init_uniprocessor (void);
121 extern void disable_APIC_timer(void);
122 extern void enable_APIC_timer(void);
124 extern void enable_NMI_through_LVT0 (void * dummy);
126 extern unsigned int nmi_watchdog;
127 #define NMI_NONE 0
128 #define NMI_IO_APIC 1
129 #define NMI_LOCAL_APIC 2
130 #define NMI_INVALID 3
132 extern int disable_timer_pin_1;
134 void smp_send_timer_broadcast_ipi(struct pt_regs *regs);
135 void switch_APIC_timer_to_ipi(void *cpumask);
136 void switch_ipi_to_APIC_timer(void *cpumask);
137 #define ARCH_APICTIMER_STOPS_ON_C3 1
139 extern int timer_over_8254;
141 #else /* !CONFIG_X86_LOCAL_APIC */
142 static inline void lapic_shutdown(void) { }
144 #endif /* !CONFIG_X86_LOCAL_APIC */
146 #endif /* __ASM_APIC_H */