arch/arm/mach-davinci/clock.h

   1 /*
   2  * TI DaVinci clock definitions
   3  *
   4  * Copyright (C) 2006-2007 Texas Instruments.
   5  * Copyright (C) 2008-2009 Deep Root Systems, LLC
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #ifndef __ARCH_ARM_DAVINCI_CLOCK_H
  13 #define __ARCH_ARM_DAVINCI_CLOCK_H
  14
  15 #include <linux/list.h>
  16 #include <asm/clkdev.h>
  17
  18 #define DAVINCI_PLL1_BASE 0x01c40800
  19 #define DAVINCI_PLL2_BASE 0x01c40c00
  20 #define MAX_PLL 2
  21
  22 /* PLL/Reset register offsets */
  23 #define PLLCTL          0x100
  24 #define PLLCTL_PLLEN    BIT(0)
  25 #define PLLCTL_PLLPWRDN BIT(1)
  26 #define PLLCTL_PLLRST   BIT(3)
  27 #define PLLCTL_PLLDIS   BIT(4)
  28 #define PLLCTL_PLLENSRC BIT(5)
  29 #define PLLCTL_CLKMODE  BIT(8)
  30
  31 #define PLLM            0x110
  32 #define PLLM_PLLM_MASK  0xff
  33
  34 #define PREDIV          0x114
  35 #define PLLDIV1         0x118
  36 #define PLLDIV2         0x11c
  37 #define PLLDIV3         0x120
  38 #define POSTDIV         0x128
  39 #define BPDIV           0x12c
  40 #define PLLCMD          0x138
  41 #define PLLSTAT         0x13c
  42 #define PLLALNCTL       0x140
  43 #define PLLDCHANGE      0x144
  44 #define PLLCKEN         0x148
  45 #define PLLCKSTAT       0x14c
  46 #define PLLSYSTAT       0x150
  47 #define PLLDIV4         0x160
  48 #define PLLDIV5         0x164
  49 #define PLLDIV6         0x168
  50 #define PLLDIV7         0x16c
  51 #define PLLDIV8         0x170
  52 #define PLLDIV9         0x174
  53 #define PLLDIV_EN       BIT(15)
  54 #define PLLDIV_RATIO_MASK 0x1f
  55
  56 struct pll_data {
  57         u32 phys_base;
  58         void __iomem *base;
  59         u32 num;
  60         u32 flags;
  61         u32 input_rate;
  62 };
  63 #define PLL_HAS_PREDIV          0x01
  64 #define PLL_HAS_POSTDIV         0x02
  65
  66 struct clk {
  67         struct list_head        node;
  68         struct module           *owner;
  69         const char              *name;
  70         unsigned long           rate;
  71         u8                      usecount;
  72         u8                      lpsc;
  73         u8                      gpsc;
  74         u32                     flags;
  75         struct clk              *parent;
  76         struct list_head        children;       /* list of children */
  77         struct list_head        childnode;      /* parent's child list node */
  78         struct pll_data         *pll_data;
  79         u32                     div_reg;
  80         unsigned long (*recalc) (struct clk *);
  81         int (*set_rate) (struct clk *clk, unsigned long rate);
  82         int (*round_rate) (struct clk *clk, unsigned long rate);
  83 };
  84
  85 /* Clock flags: SoC-specific flags start at BIT(16) */
  86 #define ALWAYS_ENABLED          BIT(1)
  87 #define CLK_PSC                 BIT(2)
  88 #define PSC_DSP                 BIT(3) /* PSC uses DSP domain, not ARM */
  89 #define CLK_PLL                 BIT(4) /* PLL-derived clock */
  90 #define PRE_PLL                 BIT(5) /* source is before PLL mult/div */
  91
  92 struct davinci_clk {
  93         struct clk_lookup lk;
  94 };
  95
  96 #define CLK(dev, con, ck)               \
  97         {                               \
  98                 .lk = {                 \
  99                         .dev_id = dev,  \
 100                         .con_id = con,  \
 101                         .clk = ck,      \
 102                 },                      \
 103         }
 104
 105 int davinci_clk_init(struct davinci_clk *clocks);
 106 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
 107                                 unsigned int mult, unsigned int postdiv);
 108
 109 extern struct platform_device davinci_wdt_device;
 110
 111 #endif