2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include <linux/kallsyms.h>
25 #include <linux/dmi.h>
26 #include <linux/pci-aspm.h>
27 #include <linux/ioport.h>
28 #include <asm/dma.h> /* isa_dma_bridge_buggy */
32 * This quirk function disables memory decoding and releases memory resources
33 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
34 * It also rounds up size to specified alignment.
35 * Later on, the kernel will assign page-aligned memory resource back
38 static void __devinit
quirk_resource_alignment(struct pci_dev
*dev
)
42 resource_size_t align
, size
;
45 if (!pci_is_reassigndev(dev
))
48 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
49 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
51 "Can't reassign resources to host bridge.\n");
56 "Disabling memory decoding and releasing memory resources.\n");
57 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
58 command
&= ~PCI_COMMAND_MEMORY
;
59 pci_write_config_word(dev
, PCI_COMMAND
, command
);
61 align
= pci_specified_resource_alignment(dev
);
62 for (i
=0; i
< PCI_BRIDGE_RESOURCES
; i
++) {
63 r
= &dev
->resource
[i
];
64 if (!(r
->flags
& IORESOURCE_MEM
))
66 size
= resource_size(r
);
70 "Rounding up size of resource #%d to %#llx.\n",
71 i
, (unsigned long long)size
);
76 /* Need to disable bridge's resource window,
77 * to enable the kernel to reassign new resource
80 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
81 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
82 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
83 r
= &dev
->resource
[i
];
84 if (!(r
->flags
& IORESOURCE_MEM
))
86 r
->end
= resource_size(r
) - 1;
89 pci_disable_bridge_window(dev
);
92 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, quirk_resource_alignment
);
95 * Decoding should be disabled for a PCI device during BAR sizing to avoid
96 * conflict. But doing so may cause problems on host bridge and perhaps other
97 * key system devices. For devices that need to have mmio decoding always-on,
98 * we need to set the dev->mmio_always_on bit.
100 static void __devinit
quirk_mmio_always_on(struct pci_dev
*dev
)
102 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
)
103 dev
->mmio_always_on
= 1;
105 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID
, PCI_ANY_ID
, quirk_mmio_always_on
);
107 /* The Mellanox Tavor device gives false positive parity errors
108 * Mark this device with a broken_parity_status, to allow
109 * PCI scanning code to "skip" this now blacklisted device.
111 static void __devinit
quirk_mellanox_tavor(struct pci_dev
*dev
)
113 dev
->broken_parity_status
= 1; /* This device gives false positives */
115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
,PCI_DEVICE_ID_MELLANOX_TAVOR
,quirk_mellanox_tavor
);
116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE
,quirk_mellanox_tavor
);
118 /* Deal with broken BIOS'es that neglect to enable passive release,
119 which can cause problems in combination with the 82441FX/PPro MTRRs */
120 static void quirk_passive_release(struct pci_dev
*dev
)
122 struct pci_dev
*d
= NULL
;
125 /* We have to make sure a particular bit is set in the PIIX3
126 ISA bridge, so we have to go out and find it. */
127 while ((d
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
128 pci_read_config_byte(d
, 0x82, &dlc
);
130 dev_info(&d
->dev
, "PIIX3: Enabling Passive Release\n");
132 pci_write_config_byte(d
, 0x82, dlc
);
136 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
137 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
139 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
140 but VIA don't answer queries. If you happen to have good contacts at VIA
141 ask them for me please -- Alan
143 This appears to be BIOS not version dependent. So presumably there is a
146 static void __devinit
quirk_isa_dma_hangs(struct pci_dev
*dev
)
148 if (!isa_dma_bridge_buggy
) {
149 isa_dma_bridge_buggy
=1;
150 dev_info(&dev
->dev
, "Activating ISA DMA hang workarounds\n");
154 * Its not totally clear which chipsets are the problematic ones
155 * We know 82C586 and 82C596 variants are affected.
157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
);
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C596
, quirk_isa_dma_hangs
);
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, quirk_isa_dma_hangs
);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, quirk_isa_dma_hangs
);
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_1
, quirk_isa_dma_hangs
);
162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_2
, quirk_isa_dma_hangs
);
163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_3
, quirk_isa_dma_hangs
);
166 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
167 * for some HT machines to use C4 w/o hanging.
169 static void __devinit
quirk_tigerpoint_bm_sts(struct pci_dev
*dev
)
174 pci_read_config_dword(dev
, 0x40, &pmbase
);
175 pmbase
= pmbase
& 0xff80;
179 dev_info(&dev
->dev
, FW_BUG
"TigerPoint LPC.BM_STS cleared\n");
183 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_TGP_LPC
, quirk_tigerpoint_bm_sts
);
186 * Chipsets where PCI->PCI transfers vanish or hang
188 static void __devinit
quirk_nopcipci(struct pci_dev
*dev
)
190 if ((pci_pci_problems
& PCIPCI_FAIL
)==0) {
191 dev_info(&dev
->dev
, "Disabling direct PCI/PCI transfers\n");
192 pci_pci_problems
|= PCIPCI_FAIL
;
195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, quirk_nopcipci
);
196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_496
, quirk_nopcipci
);
198 static void __devinit
quirk_nopciamd(struct pci_dev
*dev
)
201 pci_read_config_byte(dev
, 0x08, &rev
);
204 dev_info(&dev
->dev
, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
205 pci_pci_problems
|= PCIAGP_FAIL
;
208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8151_0
, quirk_nopciamd
);
211 * Triton requires workarounds to be used by the drivers
213 static void __devinit
quirk_triton(struct pci_dev
*dev
)
215 if ((pci_pci_problems
&PCIPCI_TRITON
)==0) {
216 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
217 pci_pci_problems
|= PCIPCI_TRITON
;
220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437
, quirk_triton
);
221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
, quirk_triton
);
222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439
, quirk_triton
);
223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439TX
, quirk_triton
);
226 * VIA Apollo KT133 needs PCI latency patch
227 * Made according to a windows driver based patch by George E. Breese
228 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
229 * and http://www.georgebreese.com/net/software/#PCI
230 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
231 * the info on which Mr Breese based his work.
233 * Updated based on further information from the site and also on
234 * information provided by VIA
236 static void quirk_vialatency(struct pci_dev
*dev
)
240 /* Ok we have a potential problem chipset here. Now see if we have
241 a buggy southbridge */
243 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, NULL
);
245 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
246 /* Check for buggy part revisions */
247 if (p
->revision
< 0x40 || p
->revision
> 0x42)
250 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
251 if (p
==NULL
) /* No problem parts */
253 /* Check for buggy part revisions */
254 if (p
->revision
< 0x10 || p
->revision
> 0x12)
259 * Ok we have the problem. Now set the PCI master grant to
260 * occur every master grant. The apparent bug is that under high
261 * PCI load (quite common in Linux of course) you can get data
262 * loss when the CPU is held off the bus for 3 bus master requests
263 * This happens to include the IDE controllers....
265 * VIA only apply this fix when an SB Live! is present but under
266 * both Linux and Windows this isnt enough, and we have seen
267 * corruption without SB Live! but with things like 3 UDMA IDE
268 * controllers. So we ignore that bit of the VIA recommendation..
271 pci_read_config_byte(dev
, 0x76, &busarb
);
272 /* Set bit 4 and bi 5 of byte 76 to 0x01
273 "Master priority rotation on every PCI master grant */
276 pci_write_config_byte(dev
, 0x76, busarb
);
277 dev_info(&dev
->dev
, "Applying VIA southbridge workaround\n");
281 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
282 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
284 /* Must restore this on a resume from RAM */
285 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
286 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
287 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
290 * VIA Apollo VP3 needs ETBF on BT848/878
292 static void __devinit
quirk_viaetbf(struct pci_dev
*dev
)
294 if ((pci_pci_problems
&PCIPCI_VIAETBF
)==0) {
295 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
296 pci_pci_problems
|= PCIPCI_VIAETBF
;
299 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_viaetbf
);
301 static void __devinit
quirk_vsfx(struct pci_dev
*dev
)
303 if ((pci_pci_problems
&PCIPCI_VSFX
)==0) {
304 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
305 pci_pci_problems
|= PCIPCI_VSFX
;
308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C576
, quirk_vsfx
);
311 * Ali Magik requires workarounds to be used by the drivers
312 * that DMA to AGP space. Latency must be set to 0xA and triton
313 * workaround applied too
314 * [Info kindly provided by ALi]
316 static void __init
quirk_alimagik(struct pci_dev
*dev
)
318 if ((pci_pci_problems
&PCIPCI_ALIMAGIK
)==0) {
319 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
320 pci_pci_problems
|= PCIPCI_ALIMAGIK
|PCIPCI_TRITON
;
323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1647
, quirk_alimagik
);
324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1651
, quirk_alimagik
);
327 * Natoma has some interesting boundary conditions with Zoran stuff
330 static void __devinit
quirk_natoma(struct pci_dev
*dev
)
332 if ((pci_pci_problems
&PCIPCI_NATOMA
)==0) {
333 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
334 pci_pci_problems
|= PCIPCI_NATOMA
;
337 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_natoma
);
338 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_0
, quirk_natoma
);
339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_1
, quirk_natoma
);
340 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
, quirk_natoma
);
341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_1
, quirk_natoma
);
342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
, quirk_natoma
);
345 * This chip can cause PCI parity errors if config register 0xA0 is read
346 * while DMAs are occurring.
348 static void __devinit
quirk_citrine(struct pci_dev
*dev
)
350 dev
->cfg_size
= 0xA0;
352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CITRINE
, quirk_citrine
);
355 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
356 * If it's needed, re-allocate the region.
358 static void __devinit
quirk_s3_64M(struct pci_dev
*dev
)
360 struct resource
*r
= &dev
->resource
[0];
362 if ((r
->start
& 0x3ffffff) || r
->end
!= r
->start
+ 0x3ffffff) {
367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_868
, quirk_s3_64M
);
368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_968
, quirk_s3_64M
);
371 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
372 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
373 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
374 * (which conflicts w/ BAR1's memory range).
376 static void __devinit
quirk_cs5536_vsa(struct pci_dev
*dev
)
378 if (pci_resource_len(dev
, 0) != 8) {
379 struct resource
*res
= &dev
->resource
[0];
380 res
->end
= res
->start
+ 8 - 1;
381 dev_info(&dev
->dev
, "CS5536 ISA bridge bug detected "
382 "(incorrect header); workaround applied.\n");
385 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_CS5536_ISA
, quirk_cs5536_vsa
);
387 static void __devinit
quirk_io_region(struct pci_dev
*dev
, unsigned region
,
388 unsigned size
, int nr
, const char *name
)
392 struct pci_bus_region bus_region
;
393 struct resource
*res
= dev
->resource
+ nr
;
395 res
->name
= pci_name(dev
);
397 res
->end
= region
+ size
- 1;
398 res
->flags
= IORESOURCE_IO
;
400 /* Convert from PCI bus to resource space. */
401 bus_region
.start
= res
->start
;
402 bus_region
.end
= res
->end
;
403 pcibios_bus_to_resource(dev
, res
, &bus_region
);
405 if (pci_claim_resource(dev
, nr
) == 0)
406 dev_info(&dev
->dev
, "quirk: %pR claimed by %s\n",
412 * ATI Northbridge setups MCE the processor if you even
413 * read somewhere between 0x3b0->0x3bb or read 0x3d3
415 static void __devinit
quirk_ati_exploding_mce(struct pci_dev
*dev
)
417 dev_info(&dev
->dev
, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
418 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
419 request_region(0x3b0, 0x0C, "RadeonIGP");
420 request_region(0x3d3, 0x01, "RadeonIGP");
422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, quirk_ati_exploding_mce
);
425 * Let's make the southbridge information explicit instead
426 * of having to worry about people probing the ACPI areas,
427 * for example.. (Yes, it happens, and if you read the wrong
428 * ACPI register it will put the machine to sleep with no
429 * way of waking it up again. Bummer).
431 * ALI M7101: Two IO regions pointed to by words at
432 * 0xE0 (64 bytes of ACPI registers)
433 * 0xE2 (32 bytes of SMB registers)
435 static void __devinit
quirk_ali7101_acpi(struct pci_dev
*dev
)
439 pci_read_config_word(dev
, 0xE0, ®ion
);
440 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "ali7101 ACPI");
441 pci_read_config_word(dev
, 0xE2, ®ion
);
442 quirk_io_region(dev
, region
, 32, PCI_BRIDGE_RESOURCES
+1, "ali7101 SMB");
444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M7101
, quirk_ali7101_acpi
);
446 static void piix4_io_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
449 u32 mask
, size
, base
;
451 pci_read_config_dword(dev
, port
, &devres
);
452 if ((devres
& enable
) != enable
)
454 mask
= (devres
>> 16) & 15;
455 base
= devres
& 0xffff;
458 unsigned bit
= size
>> 1;
459 if ((bit
& mask
) == bit
)
464 * For now we only print it out. Eventually we'll want to
465 * reserve it (at least if it's in the 0x1000+ range), but
466 * let's get enough confirmation reports first.
469 dev_info(&dev
->dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
472 static void piix4_mem_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
475 u32 mask
, size
, base
;
477 pci_read_config_dword(dev
, port
, &devres
);
478 if ((devres
& enable
) != enable
)
480 base
= devres
& 0xffff0000;
481 mask
= (devres
& 0x3f) << 16;
484 unsigned bit
= size
>> 1;
485 if ((bit
& mask
) == bit
)
490 * For now we only print it out. Eventually we'll want to
491 * reserve it, but let's get enough confirmation reports first.
494 dev_info(&dev
->dev
, "%s MMIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
498 * PIIX4 ACPI: Two IO regions pointed to by longwords at
499 * 0x40 (64 bytes of ACPI registers)
500 * 0x90 (16 bytes of SMB registers)
501 * and a few strange programmable PIIX4 device resources.
503 static void __devinit
quirk_piix4_acpi(struct pci_dev
*dev
)
507 pci_read_config_dword(dev
, 0x40, ®ion
);
508 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "PIIX4 ACPI");
509 pci_read_config_dword(dev
, 0x90, ®ion
);
510 quirk_io_region(dev
, region
, 16, PCI_BRIDGE_RESOURCES
+1, "PIIX4 SMB");
512 /* Device resource A has enables for some of the other ones */
513 pci_read_config_dword(dev
, 0x5c, &res_a
);
515 piix4_io_quirk(dev
, "PIIX4 devres B", 0x60, 3 << 21);
516 piix4_io_quirk(dev
, "PIIX4 devres C", 0x64, 3 << 21);
518 /* Device resource D is just bitfields for static resources */
520 /* Device 12 enabled? */
521 if (res_a
& (1 << 29)) {
522 piix4_io_quirk(dev
, "PIIX4 devres E", 0x68, 1 << 20);
523 piix4_mem_quirk(dev
, "PIIX4 devres F", 0x6c, 1 << 7);
525 /* Device 13 enabled? */
526 if (res_a
& (1 << 30)) {
527 piix4_io_quirk(dev
, "PIIX4 devres G", 0x70, 1 << 20);
528 piix4_mem_quirk(dev
, "PIIX4 devres H", 0x74, 1 << 7);
530 piix4_io_quirk(dev
, "PIIX4 devres I", 0x78, 1 << 20);
531 piix4_io_quirk(dev
, "PIIX4 devres J", 0x7c, 1 << 20);
533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, quirk_piix4_acpi
);
534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_3
, quirk_piix4_acpi
);
536 #define ICH_PMBASE 0x40
537 #define ICH_ACPI_CNTL 0x44
538 #define ICH4_ACPI_EN 0x10
539 #define ICH6_ACPI_EN 0x80
540 #define ICH4_GPIOBASE 0x58
541 #define ICH4_GPIO_CNTL 0x5c
542 #define ICH4_GPIO_EN 0x10
543 #define ICH6_GPIOBASE 0x48
544 #define ICH6_GPIO_CNTL 0x4c
545 #define ICH6_GPIO_EN 0x10
548 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
549 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
550 * 0x58 (64 bytes of GPIO I/O space)
552 static void __devinit
quirk_ich4_lpc_acpi(struct pci_dev
*dev
)
557 pci_read_config_byte(dev
, ICH_ACPI_CNTL
, &enable
);
558 if (enable
& ICH4_ACPI_EN
) {
559 pci_read_config_dword(dev
, ICH_PMBASE
, ®ion
);
560 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
,
561 "ICH4 ACPI/GPIO/TCO");
564 pci_read_config_byte(dev
, ICH4_GPIO_CNTL
, &enable
);
565 if (enable
& ICH4_GPIO_EN
) {
566 pci_read_config_dword(dev
, ICH4_GPIOBASE
, ®ion
);
567 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
+ 1,
571 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, quirk_ich4_lpc_acpi
);
572 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_0
, quirk_ich4_lpc_acpi
);
573 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, quirk_ich4_lpc_acpi
);
574 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_10
, quirk_ich4_lpc_acpi
);
575 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, quirk_ich4_lpc_acpi
);
576 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, quirk_ich4_lpc_acpi
);
577 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, quirk_ich4_lpc_acpi
);
578 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, quirk_ich4_lpc_acpi
);
579 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, quirk_ich4_lpc_acpi
);
580 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_1
, quirk_ich4_lpc_acpi
);
582 static void __devinit
ich6_lpc_acpi_gpio(struct pci_dev
*dev
)
587 pci_read_config_byte(dev
, ICH_ACPI_CNTL
, &enable
);
588 if (enable
& ICH6_ACPI_EN
) {
589 pci_read_config_dword(dev
, ICH_PMBASE
, ®ion
);
590 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
,
591 "ICH6 ACPI/GPIO/TCO");
594 pci_read_config_byte(dev
, ICH6_GPIO_CNTL
, &enable
);
595 if (enable
& ICH4_GPIO_EN
) {
596 pci_read_config_dword(dev
, ICH6_GPIOBASE
, ®ion
);
597 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
+ 1,
602 static void __devinit
ich6_lpc_generic_decode(struct pci_dev
*dev
, unsigned reg
, const char *name
, int dynsize
)
607 pci_read_config_dword(dev
, reg
, &val
);
615 * This is not correct. It is 16, 32 or 64 bytes depending on
616 * register D31:F0:ADh bits 5:4.
618 * But this gets us at least _part_ of it.
626 /* Just print it out for now. We should reserve it after more debugging */
627 dev_info(&dev
->dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+size
-1);
630 static void __devinit
quirk_ich6_lpc(struct pci_dev
*dev
)
632 /* Shared ACPI/GPIO decode with all ICH6+ */
633 ich6_lpc_acpi_gpio(dev
);
635 /* ICH6-specific generic IO decode */
636 ich6_lpc_generic_decode(dev
, 0x84, "LPC Generic IO decode 1", 0);
637 ich6_lpc_generic_decode(dev
, 0x88, "LPC Generic IO decode 2", 1);
639 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_0
, quirk_ich6_lpc
);
640 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, quirk_ich6_lpc
);
642 static void __devinit
ich7_lpc_generic_decode(struct pci_dev
*dev
, unsigned reg
, const char *name
)
647 pci_read_config_dword(dev
, reg
, &val
);
654 * IO base in bits 15:2, mask in bits 23:18, both
658 mask
= (val
>> 16) & 0xfc;
661 /* Just print it out for now. We should reserve it after more debugging */
662 dev_info(&dev
->dev
, "%s PIO at %04x (mask %04x)\n", name
, base
, mask
);
665 /* ICH7-10 has the same common LPC generic IO decode registers */
666 static void __devinit
quirk_ich7_lpc(struct pci_dev
*dev
)
668 /* We share the common ACPI/DPIO decode with ICH6 */
669 ich6_lpc_acpi_gpio(dev
);
671 /* And have 4 ICH7+ generic decodes */
672 ich7_lpc_generic_decode(dev
, 0x84, "ICH7 LPC Generic IO decode 1");
673 ich7_lpc_generic_decode(dev
, 0x88, "ICH7 LPC Generic IO decode 2");
674 ich7_lpc_generic_decode(dev
, 0x8c, "ICH7 LPC Generic IO decode 3");
675 ich7_lpc_generic_decode(dev
, 0x90, "ICH7 LPC Generic IO decode 4");
677 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_0
, quirk_ich7_lpc
);
678 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_1
, quirk_ich7_lpc
);
679 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_31
, quirk_ich7_lpc
);
680 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_0
, quirk_ich7_lpc
);
681 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_2
, quirk_ich7_lpc
);
682 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_3
, quirk_ich7_lpc
);
683 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_1
, quirk_ich7_lpc
);
684 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_4
, quirk_ich7_lpc
);
685 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_2
, quirk_ich7_lpc
);
686 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_4
, quirk_ich7_lpc
);
687 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_7
, quirk_ich7_lpc
);
688 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_8
, quirk_ich7_lpc
);
689 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH10_1
, quirk_ich7_lpc
);
692 * VIA ACPI: One IO region pointed to by longword at
693 * 0x48 or 0x20 (256 bytes of ACPI registers)
695 static void __devinit
quirk_vt82c586_acpi(struct pci_dev
*dev
)
699 if (dev
->revision
& 0x10) {
700 pci_read_config_dword(dev
, 0x48, ®ion
);
701 region
&= PCI_BASE_ADDRESS_IO_MASK
;
702 quirk_io_region(dev
, region
, 256, PCI_BRIDGE_RESOURCES
, "vt82c586 ACPI");
705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_vt82c586_acpi
);
708 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
709 * 0x48 (256 bytes of ACPI registers)
710 * 0x70 (128 bytes of hardware monitoring register)
711 * 0x90 (16 bytes of SMB registers)
713 static void __devinit
quirk_vt82c686_acpi(struct pci_dev
*dev
)
718 quirk_vt82c586_acpi(dev
);
720 pci_read_config_word(dev
, 0x70, &hm
);
721 hm
&= PCI_BASE_ADDRESS_IO_MASK
;
722 quirk_io_region(dev
, hm
, 128, PCI_BRIDGE_RESOURCES
+ 1, "vt82c686 HW-mon");
724 pci_read_config_dword(dev
, 0x90, &smb
);
725 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
726 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 2, "vt82c686 SMB");
728 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_vt82c686_acpi
);
731 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
732 * 0x88 (128 bytes of power management registers)
733 * 0xd0 (16 bytes of SMB registers)
735 static void __devinit
quirk_vt8235_acpi(struct pci_dev
*dev
)
739 pci_read_config_word(dev
, 0x88, &pm
);
740 pm
&= PCI_BASE_ADDRESS_IO_MASK
;
741 quirk_io_region(dev
, pm
, 128, PCI_BRIDGE_RESOURCES
, "vt8235 PM");
743 pci_read_config_word(dev
, 0xd0, &smb
);
744 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
745 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 1, "vt8235 SMB");
747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_vt8235_acpi
);
750 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
751 * Disable fast back-to-back on the secondary bus segment
753 static void __devinit
quirk_xio2000a(struct pci_dev
*dev
)
755 struct pci_dev
*pdev
;
758 dev_warn(&dev
->dev
, "TI XIO2000a quirk detected; "
759 "secondary bus fast back-to-back transfers disabled\n");
760 list_for_each_entry(pdev
, &dev
->subordinate
->devices
, bus_list
) {
761 pci_read_config_word(pdev
, PCI_COMMAND
, &command
);
762 if (command
& PCI_COMMAND_FAST_BACK
)
763 pci_write_config_word(pdev
, PCI_COMMAND
, command
& ~PCI_COMMAND_FAST_BACK
);
766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_XIO2000A
,
769 #ifdef CONFIG_X86_IO_APIC
771 #include <asm/io_apic.h>
774 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
775 * devices to the external APIC.
777 * TODO: When we have device-specific interrupt routers,
778 * this code will go away from quirks.
780 static void quirk_via_ioapic(struct pci_dev
*dev
)
785 tmp
= 0; /* nothing routed to external APIC */
787 tmp
= 0x1f; /* all known bits (4-0) routed to external APIC */
789 dev_info(&dev
->dev
, "%sbling VIA external APIC routing\n",
790 tmp
== 0 ? "Disa" : "Ena");
792 /* Offset 0x58: External APIC IRQ output control */
793 pci_write_config_byte (dev
, 0x58, tmp
);
795 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
796 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
799 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
800 * This leads to doubled level interrupt rates.
801 * Set this bit to get rid of cycle wastage.
802 * Otherwise uncritical.
804 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev
*dev
)
807 #define BYPASS_APIC_DEASSERT 8
809 pci_read_config_byte(dev
, 0x5B, &misc_control2
);
810 if (!(misc_control2
& BYPASS_APIC_DEASSERT
)) {
811 dev_info(&dev
->dev
, "Bypassing VIA 8237 APIC De-Assert Message\n");
812 pci_write_config_byte(dev
, 0x5B, misc_control2
|BYPASS_APIC_DEASSERT
);
815 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
816 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
819 * The AMD io apic can hang the box when an apic irq is masked.
820 * We check all revs >= B0 (yet not in the pre production!) as the bug
821 * is currently marked NoFix
823 * We have multiple reports of hangs with this chipset that went away with
824 * noapic specified. For the moment we assume it's the erratum. We may be wrong
825 * of course. However the advice is demonstrably good even if so..
827 static void __devinit
quirk_amd_ioapic(struct pci_dev
*dev
)
829 if (dev
->revision
>= 0x02) {
830 dev_warn(&dev
->dev
, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
831 dev_warn(&dev
->dev
, " : booting with the \"noapic\" option\n");
834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_VIPER_7410
, quirk_amd_ioapic
);
836 static void __init
quirk_ioapic_rmw(struct pci_dev
*dev
)
838 if (dev
->devfn
== 0 && dev
->bus
->number
== 0)
841 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_ANY_ID
, quirk_ioapic_rmw
);
842 #endif /* CONFIG_X86_IO_APIC */
845 * Some settings of MMRBC can lead to data corruption so block changes.
846 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
848 static void __init
quirk_amd_8131_mmrbc(struct pci_dev
*dev
)
850 if (dev
->subordinate
&& dev
->revision
<= 0x12) {
851 dev_info(&dev
->dev
, "AMD8131 rev %x detected; "
852 "disabling PCI-X MMRBC\n", dev
->revision
);
853 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MMRBC
;
856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_mmrbc
);
859 * FIXME: it is questionable that quirk_via_acpi
860 * is needed. It shows up as an ISA bridge, and does not
861 * support the PCI_INTERRUPT_LINE register at all. Therefore
862 * it seems like setting the pci_dev's 'irq' to the
863 * value of the ACPI SCI interrupt is only done for convenience.
866 static void __devinit
quirk_via_acpi(struct pci_dev
*d
)
869 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
872 pci_read_config_byte(d
, 0x42, &irq
);
874 if (irq
&& (irq
!= 2))
877 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_acpi
);
878 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_acpi
);
882 * VIA bridges which have VLink
885 static int via_vlink_dev_lo
= -1, via_vlink_dev_hi
= 18;
887 static void quirk_via_bridge(struct pci_dev
*dev
)
889 /* See what bridge we have and find the device ranges */
890 switch (dev
->device
) {
891 case PCI_DEVICE_ID_VIA_82C686
:
892 /* The VT82C686 is special, it attaches to PCI and can have
893 any device number. All its subdevices are functions of
894 that single device. */
895 via_vlink_dev_lo
= PCI_SLOT(dev
->devfn
);
896 via_vlink_dev_hi
= PCI_SLOT(dev
->devfn
);
898 case PCI_DEVICE_ID_VIA_8237
:
899 case PCI_DEVICE_ID_VIA_8237A
:
900 via_vlink_dev_lo
= 15;
902 case PCI_DEVICE_ID_VIA_8235
:
903 via_vlink_dev_lo
= 16;
905 case PCI_DEVICE_ID_VIA_8231
:
906 case PCI_DEVICE_ID_VIA_8233_0
:
907 case PCI_DEVICE_ID_VIA_8233A
:
908 case PCI_DEVICE_ID_VIA_8233C_0
:
909 via_vlink_dev_lo
= 17;
913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_bridge
);
914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, quirk_via_bridge
);
915 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233_0
, quirk_via_bridge
);
916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233A
, quirk_via_bridge
);
917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233C_0
, quirk_via_bridge
);
918 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_via_bridge
);
919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_bridge
);
920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237A
, quirk_via_bridge
);
923 * quirk_via_vlink - VIA VLink IRQ number update
926 * If the device we are dealing with is on a PIC IRQ we need to
927 * ensure that the IRQ line register which usually is not relevant
928 * for PCI cards, is actually written so that interrupts get sent
929 * to the right place.
930 * We only do this on systems where a VIA south bridge was detected,
931 * and only for VIA devices on the motherboard (see quirk_via_bridge
935 static void quirk_via_vlink(struct pci_dev
*dev
)
939 /* Check if we have VLink at all */
940 if (via_vlink_dev_lo
== -1)
945 /* Don't quirk interrupts outside the legacy IRQ range */
946 if (!new_irq
|| new_irq
> 15)
949 /* Internal device ? */
950 if (dev
->bus
->number
!= 0 || PCI_SLOT(dev
->devfn
) > via_vlink_dev_hi
||
951 PCI_SLOT(dev
->devfn
) < via_vlink_dev_lo
)
954 /* This is an internal VLink device on a PIC interrupt. The BIOS
955 ought to have set this but may not have, so we redo it */
957 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
958 if (new_irq
!= irq
) {
959 dev_info(&dev
->dev
, "VIA VLink IRQ fixup, from %d to %d\n",
961 udelay(15); /* unknown if delay really needed */
962 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, new_irq
);
965 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_via_vlink
);
968 * VIA VT82C598 has its device ID settable and many BIOSes
969 * set it to the ID of VT82C597 for backward compatibility.
970 * We need to switch it off to be able to recognize the real
973 static void __devinit
quirk_vt82c598_id(struct pci_dev
*dev
)
975 pci_write_config_byte(dev
, 0xfc, 0);
976 pci_read_config_word(dev
, PCI_DEVICE_ID
, &dev
->device
);
978 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_vt82c598_id
);
981 * CardBus controllers have a legacy base address that enables them
982 * to respond as i82365 pcmcia controllers. We don't want them to
983 * do this even if the Linux CardBus driver is not loaded, because
984 * the Linux i82365 driver does not (and should not) handle CardBus.
986 static void quirk_cardbus_legacy(struct pci_dev
*dev
)
988 if ((PCI_CLASS_BRIDGE_CARDBUS
<< 8) ^ dev
->class)
990 pci_write_config_dword(dev
, PCI_CB_LEGACY_MODE_BASE
, 0);
992 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, quirk_cardbus_legacy
);
993 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID
, PCI_ANY_ID
, quirk_cardbus_legacy
);
996 * Following the PCI ordering rules is optional on the AMD762. I'm not
997 * sure what the designers were smoking but let's not inhale...
999 * To be fair to AMD, it follows the spec by default, its BIOS people
1002 static void quirk_amd_ordering(struct pci_dev
*dev
)
1005 pci_read_config_dword(dev
, 0x4C, &pcic
);
1008 dev_warn(&dev
->dev
, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1009 pci_write_config_dword(dev
, 0x4C, pcic
);
1010 pci_read_config_dword(dev
, 0x84, &pcic
);
1011 pcic
|= (1<<23); /* Required in this mode */
1012 pci_write_config_dword(dev
, 0x84, pcic
);
1015 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
1016 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
1019 * DreamWorks provided workaround for Dunord I-3000 problem
1021 * This card decodes and responds to addresses not apparently
1022 * assigned to it. We force a larger allocation to ensure that
1023 * nothing gets put too close to it.
1025 static void __devinit
quirk_dunord ( struct pci_dev
* dev
)
1027 struct resource
*r
= &dev
->resource
[1];
1031 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD
, PCI_DEVICE_ID_DUNORD_I3000
, quirk_dunord
);
1034 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1035 * is subtractive decoding (transparent), and does indicate this
1036 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1039 static void __devinit
quirk_transparent_bridge(struct pci_dev
*dev
)
1041 dev
->transparent
= 1;
1043 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82380FB
, quirk_transparent_bridge
);
1044 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA
, 0x605, quirk_transparent_bridge
);
1047 * Common misconfiguration of the MediaGX/Geode PCI master that will
1048 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1049 * datasheets found at http://www.national.com/analog for info on what
1050 * these bits do. <christer@weinigel.se>
1052 static void quirk_mediagx_master(struct pci_dev
*dev
)
1055 pci_read_config_byte(dev
, 0x41, ®
);
1058 dev_info(&dev
->dev
, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg
);
1059 pci_write_config_byte(dev
, 0x41, reg
);
1062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
1063 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
1066 * Ensure C0 rev restreaming is off. This is normally done by
1067 * the BIOS but in the odd case it is not the results are corruption
1068 * hence the presence of a Linux check
1070 static void quirk_disable_pxb(struct pci_dev
*pdev
)
1074 if (pdev
->revision
!= 0x04) /* Only C0 requires this */
1076 pci_read_config_word(pdev
, 0x40, &config
);
1077 if (config
& (1<<6)) {
1079 pci_write_config_word(pdev
, 0x40, config
);
1080 dev_info(&pdev
->dev
, "C0 revision 450NX. Disabling PCI restreaming\n");
1083 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
1084 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
1086 static void __devinit
quirk_amd_ide_mode(struct pci_dev
*pdev
)
1088 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1091 pci_read_config_byte(pdev
, PCI_CLASS_DEVICE
, &tmp
);
1093 pci_read_config_byte(pdev
, 0x40, &tmp
);
1094 pci_write_config_byte(pdev
, 0x40, tmp
|1);
1095 pci_write_config_byte(pdev
, 0x9, 1);
1096 pci_write_config_byte(pdev
, 0xa, 6);
1097 pci_write_config_byte(pdev
, 0x40, tmp
);
1099 pdev
->class = PCI_CLASS_STORAGE_SATA_AHCI
;
1100 dev_info(&pdev
->dev
, "set SATA to AHCI mode\n");
1103 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
1104 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
1105 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
1106 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
1107 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
, quirk_amd_ide_mode
);
1108 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
, quirk_amd_ide_mode
);
1111 * Serverworks CSB5 IDE does not fully support native mode
1113 static void __devinit
quirk_svwks_csb5ide(struct pci_dev
*pdev
)
1116 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1120 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
1121 /* PCI layer will sort out resources */
1124 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, quirk_svwks_csb5ide
);
1127 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1129 static void __init
quirk_ide_samemode(struct pci_dev
*pdev
)
1133 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1135 if (((prog
& 1) && !(prog
& 4)) || ((prog
& 4) && !(prog
& 1))) {
1136 dev_info(&pdev
->dev
, "IDE mode mismatch; forcing legacy mode\n");
1139 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
1142 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
, quirk_ide_samemode
);
1145 * Some ATA devices break if put into D3
1148 static void __devinit
quirk_no_ata_d3(struct pci_dev
*pdev
)
1150 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1151 if ((pdev
->class >> 8) == PCI_CLASS_STORAGE_IDE
)
1152 pdev
->dev_flags
|= PCI_DEV_FLAGS_NO_D3
;
1154 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_ANY_ID
, quirk_no_ata_d3
);
1155 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
, quirk_no_ata_d3
);
1156 /* ALi loses some register settings that we cannot then restore */
1157 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, quirk_no_ata_d3
);
1158 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1159 occur when mode detecting */
1160 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_no_ata_d3
);
1162 /* This was originally an Alpha specific thing, but it really fits here.
1163 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1165 static void __init
quirk_eisa_bridge(struct pci_dev
*dev
)
1167 dev
->class = PCI_CLASS_BRIDGE_EISA
<< 8;
1169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
, quirk_eisa_bridge
);
1173 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1174 * is not activated. The myth is that Asus said that they do not want the
1175 * users to be irritated by just another PCI Device in the Win98 device
1176 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1177 * package 2.7.0 for details)
1179 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1180 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1181 * becomes necessary to do this tweak in two steps -- the chosen trigger
1182 * is either the Host bridge (preferred) or on-board VGA controller.
1184 * Note that we used to unhide the SMBus that way on Toshiba laptops
1185 * (Satellite A40 and Tecra M2) but then found that the thermal management
1186 * was done by SMM code, which could cause unsynchronized concurrent
1187 * accesses to the SMBus registers, with potentially bad effects. Thus you
1188 * should be very careful when adding new entries: if SMM is accessing the
1189 * Intel SMBus, this is a very good reason to leave it hidden.
1191 * Likewise, many recent laptops use ACPI for thermal management. If the
1192 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1193 * natively, and keeping the SMBus hidden is the right thing to do. If you
1194 * are about to add an entry in the table below, please first disassemble
1195 * the DSDT and double-check that there is no code accessing the SMBus.
1197 static int asus_hides_smbus
;
1199 static void __init
asus_hides_smbus_hostbridge(struct pci_dev
*dev
)
1201 if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1202 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845_HB
)
1203 switch(dev
->subsystem_device
) {
1204 case 0x8025: /* P4B-LX */
1205 case 0x8070: /* P4B */
1206 case 0x8088: /* P4B533 */
1207 case 0x1626: /* L3C notebook */
1208 asus_hides_smbus
= 1;
1210 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
)
1211 switch(dev
->subsystem_device
) {
1212 case 0x80b1: /* P4GE-V */
1213 case 0x80b2: /* P4PE */
1214 case 0x8093: /* P4B533-V */
1215 asus_hides_smbus
= 1;
1217 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82850_HB
)
1218 switch(dev
->subsystem_device
) {
1219 case 0x8030: /* P4T533 */
1220 asus_hides_smbus
= 1;
1222 else if (dev
->device
== PCI_DEVICE_ID_INTEL_7205_0
)
1223 switch (dev
->subsystem_device
) {
1224 case 0x8070: /* P4G8X Deluxe */
1225 asus_hides_smbus
= 1;
1227 else if (dev
->device
== PCI_DEVICE_ID_INTEL_E7501_MCH
)
1228 switch (dev
->subsystem_device
) {
1229 case 0x80c9: /* PU-DLS */
1230 asus_hides_smbus
= 1;
1232 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
1233 switch (dev
->subsystem_device
) {
1234 case 0x1751: /* M2N notebook */
1235 case 0x1821: /* M5N notebook */
1236 case 0x1897: /* A6L notebook */
1237 asus_hides_smbus
= 1;
1239 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1240 switch (dev
->subsystem_device
) {
1241 case 0x184b: /* W1N notebook */
1242 case 0x186a: /* M6Ne notebook */
1243 asus_hides_smbus
= 1;
1245 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1246 switch (dev
->subsystem_device
) {
1247 case 0x80f2: /* P4P800-X */
1248 asus_hides_smbus
= 1;
1250 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
)
1251 switch (dev
->subsystem_device
) {
1252 case 0x1882: /* M6V notebook */
1253 case 0x1977: /* A6VA notebook */
1254 asus_hides_smbus
= 1;
1256 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_HP
)) {
1257 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1258 switch(dev
->subsystem_device
) {
1259 case 0x088C: /* HP Compaq nc8000 */
1260 case 0x0890: /* HP Compaq nc6000 */
1261 asus_hides_smbus
= 1;
1263 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1264 switch (dev
->subsystem_device
) {
1265 case 0x12bc: /* HP D330L */
1266 case 0x12bd: /* HP D530 */
1267 case 0x006a: /* HP Compaq nx9500 */
1268 asus_hides_smbus
= 1;
1270 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82875_HB
)
1271 switch (dev
->subsystem_device
) {
1272 case 0x12bf: /* HP xw4100 */
1273 asus_hides_smbus
= 1;
1275 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_SAMSUNG
)) {
1276 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1277 switch(dev
->subsystem_device
) {
1278 case 0xC00C: /* Samsung P35 notebook */
1279 asus_hides_smbus
= 1;
1281 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
)) {
1282 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1283 switch(dev
->subsystem_device
) {
1284 case 0x0058: /* Compaq Evo N620c */
1285 asus_hides_smbus
= 1;
1287 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82810_IG3
)
1288 switch(dev
->subsystem_device
) {
1289 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1290 /* Motherboard doesn't have Host bridge
1291 * subvendor/subdevice IDs, therefore checking
1292 * its on-board VGA controller */
1293 asus_hides_smbus
= 1;
1295 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82801DB_2
)
1296 switch(dev
->subsystem_device
) {
1297 case 0x00b8: /* Compaq Evo D510 CMT */
1298 case 0x00b9: /* Compaq Evo D510 SFF */
1299 case 0x00ba: /* Compaq Evo D510 USDT */
1300 /* Motherboard doesn't have Host bridge
1301 * subvendor/subdevice IDs and on-board VGA
1302 * controller is disabled if an AGP card is
1303 * inserted, therefore checking USB UHCI
1305 asus_hides_smbus
= 1;
1307 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82815_CGC
)
1308 switch (dev
->subsystem_device
) {
1309 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1310 /* Motherboard doesn't have host bridge
1311 * subvendor/subdevice IDs, therefore checking
1312 * its on-board VGA controller */
1313 asus_hides_smbus
= 1;
1317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845_HB
, asus_hides_smbus_hostbridge
);
1318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_HB
, asus_hides_smbus_hostbridge
);
1319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82850_HB
, asus_hides_smbus_hostbridge
);
1320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
, asus_hides_smbus_hostbridge
);
1321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
, asus_hides_smbus_hostbridge
);
1322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_7205_0
, asus_hides_smbus_hostbridge
);
1323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7501_MCH
, asus_hides_smbus_hostbridge
);
1324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855PM_HB
, asus_hides_smbus_hostbridge
);
1325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855GM_HB
, asus_hides_smbus_hostbridge
);
1326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82915GM_HB
, asus_hides_smbus_hostbridge
);
1328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82810_IG3
, asus_hides_smbus_hostbridge
);
1329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_2
, asus_hides_smbus_hostbridge
);
1330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82815_CGC
, asus_hides_smbus_hostbridge
);
1332 static void asus_hides_smbus_lpc(struct pci_dev
*dev
)
1336 if (likely(!asus_hides_smbus
))
1339 pci_read_config_word(dev
, 0xF2, &val
);
1341 pci_write_config_word(dev
, 0xF2, val
& (~0x8));
1342 pci_read_config_word(dev
, 0xF2, &val
);
1344 dev_info(&dev
->dev
, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val
);
1346 dev_info(&dev
->dev
, "Enabled i801 SMBus device\n");
1349 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1354 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1355 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1356 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1357 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1358 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1359 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1360 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1361 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1362 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1364 /* It appears we just have one such device. If not, we have a warning */
1365 static void __iomem
*asus_rcba_base
;
1366 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev
*dev
)
1370 if (likely(!asus_hides_smbus
))
1372 WARN_ON(asus_rcba_base
);
1374 pci_read_config_dword(dev
, 0xF0, &rcba
);
1375 /* use bits 31:14, 16 kB aligned */
1376 asus_rcba_base
= ioremap_nocache(rcba
& 0xFFFFC000, 0x4000);
1377 if (asus_rcba_base
== NULL
)
1381 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev
*dev
)
1385 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1387 /* read the Function Disable register, dword mode only */
1388 val
= readl(asus_rcba_base
+ 0x3418);
1389 writel(val
& 0xFFFFFFF7, asus_rcba_base
+ 0x3418); /* enable the SMBus device */
1392 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev
*dev
)
1394 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1396 iounmap(asus_rcba_base
);
1397 asus_rcba_base
= NULL
;
1398 dev_info(&dev
->dev
, "Enabled ICH6/i801 SMBus device\n");
1401 static void asus_hides_smbus_lpc_ich6(struct pci_dev
*dev
)
1403 asus_hides_smbus_lpc_ich6_suspend(dev
);
1404 asus_hides_smbus_lpc_ich6_resume_early(dev
);
1405 asus_hides_smbus_lpc_ich6_resume(dev
);
1407 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6
);
1408 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_suspend
);
1409 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume
);
1410 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume_early
);
1413 * SiS 96x south bridge: BIOS typically hides SMBus device...
1415 static void quirk_sis_96x_smbus(struct pci_dev
*dev
)
1418 pci_read_config_byte(dev
, 0x77, &val
);
1420 dev_info(&dev
->dev
, "Enabling SiS 96x SMBus\n");
1421 pci_write_config_byte(dev
, 0x77, val
& ~0x10);
1424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1425 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1426 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1427 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1428 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1429 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1430 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1431 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1434 * ... This is further complicated by the fact that some SiS96x south
1435 * bridges pretend to be 85C503/5513 instead. In that case see if we
1436 * spotted a compatible north bridge to make sure.
1437 * (pci_find_device doesn't work yet)
1439 * We can also enable the sis96x bit in the discovery register..
1441 #define SIS_DETECT_REGISTER 0x40
1443 static void quirk_sis_503(struct pci_dev
*dev
)
1448 pci_read_config_byte(dev
, SIS_DETECT_REGISTER
, ®
);
1449 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
| (1 << 6));
1450 pci_read_config_word(dev
, PCI_DEVICE_ID
, &devid
);
1451 if (((devid
& 0xfff0) != 0x0960) && (devid
!= 0x0018)) {
1452 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
);
1457 * Ok, it now shows up as a 96x.. run the 96x quirk by
1458 * hand in case it has already been processed.
1459 * (depends on link order, which is apparently not guaranteed)
1461 dev
->device
= devid
;
1462 quirk_sis_96x_smbus(dev
);
1464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1465 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1469 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1470 * and MC97 modem controller are disabled when a second PCI soundcard is
1471 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1474 static void asus_hides_ac97_lpc(struct pci_dev
*dev
)
1477 int asus_hides_ac97
= 0;
1479 if (likely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1480 if (dev
->device
== PCI_DEVICE_ID_VIA_8237
)
1481 asus_hides_ac97
= 1;
1484 if (!asus_hides_ac97
)
1487 pci_read_config_byte(dev
, 0x50, &val
);
1489 pci_write_config_byte(dev
, 0x50, val
& (~0xc0));
1490 pci_read_config_byte(dev
, 0x50, &val
);
1492 dev_info(&dev
->dev
, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val
);
1494 dev_info(&dev
->dev
, "Enabled onboard AC97/MC97 devices\n");
1497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1498 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1500 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1503 * If we are using libata we can drive this chip properly but must
1504 * do this early on to make the additional device appear during
1507 static void quirk_jmicron_ata(struct pci_dev
*pdev
)
1509 u32 conf1
, conf5
, class;
1512 /* Only poke fn 0 */
1513 if (PCI_FUNC(pdev
->devfn
))
1516 pci_read_config_dword(pdev
, 0x40, &conf1
);
1517 pci_read_config_dword(pdev
, 0x80, &conf5
);
1519 conf1
&= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1520 conf5
&= ~(1 << 24); /* Clear bit 24 */
1522 switch (pdev
->device
) {
1523 case PCI_DEVICE_ID_JMICRON_JMB360
: /* SATA single port */
1524 case PCI_DEVICE_ID_JMICRON_JMB362
: /* SATA dual ports */
1525 case PCI_DEVICE_ID_JMICRON_JMB364
: /* SATA dual ports */
1526 /* The controller should be in single function ahci mode */
1527 conf1
|= 0x0002A100; /* Set 8, 13, 15, 17 */
1530 case PCI_DEVICE_ID_JMICRON_JMB365
:
1531 case PCI_DEVICE_ID_JMICRON_JMB366
:
1532 /* Redirect IDE second PATA port to the right spot */
1535 case PCI_DEVICE_ID_JMICRON_JMB361
:
1536 case PCI_DEVICE_ID_JMICRON_JMB363
:
1537 case PCI_DEVICE_ID_JMICRON_JMB369
:
1538 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1539 /* Set the class codes correctly and then direct IDE 0 */
1540 conf1
|= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1543 case PCI_DEVICE_ID_JMICRON_JMB368
:
1544 /* The controller should be in single function IDE mode */
1545 conf1
|= 0x00C00000; /* Set 22, 23 */
1549 pci_write_config_dword(pdev
, 0x40, conf1
);
1550 pci_write_config_dword(pdev
, 0x80, conf5
);
1552 /* Update pdev accordingly */
1553 pci_read_config_byte(pdev
, PCI_HEADER_TYPE
, &hdr
);
1554 pdev
->hdr_type
= hdr
& 0x7f;
1555 pdev
->multifunction
= !!(hdr
& 0x80);
1557 pci_read_config_dword(pdev
, PCI_CLASS_REVISION
, &class);
1558 pdev
->class = class >> 8;
1560 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1561 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1562 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB362
, quirk_jmicron_ata
);
1563 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1564 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB364
, quirk_jmicron_ata
);
1565 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1566 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1567 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1568 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB369
, quirk_jmicron_ata
);
1569 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1570 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1571 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB362
, quirk_jmicron_ata
);
1572 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1573 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB364
, quirk_jmicron_ata
);
1574 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1575 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1576 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1577 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB369
, quirk_jmicron_ata
);
1581 #ifdef CONFIG_X86_IO_APIC
1582 static void __init
quirk_alder_ioapic(struct pci_dev
*pdev
)
1586 if ((pdev
->class >> 8) != 0xff00)
1589 /* the first BAR is the location of the IO APIC...we must
1590 * not touch this (and it's already covered by the fixmap), so
1591 * forcibly insert it into the resource tree */
1592 if (pci_resource_start(pdev
, 0) && pci_resource_len(pdev
, 0))
1593 insert_resource(&iomem_resource
, &pdev
->resource
[0]);
1595 /* The next five BARs all seem to be rubbish, so just clean
1597 for (i
=1; i
< 6; i
++) {
1598 memset(&pdev
->resource
[i
], 0, sizeof(pdev
->resource
[i
]));
1602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EESSC
, quirk_alder_ioapic
);
1605 static void __devinit
quirk_pcie_mch(struct pci_dev
*pdev
)
1610 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
, quirk_pcie_mch
);
1611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
, quirk_pcie_mch
);
1612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
, quirk_pcie_mch
);
1616 * It's possible for the MSI to get corrupted if shpc and acpi
1617 * are used together on certain PXH-based systems.
1619 static void __devinit
quirk_pcie_pxh(struct pci_dev
*dev
)
1623 dev_warn(&dev
->dev
, "PXH quirk detected; SHPC device MSI disabled\n");
1625 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_0
, quirk_pcie_pxh
);
1626 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_1
, quirk_pcie_pxh
);
1627 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_pcie_pxh
);
1628 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_pcie_pxh
);
1629 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_pcie_pxh
);
1632 * Some Intel PCI Express chipsets have trouble with downstream
1633 * device power management.
1635 static void quirk_intel_pcie_pm(struct pci_dev
* dev
)
1637 pci_pm_d3_delay
= 120;
1641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_pcie_pm
);
1642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_pcie_pm
);
1643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_pcie_pm
);
1644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_pcie_pm
);
1645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_pcie_pm
);
1646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_pcie_pm
);
1647 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_pcie_pm
);
1648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_pcie_pm
);
1649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_pcie_pm
);
1650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_pcie_pm
);
1651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2601, quirk_intel_pcie_pm
);
1652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2602, quirk_intel_pcie_pm
);
1653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2603, quirk_intel_pcie_pm
);
1654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2604, quirk_intel_pcie_pm
);
1655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2605, quirk_intel_pcie_pm
);
1656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2606, quirk_intel_pcie_pm
);
1657 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2607, quirk_intel_pcie_pm
);
1658 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2608, quirk_intel_pcie_pm
);
1659 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2609, quirk_intel_pcie_pm
);
1660 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260a, quirk_intel_pcie_pm
);
1661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260b, quirk_intel_pcie_pm
);
1663 #ifdef CONFIG_X86_IO_APIC
1665 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1666 * remap the original interrupt in the linux kernel to the boot interrupt, so
1667 * that a PCI device's interrupt handler is installed on the boot interrupt
1670 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev
*dev
)
1672 if (noioapicquirk
|| noioapicreroute
)
1675 dev
->irq_reroute_variant
= INTEL_IRQ_REROUTE_VARIANT
;
1676 dev_info(&dev
->dev
, "rerouting interrupts for [%04x:%04x]\n",
1677 dev
->vendor
, dev
->device
);
1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_0
, quirk_reroute_to_boot_interrupts_intel
);
1680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_1
, quirk_reroute_to_boot_interrupts_intel
);
1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
, quirk_reroute_to_boot_interrupts_intel
);
1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_reroute_to_boot_interrupts_intel
);
1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_reroute_to_boot_interrupts_intel
);
1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_reroute_to_boot_interrupts_intel
);
1685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_0
, quirk_reroute_to_boot_interrupts_intel
);
1686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_1
, quirk_reroute_to_boot_interrupts_intel
);
1687 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_0
, quirk_reroute_to_boot_interrupts_intel
);
1688 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_1
, quirk_reroute_to_boot_interrupts_intel
);
1689 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
, quirk_reroute_to_boot_interrupts_intel
);
1690 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_reroute_to_boot_interrupts_intel
);
1691 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_reroute_to_boot_interrupts_intel
);
1692 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_reroute_to_boot_interrupts_intel
);
1693 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_0
, quirk_reroute_to_boot_interrupts_intel
);
1694 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_1
, quirk_reroute_to_boot_interrupts_intel
);
1697 * On some chipsets we can disable the generation of legacy INTx boot
1702 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1703 * 300641-004US, section 5.7.3.
1705 #define INTEL_6300_IOAPIC_ABAR 0x40
1706 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1708 static void quirk_disable_intel_boot_interrupt(struct pci_dev
*dev
)
1710 u16 pci_config_word
;
1715 pci_read_config_word(dev
, INTEL_6300_IOAPIC_ABAR
, &pci_config_word
);
1716 pci_config_word
|= INTEL_6300_DISABLE_BOOT_IRQ
;
1717 pci_write_config_word(dev
, INTEL_6300_IOAPIC_ABAR
, pci_config_word
);
1719 dev_info(&dev
->dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1720 dev
->vendor
, dev
->device
);
1722 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_10
, quirk_disable_intel_boot_interrupt
);
1723 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_10
, quirk_disable_intel_boot_interrupt
);
1726 * disable boot interrupts on HT-1000
1728 #define BC_HT1000_FEATURE_REG 0x64
1729 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1730 #define BC_HT1000_MAP_IDX 0xC00
1731 #define BC_HT1000_MAP_DATA 0xC01
1733 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev
*dev
)
1735 u32 pci_config_dword
;
1741 pci_read_config_dword(dev
, BC_HT1000_FEATURE_REG
, &pci_config_dword
);
1742 pci_write_config_dword(dev
, BC_HT1000_FEATURE_REG
, pci_config_dword
|
1743 BC_HT1000_PIC_REGS_ENABLE
);
1745 for (irq
= 0x10; irq
< 0x10 + 32; irq
++) {
1746 outb(irq
, BC_HT1000_MAP_IDX
);
1747 outb(0x00, BC_HT1000_MAP_DATA
);
1750 pci_write_config_dword(dev
, BC_HT1000_FEATURE_REG
, pci_config_dword
);
1752 dev_info(&dev
->dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1753 dev
->vendor
, dev
->device
);
1755 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000SB
, quirk_disable_broadcom_boot_interrupt
);
1756 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000SB
, quirk_disable_broadcom_boot_interrupt
);
1759 * disable boot interrupts on AMD and ATI chipsets
1762 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1763 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1764 * (due to an erratum).
1766 #define AMD_813X_MISC 0x40
1767 #define AMD_813X_NOIOAMODE (1<<0)
1768 #define AMD_813X_REV_B1 0x12
1769 #define AMD_813X_REV_B2 0x13
1771 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev
*dev
)
1773 u32 pci_config_dword
;
1777 if ((dev
->revision
== AMD_813X_REV_B1
) ||
1778 (dev
->revision
== AMD_813X_REV_B2
))
1781 pci_read_config_dword(dev
, AMD_813X_MISC
, &pci_config_dword
);
1782 pci_config_dword
&= ~AMD_813X_NOIOAMODE
;
1783 pci_write_config_dword(dev
, AMD_813X_MISC
, pci_config_dword
);
1785 dev_info(&dev
->dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1786 dev
->vendor
, dev
->device
);
1788 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
1789 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
1790 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
1791 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
1793 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1795 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev
*dev
)
1797 u16 pci_config_word
;
1802 pci_read_config_word(dev
, AMD_8111_PCI_IRQ_ROUTING
, &pci_config_word
);
1803 if (!pci_config_word
) {
1804 dev_info(&dev
->dev
, "boot interrupts on device [%04x:%04x] "
1805 "already disabled\n", dev
->vendor
, dev
->device
);
1808 pci_write_config_word(dev
, AMD_8111_PCI_IRQ_ROUTING
, 0);
1809 dev_info(&dev
->dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1810 dev
->vendor
, dev
->device
);
1812 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_SMBUS
, quirk_disable_amd_8111_boot_interrupt
);
1813 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_SMBUS
, quirk_disable_amd_8111_boot_interrupt
);
1814 #endif /* CONFIG_X86_IO_APIC */
1817 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1818 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1819 * Re-allocate the region if needed...
1821 static void __init
quirk_tc86c001_ide(struct pci_dev
*dev
)
1823 struct resource
*r
= &dev
->resource
[0];
1825 if (r
->start
& 0x8) {
1830 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2
,
1831 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE
,
1832 quirk_tc86c001_ide
);
1834 static void __devinit
quirk_netmos(struct pci_dev
*dev
)
1836 unsigned int num_parallel
= (dev
->subsystem_device
& 0xf0) >> 4;
1837 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
1840 * These Netmos parts are multiport serial devices with optional
1841 * parallel ports. Even when parallel ports are present, they
1842 * are identified as class SERIAL, which means the serial driver
1843 * will claim them. To prevent this, mark them as class OTHER.
1844 * These combo devices should be claimed by parport_serial.
1846 * The subdevice ID is of the form 0x00PS, where <P> is the number
1847 * of parallel ports and <S> is the number of serial ports.
1849 switch (dev
->device
) {
1850 case PCI_DEVICE_ID_NETMOS_9835
:
1851 /* Well, this rule doesn't hold for the following 9835 device */
1852 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_IBM
&&
1853 dev
->subsystem_device
== 0x0299)
1855 case PCI_DEVICE_ID_NETMOS_9735
:
1856 case PCI_DEVICE_ID_NETMOS_9745
:
1857 case PCI_DEVICE_ID_NETMOS_9845
:
1858 case PCI_DEVICE_ID_NETMOS_9855
:
1859 if ((dev
->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL
&&
1861 dev_info(&dev
->dev
, "Netmos %04x (%u parallel, "
1862 "%u serial); changing class SERIAL to OTHER "
1863 "(use parport_serial)\n",
1864 dev
->device
, num_parallel
, num_serial
);
1865 dev
->class = (PCI_CLASS_COMMUNICATION_OTHER
<< 8) |
1866 (dev
->class & 0xff);
1870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS
, PCI_ANY_ID
, quirk_netmos
);
1872 static void __devinit
quirk_e100_interrupt(struct pci_dev
*dev
)
1879 switch (dev
->device
) {
1880 /* PCI IDs taken from drivers/net/e100.c */
1882 case 0x1030 ... 0x1034:
1883 case 0x1038 ... 0x103E:
1884 case 0x1050 ... 0x1057:
1886 case 0x1064 ... 0x106B:
1887 case 0x1091 ... 0x1095:
1900 * Some firmware hands off the e100 with interrupts enabled,
1901 * which can cause a flood of interrupts if packets are
1902 * received before the driver attaches to the device. So
1903 * disable all e100 interrupts here. The driver will
1904 * re-enable them when it's ready.
1906 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1908 if (!(command
& PCI_COMMAND_MEMORY
) || !pci_resource_start(dev
, 0))
1912 * Check that the device is in the D0 power state. If it's not,
1913 * there is no point to look any further.
1915 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1917 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pmcsr
);
1918 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) != PCI_D0
)
1922 /* Convert from PCI bus to resource space. */
1923 csr
= ioremap(pci_resource_start(dev
, 0), 8);
1925 dev_warn(&dev
->dev
, "Can't map e100 registers\n");
1929 cmd_hi
= readb(csr
+ 3);
1931 dev_warn(&dev
->dev
, "Firmware left e100 interrupts enabled; "
1938 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, quirk_e100_interrupt
);
1941 * The 82575 and 82598 may experience data corruption issues when transitioning
1942 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1944 static void __devinit
quirk_disable_aspm_l0s(struct pci_dev
*dev
)
1946 dev_info(&dev
->dev
, "Disabling L0s\n");
1947 pci_disable_link_state(dev
, PCIE_LINK_STATE_L0S
);
1949 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10a7, quirk_disable_aspm_l0s
);
1950 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10a9, quirk_disable_aspm_l0s
);
1951 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10b6, quirk_disable_aspm_l0s
);
1952 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c6, quirk_disable_aspm_l0s
);
1953 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c7, quirk_disable_aspm_l0s
);
1954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c8, quirk_disable_aspm_l0s
);
1955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10d6, quirk_disable_aspm_l0s
);
1956 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10db, quirk_disable_aspm_l0s
);
1957 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10dd, quirk_disable_aspm_l0s
);
1958 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10e1, quirk_disable_aspm_l0s
);
1959 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10ec, quirk_disable_aspm_l0s
);
1960 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10f1, quirk_disable_aspm_l0s
);
1961 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10f4, quirk_disable_aspm_l0s
);
1962 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1508, quirk_disable_aspm_l0s
);
1964 static void __devinit
fixup_rev1_53c810(struct pci_dev
* dev
)
1966 /* rev 1 ncr53c810 chips don't set the class at all which means
1967 * they don't get their resources remapped. Fix that here.
1970 if (dev
->class == PCI_CLASS_NOT_DEFINED
) {
1971 dev_info(&dev
->dev
, "NCR 53c810 rev 1 detected; setting PCI class\n");
1972 dev
->class = PCI_CLASS_STORAGE_SCSI
;
1975 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR
, PCI_DEVICE_ID_NCR_53C810
, fixup_rev1_53c810
);
1977 /* Enable 1k I/O space granularity on the Intel P64H2 */
1978 static void __devinit
quirk_p64h2_1k_io(struct pci_dev
*dev
)
1981 u8 io_base_lo
, io_limit_lo
;
1982 unsigned long base
, limit
;
1983 struct resource
*res
= dev
->resource
+ PCI_BRIDGE_RESOURCES
;
1985 pci_read_config_word(dev
, 0x40, &en1k
);
1988 dev_info(&dev
->dev
, "Enable I/O Space to 1KB granularity\n");
1990 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
1991 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
1992 base
= (io_base_lo
& (PCI_IO_RANGE_MASK
| 0x0c)) << 8;
1993 limit
= (io_limit_lo
& (PCI_IO_RANGE_MASK
| 0x0c)) << 8;
1995 if (base
<= limit
) {
1997 res
->end
= limit
+ 0x3ff;
2001 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io
);
2003 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
2004 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
2005 * in drivers/pci/setup-bus.c
2007 static void __devinit
quirk_p64h2_1k_io_fix_iobl(struct pci_dev
*dev
)
2009 u16 en1k
, iobl_adr
, iobl_adr_1k
;
2010 struct resource
*res
= dev
->resource
+ PCI_BRIDGE_RESOURCES
;
2012 pci_read_config_word(dev
, 0x40, &en1k
);
2015 pci_read_config_word(dev
, PCI_IO_BASE
, &iobl_adr
);
2017 iobl_adr_1k
= iobl_adr
| (res
->start
>> 8) | (res
->end
& 0xfc00);
2019 if (iobl_adr
!= iobl_adr_1k
) {
2020 dev_info(&dev
->dev
, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
2021 iobl_adr
,iobl_adr_1k
);
2022 pci_write_config_word(dev
, PCI_IO_BASE
, iobl_adr_1k
);
2026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io_fix_iobl
);
2028 /* Under some circumstances, AER is not linked with extended capabilities.
2029 * Force it to be linked by setting the corresponding control bit in the
2032 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev
*dev
)
2035 if (pci_read_config_byte(dev
, 0xf41, &b
) == 0) {
2037 pci_write_config_byte(dev
, 0xf41, b
| 0x20);
2039 "Linking AER extended capability\n");
2043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2044 quirk_nvidia_ck804_pcie_aer_ext_cap
);
2045 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2046 quirk_nvidia_ck804_pcie_aer_ext_cap
);
2048 static void __devinit
quirk_via_cx700_pci_parking_caching(struct pci_dev
*dev
)
2051 * Disable PCI Bus Parking and PCI Master read caching on CX700
2052 * which causes unspecified timing errors with a VT6212L on the PCI
2053 * bus leading to USB2.0 packet loss.
2055 * This quirk is only enabled if a second (on the external PCI bus)
2056 * VT6212L is found -- the CX700 core itself also contains a USB
2057 * host controller with the same PCI ID as the VT6212L.
2060 /* Count VT6212L instances */
2061 struct pci_dev
*p
= pci_get_device(PCI_VENDOR_ID_VIA
,
2062 PCI_DEVICE_ID_VIA_8235_USB_2
, NULL
);
2065 /* p should contain the first (internal) VT6212L -- see if we have
2066 an external one by searching again */
2067 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235_USB_2
, p
);
2072 if (pci_read_config_byte(dev
, 0x76, &b
) == 0) {
2074 /* Turn off PCI Bus Parking */
2075 pci_write_config_byte(dev
, 0x76, b
^ 0x40);
2078 "Disabling VIA CX700 PCI parking\n");
2082 if (pci_read_config_byte(dev
, 0x72, &b
) == 0) {
2084 /* Turn off PCI Master read caching */
2085 pci_write_config_byte(dev
, 0x72, 0x0);
2087 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2088 pci_write_config_byte(dev
, 0x75, 0x1);
2090 /* Disable "Read FIFO Timer" */
2091 pci_write_config_byte(dev
, 0x77, 0x0);
2094 "Disabling VIA CX700 PCI caching\n");
2098 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, 0x324e, quirk_via_cx700_pci_parking_caching
);
2101 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2102 * VPD end tag will hang the device. This problem was initially
2103 * observed when a vpd entry was created in sysfs
2104 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2105 * will dump 32k of data. Reading a full 32k will cause an access
2106 * beyond the VPD end tag causing the device to hang. Once the device
2107 * is hung, the bnx2 driver will not be able to reset the device.
2108 * We believe that it is legal to read beyond the end tag and
2109 * therefore the solution is to limit the read/write length.
2111 static void __devinit
quirk_brcm_570x_limit_vpd(struct pci_dev
*dev
)
2114 * Only disable the VPD capability for 5706, 5706S, 5708,
2115 * 5708S and 5709 rev. A
2117 if ((dev
->device
== PCI_DEVICE_ID_NX2_5706
) ||
2118 (dev
->device
== PCI_DEVICE_ID_NX2_5706S
) ||
2119 (dev
->device
== PCI_DEVICE_ID_NX2_5708
) ||
2120 (dev
->device
== PCI_DEVICE_ID_NX2_5708S
) ||
2121 ((dev
->device
== PCI_DEVICE_ID_NX2_5709
) &&
2122 (dev
->revision
& 0xf0) == 0x0)) {
2124 dev
->vpd
->len
= 0x80;
2128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2129 PCI_DEVICE_ID_NX2_5706
,
2130 quirk_brcm_570x_limit_vpd
);
2131 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2132 PCI_DEVICE_ID_NX2_5706S
,
2133 quirk_brcm_570x_limit_vpd
);
2134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2135 PCI_DEVICE_ID_NX2_5708
,
2136 quirk_brcm_570x_limit_vpd
);
2137 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2138 PCI_DEVICE_ID_NX2_5708S
,
2139 quirk_brcm_570x_limit_vpd
);
2140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2141 PCI_DEVICE_ID_NX2_5709
,
2142 quirk_brcm_570x_limit_vpd
);
2143 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2144 PCI_DEVICE_ID_NX2_5709S
,
2145 quirk_brcm_570x_limit_vpd
);
2147 /* Originally in EDAC sources for i82875P:
2148 * Intel tells BIOS developers to hide device 6 which
2149 * configures the overflow device access containing
2150 * the DRBs - this is where we expose device 6.
2151 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2153 static void __devinit
quirk_unhide_mch_dev6(struct pci_dev
*dev
)
2157 if (pci_read_config_byte(dev
, 0xF4, ®
) == 0 && !(reg
& 0x02)) {
2158 dev_info(&dev
->dev
, "Enabling MCH 'Overflow' Device\n");
2159 pci_write_config_byte(dev
, 0xF4, reg
| 0x02);
2163 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
,
2164 quirk_unhide_mch_dev6
);
2165 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
,
2166 quirk_unhide_mch_dev6
);
2170 * The Tilera TILEmpower platform needs to set the link speed
2171 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2172 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2173 * capability register of the PEX8624 PCIe switch. The switch
2174 * supports link speed auto negotiation, but falsely sets
2175 * the link speed to 5GT/s.
2177 static void __devinit
quirk_tile_plx_gen1(struct pci_dev
*dev
)
2179 if (tile_plx_gen1
) {
2180 pci_write_config_dword(dev
, 0x98, 0x1);
2184 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX
, 0x8624, quirk_tile_plx_gen1
);
2185 #endif /* CONFIG_TILE */
2187 #ifdef CONFIG_PCI_MSI
2188 /* Some chipsets do not support MSI. We cannot easily rely on setting
2189 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2190 * some other busses controlled by the chipset even if Linux is not
2191 * aware of it. Instead of setting the flag on all busses in the
2192 * machine, simply disable MSI globally.
2194 static void __init
quirk_disable_all_msi(struct pci_dev
*dev
)
2197 dev_warn(&dev
->dev
, "MSI quirk detected; MSI disabled\n");
2199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE
, quirk_disable_all_msi
);
2200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS400_200
, quirk_disable_all_msi
);
2201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS480
, quirk_disable_all_msi
);
2202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3336
, quirk_disable_all_msi
);
2203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3351
, quirk_disable_all_msi
);
2204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3364
, quirk_disable_all_msi
);
2205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8380_0
, quirk_disable_all_msi
);
2207 /* Disable MSI on chipsets that are known to not support it */
2208 static void __devinit
quirk_disable_msi(struct pci_dev
*dev
)
2210 if (dev
->subordinate
) {
2211 dev_warn(&dev
->dev
, "MSI quirk detected; "
2212 "subordinate MSI disabled\n");
2213 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_msi
);
2217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, 0xa238, quirk_disable_msi
);
2218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x5a3f, quirk_disable_msi
);
2221 * The APC bridge device in AMD 780 family northbridges has some random
2222 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2223 * we use the possible vendor/device IDs of the host bridge for the
2224 * declared quirk, and search for the APC bridge by slot number.
2226 static void __devinit
quirk_amd_780_apc_msi(struct pci_dev
*host_bridge
)
2228 struct pci_dev
*apc_bridge
;
2230 apc_bridge
= pci_get_slot(host_bridge
->bus
, PCI_DEVFN(1, 0));
2232 if (apc_bridge
->device
== 0x9602)
2233 quirk_disable_msi(apc_bridge
);
2234 pci_dev_put(apc_bridge
);
2237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x9600, quirk_amd_780_apc_msi
);
2238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x9601, quirk_amd_780_apc_msi
);
2240 /* Go through the list of Hypertransport capabilities and
2241 * return 1 if a HT MSI capability is found and enabled */
2242 static int __devinit
msi_ht_cap_enabled(struct pci_dev
*dev
)
2246 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2247 while (pos
&& ttl
--) {
2250 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2253 dev_info(&dev
->dev
, "Found %s HT MSI Mapping\n",
2254 flags
& HT_MSI_FLAGS_ENABLE
?
2255 "enabled" : "disabled");
2256 return (flags
& HT_MSI_FLAGS_ENABLE
) != 0;
2259 pos
= pci_find_next_ht_capability(dev
, pos
,
2260 HT_CAPTYPE_MSI_MAPPING
);
2265 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2266 static void __devinit
quirk_msi_ht_cap(struct pci_dev
*dev
)
2268 if (dev
->subordinate
&& !msi_ht_cap_enabled(dev
)) {
2269 dev_warn(&dev
->dev
, "MSI quirk detected; "
2270 "subordinate MSI disabled\n");
2271 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE
,
2277 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2278 * MSI are supported if the MSI capability set in any of these mappings.
2280 static void __devinit
quirk_nvidia_ck804_msi_ht_cap(struct pci_dev
*dev
)
2282 struct pci_dev
*pdev
;
2284 if (!dev
->subordinate
)
2287 /* check HT MSI cap on this chipset and the root one.
2288 * a single one having MSI is enough to be sure that MSI are supported.
2290 pdev
= pci_get_slot(dev
->bus
, 0);
2293 if (!msi_ht_cap_enabled(dev
) && !msi_ht_cap_enabled(pdev
)) {
2294 dev_warn(&dev
->dev
, "MSI quirk detected; "
2295 "subordinate MSI disabled\n");
2296 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2300 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2301 quirk_nvidia_ck804_msi_ht_cap
);
2303 /* Force enable MSI mapping capability on HT bridges */
2304 static void __devinit
ht_enable_msi_mapping(struct pci_dev
*dev
)
2308 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2309 while (pos
&& ttl
--) {
2312 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2314 dev_info(&dev
->dev
, "Enabling HT MSI Mapping\n");
2316 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2317 flags
| HT_MSI_FLAGS_ENABLE
);
2319 pos
= pci_find_next_ht_capability(dev
, pos
,
2320 HT_CAPTYPE_MSI_MAPPING
);
2323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
,
2324 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB
,
2325 ht_enable_msi_mapping
);
2327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
,
2328 ht_enable_msi_mapping
);
2330 /* The P5N32-SLI motherboards from Asus have a problem with msi
2331 * for the MCP55 NIC. It is not yet determined whether the msi problem
2332 * also affects other devices. As for now, turn off msi for this device.
2334 static void __devinit
nvenet_msi_disable(struct pci_dev
*dev
)
2336 if (dmi_name_in_vendors("P5N32-SLI PREMIUM") ||
2337 dmi_name_in_vendors("P5N32-E SLI")) {
2339 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2343 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2344 PCI_DEVICE_ID_NVIDIA_NVENET_15
,
2345 nvenet_msi_disable
);
2348 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2349 * config register. This register controls the routing of legacy interrupts
2350 * from devices that route through the MCP55. If this register is misprogramed
2351 * interrupts are only sent to the bsp, unlike conventional systems where the
2352 * irq is broadxast to all online cpus. Not having this register set
2353 * properly prevents kdump from booting up properly, so lets make sure that
2354 * we have it set correctly.
2355 * Note this is an undocumented register.
2357 static void __devinit
nvbridge_check_legacy_irq_routing(struct pci_dev
*dev
)
2361 if (!pci_find_capability(dev
, PCI_CAP_ID_HT
))
2364 pci_read_config_dword(dev
, 0x74, &cfg
);
2366 if (cfg
& ((1 << 2) | (1 << 15))) {
2367 printk(KERN_INFO
"Rewriting irq routing register on MCP55\n");
2368 cfg
&= ~((1 << 2) | (1 << 15));
2369 pci_write_config_dword(dev
, 0x74, cfg
);
2373 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2374 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0
,
2375 nvbridge_check_legacy_irq_routing
);
2377 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2378 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4
,
2379 nvbridge_check_legacy_irq_routing
);
2381 static int __devinit
ht_check_msi_mapping(struct pci_dev
*dev
)
2386 /* check if there is HT MSI cap or enabled on this device */
2387 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2388 while (pos
&& ttl
--) {
2393 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2395 if (flags
& HT_MSI_FLAGS_ENABLE
) {
2402 pos
= pci_find_next_ht_capability(dev
, pos
,
2403 HT_CAPTYPE_MSI_MAPPING
);
2409 static int __devinit
host_bridge_with_leaf(struct pci_dev
*host_bridge
)
2411 struct pci_dev
*dev
;
2416 dev_no
= host_bridge
->devfn
>> 3;
2417 for (i
= dev_no
+ 1; i
< 0x20; i
++) {
2418 dev
= pci_get_slot(host_bridge
->bus
, PCI_DEVFN(i
, 0));
2422 /* found next host bridge ?*/
2423 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_SLAVE
);
2429 if (ht_check_msi_mapping(dev
)) {
2440 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2441 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2443 static int __devinit
is_end_of_ht_chain(struct pci_dev
*dev
)
2449 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_SLAVE
);
2454 pci_read_config_word(dev
, pos
+ PCI_CAP_FLAGS
, &flags
);
2456 ctrl_off
= ((flags
>> 10) & 1) ?
2457 PCI_HT_CAP_SLAVE_CTRL0
: PCI_HT_CAP_SLAVE_CTRL1
;
2458 pci_read_config_word(dev
, pos
+ ctrl_off
, &ctrl
);
2460 if (ctrl
& (1 << 6))
2467 static void __devinit
nv_ht_enable_msi_mapping(struct pci_dev
*dev
)
2469 struct pci_dev
*host_bridge
;
2474 dev_no
= dev
->devfn
>> 3;
2475 for (i
= dev_no
; i
>= 0; i
--) {
2476 host_bridge
= pci_get_slot(dev
->bus
, PCI_DEVFN(i
, 0));
2480 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
2485 pci_dev_put(host_bridge
);
2491 /* don't enable end_device/host_bridge with leaf directly here */
2492 if (host_bridge
== dev
&& is_end_of_ht_chain(host_bridge
) &&
2493 host_bridge_with_leaf(host_bridge
))
2496 /* root did that ! */
2497 if (msi_ht_cap_enabled(host_bridge
))
2500 ht_enable_msi_mapping(dev
);
2503 pci_dev_put(host_bridge
);
2506 static void __devinit
ht_disable_msi_mapping(struct pci_dev
*dev
)
2510 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2511 while (pos
&& ttl
--) {
2514 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2516 dev_info(&dev
->dev
, "Disabling HT MSI Mapping\n");
2518 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2519 flags
& ~HT_MSI_FLAGS_ENABLE
);
2521 pos
= pci_find_next_ht_capability(dev
, pos
,
2522 HT_CAPTYPE_MSI_MAPPING
);
2526 static void __devinit
__nv_msi_ht_cap_quirk(struct pci_dev
*dev
, int all
)
2528 struct pci_dev
*host_bridge
;
2532 if (!pci_msi_enabled())
2535 /* check if there is HT MSI cap or enabled on this device */
2536 found
= ht_check_msi_mapping(dev
);
2543 * HT MSI mapping should be disabled on devices that are below
2544 * a non-Hypertransport host bridge. Locate the host bridge...
2546 host_bridge
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2547 if (host_bridge
== NULL
) {
2549 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2553 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
2555 /* Host bridge is to HT */
2557 /* it is not enabled, try to enable it */
2559 ht_enable_msi_mapping(dev
);
2561 nv_ht_enable_msi_mapping(dev
);
2566 /* HT MSI is not enabled */
2570 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2571 ht_disable_msi_mapping(dev
);
2574 static void __devinit
nv_msi_ht_cap_quirk_all(struct pci_dev
*dev
)
2576 return __nv_msi_ht_cap_quirk(dev
, 1);
2579 static void __devinit
nv_msi_ht_cap_quirk_leaf(struct pci_dev
*dev
)
2581 return __nv_msi_ht_cap_quirk(dev
, 0);
2584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_leaf
);
2585 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_leaf
);
2587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_all
);
2588 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_all
);
2590 static void __devinit
quirk_msi_intx_disable_bug(struct pci_dev
*dev
)
2592 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2594 static void __devinit
quirk_msi_intx_disable_ati_bug(struct pci_dev
*dev
)
2598 /* SB700 MSI issue will be fixed at HW level from revision A21,
2599 * we need check PCI REVISION ID of SMBus controller to get SB700
2602 p
= pci_get_device(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
2607 if ((p
->revision
< 0x3B) && (p
->revision
>= 0x30))
2608 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2612 PCI_DEVICE_ID_TIGON3_5780
,
2613 quirk_msi_intx_disable_bug
);
2614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2615 PCI_DEVICE_ID_TIGON3_5780S
,
2616 quirk_msi_intx_disable_bug
);
2617 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2618 PCI_DEVICE_ID_TIGON3_5714
,
2619 quirk_msi_intx_disable_bug
);
2620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2621 PCI_DEVICE_ID_TIGON3_5714S
,
2622 quirk_msi_intx_disable_bug
);
2623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2624 PCI_DEVICE_ID_TIGON3_5715
,
2625 quirk_msi_intx_disable_bug
);
2626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2627 PCI_DEVICE_ID_TIGON3_5715S
,
2628 quirk_msi_intx_disable_bug
);
2630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4390,
2631 quirk_msi_intx_disable_ati_bug
);
2632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4391,
2633 quirk_msi_intx_disable_ati_bug
);
2634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4392,
2635 quirk_msi_intx_disable_ati_bug
);
2636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4393,
2637 quirk_msi_intx_disable_ati_bug
);
2638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4394,
2639 quirk_msi_intx_disable_ati_bug
);
2641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4373,
2642 quirk_msi_intx_disable_bug
);
2643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4374,
2644 quirk_msi_intx_disable_bug
);
2645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4375,
2646 quirk_msi_intx_disable_bug
);
2648 #endif /* CONFIG_PCI_MSI */
2650 /* Allow manual resource allocation for PCI hotplug bridges
2651 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2652 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2653 * kernel fails to allocate resources when hotplug device is
2654 * inserted and PCI bus is rescanned.
2656 static void __devinit
quirk_hotplug_bridge(struct pci_dev
*dev
)
2658 dev
->is_hotplug_bridge
= 1;
2661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT
, 0x0020, quirk_hotplug_bridge
);
2664 * This is a quirk for the Ricoh MMC controller found as a part of
2665 * some mulifunction chips.
2667 * This is very similiar and based on the ricoh_mmc driver written by
2668 * Philip Langdale. Thank you for these magic sequences.
2670 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2671 * and one or both of cardbus or firewire.
2673 * It happens that they implement SD and MMC
2674 * support as separate controllers (and PCI functions). The linux SDHCI
2675 * driver supports MMC cards but the chip detects MMC cards in hardware
2676 * and directs them to the MMC controller - so the SDHCI driver never sees
2679 * To get around this, we must disable the useless MMC controller.
2680 * At that point, the SDHCI controller will start seeing them
2681 * It seems to be the case that the relevant PCI registers to deactivate the
2682 * MMC controller live on PCI function 0, which might be the cardbus controller
2683 * or the firewire controller, depending on the particular chip in question
2685 * This has to be done early, because as soon as we disable the MMC controller
2686 * other pci functions shift up one level, e.g. function #2 becomes function
2687 * #1, and this will confuse the pci core.
2690 #ifdef CONFIG_MMC_RICOH_MMC
2691 static void ricoh_mmc_fixup_rl5c476(struct pci_dev
*dev
)
2693 /* disable via cardbus interface */
2698 /* disable must be done via function #0 */
2699 if (PCI_FUNC(dev
->devfn
))
2702 pci_read_config_byte(dev
, 0xB7, &disable
);
2706 pci_read_config_byte(dev
, 0x8E, &write_enable
);
2707 pci_write_config_byte(dev
, 0x8E, 0xAA);
2708 pci_read_config_byte(dev
, 0x8D, &write_target
);
2709 pci_write_config_byte(dev
, 0x8D, 0xB7);
2710 pci_write_config_byte(dev
, 0xB7, disable
| 0x02);
2711 pci_write_config_byte(dev
, 0x8E, write_enable
);
2712 pci_write_config_byte(dev
, 0x8D, write_target
);
2714 dev_notice(&dev
->dev
, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2715 dev_notice(&dev
->dev
, "MMC cards are now supported by standard SDHCI controller\n");
2717 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_RL5C476
, ricoh_mmc_fixup_rl5c476
);
2718 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_RL5C476
, ricoh_mmc_fixup_rl5c476
);
2720 static void ricoh_mmc_fixup_r5c832(struct pci_dev
*dev
)
2722 /* disable via firewire interface */
2726 /* disable must be done via function #0 */
2727 if (PCI_FUNC(dev
->devfn
))
2730 pci_read_config_byte(dev
, 0xCB, &disable
);
2735 pci_read_config_byte(dev
, 0xCA, &write_enable
);
2736 pci_write_config_byte(dev
, 0xCA, 0x57);
2737 pci_write_config_byte(dev
, 0xCB, disable
| 0x02);
2738 pci_write_config_byte(dev
, 0xCA, write_enable
);
2740 dev_notice(&dev
->dev
, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2741 dev_notice(&dev
->dev
, "MMC cards are now supported by standard SDHCI controller\n");
2743 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5C832
, ricoh_mmc_fixup_r5c832
);
2744 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5C832
, ricoh_mmc_fixup_r5c832
);
2745 #endif /*CONFIG_MMC_RICOH_MMC*/
2747 #if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
2748 #define VTUNCERRMSK_REG 0x1ac
2749 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2751 * This is a quirk for masking vt-d spec defined errors to platform error
2752 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2753 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2754 * on the RAS config settings of the platform) when a vt-d fault happens.
2755 * The resulting SMI caused the system to hang.
2757 * VT-d spec related errors are already handled by the VT-d OS code, so no
2758 * need to report the same error through other channels.
2760 static void vtd_mask_spec_errors(struct pci_dev
*dev
)
2764 pci_read_config_dword(dev
, VTUNCERRMSK_REG
, &word
);
2765 pci_write_config_dword(dev
, VTUNCERRMSK_REG
, word
| VTD_MSK_SPEC_ERRORS
);
2767 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x342e, vtd_mask_spec_errors
);
2768 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x3c28, vtd_mask_spec_errors
);
2771 static void pci_do_fixups(struct pci_dev
*dev
, struct pci_fixup
*f
,
2772 struct pci_fixup
*end
)
2775 if ((f
->vendor
== dev
->vendor
|| f
->vendor
== (u16
) PCI_ANY_ID
) &&
2776 (f
->device
== dev
->device
|| f
->device
== (u16
) PCI_ANY_ID
)) {
2777 dev_dbg(&dev
->dev
, "calling %pF\n", f
->hook
);
2784 extern struct pci_fixup __start_pci_fixups_early
[];
2785 extern struct pci_fixup __end_pci_fixups_early
[];
2786 extern struct pci_fixup __start_pci_fixups_header
[];
2787 extern struct pci_fixup __end_pci_fixups_header
[];
2788 extern struct pci_fixup __start_pci_fixups_final
[];
2789 extern struct pci_fixup __end_pci_fixups_final
[];
2790 extern struct pci_fixup __start_pci_fixups_enable
[];
2791 extern struct pci_fixup __end_pci_fixups_enable
[];
2792 extern struct pci_fixup __start_pci_fixups_resume
[];
2793 extern struct pci_fixup __end_pci_fixups_resume
[];
2794 extern struct pci_fixup __start_pci_fixups_resume_early
[];
2795 extern struct pci_fixup __end_pci_fixups_resume_early
[];
2796 extern struct pci_fixup __start_pci_fixups_suspend
[];
2797 extern struct pci_fixup __end_pci_fixups_suspend
[];
2800 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
)
2802 struct pci_fixup
*start
, *end
;
2805 case pci_fixup_early
:
2806 start
= __start_pci_fixups_early
;
2807 end
= __end_pci_fixups_early
;
2810 case pci_fixup_header
:
2811 start
= __start_pci_fixups_header
;
2812 end
= __end_pci_fixups_header
;
2815 case pci_fixup_final
:
2816 start
= __start_pci_fixups_final
;
2817 end
= __end_pci_fixups_final
;
2820 case pci_fixup_enable
:
2821 start
= __start_pci_fixups_enable
;
2822 end
= __end_pci_fixups_enable
;
2825 case pci_fixup_resume
:
2826 start
= __start_pci_fixups_resume
;
2827 end
= __end_pci_fixups_resume
;
2830 case pci_fixup_resume_early
:
2831 start
= __start_pci_fixups_resume_early
;
2832 end
= __end_pci_fixups_resume_early
;
2835 case pci_fixup_suspend
:
2836 start
= __start_pci_fixups_suspend
;
2837 end
= __end_pci_fixups_suspend
;
2841 /* stupid compiler warning, you would think with an enum... */
2844 pci_do_fixups(dev
, start
, end
);
2846 EXPORT_SYMBOL(pci_fixup_device
);
2848 static int __init
pci_apply_final_quirks(void)
2850 struct pci_dev
*dev
= NULL
;
2854 if (pci_cache_line_size
)
2855 printk(KERN_DEBUG
"PCI: CLS %u bytes\n",
2856 pci_cache_line_size
<< 2);
2858 for_each_pci_dev(dev
) {
2859 pci_fixup_device(pci_fixup_final
, dev
);
2861 * If arch hasn't set it explicitly yet, use the CLS
2862 * value shared by all PCI devices. If there's a
2863 * mismatch, fall back to the default value.
2865 if (!pci_cache_line_size
) {
2866 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &tmp
);
2869 if (!tmp
|| cls
== tmp
)
2872 printk(KERN_DEBUG
"PCI: CLS mismatch (%u != %u), "
2873 "using %u bytes\n", cls
<< 2, tmp
<< 2,
2874 pci_dfl_cache_line_size
<< 2);
2875 pci_cache_line_size
= pci_dfl_cache_line_size
;
2878 if (!pci_cache_line_size
) {
2879 printk(KERN_DEBUG
"PCI: CLS %u bytes, default %u\n",
2880 cls
<< 2, pci_dfl_cache_line_size
<< 2);
2881 pci_cache_line_size
= cls
? cls
: pci_dfl_cache_line_size
;
2887 fs_initcall_sync(pci_apply_final_quirks
);
2890 * Followings are device-specific reset methods which can be used to
2891 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
2894 static int reset_intel_generic_dev(struct pci_dev
*dev
, int probe
)
2898 /* only implement PCI_CLASS_SERIAL_USB at present */
2899 if (dev
->class == PCI_CLASS_SERIAL_USB
) {
2900 pos
= pci_find_capability(dev
, PCI_CAP_ID_VNDR
);
2907 pci_write_config_byte(dev
, pos
+ 0x4, 1);
2916 static int reset_intel_82599_sfp_virtfn(struct pci_dev
*dev
, int probe
)
2920 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2927 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
,
2928 PCI_EXP_DEVCTL_BCR_FLR
);
2934 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
2936 static const struct pci_dev_reset_methods pci_dev_reset_methods
[] = {
2937 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82599_SFP_VF
,
2938 reset_intel_82599_sfp_virtfn
},
2939 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
2940 reset_intel_generic_dev
},
2944 int pci_dev_specific_reset(struct pci_dev
*dev
, int probe
)
2946 const struct pci_dev_reset_methods
*i
;
2948 for (i
= pci_dev_reset_methods
; i
->reset
; i
++) {
2949 if ((i
->vendor
== dev
->vendor
||
2950 i
->vendor
== (u16
)PCI_ANY_ID
) &&
2951 (i
->device
== dev
->device
||
2952 i
->device
== (u16
)PCI_ANY_ID
))
2953 return i
->reset(dev
, probe
);