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ath: remove ath_regulatory::current_rd_ext
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / hw.c
blobfd7c2077dfd46d9c4788843f336a4012e49d0e39
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
20
21 #include "hw.h"
22 #include "hw-ops.h"
23 #include "rc.h"
24 #include "ar9003_mac.h"
25
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
27
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
32
33 static int __init ath9k_init(void)
34 {
35 return 0;
36 }
37 module_init(ath9k_init);
38
39 static void __exit ath9k_exit(void)
40 {
41 return;
42 }
43 module_exit(ath9k_exit);
44
45 /* Private hardware callbacks */
46
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48 {
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50 }
51
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55 }
56
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59 {
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61 }
62
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64 {
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69 }
70
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72 {
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
89
90 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
91 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
92 clockrate = 117;
93 else if (!ah->curchan) /* should really check for CCK instead */
94 clockrate = ATH9K_CLOCK_RATE_CCK;
95 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
96 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
97 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
98 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
99 else
100 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
101
102 if (conf_is_ht40(conf))
103 clockrate *= 2;
104
105 if (ah->curchan) {
106 if (IS_CHAN_HALF_RATE(ah->curchan))
107 clockrate /= 2;
108 if (IS_CHAN_QUARTER_RATE(ah->curchan))
109 clockrate /= 4;
110 }
111
112 common->clockrate = clockrate;
113 }
114
115 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
116 {
117 struct ath_common *common = ath9k_hw_common(ah);
118
119 return usecs * common->clockrate;
120 }
121
122 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
123 {
124 int i;
125
126 BUG_ON(timeout < AH_TIME_QUANTUM);
127
128 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
129 if ((REG_READ(ah, reg) & mask) == val)
130 return true;
131
132 udelay(AH_TIME_QUANTUM);
133 }
134
135 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
136 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
137 timeout, reg, REG_READ(ah, reg), mask, val);
138
139 return false;
140 }
141 EXPORT_SYMBOL(ath9k_hw_wait);
142
143 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
144 int column, unsigned int *writecnt)
145 {
146 int r;
147
148 ENABLE_REGWRITE_BUFFER(ah);
149 for (r = 0; r < array->ia_rows; r++) {
150 REG_WRITE(ah, INI_RA(array, r, 0),
151 INI_RA(array, r, column));
152 DO_DELAY(*writecnt);
153 }
154 REGWRITE_BUFFER_FLUSH(ah);
155 }
156
157 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
158 {
159 u32 retval;
160 int i;
161
162 for (i = 0, retval = 0; i < n; i++) {
163 retval = (retval << 1) | (val & 1);
164 val >>= 1;
165 }
166 return retval;
167 }
168
169 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
170 u8 phy, int kbps,
171 u32 frameLen, u16 rateix,
172 bool shortPreamble)
173 {
174 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
175
176 if (kbps == 0)
177 return 0;
178
179 switch (phy) {
180 case WLAN_RC_PHY_CCK:
181 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
182 if (shortPreamble)
183 phyTime >>= 1;
184 numBits = frameLen << 3;
185 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
186 break;
187 case WLAN_RC_PHY_OFDM:
188 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
189 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
190 numBits = OFDM_PLCP_BITS + (frameLen << 3);
191 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
192 txTime = OFDM_SIFS_TIME_QUARTER
193 + OFDM_PREAMBLE_TIME_QUARTER
194 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
195 } else if (ah->curchan &&
196 IS_CHAN_HALF_RATE(ah->curchan)) {
197 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
198 numBits = OFDM_PLCP_BITS + (frameLen << 3);
199 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
200 txTime = OFDM_SIFS_TIME_HALF +
201 OFDM_PREAMBLE_TIME_HALF
202 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
203 } else {
204 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
205 numBits = OFDM_PLCP_BITS + (frameLen << 3);
206 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
207 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
208 + (numSymbols * OFDM_SYMBOL_TIME);
209 }
210 break;
211 default:
212 ath_err(ath9k_hw_common(ah),
213 "Unknown phy %u (rate ix %u)\n", phy, rateix);
214 txTime = 0;
215 break;
216 }
217
218 return txTime;
219 }
220 EXPORT_SYMBOL(ath9k_hw_computetxtime);
221
222 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
223 struct ath9k_channel *chan,
224 struct chan_centers *centers)
225 {
226 int8_t extoff;
227
228 if (!IS_CHAN_HT40(chan)) {
229 centers->ctl_center = centers->ext_center =
230 centers->synth_center = chan->channel;
231 return;
232 }
233
234 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
235 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
236 centers->synth_center =
237 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
238 extoff = 1;
239 } else {
240 centers->synth_center =
241 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
242 extoff = -1;
243 }
244
245 centers->ctl_center =
246 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
247 /* 25 MHz spacing is supported by hw but not on upper layers */
248 centers->ext_center =
249 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
250 }
251
252 /******************/
253 /* Chip Revisions */
254 /******************/
255
256 static void ath9k_hw_read_revisions(struct ath_hw *ah)
257 {
258 u32 val;
259
260 switch (ah->hw_version.devid) {
261 case AR5416_AR9100_DEVID:
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
263 break;
264 case AR9300_DEVID_AR9330:
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
266 if (ah->get_mac_revision) {
267 ah->hw_version.macRev = ah->get_mac_revision();
268 } else {
269 val = REG_READ(ah, AR_SREV);
270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
271 }
272 return;
273 case AR9300_DEVID_AR9340:
274 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
275 val = REG_READ(ah, AR_SREV);
276 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
277 return;
278 }
279
280 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
281
282 if (val == 0xFF) {
283 val = REG_READ(ah, AR_SREV);
284 ah->hw_version.macVersion =
285 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
286 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
287
288 if (AR_SREV_9480(ah))
289 ah->is_pciexpress = true;
290 else
291 ah->is_pciexpress = (val &
292 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
293 } else {
294 if (!AR_SREV_9100(ah))
295 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
296
297 ah->hw_version.macRev = val & AR_SREV_REVISION;
298
299 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
300 ah->is_pciexpress = true;
301 }
302 }
303
304 /************************************/
305 /* HW Attach, Detach, Init Routines */
306 /************************************/
307
308 static void ath9k_hw_disablepcie(struct ath_hw *ah)
309 {
310 if (!AR_SREV_5416(ah))
311 return;
312
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
322
323 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
324 }
325
326 static void ath9k_hw_aspm_init(struct ath_hw *ah)
327 {
328 struct ath_common *common = ath9k_hw_common(ah);
329
330 if (common->bus_ops->aspm_init)
331 common->bus_ops->aspm_init(common);
332 }
333
334 /* This should work for all families including legacy */
335 static bool ath9k_hw_chip_test(struct ath_hw *ah)
336 {
337 struct ath_common *common = ath9k_hw_common(ah);
338 u32 regAddr[2] = { AR_STA_ID0 };
339 u32 regHold[2];
340 static const u32 patternData[4] = {
341 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
342 };
343 int i, j, loop_max;
344
345 if (!AR_SREV_9300_20_OR_LATER(ah)) {
346 loop_max = 2;
347 regAddr[1] = AR_PHY_BASE + (8 << 2);
348 } else
349 loop_max = 1;
350
351 for (i = 0; i < loop_max; i++) {
352 u32 addr = regAddr[i];
353 u32 wrData, rdData;
354
355 regHold[i] = REG_READ(ah, addr);
356 for (j = 0; j < 0x100; j++) {
357 wrData = (j << 16) | j;
358 REG_WRITE(ah, addr, wrData);
359 rdData = REG_READ(ah, addr);
360 if (rdData != wrData) {
361 ath_err(common,
362 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
363 addr, wrData, rdData);
364 return false;
365 }
366 }
367 for (j = 0; j < 4; j++) {
368 wrData = patternData[j];
369 REG_WRITE(ah, addr, wrData);
370 rdData = REG_READ(ah, addr);
371 if (wrData != rdData) {
372 ath_err(common,
373 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
374 addr, wrData, rdData);
375 return false;
376 }
377 }
378 REG_WRITE(ah, regAddr[i], regHold[i]);
379 }
380 udelay(100);
381
382 return true;
383 }
384
385 static void ath9k_hw_init_config(struct ath_hw *ah)
386 {
387 int i;
388
389 ah->config.dma_beacon_response_time = 2;
390 ah->config.sw_beacon_response_time = 10;
391 ah->config.additional_swba_backoff = 0;
392 ah->config.ack_6mb = 0x0;
393 ah->config.cwm_ignore_extcca = 0;
394 ah->config.pcie_clock_req = 0;
395 ah->config.pcie_waen = 0;
396 ah->config.analog_shiftreg = 1;
397 ah->config.enable_ani = true;
398
399 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
400 ah->config.spurchans[i][0] = AR_NO_SPUR;
401 ah->config.spurchans[i][1] = AR_NO_SPUR;
402 }
403
404 /* PAPRD needs some more work to be enabled */
405 ah->config.paprd_disable = 1;
406
407 ah->config.rx_intr_mitigation = true;
408 ah->config.pcieSerDesWrite = true;
409
410 /*
411 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
412 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
413 * This means we use it for all AR5416 devices, and the few
414 * minor PCI AR9280 devices out there.
415 *
416 * Serialization is required because these devices do not handle
417 * well the case of two concurrent reads/writes due to the latency
418 * involved. During one read/write another read/write can be issued
419 * on another CPU while the previous read/write may still be working
420 * on our hardware, if we hit this case the hardware poops in a loop.
421 * We prevent this by serializing reads and writes.
422 *
423 * This issue is not present on PCI-Express devices or pre-AR5416
424 * devices (legacy, 802.11abg).
425 */
426 if (num_possible_cpus() > 1)
427 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
428 }
429
430 static void ath9k_hw_init_defaults(struct ath_hw *ah)
431 {
432 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
433
434 regulatory->country_code = CTRY_DEFAULT;
435 regulatory->power_limit = MAX_RATE_POWER;
436
437 ah->hw_version.magic = AR5416_MAGIC;
438 ah->hw_version.subvendorid = 0;
439
440 ah->atim_window = 0;
441 ah->sta_id1_defaults =
442 AR_STA_ID1_CRPT_MIC_ENABLE |
443 AR_STA_ID1_MCAST_KSRCH;
444 if (AR_SREV_9100(ah))
445 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
446 ah->enable_32kHz_clock = DONT_USE_32KHZ;
447 ah->slottime = ATH9K_SLOT_TIME_9;
448 ah->globaltxtimeout = (u32) -1;
449 ah->power_mode = ATH9K_PM_UNDEFINED;
450 }
451
452 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
453 {
454 struct ath_common *common = ath9k_hw_common(ah);
455 u32 sum;
456 int i;
457 u16 eeval;
458 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
459
460 sum = 0;
461 for (i = 0; i < 3; i++) {
462 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
463 sum += eeval;
464 common->macaddr[2 * i] = eeval >> 8;
465 common->macaddr[2 * i + 1] = eeval & 0xff;
466 }
467 if (sum == 0 || sum == 0xffff * 3)
468 return -EADDRNOTAVAIL;
469
470 return 0;
471 }
472
473 static int ath9k_hw_post_init(struct ath_hw *ah)
474 {
475 struct ath_common *common = ath9k_hw_common(ah);
476 int ecode;
477
478 if (common->bus_ops->ath_bus_type != ATH_USB) {
479 if (!ath9k_hw_chip_test(ah))
480 return -ENODEV;
481 }
482
483 if (!AR_SREV_9300_20_OR_LATER(ah)) {
484 ecode = ar9002_hw_rf_claim(ah);
485 if (ecode != 0)
486 return ecode;
487 }
488
489 ecode = ath9k_hw_eeprom_init(ah);
490 if (ecode != 0)
491 return ecode;
492
493 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
494 "Eeprom VER: %d, REV: %d\n",
495 ah->eep_ops->get_eeprom_ver(ah),
496 ah->eep_ops->get_eeprom_rev(ah));
497
498 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
499 if (ecode) {
500 ath_err(ath9k_hw_common(ah),
501 "Failed allocating banks for external radio\n");
502 ath9k_hw_rf_free_ext_banks(ah);
503 return ecode;
504 }
505
506 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
507 ath9k_hw_ani_setup(ah);
508 ath9k_hw_ani_init(ah);
509 }
510
511 return 0;
512 }
513
514 static void ath9k_hw_attach_ops(struct ath_hw *ah)
515 {
516 if (AR_SREV_9300_20_OR_LATER(ah))
517 ar9003_hw_attach_ops(ah);
518 else
519 ar9002_hw_attach_ops(ah);
520 }
521
522 /* Called for all hardware families */
523 static int __ath9k_hw_init(struct ath_hw *ah)
524 {
525 struct ath_common *common = ath9k_hw_common(ah);
526 int r = 0;
527
528 ath9k_hw_read_revisions(ah);
529
530 /*
531 * Read back AR_WA into a permanent copy and set bits 14 and 17.
532 * We need to do this to avoid RMW of this register. We cannot
533 * read the reg when chip is asleep.
534 */
535 ah->WARegVal = REG_READ(ah, AR_WA);
536 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
537 AR_WA_ASPM_TIMER_BASED_DISABLE);
538
539 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
540 ath_err(common, "Couldn't reset chip\n");
541 return -EIO;
542 }
543
544 ath9k_hw_init_defaults(ah);
545 ath9k_hw_init_config(ah);
546
547 ath9k_hw_attach_ops(ah);
548
549 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
550 ath_err(common, "Couldn't wakeup chip\n");
551 return -EIO;
552 }
553
554 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
555 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
556 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
557 !ah->is_pciexpress)) {
558 ah->config.serialize_regmode =
559 SER_REG_MODE_ON;
560 } else {
561 ah->config.serialize_regmode =
562 SER_REG_MODE_OFF;
563 }
564 }
565
566 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
567 ah->config.serialize_regmode);
568
569 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
570 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
571 else
572 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
573
574 switch (ah->hw_version.macVersion) {
575 case AR_SREV_VERSION_5416_PCI:
576 case AR_SREV_VERSION_5416_PCIE:
577 case AR_SREV_VERSION_9160:
578 case AR_SREV_VERSION_9100:
579 case AR_SREV_VERSION_9280:
580 case AR_SREV_VERSION_9285:
581 case AR_SREV_VERSION_9287:
582 case AR_SREV_VERSION_9271:
583 case AR_SREV_VERSION_9300:
584 case AR_SREV_VERSION_9330:
585 case AR_SREV_VERSION_9485:
586 case AR_SREV_VERSION_9340:
587 case AR_SREV_VERSION_9480:
588 break;
589 default:
590 ath_err(common,
591 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
592 ah->hw_version.macVersion, ah->hw_version.macRev);
593 return -EOPNOTSUPP;
594 }
595
596 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
597 AR_SREV_9330(ah))
598 ah->is_pciexpress = false;
599
600 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
601 ath9k_hw_init_cal_settings(ah);
602
603 ah->ani_function = ATH9K_ANI_ALL;
604 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
605 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
606 if (!AR_SREV_9300_20_OR_LATER(ah))
607 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
608
609 ath9k_hw_init_mode_regs(ah);
610
611 if (!ah->is_pciexpress)
612 ath9k_hw_disablepcie(ah);
613
614 if (!AR_SREV_9300_20_OR_LATER(ah))
615 ar9002_hw_cck_chan14_spread(ah);
616
617 r = ath9k_hw_post_init(ah);
618 if (r)
619 return r;
620
621 ath9k_hw_init_mode_gain_regs(ah);
622 r = ath9k_hw_fill_cap_info(ah);
623 if (r)
624 return r;
625
626 if (ah->is_pciexpress)
627 ath9k_hw_aspm_init(ah);
628
629 r = ath9k_hw_init_macaddr(ah);
630 if (r) {
631 ath_err(common, "Failed to initialize MAC address\n");
632 return r;
633 }
634
635 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
636 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
637 else
638 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
639
640 if (AR_SREV_9330(ah))
641 ah->bb_watchdog_timeout_ms = 85;
642 else
643 ah->bb_watchdog_timeout_ms = 25;
644
645 common->state = ATH_HW_INITIALIZED;
646
647 return 0;
648 }
649
650 int ath9k_hw_init(struct ath_hw *ah)
651 {
652 int ret;
653 struct ath_common *common = ath9k_hw_common(ah);
654
655 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
656 switch (ah->hw_version.devid) {
657 case AR5416_DEVID_PCI:
658 case AR5416_DEVID_PCIE:
659 case AR5416_AR9100_DEVID:
660 case AR9160_DEVID_PCI:
661 case AR9280_DEVID_PCI:
662 case AR9280_DEVID_PCIE:
663 case AR9285_DEVID_PCIE:
664 case AR9287_DEVID_PCI:
665 case AR9287_DEVID_PCIE:
666 case AR2427_DEVID_PCIE:
667 case AR9300_DEVID_PCIE:
668 case AR9300_DEVID_AR9485_PCIE:
669 case AR9300_DEVID_AR9330:
670 case AR9300_DEVID_AR9340:
671 case AR9300_DEVID_AR9580:
672 case AR9300_DEVID_AR9480:
673 break;
674 default:
675 if (common->bus_ops->ath_bus_type == ATH_USB)
676 break;
677 ath_err(common, "Hardware device ID 0x%04x not supported\n",
678 ah->hw_version.devid);
679 return -EOPNOTSUPP;
680 }
681
682 ret = __ath9k_hw_init(ah);
683 if (ret) {
684 ath_err(common,
685 "Unable to initialize hardware; initialization status: %d\n",
686 ret);
687 return ret;
688 }
689
690 return 0;
691 }
692 EXPORT_SYMBOL(ath9k_hw_init);
693
694 static void ath9k_hw_init_qos(struct ath_hw *ah)
695 {
696 ENABLE_REGWRITE_BUFFER(ah);
697
698 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
699 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
700
701 REG_WRITE(ah, AR_QOS_NO_ACK,
702 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
703 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
704 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
705
706 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
707 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
708 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
709 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
710 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
711
712 REGWRITE_BUFFER_FLUSH(ah);
713 }
714
715 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
716 {
717 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
718 udelay(100);
719 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
720
721 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
722 udelay(100);
723
724 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
725 }
726 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
727
728 static void ath9k_hw_init_pll(struct ath_hw *ah,
729 struct ath9k_channel *chan)
730 {
731 u32 pll;
732
733 if (AR_SREV_9485(ah)) {
734
735 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
736 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
737 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
738 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
739 AR_CH0_DPLL2_KD, 0x40);
740 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
741 AR_CH0_DPLL2_KI, 0x4);
742
743 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
744 AR_CH0_BB_DPLL1_REFDIV, 0x5);
745 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
746 AR_CH0_BB_DPLL1_NINI, 0x58);
747 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
748 AR_CH0_BB_DPLL1_NFRAC, 0x0);
749
750 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
751 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
752 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
753 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
755 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
756
757 /* program BB PLL phase_shift to 0x6 */
758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
759 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
760
761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
762 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
763 udelay(1000);
764 } else if (AR_SREV_9330(ah)) {
765 u32 ddr_dpll2, pll_control2, kd;
766
767 if (ah->is_clk_25mhz) {
768 ddr_dpll2 = 0x18e82f01;
769 pll_control2 = 0xe04a3d;
770 kd = 0x1d;
771 } else {
772 ddr_dpll2 = 0x19e82f01;
773 pll_control2 = 0x886666;
774 kd = 0x3d;
775 }
776
777 /* program DDR PLL ki and kd value */
778 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
779
780 /* program DDR PLL phase_shift */
781 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
782 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
783
784 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
785 udelay(1000);
786
787 /* program refdiv, nint, frac to RTC register */
788 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
789
790 /* program BB PLL kd and ki value */
791 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
792 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
793
794 /* program BB PLL phase_shift */
795 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
796 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
797 } else if (AR_SREV_9340(ah)) {
798 u32 regval, pll2_divint, pll2_divfrac, refdiv;
799
800 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
801 udelay(1000);
802
803 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
804 udelay(100);
805
806 if (ah->is_clk_25mhz) {
807 pll2_divint = 0x54;
808 pll2_divfrac = 0x1eb85;
809 refdiv = 3;
810 } else {
811 pll2_divint = 88;
812 pll2_divfrac = 0;
813 refdiv = 5;
814 }
815
816 regval = REG_READ(ah, AR_PHY_PLL_MODE);
817 regval |= (0x1 << 16);
818 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
819 udelay(100);
820
821 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
822 (pll2_divint << 18) | pll2_divfrac);
823 udelay(100);
824
825 regval = REG_READ(ah, AR_PHY_PLL_MODE);
826 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
827 (0x4 << 26) | (0x18 << 19);
828 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
829 REG_WRITE(ah, AR_PHY_PLL_MODE,
830 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
831 udelay(1000);
832 }
833
834 pll = ath9k_hw_compute_pll_control(ah, chan);
835
836 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
837
838 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
839 udelay(1000);
840
841 /* Switch the core clock for ar9271 to 117Mhz */
842 if (AR_SREV_9271(ah)) {
843 udelay(500);
844 REG_WRITE(ah, 0x50040, 0x304);
845 }
846
847 udelay(RTC_PLL_SETTLE_DELAY);
848
849 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
850
851 if (AR_SREV_9340(ah)) {
852 if (ah->is_clk_25mhz) {
853 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
854 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
855 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
856 } else {
857 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
858 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
859 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
860 }
861 udelay(100);
862 }
863 }
864
865 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
866 enum nl80211_iftype opmode)
867 {
868 u32 sync_default = AR_INTR_SYNC_DEFAULT;
869 u32 imr_reg = AR_IMR_TXERR |
870 AR_IMR_TXURN |
871 AR_IMR_RXERR |
872 AR_IMR_RXORN |
873 AR_IMR_BCNMISC;
874
875 if (AR_SREV_9340(ah))
876 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
877
878 if (AR_SREV_9300_20_OR_LATER(ah)) {
879 imr_reg |= AR_IMR_RXOK_HP;
880 if (ah->config.rx_intr_mitigation)
881 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
882 else
883 imr_reg |= AR_IMR_RXOK_LP;
884
885 } else {
886 if (ah->config.rx_intr_mitigation)
887 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
888 else
889 imr_reg |= AR_IMR_RXOK;
890 }
891
892 if (ah->config.tx_intr_mitigation)
893 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
894 else
895 imr_reg |= AR_IMR_TXOK;
896
897 if (opmode == NL80211_IFTYPE_AP)
898 imr_reg |= AR_IMR_MIB;
899
900 ENABLE_REGWRITE_BUFFER(ah);
901
902 REG_WRITE(ah, AR_IMR, imr_reg);
903 ah->imrs2_reg |= AR_IMR_S2_GTT;
904 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
905
906 if (!AR_SREV_9100(ah)) {
907 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
908 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
909 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
910 }
911
912 REGWRITE_BUFFER_FLUSH(ah);
913
914 if (AR_SREV_9300_20_OR_LATER(ah)) {
915 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
916 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
917 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
918 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
919 }
920 }
921
922 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
923 {
924 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
925 val = min(val, (u32) 0xFFFF);
926 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
927 }
928
929 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
930 {
931 u32 val = ath9k_hw_mac_to_clks(ah, us);
932 val = min(val, (u32) 0xFFFF);
933 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
934 }
935
936 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
937 {
938 u32 val = ath9k_hw_mac_to_clks(ah, us);
939 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
940 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
941 }
942
943 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
944 {
945 u32 val = ath9k_hw_mac_to_clks(ah, us);
946 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
947 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
948 }
949
950 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
951 {
952 if (tu > 0xFFFF) {
953 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
954 "bad global tx timeout %u\n", tu);
955 ah->globaltxtimeout = (u32) -1;
956 return false;
957 } else {
958 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
959 ah->globaltxtimeout = tu;
960 return true;
961 }
962 }
963
964 void ath9k_hw_init_global_settings(struct ath_hw *ah)
965 {
966 struct ath_common *common = ath9k_hw_common(ah);
967 struct ieee80211_conf *conf = &common->hw->conf;
968 const struct ath9k_channel *chan = ah->curchan;
969 int acktimeout, ctstimeout;
970 int slottime;
971 int sifstime;
972 int rx_lat = 0, tx_lat = 0, eifs = 0;
973 u32 reg;
974
975 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
976 ah->misc_mode);
977
978 if (!chan)
979 return;
980
981 if (ah->misc_mode != 0)
982 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
983
984 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
985 rx_lat = 41;
986 else
987 rx_lat = 37;
988 tx_lat = 54;
989
990 if (IS_CHAN_HALF_RATE(chan)) {
991 eifs = 175;
992 rx_lat *= 2;
993 tx_lat *= 2;
994 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
995 tx_lat += 11;
996
997 slottime = 13;
998 sifstime = 32;
999 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1000 eifs = 340;
1001 rx_lat = (rx_lat * 4) - 1;
1002 tx_lat *= 4;
1003 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1004 tx_lat += 22;
1005
1006 slottime = 21;
1007 sifstime = 64;
1008 } else {
1009 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1010 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1011 reg = AR_USEC_ASYNC_FIFO;
1012 } else {
1013 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1014 common->clockrate;
1015 reg = REG_READ(ah, AR_USEC);
1016 }
1017 rx_lat = MS(reg, AR_USEC_RX_LAT);
1018 tx_lat = MS(reg, AR_USEC_TX_LAT);
1019
1020 slottime = ah->slottime;
1021 if (IS_CHAN_5GHZ(chan))
1022 sifstime = 16;
1023 else
1024 sifstime = 10;
1025 }
1026
1027 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1028 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
1029 ctstimeout = acktimeout;
1030
1031 /*
1032 * Workaround for early ACK timeouts, add an offset to match the
1033 * initval's 64us ack timeout value.
1034 * This was initially only meant to work around an issue with delayed
1035 * BA frames in some implementations, but it has been found to fix ACK
1036 * timeout issues in other cases as well.
1037 */
1038 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1039 acktimeout += 64 - sifstime - ah->slottime;
1040
1041 ath9k_hw_set_sifs_time(ah, sifstime);
1042 ath9k_hw_setslottime(ah, slottime);
1043 ath9k_hw_set_ack_timeout(ah, acktimeout);
1044 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1045 if (ah->globaltxtimeout != (u32) -1)
1046 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1047
1048 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1049 REG_RMW(ah, AR_USEC,
1050 (common->clockrate - 1) |
1051 SM(rx_lat, AR_USEC_RX_LAT) |
1052 SM(tx_lat, AR_USEC_TX_LAT),
1053 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1054
1055 }
1056 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1057
1058 void ath9k_hw_deinit(struct ath_hw *ah)
1059 {
1060 struct ath_common *common = ath9k_hw_common(ah);
1061
1062 if (common->state < ATH_HW_INITIALIZED)
1063 goto free_hw;
1064
1065 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1066
1067 free_hw:
1068 ath9k_hw_rf_free_ext_banks(ah);
1069 }
1070 EXPORT_SYMBOL(ath9k_hw_deinit);
1071
1072 /*******/
1073 /* INI */
1074 /*******/
1075
1076 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1077 {
1078 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1079
1080 if (IS_CHAN_B(chan))
1081 ctl |= CTL_11B;
1082 else if (IS_CHAN_G(chan))
1083 ctl |= CTL_11G;
1084 else
1085 ctl |= CTL_11A;
1086
1087 return ctl;
1088 }
1089
1090 /****************************************/
1091 /* Reset and Channel Switching Routines */
1092 /****************************************/
1093
1094 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1095 {
1096 struct ath_common *common = ath9k_hw_common(ah);
1097
1098 ENABLE_REGWRITE_BUFFER(ah);
1099
1100 /*
1101 * set AHB_MODE not to do cacheline prefetches
1102 */
1103 if (!AR_SREV_9300_20_OR_LATER(ah))
1104 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1105
1106 /*
1107 * let mac dma reads be in 128 byte chunks
1108 */
1109 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1110
1111 REGWRITE_BUFFER_FLUSH(ah);
1112
1113 /*
1114 * Restore TX Trigger Level to its pre-reset value.
1115 * The initial value depends on whether aggregation is enabled, and is
1116 * adjusted whenever underruns are detected.
1117 */
1118 if (!AR_SREV_9300_20_OR_LATER(ah))
1119 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1120
1121 ENABLE_REGWRITE_BUFFER(ah);
1122
1123 /*
1124 * let mac dma writes be in 128 byte chunks
1125 */
1126 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1127
1128 /*
1129 * Setup receive FIFO threshold to hold off TX activities
1130 */
1131 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1132
1133 if (AR_SREV_9300_20_OR_LATER(ah)) {
1134 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1135 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1136
1137 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1138 ah->caps.rx_status_len);
1139 }
1140
1141 /*
1142 * reduce the number of usable entries in PCU TXBUF to avoid
1143 * wrap around issues.
1144 */
1145 if (AR_SREV_9285(ah)) {
1146 /* For AR9285 the number of Fifos are reduced to half.
1147 * So set the usable tx buf size also to half to
1148 * avoid data/delimiter underruns
1149 */
1150 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1151 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1152 } else if (!AR_SREV_9271(ah)) {
1153 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1154 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1155 }
1156
1157 REGWRITE_BUFFER_FLUSH(ah);
1158
1159 if (AR_SREV_9300_20_OR_LATER(ah))
1160 ath9k_hw_reset_txstatus_ring(ah);
1161 }
1162
1163 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1164 {
1165 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1166 u32 set = AR_STA_ID1_KSRCH_MODE;
1167
1168 switch (opmode) {
1169 case NL80211_IFTYPE_ADHOC:
1170 case NL80211_IFTYPE_MESH_POINT:
1171 set |= AR_STA_ID1_ADHOC;
1172 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1173 break;
1174 case NL80211_IFTYPE_AP:
1175 set |= AR_STA_ID1_STA_AP;
1176 /* fall through */
1177 case NL80211_IFTYPE_STATION:
1178 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1179 break;
1180 default:
1181 if (!ah->is_monitoring)
1182 set = 0;
1183 break;
1184 }
1185 REG_RMW(ah, AR_STA_ID1, set, mask);
1186 }
1187
1188 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1189 u32 *coef_mantissa, u32 *coef_exponent)
1190 {
1191 u32 coef_exp, coef_man;
1192
1193 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1194 if ((coef_scaled >> coef_exp) & 0x1)
1195 break;
1196
1197 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1198
1199 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1200
1201 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1202 *coef_exponent = coef_exp - 16;
1203 }
1204
1205 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1206 {
1207 u32 rst_flags;
1208 u32 tmpReg;
1209
1210 if (AR_SREV_9100(ah)) {
1211 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1212 AR_RTC_DERIVED_CLK_PERIOD, 1);
1213 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1214 }
1215
1216 ENABLE_REGWRITE_BUFFER(ah);
1217
1218 if (AR_SREV_9300_20_OR_LATER(ah)) {
1219 REG_WRITE(ah, AR_WA, ah->WARegVal);
1220 udelay(10);
1221 }
1222
1223 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1224 AR_RTC_FORCE_WAKE_ON_INT);
1225
1226 if (AR_SREV_9100(ah)) {
1227 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1228 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1229 } else {
1230 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1231 if (tmpReg &
1232 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1233 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1234 u32 val;
1235 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1236
1237 val = AR_RC_HOSTIF;
1238 if (!AR_SREV_9300_20_OR_LATER(ah))
1239 val |= AR_RC_AHB;
1240 REG_WRITE(ah, AR_RC, val);
1241
1242 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1243 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1244
1245 rst_flags = AR_RTC_RC_MAC_WARM;
1246 if (type == ATH9K_RESET_COLD)
1247 rst_flags |= AR_RTC_RC_MAC_COLD;
1248 }
1249
1250 if (AR_SREV_9330(ah)) {
1251 int npend = 0;
1252 int i;
1253
1254 /* AR9330 WAR:
1255 * call external reset function to reset WMAC if:
1256 * - doing a cold reset
1257 * - we have pending frames in the TX queues
1258 */
1259
1260 for (i = 0; i < AR_NUM_QCU; i++) {
1261 npend = ath9k_hw_numtxpending(ah, i);
1262 if (npend)
1263 break;
1264 }
1265
1266 if (ah->external_reset &&
1267 (npend || type == ATH9K_RESET_COLD)) {
1268 int reset_err = 0;
1269
1270 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1271 "reset MAC via external reset\n");
1272
1273 reset_err = ah->external_reset();
1274 if (reset_err) {
1275 ath_err(ath9k_hw_common(ah),
1276 "External reset failed, err=%d\n",
1277 reset_err);
1278 return false;
1279 }
1280
1281 REG_WRITE(ah, AR_RTC_RESET, 1);
1282 }
1283 }
1284
1285 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1286
1287 REGWRITE_BUFFER_FLUSH(ah);
1288
1289 udelay(50);
1290
1291 REG_WRITE(ah, AR_RTC_RC, 0);
1292 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1293 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1294 "RTC stuck in MAC reset\n");
1295 return false;
1296 }
1297
1298 if (!AR_SREV_9100(ah))
1299 REG_WRITE(ah, AR_RC, 0);
1300
1301 if (AR_SREV_9100(ah))
1302 udelay(50);
1303
1304 return true;
1305 }
1306
1307 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1308 {
1309 ENABLE_REGWRITE_BUFFER(ah);
1310
1311 if (AR_SREV_9300_20_OR_LATER(ah)) {
1312 REG_WRITE(ah, AR_WA, ah->WARegVal);
1313 udelay(10);
1314 }
1315
1316 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1317 AR_RTC_FORCE_WAKE_ON_INT);
1318
1319 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1320 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1321
1322 REG_WRITE(ah, AR_RTC_RESET, 0);
1323
1324 REGWRITE_BUFFER_FLUSH(ah);
1325
1326 if (!AR_SREV_9300_20_OR_LATER(ah))
1327 udelay(2);
1328
1329 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1330 REG_WRITE(ah, AR_RC, 0);
1331
1332 REG_WRITE(ah, AR_RTC_RESET, 1);
1333
1334 if (!ath9k_hw_wait(ah,
1335 AR_RTC_STATUS,
1336 AR_RTC_STATUS_M,
1337 AR_RTC_STATUS_ON,
1338 AH_WAIT_TIMEOUT)) {
1339 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1340 "RTC not waking up\n");
1341 return false;
1342 }
1343
1344 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1345 }
1346
1347 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1348 {
1349
1350 if (AR_SREV_9300_20_OR_LATER(ah)) {
1351 REG_WRITE(ah, AR_WA, ah->WARegVal);
1352 udelay(10);
1353 }
1354
1355 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1356 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1357
1358 switch (type) {
1359 case ATH9K_RESET_POWER_ON:
1360 return ath9k_hw_set_reset_power_on(ah);
1361 case ATH9K_RESET_WARM:
1362 case ATH9K_RESET_COLD:
1363 return ath9k_hw_set_reset(ah, type);
1364 default:
1365 return false;
1366 }
1367 }
1368
1369 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1370 struct ath9k_channel *chan)
1371 {
1372 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1373 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1374 return false;
1375 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1376 return false;
1377
1378 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1379 return false;
1380
1381 ah->chip_fullsleep = false;
1382 ath9k_hw_init_pll(ah, chan);
1383 ath9k_hw_set_rfmode(ah, chan);
1384
1385 return true;
1386 }
1387
1388 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1389 struct ath9k_channel *chan)
1390 {
1391 struct ath_common *common = ath9k_hw_common(ah);
1392 u32 qnum;
1393 int r;
1394
1395 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1396 if (ath9k_hw_numtxpending(ah, qnum)) {
1397 ath_dbg(common, ATH_DBG_QUEUE,
1398 "Transmit frames pending on queue %d\n", qnum);
1399 return false;
1400 }
1401 }
1402
1403 if (!ath9k_hw_rfbus_req(ah)) {
1404 ath_err(common, "Could not kill baseband RX\n");
1405 return false;
1406 }
1407
1408 ath9k_hw_set_channel_regs(ah, chan);
1409
1410 r = ath9k_hw_rf_set_freq(ah, chan);
1411 if (r) {
1412 ath_err(common, "Failed to set channel\n");
1413 return false;
1414 }
1415 ath9k_hw_set_clockrate(ah);
1416 ath9k_hw_apply_txpower(ah, chan);
1417 ath9k_hw_rfbus_done(ah);
1418
1419 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1420 ath9k_hw_set_delta_slope(ah, chan);
1421
1422 ath9k_hw_spur_mitigate_freq(ah, chan);
1423
1424 return true;
1425 }
1426
1427 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1428 {
1429 u32 gpio_mask = ah->gpio_mask;
1430 int i;
1431
1432 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1433 if (!(gpio_mask & 1))
1434 continue;
1435
1436 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1437 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1438 }
1439 }
1440
1441 bool ath9k_hw_check_alive(struct ath_hw *ah)
1442 {
1443 int count = 50;
1444 u32 reg;
1445
1446 if (AR_SREV_9285_12_OR_LATER(ah))
1447 return true;
1448
1449 do {
1450 reg = REG_READ(ah, AR_OBS_BUS_1);
1451
1452 if ((reg & 0x7E7FFFEF) == 0x00702400)
1453 continue;
1454
1455 switch (reg & 0x7E000B00) {
1456 case 0x1E000000:
1457 case 0x52000B00:
1458 case 0x18000B00:
1459 continue;
1460 default:
1461 return true;
1462 }
1463 } while (count-- > 0);
1464
1465 return false;
1466 }
1467 EXPORT_SYMBOL(ath9k_hw_check_alive);
1468
1469 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1470 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1471 {
1472 struct ath_common *common = ath9k_hw_common(ah);
1473 u32 saveLedState;
1474 struct ath9k_channel *curchan = ah->curchan;
1475 u32 saveDefAntenna;
1476 u32 macStaId1;
1477 u64 tsf = 0;
1478 int i, r;
1479
1480 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1481 return -EIO;
1482
1483 if (curchan && !ah->chip_fullsleep)
1484 ath9k_hw_getnf(ah, curchan);
1485
1486 ah->caldata = caldata;
1487 if (caldata &&
1488 (chan->channel != caldata->channel ||
1489 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1490 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1491 /* Operating channel changed, reset channel calibration data */
1492 memset(caldata, 0, sizeof(*caldata));
1493 ath9k_init_nfcal_hist_buffer(ah, chan);
1494 }
1495 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1496
1497 if ((AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) ||
1498 (AR_SREV_9300_20_OR_LATER(ah) && IS_CHAN_5GHZ(chan)))
1499 bChannelChange = false;
1500
1501 if (bChannelChange &&
1502 (ah->chip_fullsleep != true) &&
1503 (ah->curchan != NULL) &&
1504 (chan->channel != ah->curchan->channel) &&
1505 ((chan->channelFlags & CHANNEL_ALL) ==
1506 (ah->curchan->channelFlags & CHANNEL_ALL))) {
1507 if (ath9k_hw_channel_change(ah, chan)) {
1508 ath9k_hw_loadnf(ah, ah->curchan);
1509 ath9k_hw_start_nfcal(ah, true);
1510 if (AR_SREV_9271(ah))
1511 ar9002_hw_load_ani_reg(ah, chan);
1512 return 0;
1513 }
1514 }
1515
1516 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1517 if (saveDefAntenna == 0)
1518 saveDefAntenna = 1;
1519
1520 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1521
1522 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1523 if (AR_SREV_9100(ah) ||
1524 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1525 tsf = ath9k_hw_gettsf64(ah);
1526
1527 saveLedState = REG_READ(ah, AR_CFG_LED) &
1528 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1529 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1530
1531 ath9k_hw_mark_phy_inactive(ah);
1532
1533 ah->paprd_table_write_done = false;
1534
1535 /* Only required on the first reset */
1536 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1537 REG_WRITE(ah,
1538 AR9271_RESET_POWER_DOWN_CONTROL,
1539 AR9271_RADIO_RF_RST);
1540 udelay(50);
1541 }
1542
1543 if (!ath9k_hw_chip_reset(ah, chan)) {
1544 ath_err(common, "Chip reset failed\n");
1545 return -EINVAL;
1546 }
1547
1548 /* Only required on the first reset */
1549 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1550 ah->htc_reset_init = false;
1551 REG_WRITE(ah,
1552 AR9271_RESET_POWER_DOWN_CONTROL,
1553 AR9271_GATE_MAC_CTL);
1554 udelay(50);
1555 }
1556
1557 /* Restore TSF */
1558 if (tsf)
1559 ath9k_hw_settsf64(ah, tsf);
1560
1561 if (AR_SREV_9280_20_OR_LATER(ah))
1562 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1563
1564 if (!AR_SREV_9300_20_OR_LATER(ah))
1565 ar9002_hw_enable_async_fifo(ah);
1566
1567 r = ath9k_hw_process_ini(ah, chan);
1568 if (r)
1569 return r;
1570
1571 /*
1572 * Some AR91xx SoC devices frequently fail to accept TSF writes
1573 * right after the chip reset. When that happens, write a new
1574 * value after the initvals have been applied, with an offset
1575 * based on measured time difference
1576 */
1577 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1578 tsf += 1500;
1579 ath9k_hw_settsf64(ah, tsf);
1580 }
1581
1582 /* Setup MFP options for CCMP */
1583 if (AR_SREV_9280_20_OR_LATER(ah)) {
1584 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1585 * frames when constructing CCMP AAD. */
1586 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1587 0xc7ff);
1588 ah->sw_mgmt_crypto = false;
1589 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1590 /* Disable hardware crypto for management frames */
1591 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1592 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1593 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1594 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1595 ah->sw_mgmt_crypto = true;
1596 } else
1597 ah->sw_mgmt_crypto = true;
1598
1599 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1600 ath9k_hw_set_delta_slope(ah, chan);
1601
1602 ath9k_hw_spur_mitigate_freq(ah, chan);
1603 ah->eep_ops->set_board_values(ah, chan);
1604
1605 ENABLE_REGWRITE_BUFFER(ah);
1606
1607 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1608 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1609 | macStaId1
1610 | AR_STA_ID1_RTS_USE_DEF
1611 | (ah->config.
1612 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1613 | ah->sta_id1_defaults);
1614 ath_hw_setbssidmask(common);
1615 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1616 ath9k_hw_write_associd(ah);
1617 REG_WRITE(ah, AR_ISR, ~0);
1618 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1619
1620 REGWRITE_BUFFER_FLUSH(ah);
1621
1622 ath9k_hw_set_operating_mode(ah, ah->opmode);
1623
1624 r = ath9k_hw_rf_set_freq(ah, chan);
1625 if (r)
1626 return r;
1627
1628 ath9k_hw_set_clockrate(ah);
1629
1630 ENABLE_REGWRITE_BUFFER(ah);
1631
1632 for (i = 0; i < AR_NUM_DCU; i++)
1633 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1634
1635 REGWRITE_BUFFER_FLUSH(ah);
1636
1637 ah->intr_txqs = 0;
1638 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1639 ath9k_hw_resettxqueue(ah, i);
1640
1641 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1642 ath9k_hw_ani_cache_ini_regs(ah);
1643 ath9k_hw_init_qos(ah);
1644
1645 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1646 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1647
1648 ath9k_hw_init_global_settings(ah);
1649
1650 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1651 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1652 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1653 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1654 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1655 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1656 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1657 }
1658
1659 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1660
1661 ath9k_hw_set_dma(ah);
1662
1663 REG_WRITE(ah, AR_OBS, 8);
1664
1665 if (ah->config.rx_intr_mitigation) {
1666 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1667 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1668 }
1669
1670 if (ah->config.tx_intr_mitigation) {
1671 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1672 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1673 }
1674
1675 ath9k_hw_init_bb(ah, chan);
1676
1677 if (!ath9k_hw_init_cal(ah, chan))
1678 return -EIO;
1679
1680 ENABLE_REGWRITE_BUFFER(ah);
1681
1682 ath9k_hw_restore_chainmask(ah);
1683 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1684
1685 REGWRITE_BUFFER_FLUSH(ah);
1686
1687 /*
1688 * For big endian systems turn on swapping for descriptors
1689 */
1690 if (AR_SREV_9100(ah)) {
1691 u32 mask;
1692 mask = REG_READ(ah, AR_CFG);
1693 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1694 ath_dbg(common, ATH_DBG_RESET,
1695 "CFG Byte Swap Set 0x%x\n", mask);
1696 } else {
1697 mask =
1698 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1699 REG_WRITE(ah, AR_CFG, mask);
1700 ath_dbg(common, ATH_DBG_RESET,
1701 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1702 }
1703 } else {
1704 if (common->bus_ops->ath_bus_type == ATH_USB) {
1705 /* Configure AR9271 target WLAN */
1706 if (AR_SREV_9271(ah))
1707 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1708 else
1709 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1710 }
1711 #ifdef __BIG_ENDIAN
1712 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
1713 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1714 else
1715 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1716 #endif
1717 }
1718
1719 if (ah->btcoex_hw.enabled)
1720 ath9k_hw_btcoex_enable(ah);
1721
1722 if (AR_SREV_9300_20_OR_LATER(ah)) {
1723 ar9003_hw_bb_watchdog_config(ah);
1724
1725 ar9003_hw_disable_phy_restart(ah);
1726 }
1727
1728 ath9k_hw_apply_gpio_override(ah);
1729
1730 return 0;
1731 }
1732 EXPORT_SYMBOL(ath9k_hw_reset);
1733
1734 /******************************/
1735 /* Power Management (Chipset) */
1736 /******************************/
1737
1738 /*
1739 * Notify Power Mgt is disabled in self-generated frames.
1740 * If requested, force chip to sleep.
1741 */
1742 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1743 {
1744 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1745 if (setChip) {
1746 if (AR_SREV_9480(ah)) {
1747 REG_WRITE(ah, AR_TIMER_MODE,
1748 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
1749 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
1750 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
1751 REG_WRITE(ah, AR_SLP32_INC,
1752 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
1753 /* xxx Required for WLAN only case ? */
1754 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1755 udelay(100);
1756 }
1757
1758 /*
1759 * Clear the RTC force wake bit to allow the
1760 * mac to go to sleep.
1761 */
1762 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1763
1764 if (AR_SREV_9480(ah))
1765 udelay(100);
1766
1767 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1768 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1769
1770 /* Shutdown chip. Active low */
1771 if (!AR_SREV_5416(ah) &&
1772 !AR_SREV_9271(ah) && !AR_SREV_9480_10(ah)) {
1773 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1774 udelay(2);
1775 }
1776 }
1777
1778 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1779 if (!AR_SREV_9480(ah))
1780 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1781 }
1782
1783 /*
1784 * Notify Power Management is enabled in self-generating
1785 * frames. If request, set power mode of chip to
1786 * auto/normal. Duration in units of 128us (1/8 TU).
1787 */
1788 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1789 {
1790 u32 val;
1791
1792 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1793 if (setChip) {
1794 struct ath9k_hw_capabilities *pCap = &ah->caps;
1795
1796 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1797 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1798 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1799 AR_RTC_FORCE_WAKE_ON_INT);
1800 } else {
1801
1802 /* When chip goes into network sleep, it could be waken
1803 * up by MCI_INT interrupt caused by BT's HW messages
1804 * (LNA_xxx, CONT_xxx) which chould be in a very fast
1805 * rate (~100us). This will cause chip to leave and
1806 * re-enter network sleep mode frequently, which in
1807 * consequence will have WLAN MCI HW to generate lots of
1808 * SYS_WAKING and SYS_SLEEPING messages which will make
1809 * BT CPU to busy to process.
1810 */
1811 if (AR_SREV_9480(ah)) {
1812 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
1813 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
1814 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
1815 }
1816 /*
1817 * Clear the RTC force wake bit to allow the
1818 * mac to go to sleep.
1819 */
1820 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1821 AR_RTC_FORCE_WAKE_EN);
1822
1823 if (AR_SREV_9480(ah))
1824 udelay(30);
1825 }
1826 }
1827
1828 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1829 if (AR_SREV_9300_20_OR_LATER(ah))
1830 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1831 }
1832
1833 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1834 {
1835 u32 val;
1836 int i;
1837
1838 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1839 if (AR_SREV_9300_20_OR_LATER(ah)) {
1840 REG_WRITE(ah, AR_WA, ah->WARegVal);
1841 udelay(10);
1842 }
1843
1844 if (setChip) {
1845 if ((REG_READ(ah, AR_RTC_STATUS) &
1846 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1847 if (ath9k_hw_set_reset_reg(ah,
1848 ATH9K_RESET_POWER_ON) != true) {
1849 return false;
1850 }
1851 if (!AR_SREV_9300_20_OR_LATER(ah))
1852 ath9k_hw_init_pll(ah, NULL);
1853 }
1854 if (AR_SREV_9100(ah))
1855 REG_SET_BIT(ah, AR_RTC_RESET,
1856 AR_RTC_RESET_EN);
1857
1858 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1859 AR_RTC_FORCE_WAKE_EN);
1860 udelay(50);
1861
1862 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1863 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1864 if (val == AR_RTC_STATUS_ON)
1865 break;
1866 udelay(50);
1867 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1868 AR_RTC_FORCE_WAKE_EN);
1869 }
1870 if (i == 0) {
1871 ath_err(ath9k_hw_common(ah),
1872 "Failed to wakeup in %uus\n",
1873 POWER_UP_TIME / 20);
1874 return false;
1875 }
1876 }
1877
1878 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1879
1880 return true;
1881 }
1882
1883 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1884 {
1885 struct ath_common *common = ath9k_hw_common(ah);
1886 int status = true, setChip = true;
1887 static const char *modes[] = {
1888 "AWAKE",
1889 "FULL-SLEEP",
1890 "NETWORK SLEEP",
1891 "UNDEFINED"
1892 };
1893
1894 if (ah->power_mode == mode)
1895 return status;
1896
1897 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1898 modes[ah->power_mode], modes[mode]);
1899
1900 switch (mode) {
1901 case ATH9K_PM_AWAKE:
1902 status = ath9k_hw_set_power_awake(ah, setChip);
1903 break;
1904 case ATH9K_PM_FULL_SLEEP:
1905 ath9k_set_power_sleep(ah, setChip);
1906 ah->chip_fullsleep = true;
1907 break;
1908 case ATH9K_PM_NETWORK_SLEEP:
1909 ath9k_set_power_network_sleep(ah, setChip);
1910 break;
1911 default:
1912 ath_err(common, "Unknown power mode %u\n", mode);
1913 return false;
1914 }
1915 ah->power_mode = mode;
1916
1917 /*
1918 * XXX: If this warning never comes up after a while then
1919 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1920 * ath9k_hw_setpower() return type void.
1921 */
1922
1923 if (!(ah->ah_flags & AH_UNPLUGGED))
1924 ATH_DBG_WARN_ON_ONCE(!status);
1925
1926 return status;
1927 }
1928 EXPORT_SYMBOL(ath9k_hw_setpower);
1929
1930 /*******************/
1931 /* Beacon Handling */
1932 /*******************/
1933
1934 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1935 {
1936 int flags = 0;
1937
1938 ENABLE_REGWRITE_BUFFER(ah);
1939
1940 switch (ah->opmode) {
1941 case NL80211_IFTYPE_ADHOC:
1942 case NL80211_IFTYPE_MESH_POINT:
1943 REG_SET_BIT(ah, AR_TXCFG,
1944 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1945 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1946 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1947 flags |= AR_NDP_TIMER_EN;
1948 case NL80211_IFTYPE_AP:
1949 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1950 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1951 TU_TO_USEC(ah->config.dma_beacon_response_time));
1952 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1953 TU_TO_USEC(ah->config.sw_beacon_response_time));
1954 flags |=
1955 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1956 break;
1957 default:
1958 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1959 "%s: unsupported opmode: %d\n",
1960 __func__, ah->opmode);
1961 return;
1962 break;
1963 }
1964
1965 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1966 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1967 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1968 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1969
1970 REGWRITE_BUFFER_FLUSH(ah);
1971
1972 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1973 }
1974 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1975
1976 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1977 const struct ath9k_beacon_state *bs)
1978 {
1979 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1980 struct ath9k_hw_capabilities *pCap = &ah->caps;
1981 struct ath_common *common = ath9k_hw_common(ah);
1982
1983 ENABLE_REGWRITE_BUFFER(ah);
1984
1985 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1986
1987 REG_WRITE(ah, AR_BEACON_PERIOD,
1988 TU_TO_USEC(bs->bs_intval));
1989 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1990 TU_TO_USEC(bs->bs_intval));
1991
1992 REGWRITE_BUFFER_FLUSH(ah);
1993
1994 REG_RMW_FIELD(ah, AR_RSSI_THR,
1995 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1996
1997 beaconintval = bs->bs_intval;
1998
1999 if (bs->bs_sleepduration > beaconintval)
2000 beaconintval = bs->bs_sleepduration;
2001
2002 dtimperiod = bs->bs_dtimperiod;
2003 if (bs->bs_sleepduration > dtimperiod)
2004 dtimperiod = bs->bs_sleepduration;
2005
2006 if (beaconintval == dtimperiod)
2007 nextTbtt = bs->bs_nextdtim;
2008 else
2009 nextTbtt = bs->bs_nexttbtt;
2010
2011 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2012 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2013 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2014 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
2015
2016 ENABLE_REGWRITE_BUFFER(ah);
2017
2018 REG_WRITE(ah, AR_NEXT_DTIM,
2019 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2020 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2021
2022 REG_WRITE(ah, AR_SLEEP1,
2023 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2024 | AR_SLEEP1_ASSUME_DTIM);
2025
2026 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2027 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2028 else
2029 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2030
2031 REG_WRITE(ah, AR_SLEEP2,
2032 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2033
2034 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2035 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2036
2037 REGWRITE_BUFFER_FLUSH(ah);
2038
2039 REG_SET_BIT(ah, AR_TIMER_MODE,
2040 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2041 AR_DTIM_TIMER_EN);
2042
2043 /* TSF Out of Range Threshold */
2044 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2045 }
2046 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2047
2048 /*******************/
2049 /* HW Capabilities */
2050 /*******************/
2051
2052 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2053 {
2054 eeprom_chainmask &= chip_chainmask;
2055 if (eeprom_chainmask)
2056 return eeprom_chainmask;
2057 else
2058 return chip_chainmask;
2059 }
2060
2061 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2062 {
2063 struct ath9k_hw_capabilities *pCap = &ah->caps;
2064 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2065 struct ath_common *common = ath9k_hw_common(ah);
2066 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2067 unsigned int chip_chainmask;
2068
2069 u16 eeval;
2070 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2071
2072 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2073 regulatory->current_rd = eeval;
2074
2075 if (ah->opmode != NL80211_IFTYPE_AP &&
2076 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2077 if (regulatory->current_rd == 0x64 ||
2078 regulatory->current_rd == 0x65)
2079 regulatory->current_rd += 5;
2080 else if (regulatory->current_rd == 0x41)
2081 regulatory->current_rd = 0x43;
2082 ath_dbg(common, ATH_DBG_REGULATORY,
2083 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2084 }
2085
2086 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2087 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2088 ath_err(common,
2089 "no band has been marked as supported in EEPROM\n");
2090 return -EINVAL;
2091 }
2092
2093 if (eeval & AR5416_OPFLAGS_11A)
2094 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2095
2096 if (eeval & AR5416_OPFLAGS_11G)
2097 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2098
2099 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2100 chip_chainmask = 1;
2101 else if (!AR_SREV_9280_20_OR_LATER(ah))
2102 chip_chainmask = 7;
2103 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2104 chip_chainmask = 3;
2105 else
2106 chip_chainmask = 7;
2107
2108 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2109 /*
2110 * For AR9271 we will temporarilly uses the rx chainmax as read from
2111 * the EEPROM.
2112 */
2113 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2114 !(eeval & AR5416_OPFLAGS_11A) &&
2115 !(AR_SREV_9271(ah)))
2116 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2117 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2118 else if (AR_SREV_9100(ah))
2119 pCap->rx_chainmask = 0x7;
2120 else
2121 /* Use rx_chainmask from EEPROM. */
2122 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2123
2124 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2125 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2126 ah->txchainmask = pCap->tx_chainmask;
2127 ah->rxchainmask = pCap->rx_chainmask;
2128
2129 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2130
2131 /* enable key search for every frame in an aggregate */
2132 if (AR_SREV_9300_20_OR_LATER(ah))
2133 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2134
2135 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2136
2137 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2138 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2139 else
2140 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2141
2142 if (AR_SREV_9271(ah))
2143 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2144 else if (AR_DEVID_7010(ah))
2145 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2146 else if (AR_SREV_9300_20_OR_LATER(ah))
2147 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2148 else if (AR_SREV_9287_11_OR_LATER(ah))
2149 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2150 else if (AR_SREV_9285_12_OR_LATER(ah))
2151 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2152 else if (AR_SREV_9280_20_OR_LATER(ah))
2153 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2154 else
2155 pCap->num_gpio_pins = AR_NUM_GPIO;
2156
2157 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2158 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2159 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2160 } else {
2161 pCap->rts_aggr_limit = (8 * 1024);
2162 }
2163
2164 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2165 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2166 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2167 ah->rfkill_gpio =
2168 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2169 ah->rfkill_polarity =
2170 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2171
2172 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2173 }
2174 #endif
2175 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2176 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2177 else
2178 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2179
2180 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2181 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2182 else
2183 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2184
2185 if (common->btcoex_enabled) {
2186 if (AR_SREV_9300_20_OR_LATER(ah)) {
2187 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2188 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
2189 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
2190 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
2191 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2192 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
2193 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
2194
2195 if (AR_SREV_9285(ah)) {
2196 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2197 btcoex_hw->btpriority_gpio =
2198 ATH_BTPRIORITY_GPIO_9285;
2199 } else {
2200 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2201 }
2202 }
2203 } else {
2204 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2205 }
2206
2207 if (AR_SREV_9300_20_OR_LATER(ah)) {
2208 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2209 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
2210 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2211
2212 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2213 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2214 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2215 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2216 pCap->txs_len = sizeof(struct ar9003_txs);
2217 if (!ah->config.paprd_disable &&
2218 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2219 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2220 } else {
2221 pCap->tx_desc_len = sizeof(struct ath_desc);
2222 if (AR_SREV_9280_20(ah))
2223 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2224 }
2225
2226 if (AR_SREV_9300_20_OR_LATER(ah))
2227 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2228
2229 if (AR_SREV_9300_20_OR_LATER(ah))
2230 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2231
2232 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2233 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2234
2235 if (AR_SREV_9285(ah))
2236 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2237 ant_div_ctl1 =
2238 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2239 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2240 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2241 }
2242 if (AR_SREV_9300_20_OR_LATER(ah)) {
2243 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2244 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2245 }
2246
2247
2248 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2249 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2250 /*
2251 * enable the diversity-combining algorithm only when
2252 * both enable_lna_div and enable_fast_div are set
2253 * Table for Diversity
2254 * ant_div_alt_lnaconf bit 0-1
2255 * ant_div_main_lnaconf bit 2-3
2256 * ant_div_alt_gaintb bit 4
2257 * ant_div_main_gaintb bit 5
2258 * enable_ant_div_lnadiv bit 6
2259 * enable_ant_fast_div bit 7
2260 */
2261 if ((ant_div_ctl1 >> 0x6) == 0x3)
2262 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2263 }
2264
2265 if (AR_SREV_9485_10(ah)) {
2266 pCap->pcie_lcr_extsync_en = true;
2267 pCap->pcie_lcr_offset = 0x80;
2268 }
2269
2270 tx_chainmask = pCap->tx_chainmask;
2271 rx_chainmask = pCap->rx_chainmask;
2272 while (tx_chainmask || rx_chainmask) {
2273 if (tx_chainmask & BIT(0))
2274 pCap->max_txchains++;
2275 if (rx_chainmask & BIT(0))
2276 pCap->max_rxchains++;
2277
2278 tx_chainmask >>= 1;
2279 rx_chainmask >>= 1;
2280 }
2281
2282 return 0;
2283 }
2284
2285 /****************************/
2286 /* GPIO / RFKILL / Antennae */
2287 /****************************/
2288
2289 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2290 u32 gpio, u32 type)
2291 {
2292 int addr;
2293 u32 gpio_shift, tmp;
2294
2295 if (gpio > 11)
2296 addr = AR_GPIO_OUTPUT_MUX3;
2297 else if (gpio > 5)
2298 addr = AR_GPIO_OUTPUT_MUX2;
2299 else
2300 addr = AR_GPIO_OUTPUT_MUX1;
2301
2302 gpio_shift = (gpio % 6) * 5;
2303
2304 if (AR_SREV_9280_20_OR_LATER(ah)
2305 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2306 REG_RMW(ah, addr, (type << gpio_shift),
2307 (0x1f << gpio_shift));
2308 } else {
2309 tmp = REG_READ(ah, addr);
2310 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2311 tmp &= ~(0x1f << gpio_shift);
2312 tmp |= (type << gpio_shift);
2313 REG_WRITE(ah, addr, tmp);
2314 }
2315 }
2316
2317 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2318 {
2319 u32 gpio_shift;
2320
2321 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2322
2323 if (AR_DEVID_7010(ah)) {
2324 gpio_shift = gpio;
2325 REG_RMW(ah, AR7010_GPIO_OE,
2326 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2327 (AR7010_GPIO_OE_MASK << gpio_shift));
2328 return;
2329 }
2330
2331 gpio_shift = gpio << 1;
2332 REG_RMW(ah,
2333 AR_GPIO_OE_OUT,
2334 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2335 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2336 }
2337 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2338
2339 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2340 {
2341 #define MS_REG_READ(x, y) \
2342 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2343
2344 if (gpio >= ah->caps.num_gpio_pins)
2345 return 0xffffffff;
2346
2347 if (AR_DEVID_7010(ah)) {
2348 u32 val;
2349 val = REG_READ(ah, AR7010_GPIO_IN);
2350 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2351 } else if (AR_SREV_9300_20_OR_LATER(ah))
2352 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2353 AR_GPIO_BIT(gpio)) != 0;
2354 else if (AR_SREV_9271(ah))
2355 return MS_REG_READ(AR9271, gpio) != 0;
2356 else if (AR_SREV_9287_11_OR_LATER(ah))
2357 return MS_REG_READ(AR9287, gpio) != 0;
2358 else if (AR_SREV_9285_12_OR_LATER(ah))
2359 return MS_REG_READ(AR9285, gpio) != 0;
2360 else if (AR_SREV_9280_20_OR_LATER(ah))
2361 return MS_REG_READ(AR928X, gpio) != 0;
2362 else
2363 return MS_REG_READ(AR, gpio) != 0;
2364 }
2365 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2366
2367 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2368 u32 ah_signal_type)
2369 {
2370 u32 gpio_shift;
2371
2372 if (AR_DEVID_7010(ah)) {
2373 gpio_shift = gpio;
2374 REG_RMW(ah, AR7010_GPIO_OE,
2375 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2376 (AR7010_GPIO_OE_MASK << gpio_shift));
2377 return;
2378 }
2379
2380 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2381 gpio_shift = 2 * gpio;
2382 REG_RMW(ah,
2383 AR_GPIO_OE_OUT,
2384 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2385 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2386 }
2387 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2388
2389 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2390 {
2391 if (AR_DEVID_7010(ah)) {
2392 val = val ? 0 : 1;
2393 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2394 AR_GPIO_BIT(gpio));
2395 return;
2396 }
2397
2398 if (AR_SREV_9271(ah))
2399 val = ~val;
2400
2401 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2402 AR_GPIO_BIT(gpio));
2403 }
2404 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2405
2406 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2407 {
2408 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2409 }
2410 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2411
2412 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2413 {
2414 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2415 }
2416 EXPORT_SYMBOL(ath9k_hw_setantenna);
2417
2418 /*********************/
2419 /* General Operation */
2420 /*********************/
2421
2422 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2423 {
2424 u32 bits = REG_READ(ah, AR_RX_FILTER);
2425 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2426
2427 if (phybits & AR_PHY_ERR_RADAR)
2428 bits |= ATH9K_RX_FILTER_PHYRADAR;
2429 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2430 bits |= ATH9K_RX_FILTER_PHYERR;
2431
2432 return bits;
2433 }
2434 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2435
2436 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2437 {
2438 u32 phybits;
2439
2440 ENABLE_REGWRITE_BUFFER(ah);
2441
2442 if (AR_SREV_9480(ah))
2443 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2444
2445 REG_WRITE(ah, AR_RX_FILTER, bits);
2446
2447 phybits = 0;
2448 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2449 phybits |= AR_PHY_ERR_RADAR;
2450 if (bits & ATH9K_RX_FILTER_PHYERR)
2451 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2452 REG_WRITE(ah, AR_PHY_ERR, phybits);
2453
2454 if (phybits)
2455 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2456 else
2457 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2458
2459 REGWRITE_BUFFER_FLUSH(ah);
2460 }
2461 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2462
2463 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2464 {
2465 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2466 return false;
2467
2468 ath9k_hw_init_pll(ah, NULL);
2469 return true;
2470 }
2471 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2472
2473 bool ath9k_hw_disable(struct ath_hw *ah)
2474 {
2475 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2476 return false;
2477
2478 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2479 return false;
2480
2481 ath9k_hw_init_pll(ah, NULL);
2482 return true;
2483 }
2484 EXPORT_SYMBOL(ath9k_hw_disable);
2485
2486 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2487 {
2488 enum eeprom_param gain_param;
2489
2490 if (IS_CHAN_2GHZ(chan))
2491 gain_param = EEP_ANTENNA_GAIN_2G;
2492 else
2493 gain_param = EEP_ANTENNA_GAIN_5G;
2494
2495 return ah->eep_ops->get_eeprom(ah, gain_param);
2496 }
2497
2498 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan)
2499 {
2500 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2501 struct ieee80211_channel *channel;
2502 int chan_pwr, new_pwr, max_gain;
2503 int ant_gain, ant_reduction = 0;
2504
2505 if (!chan)
2506 return;
2507
2508 channel = chan->chan;
2509 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2510 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2511 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2512
2513 ant_gain = get_antenna_gain(ah, chan);
2514 if (ant_gain > max_gain)
2515 ant_reduction = ant_gain - max_gain;
2516
2517 ah->eep_ops->set_txpower(ah, chan,
2518 ath9k_regd_get_ctl(reg, chan),
2519 ant_reduction, new_pwr, false);
2520 }
2521
2522 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2523 {
2524 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2525 struct ath9k_channel *chan = ah->curchan;
2526 struct ieee80211_channel *channel = chan->chan;
2527
2528 reg->power_limit = min_t(int, limit, MAX_RATE_POWER);
2529 if (test)
2530 channel->max_power = MAX_RATE_POWER / 2;
2531
2532 ath9k_hw_apply_txpower(ah, chan);
2533
2534 if (test)
2535 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2536 }
2537 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2538
2539 void ath9k_hw_setopmode(struct ath_hw *ah)
2540 {
2541 ath9k_hw_set_operating_mode(ah, ah->opmode);
2542 }
2543 EXPORT_SYMBOL(ath9k_hw_setopmode);
2544
2545 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2546 {
2547 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2548 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2549 }
2550 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2551
2552 void ath9k_hw_write_associd(struct ath_hw *ah)
2553 {
2554 struct ath_common *common = ath9k_hw_common(ah);
2555
2556 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2557 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2558 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2559 }
2560 EXPORT_SYMBOL(ath9k_hw_write_associd);
2561
2562 #define ATH9K_MAX_TSF_READ 10
2563
2564 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2565 {
2566 u32 tsf_lower, tsf_upper1, tsf_upper2;
2567 int i;
2568
2569 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2570 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2571 tsf_lower = REG_READ(ah, AR_TSF_L32);
2572 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2573 if (tsf_upper2 == tsf_upper1)
2574 break;
2575 tsf_upper1 = tsf_upper2;
2576 }
2577
2578 WARN_ON( i == ATH9K_MAX_TSF_READ );
2579
2580 return (((u64)tsf_upper1 << 32) | tsf_lower);
2581 }
2582 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2583
2584 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2585 {
2586 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2587 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2588 }
2589 EXPORT_SYMBOL(ath9k_hw_settsf64);
2590
2591 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2592 {
2593 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2594 AH_TSF_WRITE_TIMEOUT))
2595 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2596 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2597
2598 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2599 }
2600 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2601
2602 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2603 {
2604 if (setting)
2605 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2606 else
2607 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2608 }
2609 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2610
2611 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2612 {
2613 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2614 u32 macmode;
2615
2616 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2617 macmode = AR_2040_JOINED_RX_CLEAR;
2618 else
2619 macmode = 0;
2620
2621 REG_WRITE(ah, AR_2040_MODE, macmode);
2622 }
2623
2624 /* HW Generic timers configuration */
2625
2626 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2627 {
2628 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2629 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2630 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2631 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2632 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2633 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2634 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2635 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2636 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2637 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2638 AR_NDP2_TIMER_MODE, 0x0002},
2639 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2640 AR_NDP2_TIMER_MODE, 0x0004},
2641 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2642 AR_NDP2_TIMER_MODE, 0x0008},
2643 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2644 AR_NDP2_TIMER_MODE, 0x0010},
2645 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2646 AR_NDP2_TIMER_MODE, 0x0020},
2647 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2648 AR_NDP2_TIMER_MODE, 0x0040},
2649 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2650 AR_NDP2_TIMER_MODE, 0x0080}
2651 };
2652
2653 /* HW generic timer primitives */
2654
2655 /* compute and clear index of rightmost 1 */
2656 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2657 {
2658 u32 b;
2659
2660 b = *mask;
2661 b &= (0-b);
2662 *mask &= ~b;
2663 b *= debruijn32;
2664 b >>= 27;
2665
2666 return timer_table->gen_timer_index[b];
2667 }
2668
2669 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2670 {
2671 return REG_READ(ah, AR_TSF_L32);
2672 }
2673 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2674
2675 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2676 void (*trigger)(void *),
2677 void (*overflow)(void *),
2678 void *arg,
2679 u8 timer_index)
2680 {
2681 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2682 struct ath_gen_timer *timer;
2683
2684 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2685
2686 if (timer == NULL) {
2687 ath_err(ath9k_hw_common(ah),
2688 "Failed to allocate memory for hw timer[%d]\n",
2689 timer_index);
2690 return NULL;
2691 }
2692
2693 /* allocate a hardware generic timer slot */
2694 timer_table->timers[timer_index] = timer;
2695 timer->index = timer_index;
2696 timer->trigger = trigger;
2697 timer->overflow = overflow;
2698 timer->arg = arg;
2699
2700 return timer;
2701 }
2702 EXPORT_SYMBOL(ath_gen_timer_alloc);
2703
2704 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2705 struct ath_gen_timer *timer,
2706 u32 trig_timeout,
2707 u32 timer_period)
2708 {
2709 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2710 u32 tsf, timer_next;
2711
2712 BUG_ON(!timer_period);
2713
2714 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2715
2716 tsf = ath9k_hw_gettsf32(ah);
2717
2718 timer_next = tsf + trig_timeout;
2719
2720 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2721 "current tsf %x period %x timer_next %x\n",
2722 tsf, timer_period, timer_next);
2723
2724 /*
2725 * Program generic timer registers
2726 */
2727 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2728 timer_next);
2729 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2730 timer_period);
2731 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2732 gen_tmr_configuration[timer->index].mode_mask);
2733
2734 if (AR_SREV_9480(ah)) {
2735 /*
2736 * Starting from AR9480, each generic timer can select which tsf
2737 * to use. But we still follow the old rule, 0 - 7 use tsf and
2738 * 8 - 15 use tsf2.
2739 */
2740 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2741 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2742 (1 << timer->index));
2743 else
2744 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2745 (1 << timer->index));
2746 }
2747
2748 /* Enable both trigger and thresh interrupt masks */
2749 REG_SET_BIT(ah, AR_IMR_S5,
2750 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2751 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2752 }
2753 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2754
2755 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2756 {
2757 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2758
2759 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2760 (timer->index >= ATH_MAX_GEN_TIMER)) {
2761 return;
2762 }
2763
2764 /* Clear generic timer enable bits. */
2765 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2766 gen_tmr_configuration[timer->index].mode_mask);
2767
2768 /* Disable both trigger and thresh interrupt masks */
2769 REG_CLR_BIT(ah, AR_IMR_S5,
2770 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2771 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2772
2773 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2774 }
2775 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2776
2777 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2778 {
2779 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2780
2781 /* free the hardware generic timer slot */
2782 timer_table->timers[timer->index] = NULL;
2783 kfree(timer);
2784 }
2785 EXPORT_SYMBOL(ath_gen_timer_free);
2786
2787 /*
2788 * Generic Timer Interrupts handling
2789 */
2790 void ath_gen_timer_isr(struct ath_hw *ah)
2791 {
2792 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2793 struct ath_gen_timer *timer;
2794 struct ath_common *common = ath9k_hw_common(ah);
2795 u32 trigger_mask, thresh_mask, index;
2796
2797 /* get hardware generic timer interrupt status */
2798 trigger_mask = ah->intr_gen_timer_trigger;
2799 thresh_mask = ah->intr_gen_timer_thresh;
2800 trigger_mask &= timer_table->timer_mask.val;
2801 thresh_mask &= timer_table->timer_mask.val;
2802
2803 trigger_mask &= ~thresh_mask;
2804
2805 while (thresh_mask) {
2806 index = rightmost_index(timer_table, &thresh_mask);
2807 timer = timer_table->timers[index];
2808 BUG_ON(!timer);
2809 ath_dbg(common, ATH_DBG_HWTIMER,
2810 "TSF overflow for Gen timer %d\n", index);
2811 timer->overflow(timer->arg);
2812 }
2813
2814 while (trigger_mask) {
2815 index = rightmost_index(timer_table, &trigger_mask);
2816 timer = timer_table->timers[index];
2817 BUG_ON(!timer);
2818 ath_dbg(common, ATH_DBG_HWTIMER,
2819 "Gen timer[%d] trigger\n", index);
2820 timer->trigger(timer->arg);
2821 }
2822 }
2823 EXPORT_SYMBOL(ath_gen_timer_isr);
2824
2825 /********/
2826 /* HTC */
2827 /********/
2828
2829 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2830 {
2831 ah->htc_reset_init = true;
2832 }
2833 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2834
2835 static struct {
2836 u32 version;
2837 const char * name;
2838 } ath_mac_bb_names[] = {
2839 /* Devices with external radios */
2840 { AR_SREV_VERSION_5416_PCI, "5416" },
2841 { AR_SREV_VERSION_5416_PCIE, "5418" },
2842 { AR_SREV_VERSION_9100, "9100" },
2843 { AR_SREV_VERSION_9160, "9160" },
2844 /* Single-chip solutions */
2845 { AR_SREV_VERSION_9280, "9280" },
2846 { AR_SREV_VERSION_9285, "9285" },
2847 { AR_SREV_VERSION_9287, "9287" },
2848 { AR_SREV_VERSION_9271, "9271" },
2849 { AR_SREV_VERSION_9300, "9300" },
2850 { AR_SREV_VERSION_9330, "9330" },
2851 { AR_SREV_VERSION_9340, "9340" },
2852 { AR_SREV_VERSION_9485, "9485" },
2853 { AR_SREV_VERSION_9480, "9480" },
2854 };
2855
2856 /* For devices with external radios */
2857 static struct {
2858 u16 version;
2859 const char * name;
2860 } ath_rf_names[] = {
2861 { 0, "5133" },
2862 { AR_RAD5133_SREV_MAJOR, "5133" },
2863 { AR_RAD5122_SREV_MAJOR, "5122" },
2864 { AR_RAD2133_SREV_MAJOR, "2133" },
2865 { AR_RAD2122_SREV_MAJOR, "2122" }
2866 };
2867
2868 /*
2869 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2870 */
2871 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2872 {
2873 int i;
2874
2875 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2876 if (ath_mac_bb_names[i].version == mac_bb_version) {
2877 return ath_mac_bb_names[i].name;
2878 }
2879 }
2880
2881 return "????";
2882 }
2883
2884 /*
2885 * Return the RF name. "????" is returned if the RF is unknown.
2886 * Used for devices with external radios.
2887 */
2888 static const char *ath9k_hw_rf_name(u16 rf_version)
2889 {
2890 int i;
2891
2892 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2893 if (ath_rf_names[i].version == rf_version) {
2894 return ath_rf_names[i].name;
2895 }
2896 }
2897
2898 return "????";
2899 }
2900
2901 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2902 {
2903 int used;
2904
2905 /* chipsets >= AR9280 are single-chip */
2906 if (AR_SREV_9280_20_OR_LATER(ah)) {
2907 used = snprintf(hw_name, len,
2908 "Atheros AR%s Rev:%x",
2909 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2910 ah->hw_version.macRev);
2911 }
2912 else {
2913 used = snprintf(hw_name, len,
2914 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2915 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2916 ah->hw_version.macRev,
2917 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2918 AR_RADIO_SREV_MAJOR)),
2919 ah->hw_version.phyRev);
2920 }
2921
2922 hw_name[used] = '\0';
2923 }
2924 EXPORT_SYMBOL(ath9k_hw_name);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree