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igb/ixgbe: add IPV6_CSUM support to vlan_features
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / igb / igb_main.c
blobcef4289d5716fa1abebd777fc51bc2c307fa668a
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/pci.h>
42 #include <linux/pci-aspm.h>
43 #include <linux/delay.h>
44 #include <linux/interrupt.h>
45 #include <linux/if_ether.h>
46 #include <linux/aer.h>
47 #ifdef CONFIG_IGB_DCA
48 #include <linux/dca.h>
49 #endif
50 #include "igb.h"
51
52 #define DRV_VERSION "1.3.16-k2"
53 char igb_driver_name[] = "igb";
54 char igb_driver_version[] = DRV_VERSION;
55 static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
58
59 static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61 };
62
63 static struct pci_device_id igb_pci_tbl[] = {
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
73 /* required last entry */
74 {0, }
75 };
76
77 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
78
79 void igb_reset(struct igb_adapter *);
80 static int igb_setup_all_tx_resources(struct igb_adapter *);
81 static int igb_setup_all_rx_resources(struct igb_adapter *);
82 static void igb_free_all_tx_resources(struct igb_adapter *);
83 static void igb_free_all_rx_resources(struct igb_adapter *);
84 void igb_update_stats(struct igb_adapter *);
85 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
86 static void __devexit igb_remove(struct pci_dev *pdev);
87 static int igb_sw_init(struct igb_adapter *);
88 static int igb_open(struct net_device *);
89 static int igb_close(struct net_device *);
90 static void igb_configure_tx(struct igb_adapter *);
91 static void igb_configure_rx(struct igb_adapter *);
92 static void igb_setup_rctl(struct igb_adapter *);
93 static void igb_clean_all_tx_rings(struct igb_adapter *);
94 static void igb_clean_all_rx_rings(struct igb_adapter *);
95 static void igb_clean_tx_ring(struct igb_ring *);
96 static void igb_clean_rx_ring(struct igb_ring *);
97 static void igb_set_multi(struct net_device *);
98 static void igb_update_phy_info(unsigned long);
99 static void igb_watchdog(unsigned long);
100 static void igb_watchdog_task(struct work_struct *);
101 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
102 struct igb_ring *);
103 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
104 static struct net_device_stats *igb_get_stats(struct net_device *);
105 static int igb_change_mtu(struct net_device *, int);
106 static int igb_set_mac(struct net_device *, void *);
107 static irqreturn_t igb_intr(int irq, void *);
108 static irqreturn_t igb_intr_msi(int irq, void *);
109 static irqreturn_t igb_msix_other(int irq, void *);
110 static irqreturn_t igb_msix_rx(int irq, void *);
111 static irqreturn_t igb_msix_tx(int irq, void *);
112 #ifdef CONFIG_IGB_DCA
113 static void igb_update_rx_dca(struct igb_ring *);
114 static void igb_update_tx_dca(struct igb_ring *);
115 static void igb_setup_dca(struct igb_adapter *);
116 #endif /* CONFIG_IGB_DCA */
117 static bool igb_clean_tx_irq(struct igb_ring *);
118 static int igb_poll(struct napi_struct *, int);
119 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
120 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
121 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
122 static void igb_tx_timeout(struct net_device *);
123 static void igb_reset_task(struct work_struct *);
124 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
125 static void igb_vlan_rx_add_vid(struct net_device *, u16);
126 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
127 static void igb_restore_vlan(struct igb_adapter *);
128 static void igb_ping_all_vfs(struct igb_adapter *);
129 static void igb_msg_task(struct igb_adapter *);
130 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
131 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
132 static void igb_vmm_control(struct igb_adapter *);
133 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
134 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
135
136 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
137 {
138 u32 reg_data;
139
140 reg_data = rd32(E1000_VMOLR(vfn));
141 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
142 E1000_VMOLR_ROPE | /* Accept packets matched in UTA */
143 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
144 E1000_VMOLR_AUPE | /* Accept untagged packets */
145 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
146 wr32(E1000_VMOLR(vfn), reg_data);
147 }
148
149 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
150 int vfn)
151 {
152 struct e1000_hw *hw = &adapter->hw;
153 u32 vmolr;
154
155 vmolr = rd32(E1000_VMOLR(vfn));
156 vmolr &= ~E1000_VMOLR_RLPML_MASK;
157 vmolr |= size | E1000_VMOLR_LPE;
158 wr32(E1000_VMOLR(vfn), vmolr);
159
160 return 0;
161 }
162
163 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
164 {
165 u32 reg_data;
166
167 reg_data = rd32(E1000_RAH(entry));
168 reg_data &= ~E1000_RAH_POOL_MASK;
169 reg_data |= E1000_RAH_POOL_1 << pool;;
170 wr32(E1000_RAH(entry), reg_data);
171 }
172
173 #ifdef CONFIG_PM
174 static int igb_suspend(struct pci_dev *, pm_message_t);
175 static int igb_resume(struct pci_dev *);
176 #endif
177 static void igb_shutdown(struct pci_dev *);
178 #ifdef CONFIG_IGB_DCA
179 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
180 static struct notifier_block dca_notifier = {
181 .notifier_call = igb_notify_dca,
182 .next = NULL,
183 .priority = 0
184 };
185 #endif
186 #ifdef CONFIG_NET_POLL_CONTROLLER
187 /* for netdump / net console */
188 static void igb_netpoll(struct net_device *);
189 #endif
190 #ifdef CONFIG_PCI_IOV
191 static unsigned int max_vfs = 0;
192 module_param(max_vfs, uint, 0);
193 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
194 "per physical function");
195 #endif /* CONFIG_PCI_IOV */
196
197 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
198 pci_channel_state_t);
199 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
200 static void igb_io_resume(struct pci_dev *);
201
202 static struct pci_error_handlers igb_err_handler = {
203 .error_detected = igb_io_error_detected,
204 .slot_reset = igb_io_slot_reset,
205 .resume = igb_io_resume,
206 };
207
208
209 static struct pci_driver igb_driver = {
210 .name = igb_driver_name,
211 .id_table = igb_pci_tbl,
212 .probe = igb_probe,
213 .remove = __devexit_p(igb_remove),
214 #ifdef CONFIG_PM
215 /* Power Managment Hooks */
216 .suspend = igb_suspend,
217 .resume = igb_resume,
218 #endif
219 .shutdown = igb_shutdown,
220 .err_handler = &igb_err_handler
221 };
222
223 static int global_quad_port_a; /* global quad port a indication */
224
225 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
226 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
227 MODULE_LICENSE("GPL");
228 MODULE_VERSION(DRV_VERSION);
229
230 /**
231 * Scale the NIC clock cycle by a large factor so that
232 * relatively small clock corrections can be added or
233 * substracted at each clock tick. The drawbacks of a
234 * large factor are a) that the clock register overflows
235 * more quickly (not such a big deal) and b) that the
236 * increment per tick has to fit into 24 bits.
237 *
238 * Note that
239 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
240 * IGB_TSYNC_SCALE
241 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
242 *
243 * The base scale factor is intentionally a power of two
244 * so that the division in %struct timecounter can be done with
245 * a shift.
246 */
247 #define IGB_TSYNC_SHIFT (19)
248 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
249
250 /**
251 * The duration of one clock cycle of the NIC.
252 *
253 * @todo This hard-coded value is part of the specification and might change
254 * in future hardware revisions. Add revision check.
255 */
256 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
257
258 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
259 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
260 #endif
261
262 /**
263 * igb_read_clock - read raw cycle counter (to be used by time counter)
264 */
265 static cycle_t igb_read_clock(const struct cyclecounter *tc)
266 {
267 struct igb_adapter *adapter =
268 container_of(tc, struct igb_adapter, cycles);
269 struct e1000_hw *hw = &adapter->hw;
270 u64 stamp;
271
272 stamp = rd32(E1000_SYSTIML);
273 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
274
275 return stamp;
276 }
277
278 #ifdef DEBUG
279 /**
280 * igb_get_hw_dev_name - return device name string
281 * used by hardware layer to print debugging information
282 **/
283 char *igb_get_hw_dev_name(struct e1000_hw *hw)
284 {
285 struct igb_adapter *adapter = hw->back;
286 return adapter->netdev->name;
287 }
288
289 /**
290 * igb_get_time_str - format current NIC and system time as string
291 */
292 static char *igb_get_time_str(struct igb_adapter *adapter,
293 char buffer[160])
294 {
295 cycle_t hw = adapter->cycles.read(&adapter->cycles);
296 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
297 struct timespec sys;
298 struct timespec delta;
299 getnstimeofday(&sys);
300
301 delta = timespec_sub(nic, sys);
302
303 sprintf(buffer,
304 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
305 hw,
306 (long)nic.tv_sec, nic.tv_nsec,
307 (long)sys.tv_sec, sys.tv_nsec,
308 (long)delta.tv_sec, delta.tv_nsec);
309
310 return buffer;
311 }
312 #endif
313
314 /**
315 * igb_desc_unused - calculate if we have unused descriptors
316 **/
317 static int igb_desc_unused(struct igb_ring *ring)
318 {
319 if (ring->next_to_clean > ring->next_to_use)
320 return ring->next_to_clean - ring->next_to_use - 1;
321
322 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
323 }
324
325 /**
326 * igb_init_module - Driver Registration Routine
327 *
328 * igb_init_module is the first routine called when the driver is
329 * loaded. All it does is register with the PCI subsystem.
330 **/
331 static int __init igb_init_module(void)
332 {
333 int ret;
334 printk(KERN_INFO "%s - version %s\n",
335 igb_driver_string, igb_driver_version);
336
337 printk(KERN_INFO "%s\n", igb_copyright);
338
339 global_quad_port_a = 0;
340
341 #ifdef CONFIG_IGB_DCA
342 dca_register_notify(&dca_notifier);
343 #endif
344
345 ret = pci_register_driver(&igb_driver);
346 return ret;
347 }
348
349 module_init(igb_init_module);
350
351 /**
352 * igb_exit_module - Driver Exit Cleanup Routine
353 *
354 * igb_exit_module is called just before the driver is removed
355 * from memory.
356 **/
357 static void __exit igb_exit_module(void)
358 {
359 #ifdef CONFIG_IGB_DCA
360 dca_unregister_notify(&dca_notifier);
361 #endif
362 pci_unregister_driver(&igb_driver);
363 }
364
365 module_exit(igb_exit_module);
366
367 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
368 /**
369 * igb_cache_ring_register - Descriptor ring to register mapping
370 * @adapter: board private structure to initialize
371 *
372 * Once we know the feature-set enabled for the device, we'll cache
373 * the register offset the descriptor ring is assigned to.
374 **/
375 static void igb_cache_ring_register(struct igb_adapter *adapter)
376 {
377 int i;
378 unsigned int rbase_offset = adapter->vfs_allocated_count;
379
380 switch (adapter->hw.mac.type) {
381 case e1000_82576:
382 /* The queues are allocated for virtualization such that VF 0
383 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
384 * In order to avoid collision we start at the first free queue
385 * and continue consuming queues in the same sequence
386 */
387 for (i = 0; i < adapter->num_rx_queues; i++)
388 adapter->rx_ring[i].reg_idx = rbase_offset +
389 Q_IDX_82576(i);
390 for (i = 0; i < adapter->num_tx_queues; i++)
391 adapter->tx_ring[i].reg_idx = rbase_offset +
392 Q_IDX_82576(i);
393 break;
394 case e1000_82575:
395 default:
396 for (i = 0; i < adapter->num_rx_queues; i++)
397 adapter->rx_ring[i].reg_idx = i;
398 for (i = 0; i < adapter->num_tx_queues; i++)
399 adapter->tx_ring[i].reg_idx = i;
400 break;
401 }
402 }
403
404 /**
405 * igb_alloc_queues - Allocate memory for all rings
406 * @adapter: board private structure to initialize
407 *
408 * We allocate one ring per queue at run-time since we don't know the
409 * number of queues at compile-time.
410 **/
411 static int igb_alloc_queues(struct igb_adapter *adapter)
412 {
413 int i;
414
415 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
416 sizeof(struct igb_ring), GFP_KERNEL);
417 if (!adapter->tx_ring)
418 return -ENOMEM;
419
420 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
421 sizeof(struct igb_ring), GFP_KERNEL);
422 if (!adapter->rx_ring) {
423 kfree(adapter->tx_ring);
424 return -ENOMEM;
425 }
426
427 adapter->rx_ring->buddy = adapter->tx_ring;
428
429 for (i = 0; i < adapter->num_tx_queues; i++) {
430 struct igb_ring *ring = &(adapter->tx_ring[i]);
431 ring->count = adapter->tx_ring_count;
432 ring->adapter = adapter;
433 ring->queue_index = i;
434 }
435 for (i = 0; i < adapter->num_rx_queues; i++) {
436 struct igb_ring *ring = &(adapter->rx_ring[i]);
437 ring->count = adapter->rx_ring_count;
438 ring->adapter = adapter;
439 ring->queue_index = i;
440 ring->itr_register = E1000_ITR;
441
442 /* set a default napi handler for each rx_ring */
443 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
444 }
445
446 igb_cache_ring_register(adapter);
447 return 0;
448 }
449
450 static void igb_free_queues(struct igb_adapter *adapter)
451 {
452 int i;
453
454 for (i = 0; i < adapter->num_rx_queues; i++)
455 netif_napi_del(&adapter->rx_ring[i].napi);
456
457 adapter->num_rx_queues = 0;
458 adapter->num_tx_queues = 0;
459
460 kfree(adapter->tx_ring);
461 kfree(adapter->rx_ring);
462 }
463
464 #define IGB_N0_QUEUE -1
465 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
466 int tx_queue, int msix_vector)
467 {
468 u32 msixbm = 0;
469 struct e1000_hw *hw = &adapter->hw;
470 u32 ivar, index;
471
472 switch (hw->mac.type) {
473 case e1000_82575:
474 /* The 82575 assigns vectors using a bitmask, which matches the
475 bitmask for the EICR/EIMS/EIMC registers. To assign one
476 or more queues to a vector, we write the appropriate bits
477 into the MSIXBM register for that vector. */
478 if (rx_queue > IGB_N0_QUEUE) {
479 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
480 adapter->rx_ring[rx_queue].eims_value = msixbm;
481 }
482 if (tx_queue > IGB_N0_QUEUE) {
483 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
484 adapter->tx_ring[tx_queue].eims_value =
485 E1000_EICR_TX_QUEUE0 << tx_queue;
486 }
487 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
488 break;
489 case e1000_82576:
490 /* 82576 uses a table-based method for assigning vectors.
491 Each queue has a single entry in the table to which we write
492 a vector number along with a "valid" bit. Sadly, the layout
493 of the table is somewhat counterintuitive. */
494 if (rx_queue > IGB_N0_QUEUE) {
495 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
496 ivar = array_rd32(E1000_IVAR0, index);
497 if (rx_queue & 0x1) {
498 /* vector goes into third byte of register */
499 ivar = ivar & 0xFF00FFFF;
500 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
501 } else {
502 /* vector goes into low byte of register */
503 ivar = ivar & 0xFFFFFF00;
504 ivar |= msix_vector | E1000_IVAR_VALID;
505 }
506 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
507 array_wr32(E1000_IVAR0, index, ivar);
508 }
509 if (tx_queue > IGB_N0_QUEUE) {
510 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
511 ivar = array_rd32(E1000_IVAR0, index);
512 if (tx_queue & 0x1) {
513 /* vector goes into high byte of register */
514 ivar = ivar & 0x00FFFFFF;
515 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
516 } else {
517 /* vector goes into second byte of register */
518 ivar = ivar & 0xFFFF00FF;
519 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
520 }
521 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
522 array_wr32(E1000_IVAR0, index, ivar);
523 }
524 break;
525 default:
526 BUG();
527 break;
528 }
529 }
530
531 /**
532 * igb_configure_msix - Configure MSI-X hardware
533 *
534 * igb_configure_msix sets up the hardware to properly
535 * generate MSI-X interrupts.
536 **/
537 static void igb_configure_msix(struct igb_adapter *adapter)
538 {
539 u32 tmp;
540 int i, vector = 0;
541 struct e1000_hw *hw = &adapter->hw;
542
543 adapter->eims_enable_mask = 0;
544 if (hw->mac.type == e1000_82576)
545 /* Turn on MSI-X capability first, or our settings
546 * won't stick. And it will take days to debug. */
547 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
548 E1000_GPIE_PBA | E1000_GPIE_EIAME |
549 E1000_GPIE_NSICR);
550
551 for (i = 0; i < adapter->num_tx_queues; i++) {
552 struct igb_ring *tx_ring = &adapter->tx_ring[i];
553 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
554 adapter->eims_enable_mask |= tx_ring->eims_value;
555 if (tx_ring->itr_val)
556 writel(tx_ring->itr_val,
557 hw->hw_addr + tx_ring->itr_register);
558 else
559 writel(1, hw->hw_addr + tx_ring->itr_register);
560 }
561
562 for (i = 0; i < adapter->num_rx_queues; i++) {
563 struct igb_ring *rx_ring = &adapter->rx_ring[i];
564 rx_ring->buddy = NULL;
565 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
566 adapter->eims_enable_mask |= rx_ring->eims_value;
567 if (rx_ring->itr_val)
568 writel(rx_ring->itr_val,
569 hw->hw_addr + rx_ring->itr_register);
570 else
571 writel(1, hw->hw_addr + rx_ring->itr_register);
572 }
573
574
575 /* set vector for other causes, i.e. link changes */
576 switch (hw->mac.type) {
577 case e1000_82575:
578 array_wr32(E1000_MSIXBM(0), vector++,
579 E1000_EIMS_OTHER);
580
581 tmp = rd32(E1000_CTRL_EXT);
582 /* enable MSI-X PBA support*/
583 tmp |= E1000_CTRL_EXT_PBA_CLR;
584
585 /* Auto-Mask interrupts upon ICR read. */
586 tmp |= E1000_CTRL_EXT_EIAME;
587 tmp |= E1000_CTRL_EXT_IRCA;
588
589 wr32(E1000_CTRL_EXT, tmp);
590 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
591 adapter->eims_other = E1000_EIMS_OTHER;
592
593 break;
594
595 case e1000_82576:
596 tmp = (vector++ | E1000_IVAR_VALID) << 8;
597 wr32(E1000_IVAR_MISC, tmp);
598
599 adapter->eims_enable_mask = (1 << (vector)) - 1;
600 adapter->eims_other = 1 << (vector - 1);
601 break;
602 default:
603 /* do nothing, since nothing else supports MSI-X */
604 break;
605 } /* switch (hw->mac.type) */
606 wrfl();
607 }
608
609 /**
610 * igb_request_msix - Initialize MSI-X interrupts
611 *
612 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
613 * kernel.
614 **/
615 static int igb_request_msix(struct igb_adapter *adapter)
616 {
617 struct net_device *netdev = adapter->netdev;
618 int i, err = 0, vector = 0;
619
620 vector = 0;
621
622 for (i = 0; i < adapter->num_tx_queues; i++) {
623 struct igb_ring *ring = &(adapter->tx_ring[i]);
624 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
625 err = request_irq(adapter->msix_entries[vector].vector,
626 &igb_msix_tx, 0, ring->name,
627 &(adapter->tx_ring[i]));
628 if (err)
629 goto out;
630 ring->itr_register = E1000_EITR(0) + (vector << 2);
631 ring->itr_val = 976; /* ~4000 ints/sec */
632 vector++;
633 }
634 for (i = 0; i < adapter->num_rx_queues; i++) {
635 struct igb_ring *ring = &(adapter->rx_ring[i]);
636 if (strlen(netdev->name) < (IFNAMSIZ - 5))
637 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
638 else
639 memcpy(ring->name, netdev->name, IFNAMSIZ);
640 err = request_irq(adapter->msix_entries[vector].vector,
641 &igb_msix_rx, 0, ring->name,
642 &(adapter->rx_ring[i]));
643 if (err)
644 goto out;
645 ring->itr_register = E1000_EITR(0) + (vector << 2);
646 ring->itr_val = adapter->itr;
647 vector++;
648 }
649
650 err = request_irq(adapter->msix_entries[vector].vector,
651 &igb_msix_other, 0, netdev->name, netdev);
652 if (err)
653 goto out;
654
655 igb_configure_msix(adapter);
656 return 0;
657 out:
658 return err;
659 }
660
661 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
662 {
663 if (adapter->msix_entries) {
664 pci_disable_msix(adapter->pdev);
665 kfree(adapter->msix_entries);
666 adapter->msix_entries = NULL;
667 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
668 pci_disable_msi(adapter->pdev);
669 return;
670 }
671
672
673 /**
674 * igb_set_interrupt_capability - set MSI or MSI-X if supported
675 *
676 * Attempt to configure interrupts using the best available
677 * capabilities of the hardware and kernel.
678 **/
679 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
680 {
681 int err;
682 int numvecs, i;
683
684 /* Number of supported queues. */
685 /* Having more queues than CPUs doesn't make sense. */
686 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
687 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
688
689 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
690 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
691 GFP_KERNEL);
692 if (!adapter->msix_entries)
693 goto msi_only;
694
695 for (i = 0; i < numvecs; i++)
696 adapter->msix_entries[i].entry = i;
697
698 err = pci_enable_msix(adapter->pdev,
699 adapter->msix_entries,
700 numvecs);
701 if (err == 0)
702 goto out;
703
704 igb_reset_interrupt_capability(adapter);
705
706 /* If we can't do MSI-X, try MSI */
707 msi_only:
708 #ifdef CONFIG_PCI_IOV
709 /* disable SR-IOV for non MSI-X configurations */
710 if (adapter->vf_data) {
711 struct e1000_hw *hw = &adapter->hw;
712 /* disable iov and allow time for transactions to clear */
713 pci_disable_sriov(adapter->pdev);
714 msleep(500);
715
716 kfree(adapter->vf_data);
717 adapter->vf_data = NULL;
718 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
719 msleep(100);
720 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
721 }
722 #endif
723 adapter->num_rx_queues = 1;
724 adapter->num_tx_queues = 1;
725 if (!pci_enable_msi(adapter->pdev))
726 adapter->flags |= IGB_FLAG_HAS_MSI;
727 out:
728 /* Notify the stack of the (possibly) reduced Tx Queue count. */
729 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
730 return;
731 }
732
733 /**
734 * igb_request_irq - initialize interrupts
735 *
736 * Attempts to configure interrupts using the best available
737 * capabilities of the hardware and kernel.
738 **/
739 static int igb_request_irq(struct igb_adapter *adapter)
740 {
741 struct net_device *netdev = adapter->netdev;
742 struct e1000_hw *hw = &adapter->hw;
743 int err = 0;
744
745 if (adapter->msix_entries) {
746 err = igb_request_msix(adapter);
747 if (!err)
748 goto request_done;
749 /* fall back to MSI */
750 igb_reset_interrupt_capability(adapter);
751 if (!pci_enable_msi(adapter->pdev))
752 adapter->flags |= IGB_FLAG_HAS_MSI;
753 igb_free_all_tx_resources(adapter);
754 igb_free_all_rx_resources(adapter);
755 adapter->num_rx_queues = 1;
756 igb_alloc_queues(adapter);
757 } else {
758 switch (hw->mac.type) {
759 case e1000_82575:
760 wr32(E1000_MSIXBM(0),
761 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
762 break;
763 case e1000_82576:
764 wr32(E1000_IVAR0, E1000_IVAR_VALID);
765 break;
766 default:
767 break;
768 }
769 }
770
771 if (adapter->flags & IGB_FLAG_HAS_MSI) {
772 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
773 netdev->name, netdev);
774 if (!err)
775 goto request_done;
776 /* fall back to legacy interrupts */
777 igb_reset_interrupt_capability(adapter);
778 adapter->flags &= ~IGB_FLAG_HAS_MSI;
779 }
780
781 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
782 netdev->name, netdev);
783
784 if (err)
785 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
786 err);
787
788 request_done:
789 return err;
790 }
791
792 static void igb_free_irq(struct igb_adapter *adapter)
793 {
794 struct net_device *netdev = adapter->netdev;
795
796 if (adapter->msix_entries) {
797 int vector = 0, i;
798
799 for (i = 0; i < adapter->num_tx_queues; i++)
800 free_irq(adapter->msix_entries[vector++].vector,
801 &(adapter->tx_ring[i]));
802 for (i = 0; i < adapter->num_rx_queues; i++)
803 free_irq(adapter->msix_entries[vector++].vector,
804 &(adapter->rx_ring[i]));
805
806 free_irq(adapter->msix_entries[vector++].vector, netdev);
807 return;
808 }
809
810 free_irq(adapter->pdev->irq, netdev);
811 }
812
813 /**
814 * igb_irq_disable - Mask off interrupt generation on the NIC
815 * @adapter: board private structure
816 **/
817 static void igb_irq_disable(struct igb_adapter *adapter)
818 {
819 struct e1000_hw *hw = &adapter->hw;
820
821 if (adapter->msix_entries) {
822 wr32(E1000_EIAM, 0);
823 wr32(E1000_EIMC, ~0);
824 wr32(E1000_EIAC, 0);
825 }
826
827 wr32(E1000_IAM, 0);
828 wr32(E1000_IMC, ~0);
829 wrfl();
830 synchronize_irq(adapter->pdev->irq);
831 }
832
833 /**
834 * igb_irq_enable - Enable default interrupt generation settings
835 * @adapter: board private structure
836 **/
837 static void igb_irq_enable(struct igb_adapter *adapter)
838 {
839 struct e1000_hw *hw = &adapter->hw;
840
841 if (adapter->msix_entries) {
842 wr32(E1000_EIAC, adapter->eims_enable_mask);
843 wr32(E1000_EIAM, adapter->eims_enable_mask);
844 wr32(E1000_EIMS, adapter->eims_enable_mask);
845 if (adapter->vfs_allocated_count)
846 wr32(E1000_MBVFIMR, 0xFF);
847 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
848 E1000_IMS_DOUTSYNC));
849 } else {
850 wr32(E1000_IMS, IMS_ENABLE_MASK);
851 wr32(E1000_IAM, IMS_ENABLE_MASK);
852 }
853 }
854
855 static void igb_update_mng_vlan(struct igb_adapter *adapter)
856 {
857 struct net_device *netdev = adapter->netdev;
858 u16 vid = adapter->hw.mng_cookie.vlan_id;
859 u16 old_vid = adapter->mng_vlan_id;
860 if (adapter->vlgrp) {
861 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
862 if (adapter->hw.mng_cookie.status &
863 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
864 igb_vlan_rx_add_vid(netdev, vid);
865 adapter->mng_vlan_id = vid;
866 } else
867 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
868
869 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
870 (vid != old_vid) &&
871 !vlan_group_get_device(adapter->vlgrp, old_vid))
872 igb_vlan_rx_kill_vid(netdev, old_vid);
873 } else
874 adapter->mng_vlan_id = vid;
875 }
876 }
877
878 /**
879 * igb_release_hw_control - release control of the h/w to f/w
880 * @adapter: address of board private structure
881 *
882 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
883 * For ASF and Pass Through versions of f/w this means that the
884 * driver is no longer loaded.
885 *
886 **/
887 static void igb_release_hw_control(struct igb_adapter *adapter)
888 {
889 struct e1000_hw *hw = &adapter->hw;
890 u32 ctrl_ext;
891
892 /* Let firmware take over control of h/w */
893 ctrl_ext = rd32(E1000_CTRL_EXT);
894 wr32(E1000_CTRL_EXT,
895 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
896 }
897
898
899 /**
900 * igb_get_hw_control - get control of the h/w from f/w
901 * @adapter: address of board private structure
902 *
903 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
904 * For ASF and Pass Through versions of f/w this means that
905 * the driver is loaded.
906 *
907 **/
908 static void igb_get_hw_control(struct igb_adapter *adapter)
909 {
910 struct e1000_hw *hw = &adapter->hw;
911 u32 ctrl_ext;
912
913 /* Let firmware know the driver has taken over */
914 ctrl_ext = rd32(E1000_CTRL_EXT);
915 wr32(E1000_CTRL_EXT,
916 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
917 }
918
919 /**
920 * igb_configure - configure the hardware for RX and TX
921 * @adapter: private board structure
922 **/
923 static void igb_configure(struct igb_adapter *adapter)
924 {
925 struct net_device *netdev = adapter->netdev;
926 int i;
927
928 igb_get_hw_control(adapter);
929 igb_set_multi(netdev);
930
931 igb_restore_vlan(adapter);
932
933 igb_configure_tx(adapter);
934 igb_setup_rctl(adapter);
935 igb_configure_rx(adapter);
936
937 igb_rx_fifo_flush_82575(&adapter->hw);
938
939 /* call igb_desc_unused which always leaves
940 * at least 1 descriptor unused to make sure
941 * next_to_use != next_to_clean */
942 for (i = 0; i < adapter->num_rx_queues; i++) {
943 struct igb_ring *ring = &adapter->rx_ring[i];
944 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
945 }
946
947
948 adapter->tx_queue_len = netdev->tx_queue_len;
949 }
950
951
952 /**
953 * igb_up - Open the interface and prepare it to handle traffic
954 * @adapter: board private structure
955 **/
956
957 int igb_up(struct igb_adapter *adapter)
958 {
959 struct e1000_hw *hw = &adapter->hw;
960 int i;
961
962 /* hardware has been reset, we need to reload some things */
963 igb_configure(adapter);
964
965 clear_bit(__IGB_DOWN, &adapter->state);
966
967 for (i = 0; i < adapter->num_rx_queues; i++)
968 napi_enable(&adapter->rx_ring[i].napi);
969 if (adapter->msix_entries)
970 igb_configure_msix(adapter);
971
972 igb_vmm_control(adapter);
973 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
974 igb_set_vmolr(hw, adapter->vfs_allocated_count);
975
976 /* Clear any pending interrupts. */
977 rd32(E1000_ICR);
978 igb_irq_enable(adapter);
979
980 netif_tx_start_all_queues(adapter->netdev);
981
982 /* Fire a link change interrupt to start the watchdog. */
983 wr32(E1000_ICS, E1000_ICS_LSC);
984 return 0;
985 }
986
987 void igb_down(struct igb_adapter *adapter)
988 {
989 struct e1000_hw *hw = &adapter->hw;
990 struct net_device *netdev = adapter->netdev;
991 u32 tctl, rctl;
992 int i;
993
994 /* signal that we're down so the interrupt handler does not
995 * reschedule our watchdog timer */
996 set_bit(__IGB_DOWN, &adapter->state);
997
998 /* disable receives in the hardware */
999 rctl = rd32(E1000_RCTL);
1000 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1001 /* flush and sleep below */
1002
1003 netif_tx_stop_all_queues(netdev);
1004
1005 /* disable transmits in the hardware */
1006 tctl = rd32(E1000_TCTL);
1007 tctl &= ~E1000_TCTL_EN;
1008 wr32(E1000_TCTL, tctl);
1009 /* flush both disables and wait for them to finish */
1010 wrfl();
1011 msleep(10);
1012
1013 for (i = 0; i < adapter->num_rx_queues; i++)
1014 napi_disable(&adapter->rx_ring[i].napi);
1015
1016 igb_irq_disable(adapter);
1017
1018 del_timer_sync(&adapter->watchdog_timer);
1019 del_timer_sync(&adapter->phy_info_timer);
1020
1021 netdev->tx_queue_len = adapter->tx_queue_len;
1022 netif_carrier_off(netdev);
1023
1024 /* record the stats before reset*/
1025 igb_update_stats(adapter);
1026
1027 adapter->link_speed = 0;
1028 adapter->link_duplex = 0;
1029
1030 if (!pci_channel_offline(adapter->pdev))
1031 igb_reset(adapter);
1032 igb_clean_all_tx_rings(adapter);
1033 igb_clean_all_rx_rings(adapter);
1034 #ifdef CONFIG_IGB_DCA
1035
1036 /* since we reset the hardware DCA settings were cleared */
1037 igb_setup_dca(adapter);
1038 #endif
1039 }
1040
1041 void igb_reinit_locked(struct igb_adapter *adapter)
1042 {
1043 WARN_ON(in_interrupt());
1044 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1045 msleep(1);
1046 igb_down(adapter);
1047 igb_up(adapter);
1048 clear_bit(__IGB_RESETTING, &adapter->state);
1049 }
1050
1051 void igb_reset(struct igb_adapter *adapter)
1052 {
1053 struct e1000_hw *hw = &adapter->hw;
1054 struct e1000_mac_info *mac = &hw->mac;
1055 struct e1000_fc_info *fc = &hw->fc;
1056 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1057 u16 hwm;
1058
1059 /* Repartition Pba for greater than 9k mtu
1060 * To take effect CTRL.RST is required.
1061 */
1062 switch (mac->type) {
1063 case e1000_82576:
1064 pba = E1000_PBA_64K;
1065 break;
1066 case e1000_82575:
1067 default:
1068 pba = E1000_PBA_34K;
1069 break;
1070 }
1071
1072 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1073 (mac->type < e1000_82576)) {
1074 /* adjust PBA for jumbo frames */
1075 wr32(E1000_PBA, pba);
1076
1077 /* To maintain wire speed transmits, the Tx FIFO should be
1078 * large enough to accommodate two full transmit packets,
1079 * rounded up to the next 1KB and expressed in KB. Likewise,
1080 * the Rx FIFO should be large enough to accommodate at least
1081 * one full receive packet and is similarly rounded up and
1082 * expressed in KB. */
1083 pba = rd32(E1000_PBA);
1084 /* upper 16 bits has Tx packet buffer allocation size in KB */
1085 tx_space = pba >> 16;
1086 /* lower 16 bits has Rx packet buffer allocation size in KB */
1087 pba &= 0xffff;
1088 /* the tx fifo also stores 16 bytes of information about the tx
1089 * but don't include ethernet FCS because hardware appends it */
1090 min_tx_space = (adapter->max_frame_size +
1091 sizeof(union e1000_adv_tx_desc) -
1092 ETH_FCS_LEN) * 2;
1093 min_tx_space = ALIGN(min_tx_space, 1024);
1094 min_tx_space >>= 10;
1095 /* software strips receive CRC, so leave room for it */
1096 min_rx_space = adapter->max_frame_size;
1097 min_rx_space = ALIGN(min_rx_space, 1024);
1098 min_rx_space >>= 10;
1099
1100 /* If current Tx allocation is less than the min Tx FIFO size,
1101 * and the min Tx FIFO size is less than the current Rx FIFO
1102 * allocation, take space away from current Rx allocation */
1103 if (tx_space < min_tx_space &&
1104 ((min_tx_space - tx_space) < pba)) {
1105 pba = pba - (min_tx_space - tx_space);
1106
1107 /* if short on rx space, rx wins and must trump tx
1108 * adjustment */
1109 if (pba < min_rx_space)
1110 pba = min_rx_space;
1111 }
1112 wr32(E1000_PBA, pba);
1113 }
1114
1115 /* flow control settings */
1116 /* The high water mark must be low enough to fit one full frame
1117 * (or the size used for early receive) above it in the Rx FIFO.
1118 * Set it to the lower of:
1119 * - 90% of the Rx FIFO size, or
1120 * - the full Rx FIFO size minus one full frame */
1121 hwm = min(((pba << 10) * 9 / 10),
1122 ((pba << 10) - 2 * adapter->max_frame_size));
1123
1124 if (mac->type < e1000_82576) {
1125 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1126 fc->low_water = fc->high_water - 8;
1127 } else {
1128 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1129 fc->low_water = fc->high_water - 16;
1130 }
1131 fc->pause_time = 0xFFFF;
1132 fc->send_xon = 1;
1133 fc->current_mode = fc->requested_mode;
1134
1135 /* disable receive for all VFs and wait one second */
1136 if (adapter->vfs_allocated_count) {
1137 int i;
1138 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1139 adapter->vf_data[i].clear_to_send = false;
1140
1141 /* ping all the active vfs to let them know we are going down */
1142 igb_ping_all_vfs(adapter);
1143
1144 /* disable transmits and receives */
1145 wr32(E1000_VFRE, 0);
1146 wr32(E1000_VFTE, 0);
1147 }
1148
1149 /* Allow time for pending master requests to run */
1150 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1151 wr32(E1000_WUC, 0);
1152
1153 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1154 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1155
1156 igb_update_mng_vlan(adapter);
1157
1158 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1159 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1160
1161 igb_reset_adaptive(&adapter->hw);
1162 igb_get_phy_info(&adapter->hw);
1163 }
1164
1165 static const struct net_device_ops igb_netdev_ops = {
1166 .ndo_open = igb_open,
1167 .ndo_stop = igb_close,
1168 .ndo_start_xmit = igb_xmit_frame_adv,
1169 .ndo_get_stats = igb_get_stats,
1170 .ndo_set_multicast_list = igb_set_multi,
1171 .ndo_set_mac_address = igb_set_mac,
1172 .ndo_change_mtu = igb_change_mtu,
1173 .ndo_do_ioctl = igb_ioctl,
1174 .ndo_tx_timeout = igb_tx_timeout,
1175 .ndo_validate_addr = eth_validate_addr,
1176 .ndo_vlan_rx_register = igb_vlan_rx_register,
1177 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1178 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1179 #ifdef CONFIG_NET_POLL_CONTROLLER
1180 .ndo_poll_controller = igb_netpoll,
1181 #endif
1182 };
1183
1184 /**
1185 * igb_probe - Device Initialization Routine
1186 * @pdev: PCI device information struct
1187 * @ent: entry in igb_pci_tbl
1188 *
1189 * Returns 0 on success, negative on failure
1190 *
1191 * igb_probe initializes an adapter identified by a pci_dev structure.
1192 * The OS initialization, configuring of the adapter private structure,
1193 * and a hardware reset occur.
1194 **/
1195 static int __devinit igb_probe(struct pci_dev *pdev,
1196 const struct pci_device_id *ent)
1197 {
1198 struct net_device *netdev;
1199 struct igb_adapter *adapter;
1200 struct e1000_hw *hw;
1201 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1202 unsigned long mmio_start, mmio_len;
1203 int err, pci_using_dac;
1204 u16 eeprom_data = 0;
1205 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1206 u32 part_num;
1207
1208 err = pci_enable_device_mem(pdev);
1209 if (err)
1210 return err;
1211
1212 pci_using_dac = 0;
1213 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1214 if (!err) {
1215 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1216 if (!err)
1217 pci_using_dac = 1;
1218 } else {
1219 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1220 if (err) {
1221 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1222 if (err) {
1223 dev_err(&pdev->dev, "No usable DMA "
1224 "configuration, aborting\n");
1225 goto err_dma;
1226 }
1227 }
1228 }
1229
1230 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1231 IORESOURCE_MEM),
1232 igb_driver_name);
1233 if (err)
1234 goto err_pci_reg;
1235
1236 err = pci_enable_pcie_error_reporting(pdev);
1237 if (err) {
1238 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1239 "0x%x\n", err);
1240 /* non-fatal, continue */
1241 }
1242
1243 pci_set_master(pdev);
1244 pci_save_state(pdev);
1245
1246 err = -ENOMEM;
1247 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1248 IGB_ABS_MAX_TX_QUEUES);
1249 if (!netdev)
1250 goto err_alloc_etherdev;
1251
1252 SET_NETDEV_DEV(netdev, &pdev->dev);
1253
1254 pci_set_drvdata(pdev, netdev);
1255 adapter = netdev_priv(netdev);
1256 adapter->netdev = netdev;
1257 adapter->pdev = pdev;
1258 hw = &adapter->hw;
1259 hw->back = adapter;
1260 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1261
1262 mmio_start = pci_resource_start(pdev, 0);
1263 mmio_len = pci_resource_len(pdev, 0);
1264
1265 err = -EIO;
1266 hw->hw_addr = ioremap(mmio_start, mmio_len);
1267 if (!hw->hw_addr)
1268 goto err_ioremap;
1269
1270 netdev->netdev_ops = &igb_netdev_ops;
1271 igb_set_ethtool_ops(netdev);
1272 netdev->watchdog_timeo = 5 * HZ;
1273
1274 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1275
1276 netdev->mem_start = mmio_start;
1277 netdev->mem_end = mmio_start + mmio_len;
1278
1279 /* PCI config space info */
1280 hw->vendor_id = pdev->vendor;
1281 hw->device_id = pdev->device;
1282 hw->revision_id = pdev->revision;
1283 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1284 hw->subsystem_device_id = pdev->subsystem_device;
1285
1286 /* setup the private structure */
1287 hw->back = adapter;
1288 /* Copy the default MAC, PHY and NVM function pointers */
1289 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1290 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1291 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1292 /* Initialize skew-specific constants */
1293 err = ei->get_invariants(hw);
1294 if (err)
1295 goto err_sw_init;
1296
1297 #ifdef CONFIG_PCI_IOV
1298 /* since iov functionality isn't critical to base device function we
1299 * can accept failure. If it fails we don't allow iov to be enabled */
1300 if (hw->mac.type == e1000_82576) {
1301 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1302 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1303 int i;
1304 unsigned char mac_addr[ETH_ALEN];
1305
1306 if (num_vfs) {
1307 adapter->vf_data = kcalloc(num_vfs,
1308 sizeof(struct vf_data_storage),
1309 GFP_KERNEL);
1310 if (!adapter->vf_data) {
1311 dev_err(&pdev->dev,
1312 "Could not allocate VF private data - "
1313 "IOV enable failed\n");
1314 } else {
1315 err = pci_enable_sriov(pdev, num_vfs);
1316 if (!err) {
1317 adapter->vfs_allocated_count = num_vfs;
1318 dev_info(&pdev->dev,
1319 "%d vfs allocated\n",
1320 num_vfs);
1321 for (i = 0;
1322 i < adapter->vfs_allocated_count;
1323 i++) {
1324 random_ether_addr(mac_addr);
1325 igb_set_vf_mac(adapter, i,
1326 mac_addr);
1327 }
1328 } else {
1329 kfree(adapter->vf_data);
1330 adapter->vf_data = NULL;
1331 }
1332 }
1333 }
1334 }
1335
1336 #endif
1337 /* setup the private structure */
1338 err = igb_sw_init(adapter);
1339 if (err)
1340 goto err_sw_init;
1341
1342 igb_get_bus_info_pcie(hw);
1343
1344 /* set flags */
1345 switch (hw->mac.type) {
1346 case e1000_82575:
1347 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1348 break;
1349 case e1000_82576:
1350 default:
1351 break;
1352 }
1353
1354 hw->phy.autoneg_wait_to_complete = false;
1355 hw->mac.adaptive_ifs = true;
1356
1357 /* Copper options */
1358 if (hw->phy.media_type == e1000_media_type_copper) {
1359 hw->phy.mdix = AUTO_ALL_MODES;
1360 hw->phy.disable_polarity_correction = false;
1361 hw->phy.ms_type = e1000_ms_hw_default;
1362 }
1363
1364 if (igb_check_reset_block(hw))
1365 dev_info(&pdev->dev,
1366 "PHY reset is blocked due to SOL/IDER session.\n");
1367
1368 netdev->features = NETIF_F_SG |
1369 NETIF_F_IP_CSUM |
1370 NETIF_F_HW_VLAN_TX |
1371 NETIF_F_HW_VLAN_RX |
1372 NETIF_F_HW_VLAN_FILTER;
1373
1374 netdev->features |= NETIF_F_IPV6_CSUM;
1375 netdev->features |= NETIF_F_TSO;
1376 netdev->features |= NETIF_F_TSO6;
1377
1378 netdev->features |= NETIF_F_GRO;
1379
1380 netdev->vlan_features |= NETIF_F_TSO;
1381 netdev->vlan_features |= NETIF_F_TSO6;
1382 netdev->vlan_features |= NETIF_F_IP_CSUM;
1383 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
1384 netdev->vlan_features |= NETIF_F_SG;
1385
1386 if (pci_using_dac)
1387 netdev->features |= NETIF_F_HIGHDMA;
1388
1389 if (adapter->hw.mac.type == e1000_82576)
1390 netdev->features |= NETIF_F_SCTP_CSUM;
1391
1392 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1393
1394 /* before reading the NVM, reset the controller to put the device in a
1395 * known good starting state */
1396 hw->mac.ops.reset_hw(hw);
1397
1398 /* make sure the NVM is good */
1399 if (igb_validate_nvm_checksum(hw) < 0) {
1400 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1401 err = -EIO;
1402 goto err_eeprom;
1403 }
1404
1405 /* copy the MAC address out of the NVM */
1406 if (hw->mac.ops.read_mac_addr(hw))
1407 dev_err(&pdev->dev, "NVM Read Error\n");
1408
1409 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1410 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1411
1412 if (!is_valid_ether_addr(netdev->perm_addr)) {
1413 dev_err(&pdev->dev, "Invalid MAC Address\n");
1414 err = -EIO;
1415 goto err_eeprom;
1416 }
1417
1418 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1419 (unsigned long) adapter);
1420 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1421 (unsigned long) adapter);
1422
1423 INIT_WORK(&adapter->reset_task, igb_reset_task);
1424 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1425
1426 /* Initialize link properties that are user-changeable */
1427 adapter->fc_autoneg = true;
1428 hw->mac.autoneg = true;
1429 hw->phy.autoneg_advertised = 0x2f;
1430
1431 hw->fc.requested_mode = e1000_fc_default;
1432 hw->fc.current_mode = e1000_fc_default;
1433
1434 adapter->itr_setting = IGB_DEFAULT_ITR;
1435 adapter->itr = IGB_START_ITR;
1436
1437 igb_validate_mdi_setting(hw);
1438
1439 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1440 * enable the ACPI Magic Packet filter
1441 */
1442
1443 if (hw->bus.func == 0)
1444 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1445 else if (hw->bus.func == 1)
1446 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1447
1448 if (eeprom_data & eeprom_apme_mask)
1449 adapter->eeprom_wol |= E1000_WUFC_MAG;
1450
1451 /* now that we have the eeprom settings, apply the special cases where
1452 * the eeprom may be wrong or the board simply won't support wake on
1453 * lan on a particular port */
1454 switch (pdev->device) {
1455 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1456 adapter->eeprom_wol = 0;
1457 break;
1458 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1459 case E1000_DEV_ID_82576_FIBER:
1460 case E1000_DEV_ID_82576_SERDES:
1461 /* Wake events only supported on port A for dual fiber
1462 * regardless of eeprom setting */
1463 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1464 adapter->eeprom_wol = 0;
1465 break;
1466 case E1000_DEV_ID_82576_QUAD_COPPER:
1467 /* if quad port adapter, disable WoL on all but port A */
1468 if (global_quad_port_a != 0)
1469 adapter->eeprom_wol = 0;
1470 else
1471 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1472 /* Reset for multiple quad port adapters */
1473 if (++global_quad_port_a == 4)
1474 global_quad_port_a = 0;
1475 break;
1476 }
1477
1478 /* initialize the wol settings based on the eeprom settings */
1479 adapter->wol = adapter->eeprom_wol;
1480 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1481
1482 /* reset the hardware with the new settings */
1483 igb_reset(adapter);
1484
1485 /* let the f/w know that the h/w is now under the control of the
1486 * driver. */
1487 igb_get_hw_control(adapter);
1488
1489 strcpy(netdev->name, "eth%d");
1490 err = register_netdev(netdev);
1491 if (err)
1492 goto err_register;
1493
1494 /* carrier off reporting is important to ethtool even BEFORE open */
1495 netif_carrier_off(netdev);
1496
1497 #ifdef CONFIG_IGB_DCA
1498 if (dca_add_requester(&pdev->dev) == 0) {
1499 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1500 dev_info(&pdev->dev, "DCA enabled\n");
1501 igb_setup_dca(adapter);
1502 }
1503 #endif
1504
1505 /*
1506 * Initialize hardware timer: we keep it running just in case
1507 * that some program needs it later on.
1508 */
1509 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1510 adapter->cycles.read = igb_read_clock;
1511 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1512 adapter->cycles.mult = 1;
1513 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1514 wr32(E1000_TIMINCA,
1515 (1<<24) |
1516 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1517 #if 0
1518 /*
1519 * Avoid rollover while we initialize by resetting the time counter.
1520 */
1521 wr32(E1000_SYSTIML, 0x00000000);
1522 wr32(E1000_SYSTIMH, 0x00000000);
1523 #else
1524 /*
1525 * Set registers so that rollover occurs soon to test this.
1526 */
1527 wr32(E1000_SYSTIML, 0x00000000);
1528 wr32(E1000_SYSTIMH, 0xFF800000);
1529 #endif
1530 wrfl();
1531 timecounter_init(&adapter->clock,
1532 &adapter->cycles,
1533 ktime_to_ns(ktime_get_real()));
1534
1535 /*
1536 * Synchronize our NIC clock against system wall clock. NIC
1537 * time stamp reading requires ~3us per sample, each sample
1538 * was pretty stable even under load => only require 10
1539 * samples for each offset comparison.
1540 */
1541 memset(&adapter->compare, 0, sizeof(adapter->compare));
1542 adapter->compare.source = &adapter->clock;
1543 adapter->compare.target = ktime_get_real;
1544 adapter->compare.num_samples = 10;
1545 timecompare_update(&adapter->compare, 0);
1546
1547 #ifdef DEBUG
1548 {
1549 char buffer[160];
1550 printk(KERN_DEBUG
1551 "igb: %s: hw %p initialized timer\n",
1552 igb_get_time_str(adapter, buffer),
1553 &adapter->hw);
1554 }
1555 #endif
1556
1557 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1558 /* print bus type/speed/width info */
1559 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1560 netdev->name,
1561 ((hw->bus.speed == e1000_bus_speed_2500)
1562 ? "2.5Gb/s" : "unknown"),
1563 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1564 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1565 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1566 "unknown"),
1567 netdev->dev_addr);
1568
1569 igb_read_part_num(hw, &part_num);
1570 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1571 (part_num >> 8), (part_num & 0xff));
1572
1573 dev_info(&pdev->dev,
1574 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1575 adapter->msix_entries ? "MSI-X" :
1576 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1577 adapter->num_rx_queues, adapter->num_tx_queues);
1578
1579 return 0;
1580
1581 err_register:
1582 igb_release_hw_control(adapter);
1583 err_eeprom:
1584 if (!igb_check_reset_block(hw))
1585 igb_reset_phy(hw);
1586
1587 if (hw->flash_address)
1588 iounmap(hw->flash_address);
1589
1590 igb_free_queues(adapter);
1591 err_sw_init:
1592 iounmap(hw->hw_addr);
1593 err_ioremap:
1594 free_netdev(netdev);
1595 err_alloc_etherdev:
1596 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1597 IORESOURCE_MEM));
1598 err_pci_reg:
1599 err_dma:
1600 pci_disable_device(pdev);
1601 return err;
1602 }
1603
1604 /**
1605 * igb_remove - Device Removal Routine
1606 * @pdev: PCI device information struct
1607 *
1608 * igb_remove is called by the PCI subsystem to alert the driver
1609 * that it should release a PCI device. The could be caused by a
1610 * Hot-Plug event, or because the driver is going to be removed from
1611 * memory.
1612 **/
1613 static void __devexit igb_remove(struct pci_dev *pdev)
1614 {
1615 struct net_device *netdev = pci_get_drvdata(pdev);
1616 struct igb_adapter *adapter = netdev_priv(netdev);
1617 struct e1000_hw *hw = &adapter->hw;
1618 int err;
1619
1620 /* flush_scheduled work may reschedule our watchdog task, so
1621 * explicitly disable watchdog tasks from being rescheduled */
1622 set_bit(__IGB_DOWN, &adapter->state);
1623 del_timer_sync(&adapter->watchdog_timer);
1624 del_timer_sync(&adapter->phy_info_timer);
1625
1626 flush_scheduled_work();
1627
1628 #ifdef CONFIG_IGB_DCA
1629 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1630 dev_info(&pdev->dev, "DCA disabled\n");
1631 dca_remove_requester(&pdev->dev);
1632 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1633 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1634 }
1635 #endif
1636
1637 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1638 * would have already happened in close and is redundant. */
1639 igb_release_hw_control(adapter);
1640
1641 unregister_netdev(netdev);
1642
1643 if (!igb_check_reset_block(&adapter->hw))
1644 igb_reset_phy(&adapter->hw);
1645
1646 igb_reset_interrupt_capability(adapter);
1647
1648 igb_free_queues(adapter);
1649
1650 #ifdef CONFIG_PCI_IOV
1651 /* reclaim resources allocated to VFs */
1652 if (adapter->vf_data) {
1653 /* disable iov and allow time for transactions to clear */
1654 pci_disable_sriov(pdev);
1655 msleep(500);
1656
1657 kfree(adapter->vf_data);
1658 adapter->vf_data = NULL;
1659 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1660 msleep(100);
1661 dev_info(&pdev->dev, "IOV Disabled\n");
1662 }
1663 #endif
1664 iounmap(hw->hw_addr);
1665 if (hw->flash_address)
1666 iounmap(hw->flash_address);
1667 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1668 IORESOURCE_MEM));
1669
1670 free_netdev(netdev);
1671
1672 err = pci_disable_pcie_error_reporting(pdev);
1673 if (err)
1674 dev_err(&pdev->dev,
1675 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1676
1677 pci_disable_device(pdev);
1678 }
1679
1680 /**
1681 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1682 * @adapter: board private structure to initialize
1683 *
1684 * igb_sw_init initializes the Adapter private data structure.
1685 * Fields are initialized based on PCI device information and
1686 * OS network device settings (MTU size).
1687 **/
1688 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1689 {
1690 struct e1000_hw *hw = &adapter->hw;
1691 struct net_device *netdev = adapter->netdev;
1692 struct pci_dev *pdev = adapter->pdev;
1693
1694 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1695
1696 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1697 adapter->rx_ring_count = IGB_DEFAULT_RXD;
1698 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1699 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1700 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1701 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1702
1703 /* This call may decrease the number of queues depending on
1704 * interrupt mode. */
1705 igb_set_interrupt_capability(adapter);
1706
1707 if (igb_alloc_queues(adapter)) {
1708 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1709 return -ENOMEM;
1710 }
1711
1712 /* Explicitly disable IRQ since the NIC can be in any state. */
1713 igb_irq_disable(adapter);
1714
1715 set_bit(__IGB_DOWN, &adapter->state);
1716 return 0;
1717 }
1718
1719 /**
1720 * igb_open - Called when a network interface is made active
1721 * @netdev: network interface device structure
1722 *
1723 * Returns 0 on success, negative value on failure
1724 *
1725 * The open entry point is called when a network interface is made
1726 * active by the system (IFF_UP). At this point all resources needed
1727 * for transmit and receive operations are allocated, the interrupt
1728 * handler is registered with the OS, the watchdog timer is started,
1729 * and the stack is notified that the interface is ready.
1730 **/
1731 static int igb_open(struct net_device *netdev)
1732 {
1733 struct igb_adapter *adapter = netdev_priv(netdev);
1734 struct e1000_hw *hw = &adapter->hw;
1735 int err;
1736 int i;
1737
1738 /* disallow open during test */
1739 if (test_bit(__IGB_TESTING, &adapter->state))
1740 return -EBUSY;
1741
1742 netif_carrier_off(netdev);
1743
1744 /* allocate transmit descriptors */
1745 err = igb_setup_all_tx_resources(adapter);
1746 if (err)
1747 goto err_setup_tx;
1748
1749 /* allocate receive descriptors */
1750 err = igb_setup_all_rx_resources(adapter);
1751 if (err)
1752 goto err_setup_rx;
1753
1754 /* e1000_power_up_phy(adapter); */
1755
1756 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1757 if ((adapter->hw.mng_cookie.status &
1758 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1759 igb_update_mng_vlan(adapter);
1760
1761 /* before we allocate an interrupt, we must be ready to handle it.
1762 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1763 * as soon as we call pci_request_irq, so we have to setup our
1764 * clean_rx handler before we do so. */
1765 igb_configure(adapter);
1766
1767 igb_vmm_control(adapter);
1768 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1769 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1770
1771 err = igb_request_irq(adapter);
1772 if (err)
1773 goto err_req_irq;
1774
1775 /* From here on the code is the same as igb_up() */
1776 clear_bit(__IGB_DOWN, &adapter->state);
1777
1778 for (i = 0; i < adapter->num_rx_queues; i++)
1779 napi_enable(&adapter->rx_ring[i].napi);
1780
1781 /* Clear any pending interrupts. */
1782 rd32(E1000_ICR);
1783
1784 igb_irq_enable(adapter);
1785
1786 netif_tx_start_all_queues(netdev);
1787
1788 /* Fire a link status change interrupt to start the watchdog. */
1789 wr32(E1000_ICS, E1000_ICS_LSC);
1790
1791 return 0;
1792
1793 err_req_irq:
1794 igb_release_hw_control(adapter);
1795 /* e1000_power_down_phy(adapter); */
1796 igb_free_all_rx_resources(adapter);
1797 err_setup_rx:
1798 igb_free_all_tx_resources(adapter);
1799 err_setup_tx:
1800 igb_reset(adapter);
1801
1802 return err;
1803 }
1804
1805 /**
1806 * igb_close - Disables a network interface
1807 * @netdev: network interface device structure
1808 *
1809 * Returns 0, this is not allowed to fail
1810 *
1811 * The close entry point is called when an interface is de-activated
1812 * by the OS. The hardware is still under the driver's control, but
1813 * needs to be disabled. A global MAC reset is issued to stop the
1814 * hardware, and all transmit and receive resources are freed.
1815 **/
1816 static int igb_close(struct net_device *netdev)
1817 {
1818 struct igb_adapter *adapter = netdev_priv(netdev);
1819
1820 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1821 igb_down(adapter);
1822
1823 igb_free_irq(adapter);
1824
1825 igb_free_all_tx_resources(adapter);
1826 igb_free_all_rx_resources(adapter);
1827
1828 /* kill manageability vlan ID if supported, but not if a vlan with
1829 * the same ID is registered on the host OS (let 8021q kill it) */
1830 if ((adapter->hw.mng_cookie.status &
1831 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1832 !(adapter->vlgrp &&
1833 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1834 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1835
1836 return 0;
1837 }
1838
1839 /**
1840 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1841 * @adapter: board private structure
1842 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1843 *
1844 * Return 0 on success, negative on failure
1845 **/
1846 int igb_setup_tx_resources(struct igb_adapter *adapter,
1847 struct igb_ring *tx_ring)
1848 {
1849 struct pci_dev *pdev = adapter->pdev;
1850 int size;
1851
1852 size = sizeof(struct igb_buffer) * tx_ring->count;
1853 tx_ring->buffer_info = vmalloc(size);
1854 if (!tx_ring->buffer_info)
1855 goto err;
1856 memset(tx_ring->buffer_info, 0, size);
1857
1858 /* round up to nearest 4K */
1859 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1860 tx_ring->size = ALIGN(tx_ring->size, 4096);
1861
1862 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1863 &tx_ring->dma);
1864
1865 if (!tx_ring->desc)
1866 goto err;
1867
1868 tx_ring->adapter = adapter;
1869 tx_ring->next_to_use = 0;
1870 tx_ring->next_to_clean = 0;
1871 return 0;
1872
1873 err:
1874 vfree(tx_ring->buffer_info);
1875 dev_err(&adapter->pdev->dev,
1876 "Unable to allocate memory for the transmit descriptor ring\n");
1877 return -ENOMEM;
1878 }
1879
1880 /**
1881 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1882 * (Descriptors) for all queues
1883 * @adapter: board private structure
1884 *
1885 * Return 0 on success, negative on failure
1886 **/
1887 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1888 {
1889 int i, err = 0;
1890 int r_idx;
1891
1892 for (i = 0; i < adapter->num_tx_queues; i++) {
1893 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1894 if (err) {
1895 dev_err(&adapter->pdev->dev,
1896 "Allocation for Tx Queue %u failed\n", i);
1897 for (i--; i >= 0; i--)
1898 igb_free_tx_resources(&adapter->tx_ring[i]);
1899 break;
1900 }
1901 }
1902
1903 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1904 r_idx = i % adapter->num_tx_queues;
1905 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1906 }
1907 return err;
1908 }
1909
1910 /**
1911 * igb_configure_tx - Configure transmit Unit after Reset
1912 * @adapter: board private structure
1913 *
1914 * Configure the Tx unit of the MAC after a reset.
1915 **/
1916 static void igb_configure_tx(struct igb_adapter *adapter)
1917 {
1918 u64 tdba;
1919 struct e1000_hw *hw = &adapter->hw;
1920 u32 tctl;
1921 u32 txdctl, txctrl;
1922 int i, j;
1923
1924 for (i = 0; i < adapter->num_tx_queues; i++) {
1925 struct igb_ring *ring = &adapter->tx_ring[i];
1926 j = ring->reg_idx;
1927 wr32(E1000_TDLEN(j),
1928 ring->count * sizeof(union e1000_adv_tx_desc));
1929 tdba = ring->dma;
1930 wr32(E1000_TDBAL(j),
1931 tdba & 0x00000000ffffffffULL);
1932 wr32(E1000_TDBAH(j), tdba >> 32);
1933
1934 ring->head = E1000_TDH(j);
1935 ring->tail = E1000_TDT(j);
1936 writel(0, hw->hw_addr + ring->tail);
1937 writel(0, hw->hw_addr + ring->head);
1938 txdctl = rd32(E1000_TXDCTL(j));
1939 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1940 wr32(E1000_TXDCTL(j), txdctl);
1941
1942 /* Turn off Relaxed Ordering on head write-backs. The
1943 * writebacks MUST be delivered in order or it will
1944 * completely screw up our bookeeping.
1945 */
1946 txctrl = rd32(E1000_DCA_TXCTRL(j));
1947 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1948 wr32(E1000_DCA_TXCTRL(j), txctrl);
1949 }
1950
1951 /* disable queue 0 to prevent tail bump w/o re-configuration */
1952 if (adapter->vfs_allocated_count)
1953 wr32(E1000_TXDCTL(0), 0);
1954
1955 /* Program the Transmit Control Register */
1956 tctl = rd32(E1000_TCTL);
1957 tctl &= ~E1000_TCTL_CT;
1958 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1959 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1960
1961 igb_config_collision_dist(hw);
1962
1963 /* Setup Transmit Descriptor Settings for eop descriptor */
1964 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1965
1966 /* Enable transmits */
1967 tctl |= E1000_TCTL_EN;
1968
1969 wr32(E1000_TCTL, tctl);
1970 }
1971
1972 /**
1973 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1974 * @adapter: board private structure
1975 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1976 *
1977 * Returns 0 on success, negative on failure
1978 **/
1979 int igb_setup_rx_resources(struct igb_adapter *adapter,
1980 struct igb_ring *rx_ring)
1981 {
1982 struct pci_dev *pdev = adapter->pdev;
1983 int size, desc_len;
1984
1985 size = sizeof(struct igb_buffer) * rx_ring->count;
1986 rx_ring->buffer_info = vmalloc(size);
1987 if (!rx_ring->buffer_info)
1988 goto err;
1989 memset(rx_ring->buffer_info, 0, size);
1990
1991 desc_len = sizeof(union e1000_adv_rx_desc);
1992
1993 /* Round up to nearest 4K */
1994 rx_ring->size = rx_ring->count * desc_len;
1995 rx_ring->size = ALIGN(rx_ring->size, 4096);
1996
1997 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1998 &rx_ring->dma);
1999
2000 if (!rx_ring->desc)
2001 goto err;
2002
2003 rx_ring->next_to_clean = 0;
2004 rx_ring->next_to_use = 0;
2005
2006 rx_ring->adapter = adapter;
2007
2008 return 0;
2009
2010 err:
2011 vfree(rx_ring->buffer_info);
2012 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
2013 "the receive descriptor ring\n");
2014 return -ENOMEM;
2015 }
2016
2017 /**
2018 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2019 * (Descriptors) for all queues
2020 * @adapter: board private structure
2021 *
2022 * Return 0 on success, negative on failure
2023 **/
2024 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2025 {
2026 int i, err = 0;
2027
2028 for (i = 0; i < adapter->num_rx_queues; i++) {
2029 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2030 if (err) {
2031 dev_err(&adapter->pdev->dev,
2032 "Allocation for Rx Queue %u failed\n", i);
2033 for (i--; i >= 0; i--)
2034 igb_free_rx_resources(&adapter->rx_ring[i]);
2035 break;
2036 }
2037 }
2038
2039 return err;
2040 }
2041
2042 /**
2043 * igb_setup_rctl - configure the receive control registers
2044 * @adapter: Board private structure
2045 **/
2046 static void igb_setup_rctl(struct igb_adapter *adapter)
2047 {
2048 struct e1000_hw *hw = &adapter->hw;
2049 u32 rctl;
2050 u32 srrctl = 0;
2051 int i;
2052
2053 rctl = rd32(E1000_RCTL);
2054
2055 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2056 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2057
2058 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2059 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2060
2061 /*
2062 * enable stripping of CRC. It's unlikely this will break BMC
2063 * redirection as it did with e1000. Newer features require
2064 * that the HW strips the CRC.
2065 */
2066 rctl |= E1000_RCTL_SECRC;
2067
2068 /*
2069 * disable store bad packets and clear size bits.
2070 */
2071 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2072
2073 /* enable LPE when to prevent packets larger than max_frame_size */
2074 rctl |= E1000_RCTL_LPE;
2075
2076 /* Setup buffer sizes */
2077 switch (adapter->rx_buffer_len) {
2078 case IGB_RXBUFFER_256:
2079 rctl |= E1000_RCTL_SZ_256;
2080 break;
2081 case IGB_RXBUFFER_512:
2082 rctl |= E1000_RCTL_SZ_512;
2083 break;
2084 default:
2085 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2086 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2087 break;
2088 }
2089
2090 /* 82575 and greater support packet-split where the protocol
2091 * header is placed in skb->data and the packet data is
2092 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2093 * In the case of a non-split, skb->data is linearly filled,
2094 * followed by the page buffers. Therefore, skb->data is
2095 * sized to hold the largest protocol header.
2096 */
2097 /* allocations using alloc_page take too long for regular MTU
2098 * so only enable packet split for jumbo frames */
2099 if (adapter->netdev->mtu > ETH_DATA_LEN) {
2100 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2101 srrctl |= adapter->rx_ps_hdr_size <<
2102 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2103 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2104 } else {
2105 adapter->rx_ps_hdr_size = 0;
2106 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2107 }
2108
2109 /* Attention!!! For SR-IOV PF driver operations you must enable
2110 * queue drop for all VF and PF queues to prevent head of line blocking
2111 * if an un-trusted VF does not provide descriptors to hardware.
2112 */
2113 if (adapter->vfs_allocated_count) {
2114 u32 vmolr;
2115
2116 /* set all queue drop enable bits */
2117 wr32(E1000_QDE, ALL_QUEUES);
2118 srrctl |= E1000_SRRCTL_DROP_EN;
2119
2120 /* disable queue 0 to prevent tail write w/o re-config */
2121 wr32(E1000_RXDCTL(0), 0);
2122
2123 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
2124 if (rctl & E1000_RCTL_LPE)
2125 vmolr |= E1000_VMOLR_LPE;
2126 if (adapter->num_rx_queues > 1)
2127 vmolr |= E1000_VMOLR_RSSE;
2128 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
2129 }
2130
2131 for (i = 0; i < adapter->num_rx_queues; i++) {
2132 int j = adapter->rx_ring[i].reg_idx;
2133 wr32(E1000_SRRCTL(j), srrctl);
2134 }
2135
2136 wr32(E1000_RCTL, rctl);
2137 }
2138
2139 /**
2140 * igb_rlpml_set - set maximum receive packet size
2141 * @adapter: board private structure
2142 *
2143 * Configure maximum receivable packet size.
2144 **/
2145 static void igb_rlpml_set(struct igb_adapter *adapter)
2146 {
2147 u32 max_frame_size = adapter->max_frame_size;
2148 struct e1000_hw *hw = &adapter->hw;
2149 u16 pf_id = adapter->vfs_allocated_count;
2150
2151 if (adapter->vlgrp)
2152 max_frame_size += VLAN_TAG_SIZE;
2153
2154 /* if vfs are enabled we set RLPML to the largest possible request
2155 * size and set the VMOLR RLPML to the size we need */
2156 if (pf_id) {
2157 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2158 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2159 }
2160
2161 wr32(E1000_RLPML, max_frame_size);
2162 }
2163
2164 /**
2165 * igb_configure_vt_default_pool - Configure VT default pool
2166 * @adapter: board private structure
2167 *
2168 * Configure the default pool
2169 **/
2170 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2171 {
2172 struct e1000_hw *hw = &adapter->hw;
2173 u16 pf_id = adapter->vfs_allocated_count;
2174 u32 vtctl;
2175
2176 /* not in sr-iov mode - do nothing */
2177 if (!pf_id)
2178 return;
2179
2180 vtctl = rd32(E1000_VT_CTL);
2181 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2182 E1000_VT_CTL_DISABLE_DEF_POOL);
2183 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2184 wr32(E1000_VT_CTL, vtctl);
2185 }
2186
2187 /**
2188 * igb_configure_rx - Configure receive Unit after Reset
2189 * @adapter: board private structure
2190 *
2191 * Configure the Rx unit of the MAC after a reset.
2192 **/
2193 static void igb_configure_rx(struct igb_adapter *adapter)
2194 {
2195 u64 rdba;
2196 struct e1000_hw *hw = &adapter->hw;
2197 u32 rctl, rxcsum;
2198 u32 rxdctl;
2199 int i;
2200
2201 /* disable receives while setting up the descriptors */
2202 rctl = rd32(E1000_RCTL);
2203 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2204 wrfl();
2205 mdelay(10);
2206
2207 if (adapter->itr_setting > 3)
2208 wr32(E1000_ITR, adapter->itr);
2209
2210 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2211 * the Base and Length of the Rx Descriptor Ring */
2212 for (i = 0; i < adapter->num_rx_queues; i++) {
2213 struct igb_ring *ring = &adapter->rx_ring[i];
2214 int j = ring->reg_idx;
2215 rdba = ring->dma;
2216 wr32(E1000_RDBAL(j),
2217 rdba & 0x00000000ffffffffULL);
2218 wr32(E1000_RDBAH(j), rdba >> 32);
2219 wr32(E1000_RDLEN(j),
2220 ring->count * sizeof(union e1000_adv_rx_desc));
2221
2222 ring->head = E1000_RDH(j);
2223 ring->tail = E1000_RDT(j);
2224 writel(0, hw->hw_addr + ring->tail);
2225 writel(0, hw->hw_addr + ring->head);
2226
2227 rxdctl = rd32(E1000_RXDCTL(j));
2228 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2229 rxdctl &= 0xFFF00000;
2230 rxdctl |= IGB_RX_PTHRESH;
2231 rxdctl |= IGB_RX_HTHRESH << 8;
2232 rxdctl |= IGB_RX_WTHRESH << 16;
2233 wr32(E1000_RXDCTL(j), rxdctl);
2234 }
2235
2236 if (adapter->num_rx_queues > 1) {
2237 u32 random[10];
2238 u32 mrqc;
2239 u32 j, shift;
2240 union e1000_reta {
2241 u32 dword;
2242 u8 bytes[4];
2243 } reta;
2244
2245 get_random_bytes(&random[0], 40);
2246
2247 if (hw->mac.type >= e1000_82576)
2248 shift = 0;
2249 else
2250 shift = 6;
2251 for (j = 0; j < (32 * 4); j++) {
2252 reta.bytes[j & 3] =
2253 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2254 if ((j & 3) == 3)
2255 writel(reta.dword,
2256 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2257 }
2258 if (adapter->vfs_allocated_count)
2259 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2260 else
2261 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2262
2263 /* Fill out hash function seeds */
2264 for (j = 0; j < 10; j++)
2265 array_wr32(E1000_RSSRK(0), j, random[j]);
2266
2267 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2268 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2269 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2270 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2271 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2272 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2273 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2274 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2275
2276 wr32(E1000_MRQC, mrqc);
2277 } else if (adapter->vfs_allocated_count) {
2278 /* Enable multi-queue for sr-iov */
2279 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2280 }
2281
2282 /* Enable Receive Checksum Offload for TCP and UDP */
2283 rxcsum = rd32(E1000_RXCSUM);
2284 /* Disable raw packet checksumming */
2285 rxcsum |= E1000_RXCSUM_PCSD;
2286
2287 if (adapter->hw.mac.type == e1000_82576)
2288 /* Enable Receive Checksum Offload for SCTP */
2289 rxcsum |= E1000_RXCSUM_CRCOFL;
2290
2291 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2292 wr32(E1000_RXCSUM, rxcsum);
2293
2294 /* Set the default pool for the PF's first queue */
2295 igb_configure_vt_default_pool(adapter);
2296
2297 igb_rlpml_set(adapter);
2298
2299 /* Enable Receives */
2300 wr32(E1000_RCTL, rctl);
2301 }
2302
2303 /**
2304 * igb_free_tx_resources - Free Tx Resources per Queue
2305 * @tx_ring: Tx descriptor ring for a specific queue
2306 *
2307 * Free all transmit software resources
2308 **/
2309 void igb_free_tx_resources(struct igb_ring *tx_ring)
2310 {
2311 struct pci_dev *pdev = tx_ring->adapter->pdev;
2312
2313 igb_clean_tx_ring(tx_ring);
2314
2315 vfree(tx_ring->buffer_info);
2316 tx_ring->buffer_info = NULL;
2317
2318 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2319
2320 tx_ring->desc = NULL;
2321 }
2322
2323 /**
2324 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2325 * @adapter: board private structure
2326 *
2327 * Free all transmit software resources
2328 **/
2329 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2330 {
2331 int i;
2332
2333 for (i = 0; i < adapter->num_tx_queues; i++)
2334 igb_free_tx_resources(&adapter->tx_ring[i]);
2335 }
2336
2337 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2338 struct igb_buffer *buffer_info)
2339 {
2340 buffer_info->dma = 0;
2341 if (buffer_info->skb) {
2342 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2343 DMA_TO_DEVICE);
2344 dev_kfree_skb_any(buffer_info->skb);
2345 buffer_info->skb = NULL;
2346 }
2347 buffer_info->time_stamp = 0;
2348 /* buffer_info must be completely set up in the transmit path */
2349 }
2350
2351 /**
2352 * igb_clean_tx_ring - Free Tx Buffers
2353 * @tx_ring: ring to be cleaned
2354 **/
2355 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2356 {
2357 struct igb_adapter *adapter = tx_ring->adapter;
2358 struct igb_buffer *buffer_info;
2359 unsigned long size;
2360 unsigned int i;
2361
2362 if (!tx_ring->buffer_info)
2363 return;
2364 /* Free all the Tx ring sk_buffs */
2365
2366 for (i = 0; i < tx_ring->count; i++) {
2367 buffer_info = &tx_ring->buffer_info[i];
2368 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2369 }
2370
2371 size = sizeof(struct igb_buffer) * tx_ring->count;
2372 memset(tx_ring->buffer_info, 0, size);
2373
2374 /* Zero out the descriptor ring */
2375
2376 memset(tx_ring->desc, 0, tx_ring->size);
2377
2378 tx_ring->next_to_use = 0;
2379 tx_ring->next_to_clean = 0;
2380
2381 writel(0, adapter->hw.hw_addr + tx_ring->head);
2382 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2383 }
2384
2385 /**
2386 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2387 * @adapter: board private structure
2388 **/
2389 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2390 {
2391 int i;
2392
2393 for (i = 0; i < adapter->num_tx_queues; i++)
2394 igb_clean_tx_ring(&adapter->tx_ring[i]);
2395 }
2396
2397 /**
2398 * igb_free_rx_resources - Free Rx Resources
2399 * @rx_ring: ring to clean the resources from
2400 *
2401 * Free all receive software resources
2402 **/
2403 void igb_free_rx_resources(struct igb_ring *rx_ring)
2404 {
2405 struct pci_dev *pdev = rx_ring->adapter->pdev;
2406
2407 igb_clean_rx_ring(rx_ring);
2408
2409 vfree(rx_ring->buffer_info);
2410 rx_ring->buffer_info = NULL;
2411
2412 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2413
2414 rx_ring->desc = NULL;
2415 }
2416
2417 /**
2418 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2419 * @adapter: board private structure
2420 *
2421 * Free all receive software resources
2422 **/
2423 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2424 {
2425 int i;
2426
2427 for (i = 0; i < adapter->num_rx_queues; i++)
2428 igb_free_rx_resources(&adapter->rx_ring[i]);
2429 }
2430
2431 /**
2432 * igb_clean_rx_ring - Free Rx Buffers per Queue
2433 * @rx_ring: ring to free buffers from
2434 **/
2435 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2436 {
2437 struct igb_adapter *adapter = rx_ring->adapter;
2438 struct igb_buffer *buffer_info;
2439 struct pci_dev *pdev = adapter->pdev;
2440 unsigned long size;
2441 unsigned int i;
2442
2443 if (!rx_ring->buffer_info)
2444 return;
2445 /* Free all the Rx ring sk_buffs */
2446 for (i = 0; i < rx_ring->count; i++) {
2447 buffer_info = &rx_ring->buffer_info[i];
2448 if (buffer_info->dma) {
2449 if (adapter->rx_ps_hdr_size)
2450 pci_unmap_single(pdev, buffer_info->dma,
2451 adapter->rx_ps_hdr_size,
2452 PCI_DMA_FROMDEVICE);
2453 else
2454 pci_unmap_single(pdev, buffer_info->dma,
2455 adapter->rx_buffer_len,
2456 PCI_DMA_FROMDEVICE);
2457 buffer_info->dma = 0;
2458 }
2459
2460 if (buffer_info->skb) {
2461 dev_kfree_skb(buffer_info->skb);
2462 buffer_info->skb = NULL;
2463 }
2464 if (buffer_info->page) {
2465 if (buffer_info->page_dma)
2466 pci_unmap_page(pdev, buffer_info->page_dma,
2467 PAGE_SIZE / 2,
2468 PCI_DMA_FROMDEVICE);
2469 put_page(buffer_info->page);
2470 buffer_info->page = NULL;
2471 buffer_info->page_dma = 0;
2472 buffer_info->page_offset = 0;
2473 }
2474 }
2475
2476 size = sizeof(struct igb_buffer) * rx_ring->count;
2477 memset(rx_ring->buffer_info, 0, size);
2478
2479 /* Zero out the descriptor ring */
2480 memset(rx_ring->desc, 0, rx_ring->size);
2481
2482 rx_ring->next_to_clean = 0;
2483 rx_ring->next_to_use = 0;
2484
2485 writel(0, adapter->hw.hw_addr + rx_ring->head);
2486 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2487 }
2488
2489 /**
2490 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2491 * @adapter: board private structure
2492 **/
2493 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2494 {
2495 int i;
2496
2497 for (i = 0; i < adapter->num_rx_queues; i++)
2498 igb_clean_rx_ring(&adapter->rx_ring[i]);
2499 }
2500
2501 /**
2502 * igb_set_mac - Change the Ethernet Address of the NIC
2503 * @netdev: network interface device structure
2504 * @p: pointer to an address structure
2505 *
2506 * Returns 0 on success, negative on failure
2507 **/
2508 static int igb_set_mac(struct net_device *netdev, void *p)
2509 {
2510 struct igb_adapter *adapter = netdev_priv(netdev);
2511 struct e1000_hw *hw = &adapter->hw;
2512 struct sockaddr *addr = p;
2513
2514 if (!is_valid_ether_addr(addr->sa_data))
2515 return -EADDRNOTAVAIL;
2516
2517 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2518 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2519
2520 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2521
2522 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2523
2524 return 0;
2525 }
2526
2527 /**
2528 * igb_set_multi - Multicast and Promiscuous mode set
2529 * @netdev: network interface device structure
2530 *
2531 * The set_multi entry point is called whenever the multicast address
2532 * list or the network interface flags are updated. This routine is
2533 * responsible for configuring the hardware for proper multicast,
2534 * promiscuous mode, and all-multi behavior.
2535 **/
2536 static void igb_set_multi(struct net_device *netdev)
2537 {
2538 struct igb_adapter *adapter = netdev_priv(netdev);
2539 struct e1000_hw *hw = &adapter->hw;
2540 struct dev_mc_list *mc_ptr;
2541 u8 *mta_list = NULL;
2542 u32 rctl;
2543 int i;
2544
2545 /* Check for Promiscuous and All Multicast modes */
2546
2547 rctl = rd32(E1000_RCTL);
2548
2549 if (netdev->flags & IFF_PROMISC) {
2550 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2551 rctl &= ~E1000_RCTL_VFE;
2552 } else {
2553 if (netdev->flags & IFF_ALLMULTI) {
2554 rctl |= E1000_RCTL_MPE;
2555 rctl &= ~E1000_RCTL_UPE;
2556 } else
2557 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2558 rctl |= E1000_RCTL_VFE;
2559 }
2560 wr32(E1000_RCTL, rctl);
2561
2562 if (!netdev->mc_count) {
2563 /* nothing to program, so clear mc list */
2564 igb_update_mc_addr_list(hw, NULL, 0);
2565 igb_restore_vf_multicasts(adapter);
2566 return;
2567 }
2568
2569 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2570 if (!mta_list) {
2571 dev_err(&adapter->pdev->dev,
2572 "failed to allocate multicast filter list\n");
2573 return;
2574 }
2575
2576 /* The shared function expects a packed array of only addresses. */
2577 mc_ptr = netdev->mc_list;
2578
2579 for (i = 0; i < netdev->mc_count; i++) {
2580 if (!mc_ptr)
2581 break;
2582 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2583 mc_ptr = mc_ptr->next;
2584 }
2585 igb_update_mc_addr_list(hw, mta_list, i);
2586 kfree(mta_list);
2587 igb_restore_vf_multicasts(adapter);
2588 }
2589
2590 /* Need to wait a few seconds after link up to get diagnostic information from
2591 * the phy */
2592 static void igb_update_phy_info(unsigned long data)
2593 {
2594 struct igb_adapter *adapter = (struct igb_adapter *) data;
2595 igb_get_phy_info(&adapter->hw);
2596 }
2597
2598 /**
2599 * igb_has_link - check shared code for link and determine up/down
2600 * @adapter: pointer to driver private info
2601 **/
2602 static bool igb_has_link(struct igb_adapter *adapter)
2603 {
2604 struct e1000_hw *hw = &adapter->hw;
2605 bool link_active = false;
2606 s32 ret_val = 0;
2607
2608 /* get_link_status is set on LSC (link status) interrupt or
2609 * rx sequence error interrupt. get_link_status will stay
2610 * false until the e1000_check_for_link establishes link
2611 * for copper adapters ONLY
2612 */
2613 switch (hw->phy.media_type) {
2614 case e1000_media_type_copper:
2615 if (hw->mac.get_link_status) {
2616 ret_val = hw->mac.ops.check_for_link(hw);
2617 link_active = !hw->mac.get_link_status;
2618 } else {
2619 link_active = true;
2620 }
2621 break;
2622 case e1000_media_type_internal_serdes:
2623 ret_val = hw->mac.ops.check_for_link(hw);
2624 link_active = hw->mac.serdes_has_link;
2625 break;
2626 default:
2627 case e1000_media_type_unknown:
2628 break;
2629 }
2630
2631 return link_active;
2632 }
2633
2634 /**
2635 * igb_watchdog - Timer Call-back
2636 * @data: pointer to adapter cast into an unsigned long
2637 **/
2638 static void igb_watchdog(unsigned long data)
2639 {
2640 struct igb_adapter *adapter = (struct igb_adapter *)data;
2641 /* Do the rest outside of interrupt context */
2642 schedule_work(&adapter->watchdog_task);
2643 }
2644
2645 static void igb_watchdog_task(struct work_struct *work)
2646 {
2647 struct igb_adapter *adapter = container_of(work,
2648 struct igb_adapter, watchdog_task);
2649 struct e1000_hw *hw = &adapter->hw;
2650 struct net_device *netdev = adapter->netdev;
2651 struct igb_ring *tx_ring = adapter->tx_ring;
2652 u32 link;
2653 u32 eics = 0;
2654 int i;
2655
2656 link = igb_has_link(adapter);
2657 if ((netif_carrier_ok(netdev)) && link)
2658 goto link_up;
2659
2660 if (link) {
2661 if (!netif_carrier_ok(netdev)) {
2662 u32 ctrl;
2663 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2664 &adapter->link_speed,
2665 &adapter->link_duplex);
2666
2667 ctrl = rd32(E1000_CTRL);
2668 /* Links status message must follow this format */
2669 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2670 "Flow Control: %s\n",
2671 netdev->name,
2672 adapter->link_speed,
2673 adapter->link_duplex == FULL_DUPLEX ?
2674 "Full Duplex" : "Half Duplex",
2675 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2676 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2677 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2678 E1000_CTRL_TFCE) ? "TX" : "None")));
2679
2680 /* tweak tx_queue_len according to speed/duplex and
2681 * adjust the timeout factor */
2682 netdev->tx_queue_len = adapter->tx_queue_len;
2683 adapter->tx_timeout_factor = 1;
2684 switch (adapter->link_speed) {
2685 case SPEED_10:
2686 netdev->tx_queue_len = 10;
2687 adapter->tx_timeout_factor = 14;
2688 break;
2689 case SPEED_100:
2690 netdev->tx_queue_len = 100;
2691 /* maybe add some timeout factor ? */
2692 break;
2693 }
2694
2695 netif_carrier_on(netdev);
2696
2697 igb_ping_all_vfs(adapter);
2698
2699 /* link state has changed, schedule phy info update */
2700 if (!test_bit(__IGB_DOWN, &adapter->state))
2701 mod_timer(&adapter->phy_info_timer,
2702 round_jiffies(jiffies + 2 * HZ));
2703 }
2704 } else {
2705 if (netif_carrier_ok(netdev)) {
2706 adapter->link_speed = 0;
2707 adapter->link_duplex = 0;
2708 /* Links status message must follow this format */
2709 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2710 netdev->name);
2711 netif_carrier_off(netdev);
2712
2713 igb_ping_all_vfs(adapter);
2714
2715 /* link state has changed, schedule phy info update */
2716 if (!test_bit(__IGB_DOWN, &adapter->state))
2717 mod_timer(&adapter->phy_info_timer,
2718 round_jiffies(jiffies + 2 * HZ));
2719 }
2720 }
2721
2722 link_up:
2723 igb_update_stats(adapter);
2724
2725 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2726 adapter->tpt_old = adapter->stats.tpt;
2727 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2728 adapter->colc_old = adapter->stats.colc;
2729
2730 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2731 adapter->gorc_old = adapter->stats.gorc;
2732 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2733 adapter->gotc_old = adapter->stats.gotc;
2734
2735 igb_update_adaptive(&adapter->hw);
2736
2737 if (!netif_carrier_ok(netdev)) {
2738 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
2739 /* We've lost link, so the controller stops DMA,
2740 * but we've got queued Tx work that's never going
2741 * to get done, so reset controller to flush Tx.
2742 * (Do the reset outside of interrupt context). */
2743 adapter->tx_timeout_count++;
2744 schedule_work(&adapter->reset_task);
2745 /* return immediately since reset is imminent */
2746 return;
2747 }
2748 }
2749
2750 /* Cause software interrupt to ensure rx ring is cleaned */
2751 if (adapter->msix_entries) {
2752 for (i = 0; i < adapter->num_rx_queues; i++)
2753 eics |= adapter->rx_ring[i].eims_value;
2754 wr32(E1000_EICS, eics);
2755 } else {
2756 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2757 }
2758
2759 /* Force detection of hung controller every watchdog period */
2760 tx_ring->detect_tx_hung = true;
2761
2762 /* Reset the timer */
2763 if (!test_bit(__IGB_DOWN, &adapter->state))
2764 mod_timer(&adapter->watchdog_timer,
2765 round_jiffies(jiffies + 2 * HZ));
2766 }
2767
2768 enum latency_range {
2769 lowest_latency = 0,
2770 low_latency = 1,
2771 bulk_latency = 2,
2772 latency_invalid = 255
2773 };
2774
2775
2776 /**
2777 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2778 *
2779 * Stores a new ITR value based on strictly on packet size. This
2780 * algorithm is less sophisticated than that used in igb_update_itr,
2781 * due to the difficulty of synchronizing statistics across multiple
2782 * receive rings. The divisors and thresholds used by this fuction
2783 * were determined based on theoretical maximum wire speed and testing
2784 * data, in order to minimize response time while increasing bulk
2785 * throughput.
2786 * This functionality is controlled by the InterruptThrottleRate module
2787 * parameter (see igb_param.c)
2788 * NOTE: This function is called only when operating in a multiqueue
2789 * receive environment.
2790 * @rx_ring: pointer to ring
2791 **/
2792 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2793 {
2794 int new_val = rx_ring->itr_val;
2795 int avg_wire_size = 0;
2796 struct igb_adapter *adapter = rx_ring->adapter;
2797
2798 if (!rx_ring->total_packets)
2799 goto clear_counts; /* no packets, so don't do anything */
2800
2801 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2802 * ints/sec - ITR timer value of 120 ticks.
2803 */
2804 if (adapter->link_speed != SPEED_1000) {
2805 new_val = 120;
2806 goto set_itr_val;
2807 }
2808 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2809
2810 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2811 avg_wire_size += 24;
2812
2813 /* Don't starve jumbo frames */
2814 avg_wire_size = min(avg_wire_size, 3000);
2815
2816 /* Give a little boost to mid-size frames */
2817 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2818 new_val = avg_wire_size / 3;
2819 else
2820 new_val = avg_wire_size / 2;
2821
2822 set_itr_val:
2823 if (new_val != rx_ring->itr_val) {
2824 rx_ring->itr_val = new_val;
2825 rx_ring->set_itr = 1;
2826 }
2827 clear_counts:
2828 rx_ring->total_bytes = 0;
2829 rx_ring->total_packets = 0;
2830 }
2831
2832 /**
2833 * igb_update_itr - update the dynamic ITR value based on statistics
2834 * Stores a new ITR value based on packets and byte
2835 * counts during the last interrupt. The advantage of per interrupt
2836 * computation is faster updates and more accurate ITR for the current
2837 * traffic pattern. Constants in this function were computed
2838 * based on theoretical maximum wire speed and thresholds were set based
2839 * on testing data as well as attempting to minimize response time
2840 * while increasing bulk throughput.
2841 * this functionality is controlled by the InterruptThrottleRate module
2842 * parameter (see igb_param.c)
2843 * NOTE: These calculations are only valid when operating in a single-
2844 * queue environment.
2845 * @adapter: pointer to adapter
2846 * @itr_setting: current adapter->itr
2847 * @packets: the number of packets during this measurement interval
2848 * @bytes: the number of bytes during this measurement interval
2849 **/
2850 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2851 int packets, int bytes)
2852 {
2853 unsigned int retval = itr_setting;
2854
2855 if (packets == 0)
2856 goto update_itr_done;
2857
2858 switch (itr_setting) {
2859 case lowest_latency:
2860 /* handle TSO and jumbo frames */
2861 if (bytes/packets > 8000)
2862 retval = bulk_latency;
2863 else if ((packets < 5) && (bytes > 512))
2864 retval = low_latency;
2865 break;
2866 case low_latency: /* 50 usec aka 20000 ints/s */
2867 if (bytes > 10000) {
2868 /* this if handles the TSO accounting */
2869 if (bytes/packets > 8000) {
2870 retval = bulk_latency;
2871 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2872 retval = bulk_latency;
2873 } else if ((packets > 35)) {
2874 retval = lowest_latency;
2875 }
2876 } else if (bytes/packets > 2000) {
2877 retval = bulk_latency;
2878 } else if (packets <= 2 && bytes < 512) {
2879 retval = lowest_latency;
2880 }
2881 break;
2882 case bulk_latency: /* 250 usec aka 4000 ints/s */
2883 if (bytes > 25000) {
2884 if (packets > 35)
2885 retval = low_latency;
2886 } else if (bytes < 1500) {
2887 retval = low_latency;
2888 }
2889 break;
2890 }
2891
2892 update_itr_done:
2893 return retval;
2894 }
2895
2896 static void igb_set_itr(struct igb_adapter *adapter)
2897 {
2898 u16 current_itr;
2899 u32 new_itr = adapter->itr;
2900
2901 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2902 if (adapter->link_speed != SPEED_1000) {
2903 current_itr = 0;
2904 new_itr = 4000;
2905 goto set_itr_now;
2906 }
2907
2908 adapter->rx_itr = igb_update_itr(adapter,
2909 adapter->rx_itr,
2910 adapter->rx_ring->total_packets,
2911 adapter->rx_ring->total_bytes);
2912
2913 if (adapter->rx_ring->buddy) {
2914 adapter->tx_itr = igb_update_itr(adapter,
2915 adapter->tx_itr,
2916 adapter->tx_ring->total_packets,
2917 adapter->tx_ring->total_bytes);
2918 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2919 } else {
2920 current_itr = adapter->rx_itr;
2921 }
2922
2923 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2924 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2925 current_itr = low_latency;
2926
2927 switch (current_itr) {
2928 /* counts and packets in update_itr are dependent on these numbers */
2929 case lowest_latency:
2930 new_itr = 56; /* aka 70,000 ints/sec */
2931 break;
2932 case low_latency:
2933 new_itr = 196; /* aka 20,000 ints/sec */
2934 break;
2935 case bulk_latency:
2936 new_itr = 980; /* aka 4,000 ints/sec */
2937 break;
2938 default:
2939 break;
2940 }
2941
2942 set_itr_now:
2943 adapter->rx_ring->total_bytes = 0;
2944 adapter->rx_ring->total_packets = 0;
2945 if (adapter->rx_ring->buddy) {
2946 adapter->rx_ring->buddy->total_bytes = 0;
2947 adapter->rx_ring->buddy->total_packets = 0;
2948 }
2949
2950 if (new_itr != adapter->itr) {
2951 /* this attempts to bias the interrupt rate towards Bulk
2952 * by adding intermediate steps when interrupt rate is
2953 * increasing */
2954 new_itr = new_itr > adapter->itr ?
2955 max((new_itr * adapter->itr) /
2956 (new_itr + (adapter->itr >> 2)), new_itr) :
2957 new_itr;
2958 /* Don't write the value here; it resets the adapter's
2959 * internal timer, and causes us to delay far longer than
2960 * we should between interrupts. Instead, we write the ITR
2961 * value at the beginning of the next interrupt so the timing
2962 * ends up being correct.
2963 */
2964 adapter->itr = new_itr;
2965 adapter->rx_ring->itr_val = new_itr;
2966 adapter->rx_ring->set_itr = 1;
2967 }
2968
2969 return;
2970 }
2971
2972
2973 #define IGB_TX_FLAGS_CSUM 0x00000001
2974 #define IGB_TX_FLAGS_VLAN 0x00000002
2975 #define IGB_TX_FLAGS_TSO 0x00000004
2976 #define IGB_TX_FLAGS_IPV4 0x00000008
2977 #define IGB_TX_FLAGS_TSTAMP 0x00000010
2978 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2979 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2980
2981 static inline int igb_tso_adv(struct igb_adapter *adapter,
2982 struct igb_ring *tx_ring,
2983 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2984 {
2985 struct e1000_adv_tx_context_desc *context_desc;
2986 unsigned int i;
2987 int err;
2988 struct igb_buffer *buffer_info;
2989 u32 info = 0, tu_cmd = 0;
2990 u32 mss_l4len_idx, l4len;
2991 *hdr_len = 0;
2992
2993 if (skb_header_cloned(skb)) {
2994 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2995 if (err)
2996 return err;
2997 }
2998
2999 l4len = tcp_hdrlen(skb);
3000 *hdr_len += l4len;
3001
3002 if (skb->protocol == htons(ETH_P_IP)) {
3003 struct iphdr *iph = ip_hdr(skb);
3004 iph->tot_len = 0;
3005 iph->check = 0;
3006 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3007 iph->daddr, 0,
3008 IPPROTO_TCP,
3009 0);
3010 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3011 ipv6_hdr(skb)->payload_len = 0;
3012 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3013 &ipv6_hdr(skb)->daddr,
3014 0, IPPROTO_TCP, 0);
3015 }
3016
3017 i = tx_ring->next_to_use;
3018
3019 buffer_info = &tx_ring->buffer_info[i];
3020 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3021 /* VLAN MACLEN IPLEN */
3022 if (tx_flags & IGB_TX_FLAGS_VLAN)
3023 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3024 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3025 *hdr_len += skb_network_offset(skb);
3026 info |= skb_network_header_len(skb);
3027 *hdr_len += skb_network_header_len(skb);
3028 context_desc->vlan_macip_lens = cpu_to_le32(info);
3029
3030 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3031 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3032
3033 if (skb->protocol == htons(ETH_P_IP))
3034 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3035 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3036
3037 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3038
3039 /* MSS L4LEN IDX */
3040 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3041 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3042
3043 /* For 82575, context index must be unique per ring. */
3044 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3045 mss_l4len_idx |= tx_ring->queue_index << 4;
3046
3047 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3048 context_desc->seqnum_seed = 0;
3049
3050 buffer_info->time_stamp = jiffies;
3051 buffer_info->next_to_watch = i;
3052 buffer_info->dma = 0;
3053 i++;
3054 if (i == tx_ring->count)
3055 i = 0;
3056
3057 tx_ring->next_to_use = i;
3058
3059 return true;
3060 }
3061
3062 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3063 struct igb_ring *tx_ring,
3064 struct sk_buff *skb, u32 tx_flags)
3065 {
3066 struct e1000_adv_tx_context_desc *context_desc;
3067 unsigned int i;
3068 struct igb_buffer *buffer_info;
3069 u32 info = 0, tu_cmd = 0;
3070
3071 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3072 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3073 i = tx_ring->next_to_use;
3074 buffer_info = &tx_ring->buffer_info[i];
3075 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3076
3077 if (tx_flags & IGB_TX_FLAGS_VLAN)
3078 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3079 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3080 if (skb->ip_summed == CHECKSUM_PARTIAL)
3081 info |= skb_network_header_len(skb);
3082
3083 context_desc->vlan_macip_lens = cpu_to_le32(info);
3084
3085 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3086
3087 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3088 __be16 protocol;
3089
3090 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3091 const struct vlan_ethhdr *vhdr =
3092 (const struct vlan_ethhdr*)skb->data;
3093
3094 protocol = vhdr->h_vlan_encapsulated_proto;
3095 } else {
3096 protocol = skb->protocol;
3097 }
3098
3099 switch (protocol) {
3100 case cpu_to_be16(ETH_P_IP):
3101 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3102 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3103 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3104 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3105 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3106 break;
3107 case cpu_to_be16(ETH_P_IPV6):
3108 /* XXX what about other V6 headers?? */
3109 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3110 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3111 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3112 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3113 break;
3114 default:
3115 if (unlikely(net_ratelimit()))
3116 dev_warn(&adapter->pdev->dev,
3117 "partial checksum but proto=%x!\n",
3118 skb->protocol);
3119 break;
3120 }
3121 }
3122
3123 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3124 context_desc->seqnum_seed = 0;
3125 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3126 context_desc->mss_l4len_idx =
3127 cpu_to_le32(tx_ring->queue_index << 4);
3128 else
3129 context_desc->mss_l4len_idx = 0;
3130
3131 buffer_info->time_stamp = jiffies;
3132 buffer_info->next_to_watch = i;
3133 buffer_info->dma = 0;
3134
3135 i++;
3136 if (i == tx_ring->count)
3137 i = 0;
3138 tx_ring->next_to_use = i;
3139
3140 return true;
3141 }
3142 return false;
3143 }
3144
3145 #define IGB_MAX_TXD_PWR 16
3146 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3147
3148 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3149 struct igb_ring *tx_ring, struct sk_buff *skb,
3150 unsigned int first)
3151 {
3152 struct igb_buffer *buffer_info;
3153 unsigned int len = skb_headlen(skb);
3154 unsigned int count = 0, i;
3155 unsigned int f;
3156 dma_addr_t *map;
3157
3158 i = tx_ring->next_to_use;
3159
3160 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3161 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3162 return 0;
3163 }
3164
3165 map = skb_shinfo(skb)->dma_maps;
3166
3167 buffer_info = &tx_ring->buffer_info[i];
3168 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3169 buffer_info->length = len;
3170 /* set time_stamp *before* dma to help avoid a possible race */
3171 buffer_info->time_stamp = jiffies;
3172 buffer_info->next_to_watch = i;
3173 buffer_info->dma = skb_shinfo(skb)->dma_head;
3174
3175 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3176 struct skb_frag_struct *frag;
3177
3178 i++;
3179 if (i == tx_ring->count)
3180 i = 0;
3181
3182 frag = &skb_shinfo(skb)->frags[f];
3183 len = frag->size;
3184
3185 buffer_info = &tx_ring->buffer_info[i];
3186 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3187 buffer_info->length = len;
3188 buffer_info->time_stamp = jiffies;
3189 buffer_info->next_to_watch = i;
3190 buffer_info->dma = map[count];
3191 count++;
3192 }
3193
3194 tx_ring->buffer_info[i].skb = skb;
3195 tx_ring->buffer_info[first].next_to_watch = i;
3196
3197 return count + 1;
3198 }
3199
3200 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3201 struct igb_ring *tx_ring,
3202 int tx_flags, int count, u32 paylen,
3203 u8 hdr_len)
3204 {
3205 union e1000_adv_tx_desc *tx_desc = NULL;
3206 struct igb_buffer *buffer_info;
3207 u32 olinfo_status = 0, cmd_type_len;
3208 unsigned int i;
3209
3210 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3211 E1000_ADVTXD_DCMD_DEXT);
3212
3213 if (tx_flags & IGB_TX_FLAGS_VLAN)
3214 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3215
3216 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3217 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3218
3219 if (tx_flags & IGB_TX_FLAGS_TSO) {
3220 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3221
3222 /* insert tcp checksum */
3223 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3224
3225 /* insert ip checksum */
3226 if (tx_flags & IGB_TX_FLAGS_IPV4)
3227 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3228
3229 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3230 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3231 }
3232
3233 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3234 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3235 IGB_TX_FLAGS_VLAN)))
3236 olinfo_status |= tx_ring->queue_index << 4;
3237
3238 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3239
3240 i = tx_ring->next_to_use;
3241 while (count--) {
3242 buffer_info = &tx_ring->buffer_info[i];
3243 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3244 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3245 tx_desc->read.cmd_type_len =
3246 cpu_to_le32(cmd_type_len | buffer_info->length);
3247 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3248 i++;
3249 if (i == tx_ring->count)
3250 i = 0;
3251 }
3252
3253 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3254 /* Force memory writes to complete before letting h/w
3255 * know there are new descriptors to fetch. (Only
3256 * applicable for weak-ordered memory model archs,
3257 * such as IA-64). */
3258 wmb();
3259
3260 tx_ring->next_to_use = i;
3261 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3262 /* we need this if more than one processor can write to our tail
3263 * at a time, it syncronizes IO on IA64/Altix systems */
3264 mmiowb();
3265 }
3266
3267 static int __igb_maybe_stop_tx(struct net_device *netdev,
3268 struct igb_ring *tx_ring, int size)
3269 {
3270 struct igb_adapter *adapter = netdev_priv(netdev);
3271
3272 netif_stop_subqueue(netdev, tx_ring->queue_index);
3273
3274 /* Herbert's original patch had:
3275 * smp_mb__after_netif_stop_queue();
3276 * but since that doesn't exist yet, just open code it. */
3277 smp_mb();
3278
3279 /* We need to check again in a case another CPU has just
3280 * made room available. */
3281 if (igb_desc_unused(tx_ring) < size)
3282 return -EBUSY;
3283
3284 /* A reprieve! */
3285 netif_wake_subqueue(netdev, tx_ring->queue_index);
3286 ++adapter->restart_queue;
3287 return 0;
3288 }
3289
3290 static int igb_maybe_stop_tx(struct net_device *netdev,
3291 struct igb_ring *tx_ring, int size)
3292 {
3293 if (igb_desc_unused(tx_ring) >= size)
3294 return 0;
3295 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3296 }
3297
3298 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3299 struct net_device *netdev,
3300 struct igb_ring *tx_ring)
3301 {
3302 struct igb_adapter *adapter = netdev_priv(netdev);
3303 unsigned int first;
3304 unsigned int tx_flags = 0;
3305 u8 hdr_len = 0;
3306 int count = 0;
3307 int tso = 0;
3308 union skb_shared_tx *shtx;
3309
3310 if (test_bit(__IGB_DOWN, &adapter->state)) {
3311 dev_kfree_skb_any(skb);
3312 return NETDEV_TX_OK;
3313 }
3314
3315 if (skb->len <= 0) {
3316 dev_kfree_skb_any(skb);
3317 return NETDEV_TX_OK;
3318 }
3319
3320 /* need: 1 descriptor per page,
3321 * + 2 desc gap to keep tail from touching head,
3322 * + 1 desc for skb->data,
3323 * + 1 desc for context descriptor,
3324 * otherwise try next time */
3325 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3326 /* this is a hard error */
3327 return NETDEV_TX_BUSY;
3328 }
3329
3330 /*
3331 * TODO: check that there currently is no other packet with
3332 * time stamping in the queue
3333 *
3334 * When doing time stamping, keep the connection to the socket
3335 * a while longer: it is still needed by skb_hwtstamp_tx(),
3336 * called either in igb_tx_hwtstamp() or by our caller when
3337 * doing software time stamping.
3338 */
3339 shtx = skb_tx(skb);
3340 if (unlikely(shtx->hardware)) {
3341 shtx->in_progress = 1;
3342 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3343 }
3344
3345 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3346 tx_flags |= IGB_TX_FLAGS_VLAN;
3347 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3348 }
3349
3350 if (skb->protocol == htons(ETH_P_IP))
3351 tx_flags |= IGB_TX_FLAGS_IPV4;
3352
3353 first = tx_ring->next_to_use;
3354 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3355 &hdr_len) : 0;
3356
3357 if (tso < 0) {
3358 dev_kfree_skb_any(skb);
3359 return NETDEV_TX_OK;
3360 }
3361
3362 if (tso)
3363 tx_flags |= IGB_TX_FLAGS_TSO;
3364 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3365 (skb->ip_summed == CHECKSUM_PARTIAL))
3366 tx_flags |= IGB_TX_FLAGS_CSUM;
3367
3368 /*
3369 * count reflects descriptors mapped, if 0 then mapping error
3370 * has occured and we need to rewind the descriptor queue
3371 */
3372 count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3373
3374 if (count) {
3375 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3376 skb->len, hdr_len);
3377 /* Make sure there is space in the ring for the next send. */
3378 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3379 } else {
3380 dev_kfree_skb_any(skb);
3381 tx_ring->buffer_info[first].time_stamp = 0;
3382 tx_ring->next_to_use = first;
3383 }
3384
3385 return NETDEV_TX_OK;
3386 }
3387
3388 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3389 {
3390 struct igb_adapter *adapter = netdev_priv(netdev);
3391 struct igb_ring *tx_ring;
3392
3393 int r_idx = 0;
3394 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3395 tx_ring = adapter->multi_tx_table[r_idx];
3396
3397 /* This goes back to the question of how to logically map a tx queue
3398 * to a flow. Right now, performance is impacted slightly negatively
3399 * if using multiple tx queues. If the stack breaks away from a
3400 * single qdisc implementation, we can look at this again. */
3401 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3402 }
3403
3404 /**
3405 * igb_tx_timeout - Respond to a Tx Hang
3406 * @netdev: network interface device structure
3407 **/
3408 static void igb_tx_timeout(struct net_device *netdev)
3409 {
3410 struct igb_adapter *adapter = netdev_priv(netdev);
3411 struct e1000_hw *hw = &adapter->hw;
3412
3413 /* Do the reset outside of interrupt context */
3414 adapter->tx_timeout_count++;
3415 schedule_work(&adapter->reset_task);
3416 wr32(E1000_EICS,
3417 (adapter->eims_enable_mask & ~adapter->eims_other));
3418 }
3419
3420 static void igb_reset_task(struct work_struct *work)
3421 {
3422 struct igb_adapter *adapter;
3423 adapter = container_of(work, struct igb_adapter, reset_task);
3424
3425 igb_reinit_locked(adapter);
3426 }
3427
3428 /**
3429 * igb_get_stats - Get System Network Statistics
3430 * @netdev: network interface device structure
3431 *
3432 * Returns the address of the device statistics structure.
3433 * The statistics are actually updated from the timer callback.
3434 **/
3435 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3436 {
3437 struct igb_adapter *adapter = netdev_priv(netdev);
3438
3439 /* only return the current stats */
3440 return &adapter->net_stats;
3441 }
3442
3443 /**
3444 * igb_change_mtu - Change the Maximum Transfer Unit
3445 * @netdev: network interface device structure
3446 * @new_mtu: new value for maximum frame size
3447 *
3448 * Returns 0 on success, negative on failure
3449 **/
3450 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3451 {
3452 struct igb_adapter *adapter = netdev_priv(netdev);
3453 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3454
3455 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3456 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3457 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3458 return -EINVAL;
3459 }
3460
3461 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3462 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3463 return -EINVAL;
3464 }
3465
3466 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3467 msleep(1);
3468
3469 /* igb_down has a dependency on max_frame_size */
3470 adapter->max_frame_size = max_frame;
3471 if (netif_running(netdev))
3472 igb_down(adapter);
3473
3474 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3475 * means we reserve 2 more, this pushes us to allocate from the next
3476 * larger slab size.
3477 * i.e. RXBUFFER_2048 --> size-4096 slab
3478 */
3479
3480 if (max_frame <= IGB_RXBUFFER_256)
3481 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3482 else if (max_frame <= IGB_RXBUFFER_512)
3483 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3484 else if (max_frame <= IGB_RXBUFFER_1024)
3485 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3486 else if (max_frame <= IGB_RXBUFFER_2048)
3487 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3488 else
3489 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3490 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3491 #else
3492 adapter->rx_buffer_len = PAGE_SIZE / 2;
3493 #endif
3494
3495 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3496 if (adapter->vfs_allocated_count &&
3497 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3498 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3499
3500 /* adjust allocation if LPE protects us, and we aren't using SBP */
3501 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3502 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3503 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3504
3505 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3506 netdev->mtu, new_mtu);
3507 netdev->mtu = new_mtu;
3508
3509 if (netif_running(netdev))
3510 igb_up(adapter);
3511 else
3512 igb_reset(adapter);
3513
3514 clear_bit(__IGB_RESETTING, &adapter->state);
3515
3516 return 0;
3517 }
3518
3519 /**
3520 * igb_update_stats - Update the board statistics counters
3521 * @adapter: board private structure
3522 **/
3523
3524 void igb_update_stats(struct igb_adapter *adapter)
3525 {
3526 struct e1000_hw *hw = &adapter->hw;
3527 struct pci_dev *pdev = adapter->pdev;
3528 u16 phy_tmp;
3529
3530 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3531
3532 /*
3533 * Prevent stats update while adapter is being reset, or if the pci
3534 * connection is down.
3535 */
3536 if (adapter->link_speed == 0)
3537 return;
3538 if (pci_channel_offline(pdev))
3539 return;
3540
3541 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3542 adapter->stats.gprc += rd32(E1000_GPRC);
3543 adapter->stats.gorc += rd32(E1000_GORCL);
3544 rd32(E1000_GORCH); /* clear GORCL */
3545 adapter->stats.bprc += rd32(E1000_BPRC);
3546 adapter->stats.mprc += rd32(E1000_MPRC);
3547 adapter->stats.roc += rd32(E1000_ROC);
3548
3549 adapter->stats.prc64 += rd32(E1000_PRC64);
3550 adapter->stats.prc127 += rd32(E1000_PRC127);
3551 adapter->stats.prc255 += rd32(E1000_PRC255);
3552 adapter->stats.prc511 += rd32(E1000_PRC511);
3553 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3554 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3555 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3556 adapter->stats.sec += rd32(E1000_SEC);
3557
3558 adapter->stats.mpc += rd32(E1000_MPC);
3559 adapter->stats.scc += rd32(E1000_SCC);
3560 adapter->stats.ecol += rd32(E1000_ECOL);
3561 adapter->stats.mcc += rd32(E1000_MCC);
3562 adapter->stats.latecol += rd32(E1000_LATECOL);
3563 adapter->stats.dc += rd32(E1000_DC);
3564 adapter->stats.rlec += rd32(E1000_RLEC);
3565 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3566 adapter->stats.xontxc += rd32(E1000_XONTXC);
3567 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3568 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3569 adapter->stats.fcruc += rd32(E1000_FCRUC);
3570 adapter->stats.gptc += rd32(E1000_GPTC);
3571 adapter->stats.gotc += rd32(E1000_GOTCL);
3572 rd32(E1000_GOTCH); /* clear GOTCL */
3573 adapter->stats.rnbc += rd32(E1000_RNBC);
3574 adapter->stats.ruc += rd32(E1000_RUC);
3575 adapter->stats.rfc += rd32(E1000_RFC);
3576 adapter->stats.rjc += rd32(E1000_RJC);
3577 adapter->stats.tor += rd32(E1000_TORH);
3578 adapter->stats.tot += rd32(E1000_TOTH);
3579 adapter->stats.tpr += rd32(E1000_TPR);
3580
3581 adapter->stats.ptc64 += rd32(E1000_PTC64);
3582 adapter->stats.ptc127 += rd32(E1000_PTC127);
3583 adapter->stats.ptc255 += rd32(E1000_PTC255);
3584 adapter->stats.ptc511 += rd32(E1000_PTC511);
3585 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3586 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3587
3588 adapter->stats.mptc += rd32(E1000_MPTC);
3589 adapter->stats.bptc += rd32(E1000_BPTC);
3590
3591 /* used for adaptive IFS */
3592
3593 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3594 adapter->stats.tpt += hw->mac.tx_packet_delta;
3595 hw->mac.collision_delta = rd32(E1000_COLC);
3596 adapter->stats.colc += hw->mac.collision_delta;
3597
3598 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3599 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3600 adapter->stats.tncrs += rd32(E1000_TNCRS);
3601 adapter->stats.tsctc += rd32(E1000_TSCTC);
3602 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3603
3604 adapter->stats.iac += rd32(E1000_IAC);
3605 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3606 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3607 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3608 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3609 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3610 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3611 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3612 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3613
3614 /* Fill out the OS statistics structure */
3615 adapter->net_stats.multicast = adapter->stats.mprc;
3616 adapter->net_stats.collisions = adapter->stats.colc;
3617
3618 /* Rx Errors */
3619
3620 if (hw->mac.type != e1000_82575) {
3621 u32 rqdpc_tmp;
3622 u64 rqdpc_total = 0;
3623 int i;
3624 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3625 * Queue Drop Packet Count) stats only gets incremented, if
3626 * the DROP_EN but it set (in the SRRCTL register for that
3627 * queue). If DROP_EN bit is NOT set, then the some what
3628 * equivalent count is stored in RNBC (not per queue basis).
3629 * Also note the drop count is due to lack of available
3630 * descriptors.
3631 */
3632 for (i = 0; i < adapter->num_rx_queues; i++) {
3633 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3634 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3635 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
3636 }
3637 adapter->net_stats.rx_fifo_errors = rqdpc_total;
3638 }
3639
3640 /* Note RNBC (Receive No Buffers Count) is an not an exact
3641 * drop count as the hardware FIFO might save the day. Thats
3642 * one of the reason for saving it in rx_fifo_errors, as its
3643 * potentially not a true drop.
3644 */
3645 adapter->net_stats.rx_fifo_errors += adapter->stats.rnbc;
3646
3647 /* RLEC on some newer hardware can be incorrect so build
3648 * our own version based on RUC and ROC */
3649 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3650 adapter->stats.crcerrs + adapter->stats.algnerrc +
3651 adapter->stats.ruc + adapter->stats.roc +
3652 adapter->stats.cexterr;
3653 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3654 adapter->stats.roc;
3655 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3656 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3657 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3658
3659 /* Tx Errors */
3660 adapter->net_stats.tx_errors = adapter->stats.ecol +
3661 adapter->stats.latecol;
3662 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3663 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3664 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3665
3666 /* Tx Dropped needs to be maintained elsewhere */
3667
3668 /* Phy Stats */
3669 if (hw->phy.media_type == e1000_media_type_copper) {
3670 if ((adapter->link_speed == SPEED_1000) &&
3671 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3672 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3673 adapter->phy_stats.idle_errors += phy_tmp;
3674 }
3675 }
3676
3677 /* Management Stats */
3678 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3679 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3680 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3681 }
3682
3683 static irqreturn_t igb_msix_other(int irq, void *data)
3684 {
3685 struct net_device *netdev = data;
3686 struct igb_adapter *adapter = netdev_priv(netdev);
3687 struct e1000_hw *hw = &adapter->hw;
3688 u32 icr = rd32(E1000_ICR);
3689
3690 /* reading ICR causes bit 31 of EICR to be cleared */
3691
3692 if(icr & E1000_ICR_DOUTSYNC) {
3693 /* HW is reporting DMA is out of sync */
3694 adapter->stats.doosync++;
3695 }
3696
3697 /* Check for a mailbox event */
3698 if (icr & E1000_ICR_VMMB)
3699 igb_msg_task(adapter);
3700
3701 if (icr & E1000_ICR_LSC) {
3702 hw->mac.get_link_status = 1;
3703 /* guard against interrupt when we're going down */
3704 if (!test_bit(__IGB_DOWN, &adapter->state))
3705 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3706 }
3707
3708 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3709 wr32(E1000_EIMS, adapter->eims_other);
3710
3711 return IRQ_HANDLED;
3712 }
3713
3714 static irqreturn_t igb_msix_tx(int irq, void *data)
3715 {
3716 struct igb_ring *tx_ring = data;
3717 struct igb_adapter *adapter = tx_ring->adapter;
3718 struct e1000_hw *hw = &adapter->hw;
3719
3720 #ifdef CONFIG_IGB_DCA
3721 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3722 igb_update_tx_dca(tx_ring);
3723 #endif
3724
3725 tx_ring->total_bytes = 0;
3726 tx_ring->total_packets = 0;
3727
3728 /* auto mask will automatically reenable the interrupt when we write
3729 * EICS */
3730 if (!igb_clean_tx_irq(tx_ring))
3731 /* Ring was not completely cleaned, so fire another interrupt */
3732 wr32(E1000_EICS, tx_ring->eims_value);
3733 else
3734 wr32(E1000_EIMS, tx_ring->eims_value);
3735
3736 return IRQ_HANDLED;
3737 }
3738
3739 static void igb_write_itr(struct igb_ring *ring)
3740 {
3741 struct e1000_hw *hw = &ring->adapter->hw;
3742 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3743 switch (hw->mac.type) {
3744 case e1000_82576:
3745 wr32(ring->itr_register, ring->itr_val |
3746 0x80000000);
3747 break;
3748 default:
3749 wr32(ring->itr_register, ring->itr_val |
3750 (ring->itr_val << 16));
3751 break;
3752 }
3753 ring->set_itr = 0;
3754 }
3755 }
3756
3757 static irqreturn_t igb_msix_rx(int irq, void *data)
3758 {
3759 struct igb_ring *rx_ring = data;
3760
3761 /* Write the ITR value calculated at the end of the
3762 * previous interrupt.
3763 */
3764
3765 igb_write_itr(rx_ring);
3766
3767 if (napi_schedule_prep(&rx_ring->napi))
3768 __napi_schedule(&rx_ring->napi);
3769
3770 #ifdef CONFIG_IGB_DCA
3771 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3772 igb_update_rx_dca(rx_ring);
3773 #endif
3774 return IRQ_HANDLED;
3775 }
3776
3777 #ifdef CONFIG_IGB_DCA
3778 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3779 {
3780 u32 dca_rxctrl;
3781 struct igb_adapter *adapter = rx_ring->adapter;
3782 struct e1000_hw *hw = &adapter->hw;
3783 int cpu = get_cpu();
3784 int q = rx_ring->reg_idx;
3785
3786 if (rx_ring->cpu != cpu) {
3787 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3788 if (hw->mac.type == e1000_82576) {
3789 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3790 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3791 E1000_DCA_RXCTRL_CPUID_SHIFT;
3792 } else {
3793 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3794 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3795 }
3796 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3797 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3798 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3799 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3800 rx_ring->cpu = cpu;
3801 }
3802 put_cpu();
3803 }
3804
3805 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3806 {
3807 u32 dca_txctrl;
3808 struct igb_adapter *adapter = tx_ring->adapter;
3809 struct e1000_hw *hw = &adapter->hw;
3810 int cpu = get_cpu();
3811 int q = tx_ring->reg_idx;
3812
3813 if (tx_ring->cpu != cpu) {
3814 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3815 if (hw->mac.type == e1000_82576) {
3816 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3817 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3818 E1000_DCA_TXCTRL_CPUID_SHIFT;
3819 } else {
3820 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3821 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3822 }
3823 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3824 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3825 tx_ring->cpu = cpu;
3826 }
3827 put_cpu();
3828 }
3829
3830 static void igb_setup_dca(struct igb_adapter *adapter)
3831 {
3832 struct e1000_hw *hw = &adapter->hw;
3833 int i;
3834
3835 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3836 return;
3837
3838 /* Always use CB2 mode, difference is masked in the CB driver. */
3839 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3840
3841 for (i = 0; i < adapter->num_tx_queues; i++) {
3842 adapter->tx_ring[i].cpu = -1;
3843 igb_update_tx_dca(&adapter->tx_ring[i]);
3844 }
3845 for (i = 0; i < adapter->num_rx_queues; i++) {
3846 adapter->rx_ring[i].cpu = -1;
3847 igb_update_rx_dca(&adapter->rx_ring[i]);
3848 }
3849 }
3850
3851 static int __igb_notify_dca(struct device *dev, void *data)
3852 {
3853 struct net_device *netdev = dev_get_drvdata(dev);
3854 struct igb_adapter *adapter = netdev_priv(netdev);
3855 struct e1000_hw *hw = &adapter->hw;
3856 unsigned long event = *(unsigned long *)data;
3857
3858 switch (event) {
3859 case DCA_PROVIDER_ADD:
3860 /* if already enabled, don't do it again */
3861 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3862 break;
3863 /* Always use CB2 mode, difference is masked
3864 * in the CB driver. */
3865 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3866 if (dca_add_requester(dev) == 0) {
3867 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3868 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3869 igb_setup_dca(adapter);
3870 break;
3871 }
3872 /* Fall Through since DCA is disabled. */
3873 case DCA_PROVIDER_REMOVE:
3874 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3875 /* without this a class_device is left
3876 * hanging around in the sysfs model */
3877 dca_remove_requester(dev);
3878 dev_info(&adapter->pdev->dev, "DCA disabled\n");
3879 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3880 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3881 }
3882 break;
3883 }
3884
3885 return 0;
3886 }
3887
3888 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3889 void *p)
3890 {
3891 int ret_val;
3892
3893 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3894 __igb_notify_dca);
3895
3896 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3897 }
3898 #endif /* CONFIG_IGB_DCA */
3899
3900 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3901 {
3902 struct e1000_hw *hw = &adapter->hw;
3903 u32 ping;
3904 int i;
3905
3906 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3907 ping = E1000_PF_CONTROL_MSG;
3908 if (adapter->vf_data[i].clear_to_send)
3909 ping |= E1000_VT_MSGTYPE_CTS;
3910 igb_write_mbx(hw, &ping, 1, i);
3911 }
3912 }
3913
3914 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3915 u32 *msgbuf, u32 vf)
3916 {
3917 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3918 u16 *hash_list = (u16 *)&msgbuf[1];
3919 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3920 int i;
3921
3922 /* only up to 30 hash values supported */
3923 if (n > 30)
3924 n = 30;
3925
3926 /* salt away the number of multi cast addresses assigned
3927 * to this VF for later use to restore when the PF multi cast
3928 * list changes
3929 */
3930 vf_data->num_vf_mc_hashes = n;
3931
3932 /* VFs are limited to using the MTA hash table for their multicast
3933 * addresses */
3934 for (i = 0; i < n; i++)
3935 vf_data->vf_mc_hashes[i] = hash_list[i];;
3936
3937 /* Flush and reset the mta with the new values */
3938 igb_set_multi(adapter->netdev);
3939
3940 return 0;
3941 }
3942
3943 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3944 {
3945 struct e1000_hw *hw = &adapter->hw;
3946 struct vf_data_storage *vf_data;
3947 int i, j;
3948
3949 for (i = 0; i < adapter->vfs_allocated_count; i++) {
3950 vf_data = &adapter->vf_data[i];
3951 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3952 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3953 }
3954 }
3955
3956 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3957 {
3958 struct e1000_hw *hw = &adapter->hw;
3959 u32 pool_mask, reg, vid;
3960 int i;
3961
3962 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3963
3964 /* Find the vlan filter for this id */
3965 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3966 reg = rd32(E1000_VLVF(i));
3967
3968 /* remove the vf from the pool */
3969 reg &= ~pool_mask;
3970
3971 /* if pool is empty then remove entry from vfta */
3972 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3973 (reg & E1000_VLVF_VLANID_ENABLE)) {
3974 reg = 0;
3975 vid = reg & E1000_VLVF_VLANID_MASK;
3976 igb_vfta_set(hw, vid, false);
3977 }
3978
3979 wr32(E1000_VLVF(i), reg);
3980 }
3981 }
3982
3983 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3984 {
3985 struct e1000_hw *hw = &adapter->hw;
3986 u32 reg, i;
3987
3988 /* It is an error to call this function when VFs are not enabled */
3989 if (!adapter->vfs_allocated_count)
3990 return -1;
3991
3992 /* Find the vlan filter for this id */
3993 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3994 reg = rd32(E1000_VLVF(i));
3995 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3996 vid == (reg & E1000_VLVF_VLANID_MASK))
3997 break;
3998 }
3999
4000 if (add) {
4001 if (i == E1000_VLVF_ARRAY_SIZE) {
4002 /* Did not find a matching VLAN ID entry that was
4003 * enabled. Search for a free filter entry, i.e.
4004 * one without the enable bit set
4005 */
4006 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4007 reg = rd32(E1000_VLVF(i));
4008 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4009 break;
4010 }
4011 }
4012 if (i < E1000_VLVF_ARRAY_SIZE) {
4013 /* Found an enabled/available entry */
4014 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4015
4016 /* if !enabled we need to set this up in vfta */
4017 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
4018 /* add VID to filter table, if bit already set
4019 * PF must have added it outside of table */
4020 if (igb_vfta_set(hw, vid, true))
4021 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4022 adapter->vfs_allocated_count);
4023 reg |= E1000_VLVF_VLANID_ENABLE;
4024 }
4025 reg &= ~E1000_VLVF_VLANID_MASK;
4026 reg |= vid;
4027
4028 wr32(E1000_VLVF(i), reg);
4029 return 0;
4030 }
4031 } else {
4032 if (i < E1000_VLVF_ARRAY_SIZE) {
4033 /* remove vf from the pool */
4034 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4035 /* if pool is empty then remove entry from vfta */
4036 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4037 reg = 0;
4038 igb_vfta_set(hw, vid, false);
4039 }
4040 wr32(E1000_VLVF(i), reg);
4041 return 0;
4042 }
4043 }
4044 return -1;
4045 }
4046
4047 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4048 {
4049 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4050 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4051
4052 return igb_vlvf_set(adapter, vid, add, vf);
4053 }
4054
4055 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4056 {
4057 struct e1000_hw *hw = &adapter->hw;
4058
4059 /* disable mailbox functionality for vf */
4060 adapter->vf_data[vf].clear_to_send = false;
4061
4062 /* reset offloads to defaults */
4063 igb_set_vmolr(hw, vf);
4064
4065 /* reset vlans for device */
4066 igb_clear_vf_vfta(adapter, vf);
4067
4068 /* reset multicast table array for vf */
4069 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4070
4071 /* Flush and reset the mta with the new values */
4072 igb_set_multi(adapter->netdev);
4073 }
4074
4075 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4076 {
4077 struct e1000_hw *hw = &adapter->hw;
4078 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4079 u32 reg, msgbuf[3];
4080 u8 *addr = (u8 *)(&msgbuf[1]);
4081
4082 /* process all the same items cleared in a function level reset */
4083 igb_vf_reset_event(adapter, vf);
4084
4085 /* set vf mac address */
4086 igb_rar_set(hw, vf_mac, vf + 1);
4087 igb_set_rah_pool(hw, vf, vf + 1);
4088
4089 /* enable transmit and receive for vf */
4090 reg = rd32(E1000_VFTE);
4091 wr32(E1000_VFTE, reg | (1 << vf));
4092 reg = rd32(E1000_VFRE);
4093 wr32(E1000_VFRE, reg | (1 << vf));
4094
4095 /* enable mailbox functionality for vf */
4096 adapter->vf_data[vf].clear_to_send = true;
4097
4098 /* reply to reset with ack and vf mac address */
4099 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4100 memcpy(addr, vf_mac, 6);
4101 igb_write_mbx(hw, msgbuf, 3, vf);
4102 }
4103
4104 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4105 {
4106 unsigned char *addr = (char *)&msg[1];
4107 int err = -1;
4108
4109 if (is_valid_ether_addr(addr))
4110 err = igb_set_vf_mac(adapter, vf, addr);
4111
4112 return err;
4113
4114 }
4115
4116 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4117 {
4118 struct e1000_hw *hw = &adapter->hw;
4119 u32 msg = E1000_VT_MSGTYPE_NACK;
4120
4121 /* if device isn't clear to send it shouldn't be reading either */
4122 if (!adapter->vf_data[vf].clear_to_send)
4123 igb_write_mbx(hw, &msg, 1, vf);
4124 }
4125
4126
4127 static void igb_msg_task(struct igb_adapter *adapter)
4128 {
4129 struct e1000_hw *hw = &adapter->hw;
4130 u32 vf;
4131
4132 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4133 /* process any reset requests */
4134 if (!igb_check_for_rst(hw, vf)) {
4135 adapter->vf_data[vf].clear_to_send = false;
4136 igb_vf_reset_event(adapter, vf);
4137 }
4138
4139 /* process any messages pending */
4140 if (!igb_check_for_msg(hw, vf))
4141 igb_rcv_msg_from_vf(adapter, vf);
4142
4143 /* process any acks */
4144 if (!igb_check_for_ack(hw, vf))
4145 igb_rcv_ack_from_vf(adapter, vf);
4146
4147 }
4148 }
4149
4150 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4151 {
4152 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4153 u32 msgbuf[mbx_size];
4154 struct e1000_hw *hw = &adapter->hw;
4155 s32 retval;
4156
4157 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4158
4159 if (retval)
4160 dev_err(&adapter->pdev->dev,
4161 "Error receiving message from VF\n");
4162
4163 /* this is a message we already processed, do nothing */
4164 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4165 return retval;
4166
4167 /*
4168 * until the vf completes a reset it should not be
4169 * allowed to start any configuration.
4170 */
4171
4172 if (msgbuf[0] == E1000_VF_RESET) {
4173 igb_vf_reset_msg(adapter, vf);
4174
4175 return retval;
4176 }
4177
4178 if (!adapter->vf_data[vf].clear_to_send) {
4179 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4180 igb_write_mbx(hw, msgbuf, 1, vf);
4181 return retval;
4182 }
4183
4184 switch ((msgbuf[0] & 0xFFFF)) {
4185 case E1000_VF_SET_MAC_ADDR:
4186 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4187 break;
4188 case E1000_VF_SET_MULTICAST:
4189 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4190 break;
4191 case E1000_VF_SET_LPE:
4192 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4193 break;
4194 case E1000_VF_SET_VLAN:
4195 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4196 break;
4197 default:
4198 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4199 retval = -1;
4200 break;
4201 }
4202
4203 /* notify the VF of the results of what it sent us */
4204 if (retval)
4205 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4206 else
4207 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4208
4209 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4210
4211 igb_write_mbx(hw, msgbuf, 1, vf);
4212
4213 return retval;
4214 }
4215
4216 /**
4217 * igb_intr_msi - Interrupt Handler
4218 * @irq: interrupt number
4219 * @data: pointer to a network interface device structure
4220 **/
4221 static irqreturn_t igb_intr_msi(int irq, void *data)
4222 {
4223 struct net_device *netdev = data;
4224 struct igb_adapter *adapter = netdev_priv(netdev);
4225 struct e1000_hw *hw = &adapter->hw;
4226 /* read ICR disables interrupts using IAM */
4227 u32 icr = rd32(E1000_ICR);
4228
4229 igb_write_itr(adapter->rx_ring);
4230
4231 if(icr & E1000_ICR_DOUTSYNC) {
4232 /* HW is reporting DMA is out of sync */
4233 adapter->stats.doosync++;
4234 }
4235
4236 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4237 hw->mac.get_link_status = 1;
4238 if (!test_bit(__IGB_DOWN, &adapter->state))
4239 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4240 }
4241
4242 napi_schedule(&adapter->rx_ring[0].napi);
4243
4244 return IRQ_HANDLED;
4245 }
4246
4247 /**
4248 * igb_intr - Legacy Interrupt Handler
4249 * @irq: interrupt number
4250 * @data: pointer to a network interface device structure
4251 **/
4252 static irqreturn_t igb_intr(int irq, void *data)
4253 {
4254 struct net_device *netdev = data;
4255 struct igb_adapter *adapter = netdev_priv(netdev);
4256 struct e1000_hw *hw = &adapter->hw;
4257 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4258 * need for the IMC write */
4259 u32 icr = rd32(E1000_ICR);
4260 if (!icr)
4261 return IRQ_NONE; /* Not our interrupt */
4262
4263 igb_write_itr(adapter->rx_ring);
4264
4265 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4266 * not set, then the adapter didn't send an interrupt */
4267 if (!(icr & E1000_ICR_INT_ASSERTED))
4268 return IRQ_NONE;
4269
4270 if(icr & E1000_ICR_DOUTSYNC) {
4271 /* HW is reporting DMA is out of sync */
4272 adapter->stats.doosync++;
4273 }
4274
4275 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4276 hw->mac.get_link_status = 1;
4277 /* guard against interrupt when we're going down */
4278 if (!test_bit(__IGB_DOWN, &adapter->state))
4279 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4280 }
4281
4282 napi_schedule(&adapter->rx_ring[0].napi);
4283
4284 return IRQ_HANDLED;
4285 }
4286
4287 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4288 {
4289 struct igb_adapter *adapter = rx_ring->adapter;
4290 struct e1000_hw *hw = &adapter->hw;
4291
4292 if (adapter->itr_setting & 3) {
4293 if (adapter->num_rx_queues == 1)
4294 igb_set_itr(adapter);
4295 else
4296 igb_update_ring_itr(rx_ring);
4297 }
4298
4299 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4300 if (adapter->msix_entries)
4301 wr32(E1000_EIMS, rx_ring->eims_value);
4302 else
4303 igb_irq_enable(adapter);
4304 }
4305 }
4306
4307 /**
4308 * igb_poll - NAPI Rx polling callback
4309 * @napi: napi polling structure
4310 * @budget: count of how many packets we should handle
4311 **/
4312 static int igb_poll(struct napi_struct *napi, int budget)
4313 {
4314 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4315 int work_done = 0;
4316
4317 #ifdef CONFIG_IGB_DCA
4318 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4319 igb_update_rx_dca(rx_ring);
4320 #endif
4321 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4322
4323 if (rx_ring->buddy) {
4324 #ifdef CONFIG_IGB_DCA
4325 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4326 igb_update_tx_dca(rx_ring->buddy);
4327 #endif
4328 if (!igb_clean_tx_irq(rx_ring->buddy))
4329 work_done = budget;
4330 }
4331
4332 /* If not enough Rx work done, exit the polling mode */
4333 if (work_done < budget) {
4334 napi_complete(napi);
4335 igb_rx_irq_enable(rx_ring);
4336 }
4337
4338 return work_done;
4339 }
4340
4341 /**
4342 * igb_hwtstamp - utility function which checks for TX time stamp
4343 * @adapter: board private structure
4344 * @skb: packet that was just sent
4345 *
4346 * If we were asked to do hardware stamping and such a time stamp is
4347 * available, then it must have been for this skb here because we only
4348 * allow only one such packet into the queue.
4349 */
4350 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4351 {
4352 union skb_shared_tx *shtx = skb_tx(skb);
4353 struct e1000_hw *hw = &adapter->hw;
4354
4355 if (unlikely(shtx->hardware)) {
4356 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4357 if (valid) {
4358 u64 regval = rd32(E1000_TXSTMPL);
4359 u64 ns;
4360 struct skb_shared_hwtstamps shhwtstamps;
4361
4362 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4363 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4364 ns = timecounter_cyc2time(&adapter->clock,
4365 regval);
4366 timecompare_update(&adapter->compare, ns);
4367 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4368 shhwtstamps.syststamp =
4369 timecompare_transform(&adapter->compare, ns);
4370 skb_tstamp_tx(skb, &shhwtstamps);
4371 }
4372 }
4373 }
4374
4375 /**
4376 * igb_clean_tx_irq - Reclaim resources after transmit completes
4377 * @adapter: board private structure
4378 * returns true if ring is completely cleaned
4379 **/
4380 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4381 {
4382 struct igb_adapter *adapter = tx_ring->adapter;
4383 struct net_device *netdev = adapter->netdev;
4384 struct e1000_hw *hw = &adapter->hw;
4385 struct igb_buffer *buffer_info;
4386 struct sk_buff *skb;
4387 union e1000_adv_tx_desc *tx_desc, *eop_desc;
4388 unsigned int total_bytes = 0, total_packets = 0;
4389 unsigned int i, eop, count = 0;
4390 bool cleaned = false;
4391
4392 i = tx_ring->next_to_clean;
4393 eop = tx_ring->buffer_info[i].next_to_watch;
4394 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4395
4396 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4397 (count < tx_ring->count)) {
4398 for (cleaned = false; !cleaned; count++) {
4399 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4400 buffer_info = &tx_ring->buffer_info[i];
4401 cleaned = (i == eop);
4402 skb = buffer_info->skb;
4403
4404 if (skb) {
4405 unsigned int segs, bytecount;
4406 /* gso_segs is currently only valid for tcp */
4407 segs = skb_shinfo(skb)->gso_segs ?: 1;
4408 /* multiply data chunks by size of headers */
4409 bytecount = ((segs - 1) * skb_headlen(skb)) +
4410 skb->len;
4411 total_packets += segs;
4412 total_bytes += bytecount;
4413
4414 igb_tx_hwtstamp(adapter, skb);
4415 }
4416
4417 igb_unmap_and_free_tx_resource(adapter, buffer_info);
4418 tx_desc->wb.status = 0;
4419
4420 i++;
4421 if (i == tx_ring->count)
4422 i = 0;
4423 }
4424 eop = tx_ring->buffer_info[i].next_to_watch;
4425 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4426 }
4427
4428 tx_ring->next_to_clean = i;
4429
4430 if (unlikely(count &&
4431 netif_carrier_ok(netdev) &&
4432 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4433 /* Make sure that anybody stopping the queue after this
4434 * sees the new next_to_clean.
4435 */
4436 smp_mb();
4437 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4438 !(test_bit(__IGB_DOWN, &adapter->state))) {
4439 netif_wake_subqueue(netdev, tx_ring->queue_index);
4440 ++adapter->restart_queue;
4441 }
4442 }
4443
4444 if (tx_ring->detect_tx_hung) {
4445 /* Detect a transmit hang in hardware, this serializes the
4446 * check with the clearing of time_stamp and movement of i */
4447 tx_ring->detect_tx_hung = false;
4448 if (tx_ring->buffer_info[i].time_stamp &&
4449 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4450 (adapter->tx_timeout_factor * HZ))
4451 && !(rd32(E1000_STATUS) &
4452 E1000_STATUS_TXOFF)) {
4453
4454 /* detected Tx unit hang */
4455 dev_err(&adapter->pdev->dev,
4456 "Detected Tx Unit Hang\n"
4457 " Tx Queue <%d>\n"
4458 " TDH <%x>\n"
4459 " TDT <%x>\n"
4460 " next_to_use <%x>\n"
4461 " next_to_clean <%x>\n"
4462 "buffer_info[next_to_clean]\n"
4463 " time_stamp <%lx>\n"
4464 " next_to_watch <%x>\n"
4465 " jiffies <%lx>\n"
4466 " desc.status <%x>\n",
4467 tx_ring->queue_index,
4468 readl(adapter->hw.hw_addr + tx_ring->head),
4469 readl(adapter->hw.hw_addr + tx_ring->tail),
4470 tx_ring->next_to_use,
4471 tx_ring->next_to_clean,
4472 tx_ring->buffer_info[i].time_stamp,
4473 eop,
4474 jiffies,
4475 eop_desc->wb.status);
4476 netif_stop_subqueue(netdev, tx_ring->queue_index);
4477 }
4478 }
4479 tx_ring->total_bytes += total_bytes;
4480 tx_ring->total_packets += total_packets;
4481 tx_ring->tx_stats.bytes += total_bytes;
4482 tx_ring->tx_stats.packets += total_packets;
4483 adapter->net_stats.tx_bytes += total_bytes;
4484 adapter->net_stats.tx_packets += total_packets;
4485 return (count < tx_ring->count);
4486 }
4487
4488 /**
4489 * igb_receive_skb - helper function to handle rx indications
4490 * @ring: pointer to receive ring receving this packet
4491 * @status: descriptor status field as written by hardware
4492 * @rx_desc: receive descriptor containing vlan and type information.
4493 * @skb: pointer to sk_buff to be indicated to stack
4494 **/
4495 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4496 union e1000_adv_rx_desc * rx_desc,
4497 struct sk_buff *skb)
4498 {
4499 struct igb_adapter * adapter = ring->adapter;
4500 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4501
4502 skb_record_rx_queue(skb, ring->queue_index);
4503 if (vlan_extracted)
4504 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4505 le16_to_cpu(rx_desc->wb.upper.vlan),
4506 skb);
4507 else
4508 napi_gro_receive(&ring->napi, skb);
4509 }
4510
4511 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4512 u32 status_err, struct sk_buff *skb)
4513 {
4514 skb->ip_summed = CHECKSUM_NONE;
4515
4516 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4517 if ((status_err & E1000_RXD_STAT_IXSM) ||
4518 (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
4519 return;
4520 /* TCP/UDP checksum error bit is set */
4521 if (status_err &
4522 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4523 /*
4524 * work around errata with sctp packets where the TCPE aka
4525 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4526 * packets, (aka let the stack check the crc32c)
4527 */
4528 if (!((adapter->hw.mac.type == e1000_82576) &&
4529 (skb->len == 60)))
4530 adapter->hw_csum_err++;
4531 /* let the stack verify checksum errors */
4532 return;
4533 }
4534 /* It must be a TCP or UDP packet with a valid checksum */
4535 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4536 skb->ip_summed = CHECKSUM_UNNECESSARY;
4537
4538 dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
4539 adapter->hw_csum_good++;
4540 }
4541
4542 static inline u16 igb_get_hlen(struct igb_adapter *adapter,
4543 union e1000_adv_rx_desc *rx_desc)
4544 {
4545 /* HW will not DMA in data larger than the given buffer, even if it
4546 * parses the (NFS, of course) header to be larger. In that case, it
4547 * fills the header buffer and spills the rest into the page.
4548 */
4549 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4550 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4551 if (hlen > adapter->rx_ps_hdr_size)
4552 hlen = adapter->rx_ps_hdr_size;
4553 return hlen;
4554 }
4555
4556 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4557 int *work_done, int budget)
4558 {
4559 struct igb_adapter *adapter = rx_ring->adapter;
4560 struct net_device *netdev = adapter->netdev;
4561 struct e1000_hw *hw = &adapter->hw;
4562 struct pci_dev *pdev = adapter->pdev;
4563 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4564 struct igb_buffer *buffer_info , *next_buffer;
4565 struct sk_buff *skb;
4566 bool cleaned = false;
4567 int cleaned_count = 0;
4568 unsigned int total_bytes = 0, total_packets = 0;
4569 unsigned int i;
4570 u32 staterr;
4571 u16 length;
4572
4573 i = rx_ring->next_to_clean;
4574 buffer_info = &rx_ring->buffer_info[i];
4575 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4576 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4577
4578 while (staterr & E1000_RXD_STAT_DD) {
4579 if (*work_done >= budget)
4580 break;
4581 (*work_done)++;
4582
4583 skb = buffer_info->skb;
4584 prefetch(skb->data - NET_IP_ALIGN);
4585 buffer_info->skb = NULL;
4586
4587 i++;
4588 if (i == rx_ring->count)
4589 i = 0;
4590 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4591 prefetch(next_rxd);
4592 next_buffer = &rx_ring->buffer_info[i];
4593
4594 length = le16_to_cpu(rx_desc->wb.upper.length);
4595 cleaned = true;
4596 cleaned_count++;
4597
4598 /* this is the fast path for the non-packet split case */
4599 if (!adapter->rx_ps_hdr_size) {
4600 pci_unmap_single(pdev, buffer_info->dma,
4601 adapter->rx_buffer_len,
4602 PCI_DMA_FROMDEVICE);
4603 buffer_info->dma = 0;
4604 skb_put(skb, length);
4605 goto send_up;
4606 }
4607
4608 if (buffer_info->dma) {
4609 u16 hlen = igb_get_hlen(adapter, rx_desc);
4610 pci_unmap_single(pdev, buffer_info->dma,
4611 adapter->rx_ps_hdr_size,
4612 PCI_DMA_FROMDEVICE);
4613 buffer_info->dma = 0;
4614 skb_put(skb, hlen);
4615 }
4616
4617 if (length) {
4618 pci_unmap_page(pdev, buffer_info->page_dma,
4619 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4620 buffer_info->page_dma = 0;
4621
4622 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4623 buffer_info->page,
4624 buffer_info->page_offset,
4625 length);
4626
4627 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4628 (page_count(buffer_info->page) != 1))
4629 buffer_info->page = NULL;
4630 else
4631 get_page(buffer_info->page);
4632
4633 skb->len += length;
4634 skb->data_len += length;
4635
4636 skb->truesize += length;
4637 }
4638
4639 if (!(staterr & E1000_RXD_STAT_EOP)) {
4640 buffer_info->skb = next_buffer->skb;
4641 buffer_info->dma = next_buffer->dma;
4642 next_buffer->skb = skb;
4643 next_buffer->dma = 0;
4644 goto next_desc;
4645 }
4646 send_up:
4647 /*
4648 * If this bit is set, then the RX registers contain
4649 * the time stamp. No other packet will be time
4650 * stamped until we read these registers, so read the
4651 * registers to make them available again. Because
4652 * only one packet can be time stamped at a time, we
4653 * know that the register values must belong to this
4654 * one here and therefore we don't need to compare
4655 * any of the additional attributes stored for it.
4656 *
4657 * If nothing went wrong, then it should have a
4658 * skb_shared_tx that we can turn into a
4659 * skb_shared_hwtstamps.
4660 *
4661 * TODO: can time stamping be triggered (thus locking
4662 * the registers) without the packet reaching this point
4663 * here? In that case RX time stamping would get stuck.
4664 *
4665 * TODO: in "time stamp all packets" mode this bit is
4666 * not set. Need a global flag for this mode and then
4667 * always read the registers. Cannot be done without
4668 * a race condition.
4669 */
4670 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4671 u64 regval;
4672 u64 ns;
4673 struct skb_shared_hwtstamps *shhwtstamps =
4674 skb_hwtstamps(skb);
4675
4676 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4677 "igb: no RX time stamp available for time stamped packet");
4678 regval = rd32(E1000_RXSTMPL);
4679 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4680 ns = timecounter_cyc2time(&adapter->clock, regval);
4681 timecompare_update(&adapter->compare, ns);
4682 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4683 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4684 shhwtstamps->syststamp =
4685 timecompare_transform(&adapter->compare, ns);
4686 }
4687
4688 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4689 dev_kfree_skb_irq(skb);
4690 goto next_desc;
4691 }
4692
4693 total_bytes += skb->len;
4694 total_packets++;
4695
4696 igb_rx_checksum_adv(adapter, staterr, skb);
4697
4698 skb->protocol = eth_type_trans(skb, netdev);
4699
4700 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4701
4702 next_desc:
4703 rx_desc->wb.upper.status_error = 0;
4704
4705 /* return some buffers to hardware, one at a time is too slow */
4706 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4707 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4708 cleaned_count = 0;
4709 }
4710
4711 /* use prefetched values */
4712 rx_desc = next_rxd;
4713 buffer_info = next_buffer;
4714 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4715 }
4716
4717 rx_ring->next_to_clean = i;
4718 cleaned_count = igb_desc_unused(rx_ring);
4719
4720 if (cleaned_count)
4721 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4722
4723 rx_ring->total_packets += total_packets;
4724 rx_ring->total_bytes += total_bytes;
4725 rx_ring->rx_stats.packets += total_packets;
4726 rx_ring->rx_stats.bytes += total_bytes;
4727 adapter->net_stats.rx_bytes += total_bytes;
4728 adapter->net_stats.rx_packets += total_packets;
4729 return cleaned;
4730 }
4731
4732 /**
4733 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4734 * @adapter: address of board private structure
4735 **/
4736 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4737 int cleaned_count)
4738 {
4739 struct igb_adapter *adapter = rx_ring->adapter;
4740 struct net_device *netdev = adapter->netdev;
4741 struct pci_dev *pdev = adapter->pdev;
4742 union e1000_adv_rx_desc *rx_desc;
4743 struct igb_buffer *buffer_info;
4744 struct sk_buff *skb;
4745 unsigned int i;
4746 int bufsz;
4747
4748 i = rx_ring->next_to_use;
4749 buffer_info = &rx_ring->buffer_info[i];
4750
4751 if (adapter->rx_ps_hdr_size)
4752 bufsz = adapter->rx_ps_hdr_size;
4753 else
4754 bufsz = adapter->rx_buffer_len;
4755
4756 while (cleaned_count--) {
4757 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4758
4759 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4760 if (!buffer_info->page) {
4761 buffer_info->page = alloc_page(GFP_ATOMIC);
4762 if (!buffer_info->page) {
4763 adapter->alloc_rx_buff_failed++;
4764 goto no_buffers;
4765 }
4766 buffer_info->page_offset = 0;
4767 } else {
4768 buffer_info->page_offset ^= PAGE_SIZE / 2;
4769 }
4770 buffer_info->page_dma =
4771 pci_map_page(pdev, buffer_info->page,
4772 buffer_info->page_offset,
4773 PAGE_SIZE / 2,
4774 PCI_DMA_FROMDEVICE);
4775 }
4776
4777 if (!buffer_info->skb) {
4778 skb = netdev_alloc_skb(netdev, bufsz + NET_IP_ALIGN);
4779 if (!skb) {
4780 adapter->alloc_rx_buff_failed++;
4781 goto no_buffers;
4782 }
4783
4784 /* Make buffer alignment 2 beyond a 16 byte boundary
4785 * this will result in a 16 byte aligned IP header after
4786 * the 14 byte MAC header is removed
4787 */
4788 skb_reserve(skb, NET_IP_ALIGN);
4789
4790 buffer_info->skb = skb;
4791 buffer_info->dma = pci_map_single(pdev, skb->data,
4792 bufsz,
4793 PCI_DMA_FROMDEVICE);
4794 }
4795 /* Refresh the desc even if buffer_addrs didn't change because
4796 * each write-back erases this info. */
4797 if (adapter->rx_ps_hdr_size) {
4798 rx_desc->read.pkt_addr =
4799 cpu_to_le64(buffer_info->page_dma);
4800 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4801 } else {
4802 rx_desc->read.pkt_addr =
4803 cpu_to_le64(buffer_info->dma);
4804 rx_desc->read.hdr_addr = 0;
4805 }
4806
4807 i++;
4808 if (i == rx_ring->count)
4809 i = 0;
4810 buffer_info = &rx_ring->buffer_info[i];
4811 }
4812
4813 no_buffers:
4814 if (rx_ring->next_to_use != i) {
4815 rx_ring->next_to_use = i;
4816 if (i == 0)
4817 i = (rx_ring->count - 1);
4818 else
4819 i--;
4820
4821 /* Force memory writes to complete before letting h/w
4822 * know there are new descriptors to fetch. (Only
4823 * applicable for weak-ordered memory model archs,
4824 * such as IA-64). */
4825 wmb();
4826 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4827 }
4828 }
4829
4830 /**
4831 * igb_mii_ioctl -
4832 * @netdev:
4833 * @ifreq:
4834 * @cmd:
4835 **/
4836 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4837 {
4838 struct igb_adapter *adapter = netdev_priv(netdev);
4839 struct mii_ioctl_data *data = if_mii(ifr);
4840
4841 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4842 return -EOPNOTSUPP;
4843
4844 switch (cmd) {
4845 case SIOCGMIIPHY:
4846 data->phy_id = adapter->hw.phy.addr;
4847 break;
4848 case SIOCGMIIREG:
4849 if (!capable(CAP_NET_ADMIN))
4850 return -EPERM;
4851 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4852 &data->val_out))
4853 return -EIO;
4854 break;
4855 case SIOCSMIIREG:
4856 default:
4857 return -EOPNOTSUPP;
4858 }
4859 return 0;
4860 }
4861
4862 /**
4863 * igb_hwtstamp_ioctl - control hardware time stamping
4864 * @netdev:
4865 * @ifreq:
4866 * @cmd:
4867 *
4868 * Outgoing time stamping can be enabled and disabled. Play nice and
4869 * disable it when requested, although it shouldn't case any overhead
4870 * when no packet needs it. At most one packet in the queue may be
4871 * marked for time stamping, otherwise it would be impossible to tell
4872 * for sure to which packet the hardware time stamp belongs.
4873 *
4874 * Incoming time stamping has to be configured via the hardware
4875 * filters. Not all combinations are supported, in particular event
4876 * type has to be specified. Matching the kind of event packet is
4877 * not supported, with the exception of "all V2 events regardless of
4878 * level 2 or 4".
4879 *
4880 **/
4881 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4882 struct ifreq *ifr, int cmd)
4883 {
4884 struct igb_adapter *adapter = netdev_priv(netdev);
4885 struct e1000_hw *hw = &adapter->hw;
4886 struct hwtstamp_config config;
4887 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4888 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4889 u32 tsync_rx_ctl_type = 0;
4890 u32 tsync_rx_cfg = 0;
4891 int is_l4 = 0;
4892 int is_l2 = 0;
4893 short port = 319; /* PTP */
4894 u32 regval;
4895
4896 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4897 return -EFAULT;
4898
4899 /* reserved for future extensions */
4900 if (config.flags)
4901 return -EINVAL;
4902
4903 switch (config.tx_type) {
4904 case HWTSTAMP_TX_OFF:
4905 tsync_tx_ctl_bit = 0;
4906 break;
4907 case HWTSTAMP_TX_ON:
4908 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4909 break;
4910 default:
4911 return -ERANGE;
4912 }
4913
4914 switch (config.rx_filter) {
4915 case HWTSTAMP_FILTER_NONE:
4916 tsync_rx_ctl_bit = 0;
4917 break;
4918 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4919 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4920 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4921 case HWTSTAMP_FILTER_ALL:
4922 /*
4923 * register TSYNCRXCFG must be set, therefore it is not
4924 * possible to time stamp both Sync and Delay_Req messages
4925 * => fall back to time stamping all packets
4926 */
4927 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4928 config.rx_filter = HWTSTAMP_FILTER_ALL;
4929 break;
4930 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4931 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4932 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4933 is_l4 = 1;
4934 break;
4935 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4936 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4937 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4938 is_l4 = 1;
4939 break;
4940 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4941 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4942 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4943 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4944 is_l2 = 1;
4945 is_l4 = 1;
4946 config.rx_filter = HWTSTAMP_FILTER_SOME;
4947 break;
4948 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4949 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4950 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4951 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4952 is_l2 = 1;
4953 is_l4 = 1;
4954 config.rx_filter = HWTSTAMP_FILTER_SOME;
4955 break;
4956 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4957 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4958 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4959 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4960 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4961 is_l2 = 1;
4962 break;
4963 default:
4964 return -ERANGE;
4965 }
4966
4967 /* enable/disable TX */
4968 regval = rd32(E1000_TSYNCTXCTL);
4969 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4970 wr32(E1000_TSYNCTXCTL, regval);
4971
4972 /* enable/disable RX, define which PTP packets are time stamped */
4973 regval = rd32(E1000_TSYNCRXCTL);
4974 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4975 regval = (regval & ~0xE) | tsync_rx_ctl_type;
4976 wr32(E1000_TSYNCRXCTL, regval);
4977 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4978
4979 /*
4980 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4981 * (Ethertype to filter on)
4982 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4983 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4984 */
4985 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4986
4987 /* L4 Queue Filter[0]: only filter by source and destination port */
4988 wr32(E1000_SPQF0, htons(port));
4989 wr32(E1000_IMIREXT(0), is_l4 ?
4990 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4991 wr32(E1000_IMIR(0), is_l4 ?
4992 (htons(port)
4993 | (0<<16) /* immediate interrupt disabled */
4994 | 0 /* (1<<17) bit cleared: do not bypass
4995 destination port check */)
4996 : 0);
4997 wr32(E1000_FTQF0, is_l4 ?
4998 (0x11 /* UDP */
4999 | (1<<15) /* VF not compared */
5000 | (1<<27) /* Enable Timestamping */
5001 | (7<<28) /* only source port filter enabled,
5002 source/target address and protocol
5003 masked */)
5004 : ((1<<15) | (15<<28) /* all mask bits set = filter not
5005 enabled */));
5006
5007 wrfl();
5008
5009 adapter->hwtstamp_config = config;
5010
5011 /* clear TX/RX time stamp registers, just to be sure */
5012 regval = rd32(E1000_TXSTMPH);
5013 regval = rd32(E1000_RXSTMPH);
5014
5015 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5016 -EFAULT : 0;
5017 }
5018
5019 /**
5020 * igb_ioctl -
5021 * @netdev:
5022 * @ifreq:
5023 * @cmd:
5024 **/
5025 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5026 {
5027 switch (cmd) {
5028 case SIOCGMIIPHY:
5029 case SIOCGMIIREG:
5030 case SIOCSMIIREG:
5031 return igb_mii_ioctl(netdev, ifr, cmd);
5032 case SIOCSHWTSTAMP:
5033 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
5034 default:
5035 return -EOPNOTSUPP;
5036 }
5037 }
5038
5039 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5040 {
5041 struct igb_adapter *adapter = hw->back;
5042 u16 cap_offset;
5043
5044 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5045 if (!cap_offset)
5046 return -E1000_ERR_CONFIG;
5047
5048 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5049
5050 return 0;
5051 }
5052
5053 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5054 {
5055 struct igb_adapter *adapter = hw->back;
5056 u16 cap_offset;
5057
5058 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5059 if (!cap_offset)
5060 return -E1000_ERR_CONFIG;
5061
5062 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5063
5064 return 0;
5065 }
5066
5067 static void igb_vlan_rx_register(struct net_device *netdev,
5068 struct vlan_group *grp)
5069 {
5070 struct igb_adapter *adapter = netdev_priv(netdev);
5071 struct e1000_hw *hw = &adapter->hw;
5072 u32 ctrl, rctl;
5073
5074 igb_irq_disable(adapter);
5075 adapter->vlgrp = grp;
5076
5077 if (grp) {
5078 /* enable VLAN tag insert/strip */
5079 ctrl = rd32(E1000_CTRL);
5080 ctrl |= E1000_CTRL_VME;
5081 wr32(E1000_CTRL, ctrl);
5082
5083 /* enable VLAN receive filtering */
5084 rctl = rd32(E1000_RCTL);
5085 rctl &= ~E1000_RCTL_CFIEN;
5086 wr32(E1000_RCTL, rctl);
5087 igb_update_mng_vlan(adapter);
5088 } else {
5089 /* disable VLAN tag insert/strip */
5090 ctrl = rd32(E1000_CTRL);
5091 ctrl &= ~E1000_CTRL_VME;
5092 wr32(E1000_CTRL, ctrl);
5093
5094 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5095 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5096 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5097 }
5098 }
5099
5100 igb_rlpml_set(adapter);
5101
5102 if (!test_bit(__IGB_DOWN, &adapter->state))
5103 igb_irq_enable(adapter);
5104 }
5105
5106 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5107 {
5108 struct igb_adapter *adapter = netdev_priv(netdev);
5109 struct e1000_hw *hw = &adapter->hw;
5110 int pf_id = adapter->vfs_allocated_count;
5111
5112 if ((hw->mng_cookie.status &
5113 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5114 (vid == adapter->mng_vlan_id))
5115 return;
5116
5117 /* add vid to vlvf if sr-iov is enabled,
5118 * if that fails add directly to filter table */
5119 if (igb_vlvf_set(adapter, vid, true, pf_id))
5120 igb_vfta_set(hw, vid, true);
5121
5122 }
5123
5124 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5125 {
5126 struct igb_adapter *adapter = netdev_priv(netdev);
5127 struct e1000_hw *hw = &adapter->hw;
5128 int pf_id = adapter->vfs_allocated_count;
5129
5130 igb_irq_disable(adapter);
5131 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5132
5133 if (!test_bit(__IGB_DOWN, &adapter->state))
5134 igb_irq_enable(adapter);
5135
5136 if ((adapter->hw.mng_cookie.status &
5137 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5138 (vid == adapter->mng_vlan_id)) {
5139 /* release control to f/w */
5140 igb_release_hw_control(adapter);
5141 return;
5142 }
5143
5144 /* remove vid from vlvf if sr-iov is enabled,
5145 * if not in vlvf remove from vfta */
5146 if (igb_vlvf_set(adapter, vid, false, pf_id))
5147 igb_vfta_set(hw, vid, false);
5148 }
5149
5150 static void igb_restore_vlan(struct igb_adapter *adapter)
5151 {
5152 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5153
5154 if (adapter->vlgrp) {
5155 u16 vid;
5156 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5157 if (!vlan_group_get_device(adapter->vlgrp, vid))
5158 continue;
5159 igb_vlan_rx_add_vid(adapter->netdev, vid);
5160 }
5161 }
5162 }
5163
5164 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5165 {
5166 struct e1000_mac_info *mac = &adapter->hw.mac;
5167
5168 mac->autoneg = 0;
5169
5170 switch (spddplx) {
5171 case SPEED_10 + DUPLEX_HALF:
5172 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5173 break;
5174 case SPEED_10 + DUPLEX_FULL:
5175 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5176 break;
5177 case SPEED_100 + DUPLEX_HALF:
5178 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5179 break;
5180 case SPEED_100 + DUPLEX_FULL:
5181 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5182 break;
5183 case SPEED_1000 + DUPLEX_FULL:
5184 mac->autoneg = 1;
5185 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5186 break;
5187 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5188 default:
5189 dev_err(&adapter->pdev->dev,
5190 "Unsupported Speed/Duplex configuration\n");
5191 return -EINVAL;
5192 }
5193 return 0;
5194 }
5195
5196 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5197 {
5198 struct net_device *netdev = pci_get_drvdata(pdev);
5199 struct igb_adapter *adapter = netdev_priv(netdev);
5200 struct e1000_hw *hw = &adapter->hw;
5201 u32 ctrl, rctl, status;
5202 u32 wufc = adapter->wol;
5203 #ifdef CONFIG_PM
5204 int retval = 0;
5205 #endif
5206
5207 netif_device_detach(netdev);
5208
5209 if (netif_running(netdev))
5210 igb_close(netdev);
5211
5212 igb_reset_interrupt_capability(adapter);
5213
5214 igb_free_queues(adapter);
5215
5216 #ifdef CONFIG_PM
5217 retval = pci_save_state(pdev);
5218 if (retval)
5219 return retval;
5220 #endif
5221
5222 status = rd32(E1000_STATUS);
5223 if (status & E1000_STATUS_LU)
5224 wufc &= ~E1000_WUFC_LNKC;
5225
5226 if (wufc) {
5227 igb_setup_rctl(adapter);
5228 igb_set_multi(netdev);
5229
5230 /* turn on all-multi mode if wake on multicast is enabled */
5231 if (wufc & E1000_WUFC_MC) {
5232 rctl = rd32(E1000_RCTL);
5233 rctl |= E1000_RCTL_MPE;
5234 wr32(E1000_RCTL, rctl);
5235 }
5236
5237 ctrl = rd32(E1000_CTRL);
5238 /* advertise wake from D3Cold */
5239 #define E1000_CTRL_ADVD3WUC 0x00100000
5240 /* phy power management enable */
5241 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5242 ctrl |= E1000_CTRL_ADVD3WUC;
5243 wr32(E1000_CTRL, ctrl);
5244
5245 /* Allow time for pending master requests to run */
5246 igb_disable_pcie_master(&adapter->hw);
5247
5248 wr32(E1000_WUC, E1000_WUC_PME_EN);
5249 wr32(E1000_WUFC, wufc);
5250 } else {
5251 wr32(E1000_WUC, 0);
5252 wr32(E1000_WUFC, 0);
5253 }
5254
5255 *enable_wake = wufc || adapter->en_mng_pt;
5256 if (!*enable_wake)
5257 igb_shutdown_fiber_serdes_link_82575(hw);
5258
5259 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5260 * would have already happened in close and is redundant. */
5261 igb_release_hw_control(adapter);
5262
5263 pci_disable_device(pdev);
5264
5265 return 0;
5266 }
5267
5268 #ifdef CONFIG_PM
5269 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5270 {
5271 int retval;
5272 bool wake;
5273
5274 retval = __igb_shutdown(pdev, &wake);
5275 if (retval)
5276 return retval;
5277
5278 if (wake) {
5279 pci_prepare_to_sleep(pdev);
5280 } else {
5281 pci_wake_from_d3(pdev, false);
5282 pci_set_power_state(pdev, PCI_D3hot);
5283 }
5284
5285 return 0;
5286 }
5287
5288 static int igb_resume(struct pci_dev *pdev)
5289 {
5290 struct net_device *netdev = pci_get_drvdata(pdev);
5291 struct igb_adapter *adapter = netdev_priv(netdev);
5292 struct e1000_hw *hw = &adapter->hw;
5293 u32 err;
5294
5295 pci_set_power_state(pdev, PCI_D0);
5296 pci_restore_state(pdev);
5297
5298 err = pci_enable_device_mem(pdev);
5299 if (err) {
5300 dev_err(&pdev->dev,
5301 "igb: Cannot enable PCI device from suspend\n");
5302 return err;
5303 }
5304 pci_set_master(pdev);
5305
5306 pci_enable_wake(pdev, PCI_D3hot, 0);
5307 pci_enable_wake(pdev, PCI_D3cold, 0);
5308
5309 igb_set_interrupt_capability(adapter);
5310
5311 if (igb_alloc_queues(adapter)) {
5312 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5313 return -ENOMEM;
5314 }
5315
5316 /* e1000_power_up_phy(adapter); */
5317
5318 igb_reset(adapter);
5319
5320 /* let the f/w know that the h/w is now under the control of the
5321 * driver. */
5322 igb_get_hw_control(adapter);
5323
5324 wr32(E1000_WUS, ~0);
5325
5326 if (netif_running(netdev)) {
5327 err = igb_open(netdev);
5328 if (err)
5329 return err;
5330 }
5331
5332 netif_device_attach(netdev);
5333
5334 return 0;
5335 }
5336 #endif
5337
5338 static void igb_shutdown(struct pci_dev *pdev)
5339 {
5340 bool wake;
5341
5342 __igb_shutdown(pdev, &wake);
5343
5344 if (system_state == SYSTEM_POWER_OFF) {
5345 pci_wake_from_d3(pdev, wake);
5346 pci_set_power_state(pdev, PCI_D3hot);
5347 }
5348 }
5349
5350 #ifdef CONFIG_NET_POLL_CONTROLLER
5351 /*
5352 * Polling 'interrupt' - used by things like netconsole to send skbs
5353 * without having to re-enable interrupts. It's not called while
5354 * the interrupt routine is executing.
5355 */
5356 static void igb_netpoll(struct net_device *netdev)
5357 {
5358 struct igb_adapter *adapter = netdev_priv(netdev);
5359 struct e1000_hw *hw = &adapter->hw;
5360 int i;
5361
5362 if (!adapter->msix_entries) {
5363 igb_irq_disable(adapter);
5364 napi_schedule(&adapter->rx_ring[0].napi);
5365 return;
5366 }
5367
5368 for (i = 0; i < adapter->num_tx_queues; i++) {
5369 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5370 wr32(E1000_EIMC, tx_ring->eims_value);
5371 igb_clean_tx_irq(tx_ring);
5372 wr32(E1000_EIMS, tx_ring->eims_value);
5373 }
5374
5375 for (i = 0; i < adapter->num_rx_queues; i++) {
5376 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5377 wr32(E1000_EIMC, rx_ring->eims_value);
5378 napi_schedule(&rx_ring->napi);
5379 }
5380 }
5381 #endif /* CONFIG_NET_POLL_CONTROLLER */
5382
5383 /**
5384 * igb_io_error_detected - called when PCI error is detected
5385 * @pdev: Pointer to PCI device
5386 * @state: The current pci connection state
5387 *
5388 * This function is called after a PCI bus error affecting
5389 * this device has been detected.
5390 */
5391 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5392 pci_channel_state_t state)
5393 {
5394 struct net_device *netdev = pci_get_drvdata(pdev);
5395 struct igb_adapter *adapter = netdev_priv(netdev);
5396
5397 netif_device_detach(netdev);
5398
5399 if (state == pci_channel_io_perm_failure)
5400 return PCI_ERS_RESULT_DISCONNECT;
5401
5402 if (netif_running(netdev))
5403 igb_down(adapter);
5404 pci_disable_device(pdev);
5405
5406 /* Request a slot slot reset. */
5407 return PCI_ERS_RESULT_NEED_RESET;
5408 }
5409
5410 /**
5411 * igb_io_slot_reset - called after the pci bus has been reset.
5412 * @pdev: Pointer to PCI device
5413 *
5414 * Restart the card from scratch, as if from a cold-boot. Implementation
5415 * resembles the first-half of the igb_resume routine.
5416 */
5417 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5418 {
5419 struct net_device *netdev = pci_get_drvdata(pdev);
5420 struct igb_adapter *adapter = netdev_priv(netdev);
5421 struct e1000_hw *hw = &adapter->hw;
5422 pci_ers_result_t result;
5423 int err;
5424
5425 if (pci_enable_device_mem(pdev)) {
5426 dev_err(&pdev->dev,
5427 "Cannot re-enable PCI device after reset.\n");
5428 result = PCI_ERS_RESULT_DISCONNECT;
5429 } else {
5430 pci_set_master(pdev);
5431 pci_restore_state(pdev);
5432
5433 pci_enable_wake(pdev, PCI_D3hot, 0);
5434 pci_enable_wake(pdev, PCI_D3cold, 0);
5435
5436 igb_reset(adapter);
5437 wr32(E1000_WUS, ~0);
5438 result = PCI_ERS_RESULT_RECOVERED;
5439 }
5440
5441 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5442 if (err) {
5443 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5444 "failed 0x%0x\n", err);
5445 /* non-fatal, continue */
5446 }
5447
5448 return result;
5449 }
5450
5451 /**
5452 * igb_io_resume - called when traffic can start flowing again.
5453 * @pdev: Pointer to PCI device
5454 *
5455 * This callback is called when the error recovery driver tells us that
5456 * its OK to resume normal operation. Implementation resembles the
5457 * second-half of the igb_resume routine.
5458 */
5459 static void igb_io_resume(struct pci_dev *pdev)
5460 {
5461 struct net_device *netdev = pci_get_drvdata(pdev);
5462 struct igb_adapter *adapter = netdev_priv(netdev);
5463
5464 if (netif_running(netdev)) {
5465 if (igb_up(adapter)) {
5466 dev_err(&pdev->dev, "igb_up failed after reset\n");
5467 return;
5468 }
5469 }
5470
5471 netif_device_attach(netdev);
5472
5473 /* let the f/w know that the h/w is now under the control of the
5474 * driver. */
5475 igb_get_hw_control(adapter);
5476 }
5477
5478 static int igb_set_vf_mac(struct igb_adapter *adapter,
5479 int vf, unsigned char *mac_addr)
5480 {
5481 struct e1000_hw *hw = &adapter->hw;
5482 int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5483
5484 igb_rar_set(hw, mac_addr, rar_entry);
5485
5486 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5487
5488 igb_set_rah_pool(hw, vf, rar_entry);
5489
5490 return 0;
5491 }
5492
5493 static void igb_vmm_control(struct igb_adapter *adapter)
5494 {
5495 struct e1000_hw *hw = &adapter->hw;
5496 u32 reg_data;
5497
5498 if (!adapter->vfs_allocated_count)
5499 return;
5500
5501 /* VF's need PF reset indication before they
5502 * can send/receive mail */
5503 reg_data = rd32(E1000_CTRL_EXT);
5504 reg_data |= E1000_CTRL_EXT_PFRSTD;
5505 wr32(E1000_CTRL_EXT, reg_data);
5506
5507 igb_vmdq_set_loopback_pf(hw, true);
5508 igb_vmdq_set_replication_pf(hw, true);
5509 }
5510
5511 /* igb_main.c */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree