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iwlagn: fix scan tx antenna setting on 5Ghz band
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn-lib.c
blob3dee87e8f55dbdf1f09633f81cc54e8280a61dd0
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-io.h"
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
40 #include "iwl-agn.h"
41 #include "iwl-sta.h"
42
43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
44 {
45 return le32_to_cpup((__le32 *)&tx_resp->status +
46 tx_resp->frame_count) & MAX_SN;
47 }
48
49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
50 {
51 status &= TX_STATUS_MSK;
52
53 switch (status) {
54 case TX_STATUS_POSTPONE_DELAY:
55 priv->_agn.reply_tx_stats.pp_delay++;
56 break;
57 case TX_STATUS_POSTPONE_FEW_BYTES:
58 priv->_agn.reply_tx_stats.pp_few_bytes++;
59 break;
60 case TX_STATUS_POSTPONE_BT_PRIO:
61 priv->_agn.reply_tx_stats.pp_bt_prio++;
62 break;
63 case TX_STATUS_POSTPONE_QUIET_PERIOD:
64 priv->_agn.reply_tx_stats.pp_quiet_period++;
65 break;
66 case TX_STATUS_POSTPONE_CALC_TTAK:
67 priv->_agn.reply_tx_stats.pp_calc_ttak++;
68 break;
69 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
70 priv->_agn.reply_tx_stats.int_crossed_retry++;
71 break;
72 case TX_STATUS_FAIL_SHORT_LIMIT:
73 priv->_agn.reply_tx_stats.short_limit++;
74 break;
75 case TX_STATUS_FAIL_LONG_LIMIT:
76 priv->_agn.reply_tx_stats.long_limit++;
77 break;
78 case TX_STATUS_FAIL_FIFO_UNDERRUN:
79 priv->_agn.reply_tx_stats.fifo_underrun++;
80 break;
81 case TX_STATUS_FAIL_DRAIN_FLOW:
82 priv->_agn.reply_tx_stats.drain_flow++;
83 break;
84 case TX_STATUS_FAIL_RFKILL_FLUSH:
85 priv->_agn.reply_tx_stats.rfkill_flush++;
86 break;
87 case TX_STATUS_FAIL_LIFE_EXPIRE:
88 priv->_agn.reply_tx_stats.life_expire++;
89 break;
90 case TX_STATUS_FAIL_DEST_PS:
91 priv->_agn.reply_tx_stats.dest_ps++;
92 break;
93 case TX_STATUS_FAIL_HOST_ABORTED:
94 priv->_agn.reply_tx_stats.host_abort++;
95 break;
96 case TX_STATUS_FAIL_BT_RETRY:
97 priv->_agn.reply_tx_stats.bt_retry++;
98 break;
99 case TX_STATUS_FAIL_STA_INVALID:
100 priv->_agn.reply_tx_stats.sta_invalid++;
101 break;
102 case TX_STATUS_FAIL_FRAG_DROPPED:
103 priv->_agn.reply_tx_stats.frag_drop++;
104 break;
105 case TX_STATUS_FAIL_TID_DISABLE:
106 priv->_agn.reply_tx_stats.tid_disable++;
107 break;
108 case TX_STATUS_FAIL_FIFO_FLUSHED:
109 priv->_agn.reply_tx_stats.fifo_flush++;
110 break;
111 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
112 priv->_agn.reply_tx_stats.insuff_cf_poll++;
113 break;
114 case TX_STATUS_FAIL_PASSIVE_NO_RX:
115 priv->_agn.reply_tx_stats.fail_hw_drop++;
116 break;
117 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
118 priv->_agn.reply_tx_stats.sta_color_mismatch++;
119 break;
120 default:
121 priv->_agn.reply_tx_stats.unknown++;
122 break;
123 }
124 }
125
126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
127 {
128 status &= AGG_TX_STATUS_MSK;
129
130 switch (status) {
131 case AGG_TX_STATE_UNDERRUN_MSK:
132 priv->_agn.reply_agg_tx_stats.underrun++;
133 break;
134 case AGG_TX_STATE_BT_PRIO_MSK:
135 priv->_agn.reply_agg_tx_stats.bt_prio++;
136 break;
137 case AGG_TX_STATE_FEW_BYTES_MSK:
138 priv->_agn.reply_agg_tx_stats.few_bytes++;
139 break;
140 case AGG_TX_STATE_ABORT_MSK:
141 priv->_agn.reply_agg_tx_stats.abort++;
142 break;
143 case AGG_TX_STATE_LAST_SENT_TTL_MSK:
144 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
145 break;
146 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
147 priv->_agn.reply_agg_tx_stats.last_sent_try++;
148 break;
149 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
150 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
151 break;
152 case AGG_TX_STATE_SCD_QUERY_MSK:
153 priv->_agn.reply_agg_tx_stats.scd_query++;
154 break;
155 case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
156 priv->_agn.reply_agg_tx_stats.bad_crc32++;
157 break;
158 case AGG_TX_STATE_RESPONSE_MSK:
159 priv->_agn.reply_agg_tx_stats.response++;
160 break;
161 case AGG_TX_STATE_DUMP_TX_MSK:
162 priv->_agn.reply_agg_tx_stats.dump_tx++;
163 break;
164 case AGG_TX_STATE_DELAY_TX_MSK:
165 priv->_agn.reply_agg_tx_stats.delay_tx++;
166 break;
167 default:
168 priv->_agn.reply_agg_tx_stats.unknown++;
169 break;
170 }
171 }
172
173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
174 struct ieee80211_tx_info *info,
175 struct iwlagn_tx_resp *tx_resp,
176 int txq_id, bool is_agg)
177 {
178 u16 status = le16_to_cpu(tx_resp->status.status);
179
180 info->status.rates[0].count = tx_resp->failure_frame + 1;
181 if (is_agg)
182 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
183 info->flags |= iwl_tx_status_to_mac80211(status);
184 iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
185 info);
186 if (!iwl_is_tx_success(status))
187 iwlagn_count_tx_err_status(priv, status);
188
189 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
190 "0x%x retries %d\n",
191 txq_id,
192 iwl_get_tx_fail_reason(status), status,
193 le32_to_cpu(tx_resp->rate_n_flags),
194 tx_resp->failure_frame);
195 }
196
197 #ifdef CONFIG_IWLWIFI_DEBUG
198 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
199
200 const char *iwl_get_agg_tx_fail_reason(u16 status)
201 {
202 status &= AGG_TX_STATUS_MSK;
203 switch (status) {
204 case AGG_TX_STATE_TRANSMITTED:
205 return "SUCCESS";
206 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
207 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
208 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
209 AGG_TX_STATE_FAIL(ABORT_MSK);
210 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
211 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
212 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
213 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
214 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
215 AGG_TX_STATE_FAIL(RESPONSE_MSK);
216 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
217 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
218 }
219
220 return "UNKNOWN";
221 }
222 #endif /* CONFIG_IWLWIFI_DEBUG */
223
224 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
225 struct iwl_ht_agg *agg,
226 struct iwlagn_tx_resp *tx_resp,
227 int txq_id, u16 start_idx)
228 {
229 u16 status;
230 struct agg_tx_status *frame_status = &tx_resp->status;
231 struct ieee80211_hdr *hdr = NULL;
232 int i, sh, idx;
233 u16 seq;
234
235 if (agg->wait_for_ba)
236 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
237
238 agg->frame_count = tx_resp->frame_count;
239 agg->start_idx = start_idx;
240 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
241 agg->bitmap = 0;
242
243 /* # frames attempted by Tx command */
244 if (agg->frame_count == 1) {
245 /* Only one frame was attempted; no block-ack will arrive */
246 idx = start_idx;
247
248 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
249 agg->frame_count, agg->start_idx, idx);
250 iwlagn_set_tx_status(priv,
251 IEEE80211_SKB_CB(
252 priv->txq[txq_id].txb[idx].skb),
253 tx_resp, txq_id, true);
254 agg->wait_for_ba = 0;
255 } else {
256 /* Two or more frames were attempted; expect block-ack */
257 u64 bitmap = 0;
258
259 /*
260 * Start is the lowest frame sent. It may not be the first
261 * frame in the batch; we figure this out dynamically during
262 * the following loop.
263 */
264 int start = agg->start_idx;
265
266 /* Construct bit-map of pending frames within Tx window */
267 for (i = 0; i < agg->frame_count; i++) {
268 u16 sc;
269 status = le16_to_cpu(frame_status[i].status);
270 seq = le16_to_cpu(frame_status[i].sequence);
271 idx = SEQ_TO_INDEX(seq);
272 txq_id = SEQ_TO_QUEUE(seq);
273
274 if (status & AGG_TX_STATUS_MSK)
275 iwlagn_count_agg_tx_err_status(priv, status);
276
277 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
278 AGG_TX_STATE_ABORT_MSK))
279 continue;
280
281 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
282 agg->frame_count, txq_id, idx);
283 IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
284 "try-count (0x%08x)\n",
285 iwl_get_agg_tx_fail_reason(status),
286 status & AGG_TX_STATUS_MSK,
287 status & AGG_TX_TRY_MSK);
288
289 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
290 if (!hdr) {
291 IWL_ERR(priv,
292 "BUG_ON idx doesn't point to valid skb"
293 " idx=%d, txq_id=%d\n", idx, txq_id);
294 return -1;
295 }
296
297 sc = le16_to_cpu(hdr->seq_ctrl);
298 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
299 IWL_ERR(priv,
300 "BUG_ON idx doesn't match seq control"
301 " idx=%d, seq_idx=%d, seq=%d\n",
302 idx, SEQ_TO_SN(sc),
303 hdr->seq_ctrl);
304 return -1;
305 }
306
307 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
308 i, idx, SEQ_TO_SN(sc));
309
310 /*
311 * sh -> how many frames ahead of the starting frame is
312 * the current one?
313 *
314 * Note that all frames sent in the batch must be in a
315 * 64-frame window, so this number should be in [0,63].
316 * If outside of this window, then we've found a new
317 * "first" frame in the batch and need to change start.
318 */
319 sh = idx - start;
320
321 /*
322 * If >= 64, out of window. start must be at the front
323 * of the circular buffer, idx must be near the end of
324 * the buffer, and idx is the new "first" frame. Shift
325 * the indices around.
326 */
327 if (sh >= 64) {
328 /* Shift bitmap by start - idx, wrapped */
329 sh = 0x100 - idx + start;
330 bitmap = bitmap << sh;
331 /* Now idx is the new start so sh = 0 */
332 sh = 0;
333 start = idx;
334 /*
335 * If <= -64 then wraps the 256-pkt circular buffer
336 * (e.g., start = 255 and idx = 0, sh should be 1)
337 */
338 } else if (sh <= -64) {
339 sh = 0x100 - start + idx;
340 /*
341 * If < 0 but > -64, out of window. idx is before start
342 * but not wrapped. Shift the indices around.
343 */
344 } else if (sh < 0) {
345 /* Shift by how far start is ahead of idx */
346 sh = start - idx;
347 bitmap = bitmap << sh;
348 /* Now idx is the new start so sh = 0 */
349 start = idx;
350 sh = 0;
351 }
352 /* Sequence number start + sh was sent in this batch */
353 bitmap |= 1ULL << sh;
354 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
355 start, (unsigned long long)bitmap);
356 }
357
358 /*
359 * Store the bitmap and possibly the new start, if we wrapped
360 * the buffer above
361 */
362 agg->bitmap = bitmap;
363 agg->start_idx = start;
364 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
365 agg->frame_count, agg->start_idx,
366 (unsigned long long)agg->bitmap);
367
368 if (bitmap)
369 agg->wait_for_ba = 1;
370 }
371 return 0;
372 }
373
374 void iwl_check_abort_status(struct iwl_priv *priv,
375 u8 frame_count, u32 status)
376 {
377 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
378 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
379 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
380 queue_work(priv->workqueue, &priv->tx_flush);
381 }
382 }
383
384 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
385 struct iwl_rx_mem_buffer *rxb)
386 {
387 struct iwl_rx_packet *pkt = rxb_addr(rxb);
388 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
389 int txq_id = SEQ_TO_QUEUE(sequence);
390 int index = SEQ_TO_INDEX(sequence);
391 struct iwl_tx_queue *txq = &priv->txq[txq_id];
392 struct ieee80211_tx_info *info;
393 struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
394 u32 status = le16_to_cpu(tx_resp->status.status);
395 int tid;
396 int sta_id;
397 int freed;
398 unsigned long flags;
399
400 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
401 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
402 "is out of range [0-%d] %d %d\n", txq_id,
403 index, txq->q.n_bd, txq->q.write_ptr,
404 txq->q.read_ptr);
405 return;
406 }
407
408 txq->time_stamp = jiffies;
409 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
410 memset(&info->status, 0, sizeof(info->status));
411
412 tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
413 IWLAGN_TX_RES_TID_POS;
414 sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
415 IWLAGN_TX_RES_RA_POS;
416
417 spin_lock_irqsave(&priv->sta_lock, flags);
418 if (txq->sched_retry) {
419 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
420 struct iwl_ht_agg *agg;
421
422 agg = &priv->stations[sta_id].tid[tid].agg;
423 /*
424 * If the BT kill count is non-zero, we'll get this
425 * notification again.
426 */
427 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
428 priv->cfg->bt_params &&
429 priv->cfg->bt_params->advanced_bt_coexist) {
430 IWL_WARN(priv, "receive reply tx with bt_kill\n");
431 }
432 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
433
434 /* check if BAR is needed */
435 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
436 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
437
438 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
439 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
440 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
441 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
442 scd_ssn , index, txq_id, txq->swq_id);
443
444 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
445 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
446
447 if (priv->mac80211_registered &&
448 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
449 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
450 iwl_wake_queue(priv, txq);
451 }
452 } else {
453 iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
454 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
455 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
456
457 if (priv->mac80211_registered &&
458 (iwl_queue_space(&txq->q) > txq->q.low_mark))
459 iwl_wake_queue(priv, txq);
460 }
461
462 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
463
464 iwl_check_abort_status(priv, tx_resp->frame_count, status);
465 spin_unlock_irqrestore(&priv->sta_lock, flags);
466 }
467
468 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
469 {
470 /* init calibration handlers */
471 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
472 iwlagn_rx_calib_result;
473 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
474 iwlagn_rx_calib_complete;
475 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
476 }
477
478 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
479 {
480 /* in agn, the tx power calibration is done in uCode */
481 priv->disable_tx_power_cal = 1;
482 }
483
484 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
485 {
486 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
487 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
488 }
489
490 int iwlagn_send_tx_power(struct iwl_priv *priv)
491 {
492 struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
493 u8 tx_ant_cfg_cmd;
494
495 if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
496 "TX Power requested while scanning!\n"))
497 return -EAGAIN;
498
499 /* half dBm need to multiply */
500 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
501
502 if (priv->tx_power_lmt_in_half_dbm &&
503 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
504 /*
505 * For the newer devices which using enhanced/extend tx power
506 * table in EEPROM, the format is in half dBm. driver need to
507 * convert to dBm format before report to mac80211.
508 * By doing so, there is a possibility of 1/2 dBm resolution
509 * lost. driver will perform "round-up" operation before
510 * reporting, but it will cause 1/2 dBm tx power over the
511 * regulatory limit. Perform the checking here, if the
512 * "tx_power_user_lmt" is higher than EEPROM value (in
513 * half-dBm format), lower the tx power based on EEPROM
514 */
515 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
516 }
517 tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
518 tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
519
520 if (IWL_UCODE_API(priv->ucode_ver) == 1)
521 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
522 else
523 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
524
525 return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
526 &tx_power_cmd);
527 }
528
529 void iwlagn_temperature(struct iwl_priv *priv)
530 {
531 /* store temperature from statistics (in Celsius) */
532 priv->temperature =
533 le32_to_cpu(priv->_agn.statistics.general.common.temperature);
534 iwl_tt_handler(priv);
535 }
536
537 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
538 {
539 struct iwl_eeprom_calib_hdr {
540 u8 version;
541 u8 pa_type;
542 u16 voltage;
543 } *hdr;
544
545 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
546 EEPROM_CALIB_ALL);
547 return hdr->version;
548
549 }
550
551 /*
552 * EEPROM
553 */
554 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
555 {
556 u16 offset = 0;
557
558 if ((address & INDIRECT_ADDRESS) == 0)
559 return address;
560
561 switch (address & INDIRECT_TYPE_MSK) {
562 case INDIRECT_HOST:
563 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
564 break;
565 case INDIRECT_GENERAL:
566 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
567 break;
568 case INDIRECT_REGULATORY:
569 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
570 break;
571 case INDIRECT_TXP_LIMIT:
572 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
573 break;
574 case INDIRECT_TXP_LIMIT_SIZE:
575 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
576 break;
577 case INDIRECT_CALIBRATION:
578 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
579 break;
580 case INDIRECT_PROCESS_ADJST:
581 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
582 break;
583 case INDIRECT_OTHERS:
584 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
585 break;
586 default:
587 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
588 address & INDIRECT_TYPE_MSK);
589 break;
590 }
591
592 /* translate the offset from words to byte */
593 return (address & ADDRESS_MSK) + (offset << 1);
594 }
595
596 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
597 size_t offset)
598 {
599 u32 address = eeprom_indirect_address(priv, offset);
600 BUG_ON(address >= priv->cfg->base_params->eeprom_size);
601 return &priv->eeprom[address];
602 }
603
604 struct iwl_mod_params iwlagn_mod_params = {
605 .amsdu_size_8K = 1,
606 .restart_fw = 1,
607 /* the rest are 0 by default */
608 };
609
610 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
611 {
612 unsigned long flags;
613 int i;
614 spin_lock_irqsave(&rxq->lock, flags);
615 INIT_LIST_HEAD(&rxq->rx_free);
616 INIT_LIST_HEAD(&rxq->rx_used);
617 /* Fill the rx_used queue with _all_ of the Rx buffers */
618 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
619 /* In the reset function, these buffers may have been allocated
620 * to an SKB, so we need to unmap and free potential storage */
621 if (rxq->pool[i].page != NULL) {
622 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
623 PAGE_SIZE << priv->hw_params.rx_page_order,
624 PCI_DMA_FROMDEVICE);
625 __iwl_free_pages(priv, rxq->pool[i].page);
626 rxq->pool[i].page = NULL;
627 }
628 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
629 }
630
631 for (i = 0; i < RX_QUEUE_SIZE; i++)
632 rxq->queue[i] = NULL;
633
634 /* Set us so that we have processed and used all buffers, but have
635 * not restocked the Rx queue with fresh buffers */
636 rxq->read = rxq->write = 0;
637 rxq->write_actual = 0;
638 rxq->free_count = 0;
639 spin_unlock_irqrestore(&rxq->lock, flags);
640 }
641
642 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
643 {
644 u32 rb_size;
645 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
646 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
647
648 if (!priv->cfg->base_params->use_isr_legacy)
649 rb_timeout = RX_RB_TIMEOUT;
650
651 if (priv->cfg->mod_params->amsdu_size_8K)
652 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
653 else
654 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
655
656 /* Stop Rx DMA */
657 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
658
659 /* Reset driver's Rx queue write index */
660 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
661
662 /* Tell device where to find RBD circular buffer in DRAM */
663 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
664 (u32)(rxq->bd_dma >> 8));
665
666 /* Tell device where in DRAM to update its Rx status */
667 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
668 rxq->rb_stts_dma >> 4);
669
670 /* Enable Rx DMA
671 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
672 * the credit mechanism in 5000 HW RX FIFO
673 * Direct rx interrupts to hosts
674 * Rx buffer size 4 or 8k
675 * RB timeout 0x10
676 * 256 RBDs
677 */
678 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
679 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
680 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
681 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
682 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
683 rb_size|
684 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
685 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
686
687 /* Set interrupt coalescing timer to default (2048 usecs) */
688 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
689
690 return 0;
691 }
692
693 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
694 {
695 /*
696 * (for documentation purposes)
697 * to set power to V_AUX, do:
698
699 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
700 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
701 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
702 ~APMG_PS_CTRL_MSK_PWR_SRC);
703 */
704
705 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
706 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
707 ~APMG_PS_CTRL_MSK_PWR_SRC);
708 }
709
710 int iwlagn_hw_nic_init(struct iwl_priv *priv)
711 {
712 unsigned long flags;
713 struct iwl_rx_queue *rxq = &priv->rxq;
714 int ret;
715
716 /* nic_init */
717 spin_lock_irqsave(&priv->lock, flags);
718 priv->cfg->ops->lib->apm_ops.init(priv);
719
720 /* Set interrupt coalescing calibration timer to default (512 usecs) */
721 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
722
723 spin_unlock_irqrestore(&priv->lock, flags);
724
725 iwlagn_set_pwr_vmain(priv);
726
727 priv->cfg->ops->lib->apm_ops.config(priv);
728
729 /* Allocate the RX queue, or reset if it is already allocated */
730 if (!rxq->bd) {
731 ret = iwl_rx_queue_alloc(priv);
732 if (ret) {
733 IWL_ERR(priv, "Unable to initialize Rx queue\n");
734 return -ENOMEM;
735 }
736 } else
737 iwlagn_rx_queue_reset(priv, rxq);
738
739 iwlagn_rx_replenish(priv);
740
741 iwlagn_rx_init(priv, rxq);
742
743 spin_lock_irqsave(&priv->lock, flags);
744
745 rxq->need_update = 1;
746 iwl_rx_queue_update_write_ptr(priv, rxq);
747
748 spin_unlock_irqrestore(&priv->lock, flags);
749
750 /* Allocate or reset and init all Tx and Command queues */
751 if (!priv->txq) {
752 ret = iwlagn_txq_ctx_alloc(priv);
753 if (ret)
754 return ret;
755 } else
756 iwlagn_txq_ctx_reset(priv);
757
758 if (priv->cfg->base_params->shadow_reg_enable) {
759 /* enable shadow regs in HW */
760 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
761 0x800FFFFF);
762 }
763
764 set_bit(STATUS_INIT, &priv->status);
765
766 return 0;
767 }
768
769 /**
770 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
771 */
772 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
773 dma_addr_t dma_addr)
774 {
775 return cpu_to_le32((u32)(dma_addr >> 8));
776 }
777
778 /**
779 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
780 *
781 * If there are slots in the RX queue that need to be restocked,
782 * and we have free pre-allocated buffers, fill the ranks as much
783 * as we can, pulling from rx_free.
784 *
785 * This moves the 'write' index forward to catch up with 'processed', and
786 * also updates the memory address in the firmware to reference the new
787 * target buffer.
788 */
789 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
790 {
791 struct iwl_rx_queue *rxq = &priv->rxq;
792 struct list_head *element;
793 struct iwl_rx_mem_buffer *rxb;
794 unsigned long flags;
795
796 spin_lock_irqsave(&rxq->lock, flags);
797 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
798 /* The overwritten rxb must be a used one */
799 rxb = rxq->queue[rxq->write];
800 BUG_ON(rxb && rxb->page);
801
802 /* Get next free Rx buffer, remove from free list */
803 element = rxq->rx_free.next;
804 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
805 list_del(element);
806
807 /* Point to Rx buffer via next RBD in circular buffer */
808 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
809 rxb->page_dma);
810 rxq->queue[rxq->write] = rxb;
811 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
812 rxq->free_count--;
813 }
814 spin_unlock_irqrestore(&rxq->lock, flags);
815 /* If the pre-allocated buffer pool is dropping low, schedule to
816 * refill it */
817 if (rxq->free_count <= RX_LOW_WATERMARK)
818 queue_work(priv->workqueue, &priv->rx_replenish);
819
820
821 /* If we've added more space for the firmware to place data, tell it.
822 * Increment device's write pointer in multiples of 8. */
823 if (rxq->write_actual != (rxq->write & ~0x7)) {
824 spin_lock_irqsave(&rxq->lock, flags);
825 rxq->need_update = 1;
826 spin_unlock_irqrestore(&rxq->lock, flags);
827 iwl_rx_queue_update_write_ptr(priv, rxq);
828 }
829 }
830
831 /**
832 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
833 *
834 * When moving to rx_free an SKB is allocated for the slot.
835 *
836 * Also restock the Rx queue via iwl_rx_queue_restock.
837 * This is called as a scheduled work item (except for during initialization)
838 */
839 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
840 {
841 struct iwl_rx_queue *rxq = &priv->rxq;
842 struct list_head *element;
843 struct iwl_rx_mem_buffer *rxb;
844 struct page *page;
845 unsigned long flags;
846 gfp_t gfp_mask = priority;
847
848 while (1) {
849 spin_lock_irqsave(&rxq->lock, flags);
850 if (list_empty(&rxq->rx_used)) {
851 spin_unlock_irqrestore(&rxq->lock, flags);
852 return;
853 }
854 spin_unlock_irqrestore(&rxq->lock, flags);
855
856 if (rxq->free_count > RX_LOW_WATERMARK)
857 gfp_mask |= __GFP_NOWARN;
858
859 if (priv->hw_params.rx_page_order > 0)
860 gfp_mask |= __GFP_COMP;
861
862 /* Alloc a new receive buffer */
863 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
864 if (!page) {
865 if (net_ratelimit())
866 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
867 "order: %d\n",
868 priv->hw_params.rx_page_order);
869
870 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
871 net_ratelimit())
872 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
873 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
874 rxq->free_count);
875 /* We don't reschedule replenish work here -- we will
876 * call the restock method and if it still needs
877 * more buffers it will schedule replenish */
878 return;
879 }
880
881 spin_lock_irqsave(&rxq->lock, flags);
882
883 if (list_empty(&rxq->rx_used)) {
884 spin_unlock_irqrestore(&rxq->lock, flags);
885 __free_pages(page, priv->hw_params.rx_page_order);
886 return;
887 }
888 element = rxq->rx_used.next;
889 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
890 list_del(element);
891
892 spin_unlock_irqrestore(&rxq->lock, flags);
893
894 BUG_ON(rxb->page);
895 rxb->page = page;
896 /* Get physical address of the RB */
897 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
898 PAGE_SIZE << priv->hw_params.rx_page_order,
899 PCI_DMA_FROMDEVICE);
900 /* dma address must be no more than 36 bits */
901 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
902 /* and also 256 byte aligned! */
903 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
904
905 spin_lock_irqsave(&rxq->lock, flags);
906
907 list_add_tail(&rxb->list, &rxq->rx_free);
908 rxq->free_count++;
909 priv->alloc_rxb_page++;
910
911 spin_unlock_irqrestore(&rxq->lock, flags);
912 }
913 }
914
915 void iwlagn_rx_replenish(struct iwl_priv *priv)
916 {
917 unsigned long flags;
918
919 iwlagn_rx_allocate(priv, GFP_KERNEL);
920
921 spin_lock_irqsave(&priv->lock, flags);
922 iwlagn_rx_queue_restock(priv);
923 spin_unlock_irqrestore(&priv->lock, flags);
924 }
925
926 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
927 {
928 iwlagn_rx_allocate(priv, GFP_ATOMIC);
929
930 iwlagn_rx_queue_restock(priv);
931 }
932
933 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
934 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
935 * This free routine walks the list of POOL entries and if SKB is set to
936 * non NULL it is unmapped and freed
937 */
938 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
939 {
940 int i;
941 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
942 if (rxq->pool[i].page != NULL) {
943 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
944 PAGE_SIZE << priv->hw_params.rx_page_order,
945 PCI_DMA_FROMDEVICE);
946 __iwl_free_pages(priv, rxq->pool[i].page);
947 rxq->pool[i].page = NULL;
948 }
949 }
950
951 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
952 rxq->bd_dma);
953 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
954 rxq->rb_stts, rxq->rb_stts_dma);
955 rxq->bd = NULL;
956 rxq->rb_stts = NULL;
957 }
958
959 int iwlagn_rxq_stop(struct iwl_priv *priv)
960 {
961
962 /* stop Rx DMA */
963 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
964 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
965 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
966
967 return 0;
968 }
969
970 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
971 {
972 int idx = 0;
973 int band_offset = 0;
974
975 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
976 if (rate_n_flags & RATE_MCS_HT_MSK) {
977 idx = (rate_n_flags & 0xff);
978 return idx;
979 /* Legacy rate format, search for match in table */
980 } else {
981 if (band == IEEE80211_BAND_5GHZ)
982 band_offset = IWL_FIRST_OFDM_RATE;
983 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
984 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
985 return idx - band_offset;
986 }
987
988 return -1;
989 }
990
991 /* Calc max signal level (dBm) among 3 possible receivers */
992 static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
993 struct iwl_rx_phy_res *rx_resp)
994 {
995 return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
996 }
997
998 static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
999 {
1000 u32 decrypt_out = 0;
1001
1002 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
1003 RX_RES_STATUS_STATION_FOUND)
1004 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
1005 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
1006
1007 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
1008
1009 /* packet was not encrypted */
1010 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
1011 RX_RES_STATUS_SEC_TYPE_NONE)
1012 return decrypt_out;
1013
1014 /* packet was encrypted with unknown alg */
1015 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
1016 RX_RES_STATUS_SEC_TYPE_ERR)
1017 return decrypt_out;
1018
1019 /* decryption was not done in HW */
1020 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
1021 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
1022 return decrypt_out;
1023
1024 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
1025
1026 case RX_RES_STATUS_SEC_TYPE_CCMP:
1027 /* alg is CCM: check MIC only */
1028 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
1029 /* Bad MIC */
1030 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1031 else
1032 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1033
1034 break;
1035
1036 case RX_RES_STATUS_SEC_TYPE_TKIP:
1037 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
1038 /* Bad TTAK */
1039 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
1040 break;
1041 }
1042 /* fall through if TTAK OK */
1043 default:
1044 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
1045 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1046 else
1047 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1048 break;
1049 }
1050
1051 IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
1052 decrypt_in, decrypt_out);
1053
1054 return decrypt_out;
1055 }
1056
1057 static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
1058 struct ieee80211_hdr *hdr,
1059 u16 len,
1060 u32 ampdu_status,
1061 struct iwl_rx_mem_buffer *rxb,
1062 struct ieee80211_rx_status *stats)
1063 {
1064 struct sk_buff *skb;
1065 __le16 fc = hdr->frame_control;
1066
1067 /* We only process data packets if the interface is open */
1068 if (unlikely(!priv->is_open)) {
1069 IWL_DEBUG_DROP_LIMIT(priv,
1070 "Dropping packet while interface is not open.\n");
1071 return;
1072 }
1073
1074 /* In case of HW accelerated crypto and bad decryption, drop */
1075 if (!priv->cfg->mod_params->sw_crypto &&
1076 iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
1077 return;
1078
1079 skb = dev_alloc_skb(128);
1080 if (!skb) {
1081 IWL_ERR(priv, "dev_alloc_skb failed\n");
1082 return;
1083 }
1084
1085 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
1086
1087 iwl_update_stats(priv, false, fc, len);
1088 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
1089
1090 ieee80211_rx(priv->hw, skb);
1091 priv->alloc_rxb_page--;
1092 rxb->page = NULL;
1093 }
1094
1095 /* Called for REPLY_RX (legacy ABG frames), or
1096 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
1097 void iwlagn_rx_reply_rx(struct iwl_priv *priv,
1098 struct iwl_rx_mem_buffer *rxb)
1099 {
1100 struct ieee80211_hdr *header;
1101 struct ieee80211_rx_status rx_status;
1102 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1103 struct iwl_rx_phy_res *phy_res;
1104 __le32 rx_pkt_status;
1105 struct iwl_rx_mpdu_res_start *amsdu;
1106 u32 len;
1107 u32 ampdu_status;
1108 u32 rate_n_flags;
1109
1110 /**
1111 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
1112 * REPLY_RX: physical layer info is in this buffer
1113 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
1114 * command and cached in priv->last_phy_res
1115 *
1116 * Here we set up local variables depending on which command is
1117 * received.
1118 */
1119 if (pkt->hdr.cmd == REPLY_RX) {
1120 phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
1121 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
1122 + phy_res->cfg_phy_cnt);
1123
1124 len = le16_to_cpu(phy_res->byte_count);
1125 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
1126 phy_res->cfg_phy_cnt + len);
1127 ampdu_status = le32_to_cpu(rx_pkt_status);
1128 } else {
1129 if (!priv->_agn.last_phy_res_valid) {
1130 IWL_ERR(priv, "MPDU frame without cached PHY data\n");
1131 return;
1132 }
1133 phy_res = &priv->_agn.last_phy_res;
1134 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
1135 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
1136 len = le16_to_cpu(amsdu->byte_count);
1137 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
1138 ampdu_status = iwlagn_translate_rx_status(priv,
1139 le32_to_cpu(rx_pkt_status));
1140 }
1141
1142 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
1143 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
1144 phy_res->cfg_phy_cnt);
1145 return;
1146 }
1147
1148 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
1149 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
1150 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
1151 le32_to_cpu(rx_pkt_status));
1152 return;
1153 }
1154
1155 /* This will be used in several places later */
1156 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
1157
1158 /* rx_status carries information about the packet to mac80211 */
1159 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
1160 rx_status.freq =
1161 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
1162 rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
1163 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1164 rx_status.rate_idx =
1165 iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
1166 rx_status.flag = 0;
1167
1168 /* TSF isn't reliable. In order to allow smooth user experience,
1169 * this W/A doesn't propagate it to the mac80211 */
1170 /*rx_status.flag |= RX_FLAG_TSFT;*/
1171
1172 priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
1173
1174 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1175 rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
1176
1177 iwl_dbg_log_rx_data_frame(priv, len, header);
1178 IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
1179 rx_status.signal, (unsigned long long)rx_status.mactime);
1180
1181 /*
1182 * "antenna number"
1183 *
1184 * It seems that the antenna field in the phy flags value
1185 * is actually a bit field. This is undefined by radiotap,
1186 * it wants an actual antenna number but I always get "7"
1187 * for most legacy frames I receive indicating that the
1188 * same frame was received on all three RX chains.
1189 *
1190 * I think this field should be removed in favor of a
1191 * new 802.11n radiotap field "RX chains" that is defined
1192 * as a bitmask.
1193 */
1194 rx_status.antenna =
1195 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
1196 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
1197
1198 /* set the preamble flag if appropriate */
1199 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
1200 rx_status.flag |= RX_FLAG_SHORTPRE;
1201
1202 /* Set up the HT phy flags */
1203 if (rate_n_flags & RATE_MCS_HT_MSK)
1204 rx_status.flag |= RX_FLAG_HT;
1205 if (rate_n_flags & RATE_MCS_HT40_MSK)
1206 rx_status.flag |= RX_FLAG_40MHZ;
1207 if (rate_n_flags & RATE_MCS_SGI_MSK)
1208 rx_status.flag |= RX_FLAG_SHORT_GI;
1209
1210 iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
1211 rxb, &rx_status);
1212 }
1213
1214 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1215 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1216 void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
1217 struct iwl_rx_mem_buffer *rxb)
1218 {
1219 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1220 priv->_agn.last_phy_res_valid = true;
1221 memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
1222 sizeof(struct iwl_rx_phy_res));
1223 }
1224
1225 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1226 struct ieee80211_vif *vif,
1227 enum ieee80211_band band,
1228 struct iwl_scan_channel *scan_ch)
1229 {
1230 const struct ieee80211_supported_band *sband;
1231 u16 passive_dwell = 0;
1232 u16 active_dwell = 0;
1233 int added = 0;
1234 u16 channel = 0;
1235
1236 sband = iwl_get_hw_mode(priv, band);
1237 if (!sband) {
1238 IWL_ERR(priv, "invalid band\n");
1239 return added;
1240 }
1241
1242 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1243 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1244
1245 if (passive_dwell <= active_dwell)
1246 passive_dwell = active_dwell + 1;
1247
1248 channel = iwl_get_single_channel_number(priv, band);
1249 if (channel) {
1250 scan_ch->channel = cpu_to_le16(channel);
1251 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1252 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1253 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1254 /* Set txpower levels to defaults */
1255 scan_ch->dsp_atten = 110;
1256 if (band == IEEE80211_BAND_5GHZ)
1257 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1258 else
1259 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1260 added++;
1261 } else
1262 IWL_ERR(priv, "no valid channel found\n");
1263 return added;
1264 }
1265
1266 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1267 struct ieee80211_vif *vif,
1268 enum ieee80211_band band,
1269 u8 is_active, u8 n_probes,
1270 struct iwl_scan_channel *scan_ch)
1271 {
1272 struct ieee80211_channel *chan;
1273 const struct ieee80211_supported_band *sband;
1274 const struct iwl_channel_info *ch_info;
1275 u16 passive_dwell = 0;
1276 u16 active_dwell = 0;
1277 int added, i;
1278 u16 channel;
1279
1280 sband = iwl_get_hw_mode(priv, band);
1281 if (!sband)
1282 return 0;
1283
1284 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1285 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1286
1287 if (passive_dwell <= active_dwell)
1288 passive_dwell = active_dwell + 1;
1289
1290 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1291 chan = priv->scan_request->channels[i];
1292
1293 if (chan->band != band)
1294 continue;
1295
1296 channel = chan->hw_value;
1297 scan_ch->channel = cpu_to_le16(channel);
1298
1299 ch_info = iwl_get_channel_info(priv, band, channel);
1300 if (!is_channel_valid(ch_info)) {
1301 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1302 channel);
1303 continue;
1304 }
1305
1306 if (!is_active || is_channel_passive(ch_info) ||
1307 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1308 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1309 else
1310 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1311
1312 if (n_probes)
1313 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1314
1315 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1316 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1317
1318 /* Set txpower levels to defaults */
1319 scan_ch->dsp_atten = 110;
1320
1321 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1322 * power level:
1323 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1324 */
1325 if (band == IEEE80211_BAND_5GHZ)
1326 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1327 else
1328 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1329
1330 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1331 channel, le32_to_cpu(scan_ch->type),
1332 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1333 "ACTIVE" : "PASSIVE",
1334 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1335 active_dwell : passive_dwell);
1336
1337 scan_ch++;
1338 added++;
1339 }
1340
1341 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1342 return added;
1343 }
1344
1345 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1346 {
1347 struct iwl_host_cmd cmd = {
1348 .id = REPLY_SCAN_CMD,
1349 .len = sizeof(struct iwl_scan_cmd),
1350 .flags = CMD_SIZE_HUGE,
1351 };
1352 struct iwl_scan_cmd *scan;
1353 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1354 u32 rate_flags = 0;
1355 u16 cmd_len;
1356 u16 rx_chain = 0;
1357 enum ieee80211_band band;
1358 u8 n_probes = 0;
1359 u8 rx_ant = priv->hw_params.valid_rx_ant;
1360 u8 rate;
1361 bool is_active = false;
1362 int chan_mod;
1363 u8 active_chains;
1364 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1365 int ret;
1366
1367 lockdep_assert_held(&priv->mutex);
1368
1369 if (vif)
1370 ctx = iwl_rxon_ctx_from_vif(vif);
1371
1372 if (!priv->scan_cmd) {
1373 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1374 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1375 if (!priv->scan_cmd) {
1376 IWL_DEBUG_SCAN(priv,
1377 "fail to allocate memory for scan\n");
1378 return -ENOMEM;
1379 }
1380 }
1381 scan = priv->scan_cmd;
1382 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1383
1384 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1385 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1386
1387 if (iwl_is_any_associated(priv)) {
1388 u16 interval = 0;
1389 u32 extra;
1390 u32 suspend_time = 100;
1391 u32 scan_suspend_time = 100;
1392 unsigned long flags;
1393
1394 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1395 spin_lock_irqsave(&priv->lock, flags);
1396 if (priv->is_internal_short_scan)
1397 interval = 0;
1398 else
1399 interval = vif->bss_conf.beacon_int;
1400 spin_unlock_irqrestore(&priv->lock, flags);
1401
1402 scan->suspend_time = 0;
1403 scan->max_out_time = cpu_to_le32(200 * 1024);
1404 if (!interval)
1405 interval = suspend_time;
1406
1407 extra = (suspend_time / interval) << 22;
1408 scan_suspend_time = (extra |
1409 ((suspend_time % interval) * 1024));
1410 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1411 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1412 scan_suspend_time, interval);
1413 }
1414
1415 if (priv->is_internal_short_scan) {
1416 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1417 } else if (priv->scan_request->n_ssids) {
1418 int i, p = 0;
1419 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1420 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1421 /* always does wildcard anyway */
1422 if (!priv->scan_request->ssids[i].ssid_len)
1423 continue;
1424 scan->direct_scan[p].id = WLAN_EID_SSID;
1425 scan->direct_scan[p].len =
1426 priv->scan_request->ssids[i].ssid_len;
1427 memcpy(scan->direct_scan[p].ssid,
1428 priv->scan_request->ssids[i].ssid,
1429 priv->scan_request->ssids[i].ssid_len);
1430 n_probes++;
1431 p++;
1432 }
1433 is_active = true;
1434 } else
1435 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1436
1437 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1438 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1439 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1440
1441 switch (priv->scan_band) {
1442 case IEEE80211_BAND_2GHZ:
1443 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1444 chan_mod = le32_to_cpu(
1445 priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1446 RXON_FLG_CHANNEL_MODE_MSK)
1447 >> RXON_FLG_CHANNEL_MODE_POS;
1448 if (chan_mod == CHANNEL_MODE_PURE_40) {
1449 rate = IWL_RATE_6M_PLCP;
1450 } else {
1451 rate = IWL_RATE_1M_PLCP;
1452 rate_flags = RATE_MCS_CCK_MSK;
1453 }
1454 /*
1455 * Internal scans are passive, so we can indiscriminately set
1456 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1457 */
1458 if (priv->cfg->bt_params &&
1459 priv->cfg->bt_params->advanced_bt_coexist)
1460 scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1461 break;
1462 case IEEE80211_BAND_5GHZ:
1463 rate = IWL_RATE_6M_PLCP;
1464 break;
1465 default:
1466 IWL_WARN(priv, "Invalid scan band\n");
1467 return -EIO;
1468 }
1469
1470 /*
1471 * If active scanning is requested but a certain channel is
1472 * marked passive, we can do active scanning if we detect
1473 * transmissions.
1474 *
1475 * There is an issue with some firmware versions that triggers
1476 * a sysassert on a "good CRC threshold" of zero (== disabled),
1477 * on a radar channel even though this means that we should NOT
1478 * send probes.
1479 *
1480 * The "good CRC threshold" is the number of frames that we
1481 * need to receive during our dwell time on a channel before
1482 * sending out probes -- setting this to a huge value will
1483 * mean we never reach it, but at the same time work around
1484 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1485 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1486 */
1487 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1488 IWL_GOOD_CRC_TH_NEVER;
1489
1490 band = priv->scan_band;
1491
1492 if (priv->cfg->scan_rx_antennas[band])
1493 rx_ant = priv->cfg->scan_rx_antennas[band];
1494
1495 if (band == IEEE80211_BAND_2GHZ &&
1496 priv->cfg->bt_params &&
1497 priv->cfg->bt_params->advanced_bt_coexist) {
1498 /* transmit 2.4 GHz probes only on first antenna */
1499 scan_tx_antennas = first_antenna(scan_tx_antennas);
1500 }
1501
1502 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1503 scan_tx_antennas);
1504 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1505 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1506
1507 /* In power save mode use one chain, otherwise use all chains */
1508 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1509 /* rx_ant has been set to all valid chains previously */
1510 active_chains = rx_ant &
1511 ((u8)(priv->chain_noise_data.active_chains));
1512 if (!active_chains)
1513 active_chains = rx_ant;
1514
1515 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1516 priv->chain_noise_data.active_chains);
1517
1518 rx_ant = first_antenna(active_chains);
1519 }
1520 if (priv->cfg->bt_params &&
1521 priv->cfg->bt_params->advanced_bt_coexist &&
1522 priv->bt_full_concurrent) {
1523 /* operated as 1x1 in full concurrency mode */
1524 rx_ant = first_antenna(rx_ant);
1525 }
1526
1527 /* MIMO is not used here, but value is required */
1528 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1529 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1530 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1531 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1532 scan->rx_chain = cpu_to_le16(rx_chain);
1533 if (!priv->is_internal_short_scan) {
1534 cmd_len = iwl_fill_probe_req(priv,
1535 (struct ieee80211_mgmt *)scan->data,
1536 vif->addr,
1537 priv->scan_request->ie,
1538 priv->scan_request->ie_len,
1539 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1540 } else {
1541 /* use bcast addr, will not be transmitted but must be valid */
1542 cmd_len = iwl_fill_probe_req(priv,
1543 (struct ieee80211_mgmt *)scan->data,
1544 iwl_bcast_addr, NULL, 0,
1545 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1546
1547 }
1548 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1549
1550 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1551 RXON_FILTER_BCON_AWARE_MSK);
1552
1553 if (priv->is_internal_short_scan) {
1554 scan->channel_count =
1555 iwl_get_single_channel_for_scan(priv, vif, band,
1556 (void *)&scan->data[le16_to_cpu(
1557 scan->tx_cmd.len)]);
1558 } else {
1559 scan->channel_count =
1560 iwl_get_channels_for_scan(priv, vif, band,
1561 is_active, n_probes,
1562 (void *)&scan->data[le16_to_cpu(
1563 scan->tx_cmd.len)]);
1564 }
1565 if (scan->channel_count == 0) {
1566 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1567 return -EIO;
1568 }
1569
1570 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1571 scan->channel_count * sizeof(struct iwl_scan_channel);
1572 cmd.data = scan;
1573 scan->len = cpu_to_le16(cmd.len);
1574
1575 /* set scan bit here for PAN params */
1576 set_bit(STATUS_SCAN_HW, &priv->status);
1577
1578 if (priv->cfg->ops->hcmd->set_pan_params) {
1579 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1580 if (ret)
1581 return ret;
1582 }
1583
1584 ret = iwl_send_cmd_sync(priv, &cmd);
1585 if (ret) {
1586 clear_bit(STATUS_SCAN_HW, &priv->status);
1587 if (priv->cfg->ops->hcmd->set_pan_params)
1588 priv->cfg->ops->hcmd->set_pan_params(priv);
1589 }
1590
1591 return ret;
1592 }
1593
1594 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1595 struct ieee80211_vif *vif, bool add)
1596 {
1597 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1598
1599 if (add)
1600 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1601 vif->bss_conf.bssid,
1602 &vif_priv->ibss_bssid_sta_id);
1603 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1604 vif->bss_conf.bssid);
1605 }
1606
1607 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1608 int sta_id, int tid, int freed)
1609 {
1610 lockdep_assert_held(&priv->sta_lock);
1611
1612 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1613 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1614 else {
1615 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1616 priv->stations[sta_id].tid[tid].tfds_in_queue,
1617 freed);
1618 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1619 }
1620 }
1621
1622 #define IWL_FLUSH_WAIT_MS 2000
1623
1624 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1625 {
1626 struct iwl_tx_queue *txq;
1627 struct iwl_queue *q;
1628 int cnt;
1629 unsigned long now = jiffies;
1630 int ret = 0;
1631
1632 /* waiting for all the tx frames complete might take a while */
1633 for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1634 if (cnt == priv->cmd_queue)
1635 continue;
1636 txq = &priv->txq[cnt];
1637 q = &txq->q;
1638 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1639 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1640 msleep(1);
1641
1642 if (q->read_ptr != q->write_ptr) {
1643 IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1644 ret = -ETIMEDOUT;
1645 break;
1646 }
1647 }
1648 return ret;
1649 }
1650
1651 #define IWL_TX_QUEUE_MSK 0xfffff
1652
1653 /**
1654 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1655 *
1656 * pre-requirements:
1657 * 1. acquire mutex before calling
1658 * 2. make sure rf is on and not in exit state
1659 */
1660 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1661 {
1662 struct iwl_txfifo_flush_cmd flush_cmd;
1663 struct iwl_host_cmd cmd = {
1664 .id = REPLY_TXFIFO_FLUSH,
1665 .len = sizeof(struct iwl_txfifo_flush_cmd),
1666 .flags = CMD_SYNC,
1667 .data = &flush_cmd,
1668 };
1669
1670 might_sleep();
1671
1672 memset(&flush_cmd, 0, sizeof(flush_cmd));
1673 flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1674 IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1675 if (priv->cfg->sku & IWL_SKU_N)
1676 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1677
1678 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1679 flush_cmd.fifo_control);
1680 flush_cmd.flush_control = cpu_to_le16(flush_control);
1681
1682 return iwl_send_cmd(priv, &cmd);
1683 }
1684
1685 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1686 {
1687 mutex_lock(&priv->mutex);
1688 ieee80211_stop_queues(priv->hw);
1689 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1690 IWL_ERR(priv, "flush request fail\n");
1691 goto done;
1692 }
1693 IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1694 iwlagn_wait_tx_queue_empty(priv);
1695 done:
1696 ieee80211_wake_queues(priv->hw);
1697 mutex_unlock(&priv->mutex);
1698 }
1699
1700 /*
1701 * BT coex
1702 */
1703 /*
1704 * Macros to access the lookup table.
1705 *
1706 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1707 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1708 *
1709 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1710 *
1711 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1712 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1713 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1714 *
1715 * These macros encode that format.
1716 */
1717 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1718 wifi_txrx, wifi_sh_ant_req) \
1719 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1720 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1721
1722 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1723 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1724 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1725 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1726 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1727 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1728 wifi_sh_ant_req))))
1729 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1730 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1731 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1732 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1733 wifi_sh_ant_req))
1734 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1735 wifi_req, wifi_prio, wifi_txrx, \
1736 wifi_sh_ant_req) \
1737 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1738 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1739 wifi_sh_ant_req))
1740
1741 #define LUT_WLAN_KILL_OP(lut, op, val) \
1742 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1743 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1744 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1745 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1746 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1747 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1748 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1749 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1750 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1751 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1752 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1753 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1754 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1755
1756 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1757 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1758 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1759 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1760 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1761 wifi_req, wifi_prio, wifi_txrx, \
1762 wifi_sh_ant_req))))
1763 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1764 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1765 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1766 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1767 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1768 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1769 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1770 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1771
1772 static const __le32 iwlagn_def_3w_lookup[12] = {
1773 cpu_to_le32(0xaaaaaaaa),
1774 cpu_to_le32(0xaaaaaaaa),
1775 cpu_to_le32(0xaeaaaaaa),
1776 cpu_to_le32(0xaaaaaaaa),
1777 cpu_to_le32(0xcc00ff28),
1778 cpu_to_le32(0x0000aaaa),
1779 cpu_to_le32(0xcc00aaaa),
1780 cpu_to_le32(0x0000aaaa),
1781 cpu_to_le32(0xc0004000),
1782 cpu_to_le32(0x00004000),
1783 cpu_to_le32(0xf0005000),
1784 cpu_to_le32(0xf0005000),
1785 };
1786
1787 static const __le32 iwlagn_concurrent_lookup[12] = {
1788 cpu_to_le32(0xaaaaaaaa),
1789 cpu_to_le32(0xaaaaaaaa),
1790 cpu_to_le32(0xaaaaaaaa),
1791 cpu_to_le32(0xaaaaaaaa),
1792 cpu_to_le32(0xaaaaaaaa),
1793 cpu_to_le32(0xaaaaaaaa),
1794 cpu_to_le32(0xaaaaaaaa),
1795 cpu_to_le32(0xaaaaaaaa),
1796 cpu_to_le32(0x00000000),
1797 cpu_to_le32(0x00000000),
1798 cpu_to_le32(0x00000000),
1799 cpu_to_le32(0x00000000),
1800 };
1801
1802 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1803 {
1804 struct iwlagn_bt_cmd bt_cmd = {
1805 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1806 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1807 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1808 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1809 };
1810
1811 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1812 sizeof(bt_cmd.bt3_lookup_table));
1813
1814 if (priv->cfg->bt_params)
1815 bt_cmd.prio_boost = priv->cfg->bt_params->bt_prio_boost;
1816 else
1817 bt_cmd.prio_boost = 0;
1818 bt_cmd.kill_ack_mask = priv->kill_ack_mask;
1819 bt_cmd.kill_cts_mask = priv->kill_cts_mask;
1820
1821 bt_cmd.valid = priv->bt_valid;
1822 bt_cmd.tx_prio_boost = 0;
1823 bt_cmd.rx_prio_boost = 0;
1824
1825 /*
1826 * Configure BT coex mode to "no coexistence" when the
1827 * user disabled BT coexistence, we have no interface
1828 * (might be in monitor mode), or the interface is in
1829 * IBSS mode (no proper uCode support for coex then).
1830 */
1831 if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1832 bt_cmd.flags = 0;
1833 } else {
1834 bt_cmd.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1835 IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1836 if (priv->cfg->bt_params &&
1837 priv->cfg->bt_params->bt_sco_disable)
1838 bt_cmd.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1839
1840 if (priv->bt_ch_announce)
1841 bt_cmd.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1842 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", bt_cmd.flags);
1843 }
1844 priv->bt_enable_flag = bt_cmd.flags;
1845 if (priv->bt_full_concurrent)
1846 memcpy(bt_cmd.bt3_lookup_table, iwlagn_concurrent_lookup,
1847 sizeof(iwlagn_concurrent_lookup));
1848 else
1849 memcpy(bt_cmd.bt3_lookup_table, iwlagn_def_3w_lookup,
1850 sizeof(iwlagn_def_3w_lookup));
1851
1852 IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1853 bt_cmd.flags ? "active" : "disabled",
1854 priv->bt_full_concurrent ?
1855 "full concurrency" : "3-wire");
1856
1857 if (iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, sizeof(bt_cmd), &bt_cmd))
1858 IWL_ERR(priv, "failed to send BT Coex Config\n");
1859
1860 /*
1861 * When we are doing a restart, need to also reconfigure BT
1862 * SCO to the device. If not doing a restart, bt_sco_active
1863 * will always be false, so there's no need to have an extra
1864 * variable to check for it.
1865 */
1866 if (priv->bt_sco_active) {
1867 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
1868
1869 if (priv->bt_sco_active)
1870 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
1871 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_SCO,
1872 sizeof(sco_cmd), &sco_cmd))
1873 IWL_ERR(priv, "failed to send BT SCO command\n");
1874 }
1875 }
1876
1877 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1878 {
1879 struct iwl_priv *priv =
1880 container_of(work, struct iwl_priv, bt_traffic_change_work);
1881 struct iwl_rxon_context *ctx;
1882 int smps_request = -1;
1883
1884 /*
1885 * Note: bt_traffic_load can be overridden by scan complete and
1886 * coex profile notifications. Ignore that since only bad consequence
1887 * can be not matching debug print with actual state.
1888 */
1889 IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1890 priv->bt_traffic_load);
1891
1892 switch (priv->bt_traffic_load) {
1893 case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1894 if (priv->bt_status)
1895 smps_request = IEEE80211_SMPS_DYNAMIC;
1896 else
1897 smps_request = IEEE80211_SMPS_AUTOMATIC;
1898 break;
1899 case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1900 smps_request = IEEE80211_SMPS_DYNAMIC;
1901 break;
1902 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1903 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1904 smps_request = IEEE80211_SMPS_STATIC;
1905 break;
1906 default:
1907 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1908 priv->bt_traffic_load);
1909 break;
1910 }
1911
1912 mutex_lock(&priv->mutex);
1913
1914 /*
1915 * We can not send command to firmware while scanning. When the scan
1916 * complete we will schedule this work again. We do check with mutex
1917 * locked to prevent new scan request to arrive. We do not check
1918 * STATUS_SCANNING to avoid race when queue_work two times from
1919 * different notifications, but quit and not perform any work at all.
1920 */
1921 if (test_bit(STATUS_SCAN_HW, &priv->status))
1922 goto out;
1923
1924 if (priv->cfg->ops->lib->update_chain_flags)
1925 priv->cfg->ops->lib->update_chain_flags(priv);
1926
1927 if (smps_request != -1) {
1928 for_each_context(priv, ctx) {
1929 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1930 ieee80211_request_smps(ctx->vif, smps_request);
1931 }
1932 }
1933 out:
1934 mutex_unlock(&priv->mutex);
1935 }
1936
1937 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1938 struct iwl_bt_uart_msg *uart_msg)
1939 {
1940 IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1941 "Update Req = 0x%X",
1942 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1943 BT_UART_MSG_FRAME1MSGTYPE_POS,
1944 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1945 BT_UART_MSG_FRAME1SSN_POS,
1946 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1947 BT_UART_MSG_FRAME1UPDATEREQ_POS);
1948
1949 IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1950 "Chl_SeqN = 0x%X, In band = 0x%X",
1951 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1952 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1953 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1954 BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1955 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1956 BT_UART_MSG_FRAME2CHLSEQN_POS,
1957 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1958 BT_UART_MSG_FRAME2INBAND_POS);
1959
1960 IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1961 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1962 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1963 BT_UART_MSG_FRAME3SCOESCO_POS,
1964 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1965 BT_UART_MSG_FRAME3SNIFF_POS,
1966 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1967 BT_UART_MSG_FRAME3A2DP_POS,
1968 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1969 BT_UART_MSG_FRAME3ACL_POS,
1970 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1971 BT_UART_MSG_FRAME3MASTER_POS,
1972 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1973 BT_UART_MSG_FRAME3OBEX_POS);
1974
1975 IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1976 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1977 BT_UART_MSG_FRAME4IDLEDURATION_POS);
1978
1979 IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1980 "eSCO Retransmissions = 0x%X",
1981 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1982 BT_UART_MSG_FRAME5TXACTIVITY_POS,
1983 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1984 BT_UART_MSG_FRAME5RXACTIVITY_POS,
1985 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1986 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1987
1988 IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1989 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1990 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1991 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1992 BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1993
1994 IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Inquiry/Page SR Mode = "
1995 "0x%X, Connectable = 0x%X",
1996 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1997 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1998 (BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_MSK & uart_msg->frame7) >>
1999 BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_POS,
2000 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
2001 BT_UART_MSG_FRAME7CONNECTABLE_POS);
2002 }
2003
2004 static void iwlagn_set_kill_msk(struct iwl_priv *priv,
2005 struct iwl_bt_uart_msg *uart_msg)
2006 {
2007 u8 kill_msk;
2008 static const __le32 bt_kill_ack_msg[2] = {
2009 IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
2010 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
2011 static const __le32 bt_kill_cts_msg[2] = {
2012 IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
2013 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
2014
2015 kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
2016 ? 1 : 0;
2017 if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
2018 priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
2019 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
2020 priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
2021 priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
2022 priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
2023
2024 /* schedule to send runtime bt_config */
2025 queue_work(priv->workqueue, &priv->bt_runtime_config);
2026 }
2027 }
2028
2029 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
2030 struct iwl_rx_mem_buffer *rxb)
2031 {
2032 unsigned long flags;
2033 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2034 struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
2035 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
2036 struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
2037
2038 IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
2039 IWL_DEBUG_NOTIF(priv, " status: %d\n", coex->bt_status);
2040 IWL_DEBUG_NOTIF(priv, " traffic load: %d\n", coex->bt_traffic_load);
2041 IWL_DEBUG_NOTIF(priv, " CI compliance: %d\n",
2042 coex->bt_ci_compliance);
2043 iwlagn_print_uartmsg(priv, uart_msg);
2044
2045 priv->last_bt_traffic_load = priv->bt_traffic_load;
2046 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2047 if (priv->bt_status != coex->bt_status ||
2048 priv->last_bt_traffic_load != coex->bt_traffic_load) {
2049 if (coex->bt_status) {
2050 /* BT on */
2051 if (!priv->bt_ch_announce)
2052 priv->bt_traffic_load =
2053 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
2054 else
2055 priv->bt_traffic_load =
2056 coex->bt_traffic_load;
2057 } else {
2058 /* BT off */
2059 priv->bt_traffic_load =
2060 IWL_BT_COEX_TRAFFIC_LOAD_NONE;
2061 }
2062 priv->bt_status = coex->bt_status;
2063 queue_work(priv->workqueue,
2064 &priv->bt_traffic_change_work);
2065 }
2066 if (priv->bt_sco_active !=
2067 (uart_msg->frame3 & BT_UART_MSG_FRAME3SCOESCO_MSK)) {
2068 priv->bt_sco_active = uart_msg->frame3 &
2069 BT_UART_MSG_FRAME3SCOESCO_MSK;
2070 if (priv->bt_sco_active)
2071 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
2072 iwl_send_cmd_pdu_async(priv, REPLY_BT_COEX_SCO,
2073 sizeof(sco_cmd), &sco_cmd, NULL);
2074 }
2075 }
2076
2077 iwlagn_set_kill_msk(priv, uart_msg);
2078
2079 /* FIXME: based on notification, adjust the prio_boost */
2080
2081 spin_lock_irqsave(&priv->lock, flags);
2082 priv->bt_ci_compliance = coex->bt_ci_compliance;
2083 spin_unlock_irqrestore(&priv->lock, flags);
2084 }
2085
2086 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
2087 {
2088 iwlagn_rx_handler_setup(priv);
2089 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
2090 iwlagn_bt_coex_profile_notif;
2091 }
2092
2093 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
2094 {
2095 iwlagn_setup_deferred_work(priv);
2096
2097 INIT_WORK(&priv->bt_traffic_change_work,
2098 iwlagn_bt_traffic_change_work);
2099 }
2100
2101 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
2102 {
2103 cancel_work_sync(&priv->bt_traffic_change_work);
2104 }
2105
2106 static bool is_single_rx_stream(struct iwl_priv *priv)
2107 {
2108 return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
2109 priv->current_ht_config.single_chain_sufficient;
2110 }
2111
2112 #define IWL_NUM_RX_CHAINS_MULTIPLE 3
2113 #define IWL_NUM_RX_CHAINS_SINGLE 2
2114 #define IWL_NUM_IDLE_CHAINS_DUAL 2
2115 #define IWL_NUM_IDLE_CHAINS_SINGLE 1
2116
2117 /*
2118 * Determine how many receiver/antenna chains to use.
2119 *
2120 * More provides better reception via diversity. Fewer saves power
2121 * at the expense of throughput, but only when not in powersave to
2122 * start with.
2123 *
2124 * MIMO (dual stream) requires at least 2, but works better with 3.
2125 * This does not determine *which* chains to use, just how many.
2126 */
2127 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
2128 {
2129 if (priv->cfg->bt_params &&
2130 priv->cfg->bt_params->advanced_bt_coexist &&
2131 (priv->bt_full_concurrent ||
2132 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2133 /*
2134 * only use chain 'A' in bt high traffic load or
2135 * full concurrency mode
2136 */
2137 return IWL_NUM_RX_CHAINS_SINGLE;
2138 }
2139 /* # of Rx chains to use when expecting MIMO. */
2140 if (is_single_rx_stream(priv))
2141 return IWL_NUM_RX_CHAINS_SINGLE;
2142 else
2143 return IWL_NUM_RX_CHAINS_MULTIPLE;
2144 }
2145
2146 /*
2147 * When we are in power saving mode, unless device support spatial
2148 * multiplexing power save, use the active count for rx chain count.
2149 */
2150 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
2151 {
2152 /* # Rx chains when idling, depending on SMPS mode */
2153 switch (priv->current_ht_config.smps) {
2154 case IEEE80211_SMPS_STATIC:
2155 case IEEE80211_SMPS_DYNAMIC:
2156 return IWL_NUM_IDLE_CHAINS_SINGLE;
2157 case IEEE80211_SMPS_OFF:
2158 return active_cnt;
2159 default:
2160 WARN(1, "invalid SMPS mode %d",
2161 priv->current_ht_config.smps);
2162 return active_cnt;
2163 }
2164 }
2165
2166 /* up to 4 chains */
2167 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
2168 {
2169 u8 res;
2170 res = (chain_bitmap & BIT(0)) >> 0;
2171 res += (chain_bitmap & BIT(1)) >> 1;
2172 res += (chain_bitmap & BIT(2)) >> 2;
2173 res += (chain_bitmap & BIT(3)) >> 3;
2174 return res;
2175 }
2176
2177 /**
2178 * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2179 *
2180 * Selects how many and which Rx receivers/antennas/chains to use.
2181 * This should not be used for scan command ... it puts data in wrong place.
2182 */
2183 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2184 {
2185 bool is_single = is_single_rx_stream(priv);
2186 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
2187 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
2188 u32 active_chains;
2189 u16 rx_chain;
2190
2191 /* Tell uCode which antennas are actually connected.
2192 * Before first association, we assume all antennas are connected.
2193 * Just after first association, iwl_chain_noise_calibration()
2194 * checks which antennas actually *are* connected. */
2195 if (priv->chain_noise_data.active_chains)
2196 active_chains = priv->chain_noise_data.active_chains;
2197 else
2198 active_chains = priv->hw_params.valid_rx_ant;
2199
2200 if (priv->cfg->bt_params &&
2201 priv->cfg->bt_params->advanced_bt_coexist &&
2202 (priv->bt_full_concurrent ||
2203 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2204 /*
2205 * only use chain 'A' in bt high traffic load or
2206 * full concurrency mode
2207 */
2208 active_chains = first_antenna(active_chains);
2209 }
2210
2211 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2212
2213 /* How many receivers should we use? */
2214 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2215 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2216
2217
2218 /* correct rx chain count according hw settings
2219 * and chain noise calibration
2220 */
2221 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2222 if (valid_rx_cnt < active_rx_cnt)
2223 active_rx_cnt = valid_rx_cnt;
2224
2225 if (valid_rx_cnt < idle_rx_cnt)
2226 idle_rx_cnt = valid_rx_cnt;
2227
2228 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2229 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
2230
2231 ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2232
2233 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2234 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2235 else
2236 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2237
2238 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2239 ctx->staging.rx_chain,
2240 active_rx_cnt, idle_rx_cnt);
2241
2242 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2243 active_rx_cnt < idle_rx_cnt);
2244 }
2245
2246 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2247 {
2248 int i;
2249 u8 ind = ant;
2250
2251 if (priv->band == IEEE80211_BAND_2GHZ &&
2252 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2253 return 0;
2254
2255 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2256 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
2257 if (valid & BIT(ind))
2258 return ind;
2259 }
2260 return ant;
2261 }
2262
2263 static const char *get_csr_string(int cmd)
2264 {
2265 switch (cmd) {
2266 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2267 IWL_CMD(CSR_INT_COALESCING);
2268 IWL_CMD(CSR_INT);
2269 IWL_CMD(CSR_INT_MASK);
2270 IWL_CMD(CSR_FH_INT_STATUS);
2271 IWL_CMD(CSR_GPIO_IN);
2272 IWL_CMD(CSR_RESET);
2273 IWL_CMD(CSR_GP_CNTRL);
2274 IWL_CMD(CSR_HW_REV);
2275 IWL_CMD(CSR_EEPROM_REG);
2276 IWL_CMD(CSR_EEPROM_GP);
2277 IWL_CMD(CSR_OTP_GP_REG);
2278 IWL_CMD(CSR_GIO_REG);
2279 IWL_CMD(CSR_GP_UCODE_REG);
2280 IWL_CMD(CSR_GP_DRIVER_REG);
2281 IWL_CMD(CSR_UCODE_DRV_GP1);
2282 IWL_CMD(CSR_UCODE_DRV_GP2);
2283 IWL_CMD(CSR_LED_REG);
2284 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2285 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2286 IWL_CMD(CSR_ANA_PLL_CFG);
2287 IWL_CMD(CSR_HW_REV_WA_REG);
2288 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2289 default:
2290 return "UNKNOWN";
2291 }
2292 }
2293
2294 void iwl_dump_csr(struct iwl_priv *priv)
2295 {
2296 int i;
2297 static const u32 csr_tbl[] = {
2298 CSR_HW_IF_CONFIG_REG,
2299 CSR_INT_COALESCING,
2300 CSR_INT,
2301 CSR_INT_MASK,
2302 CSR_FH_INT_STATUS,
2303 CSR_GPIO_IN,
2304 CSR_RESET,
2305 CSR_GP_CNTRL,
2306 CSR_HW_REV,
2307 CSR_EEPROM_REG,
2308 CSR_EEPROM_GP,
2309 CSR_OTP_GP_REG,
2310 CSR_GIO_REG,
2311 CSR_GP_UCODE_REG,
2312 CSR_GP_DRIVER_REG,
2313 CSR_UCODE_DRV_GP1,
2314 CSR_UCODE_DRV_GP2,
2315 CSR_LED_REG,
2316 CSR_DRAM_INT_TBL_REG,
2317 CSR_GIO_CHICKEN_BITS,
2318 CSR_ANA_PLL_CFG,
2319 CSR_HW_REV_WA_REG,
2320 CSR_DBG_HPET_MEM_REG
2321 };
2322 IWL_ERR(priv, "CSR values:\n");
2323 IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2324 "CSR_INT_PERIODIC_REG)\n");
2325 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2326 IWL_ERR(priv, " %25s: 0X%08x\n",
2327 get_csr_string(csr_tbl[i]),
2328 iwl_read32(priv, csr_tbl[i]));
2329 }
2330 }
2331
2332 static const char *get_fh_string(int cmd)
2333 {
2334 switch (cmd) {
2335 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2336 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2337 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2338 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2339 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2340 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2341 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2342 IWL_CMD(FH_TSSR_TX_STATUS_REG);
2343 IWL_CMD(FH_TSSR_TX_ERROR_REG);
2344 default:
2345 return "UNKNOWN";
2346 }
2347 }
2348
2349 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2350 {
2351 int i;
2352 #ifdef CONFIG_IWLWIFI_DEBUG
2353 int pos = 0;
2354 size_t bufsz = 0;
2355 #endif
2356 static const u32 fh_tbl[] = {
2357 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2358 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2359 FH_RSCSR_CHNL0_WPTR,
2360 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2361 FH_MEM_RSSR_SHARED_CTRL_REG,
2362 FH_MEM_RSSR_RX_STATUS_REG,
2363 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2364 FH_TSSR_TX_STATUS_REG,
2365 FH_TSSR_TX_ERROR_REG
2366 };
2367 #ifdef CONFIG_IWLWIFI_DEBUG
2368 if (display) {
2369 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2370 *buf = kmalloc(bufsz, GFP_KERNEL);
2371 if (!*buf)
2372 return -ENOMEM;
2373 pos += scnprintf(*buf + pos, bufsz - pos,
2374 "FH register values:\n");
2375 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2376 pos += scnprintf(*buf + pos, bufsz - pos,
2377 " %34s: 0X%08x\n",
2378 get_fh_string(fh_tbl[i]),
2379 iwl_read_direct32(priv, fh_tbl[i]));
2380 }
2381 return pos;
2382 }
2383 #endif
2384 IWL_ERR(priv, "FH register values:\n");
2385 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2386 IWL_ERR(priv, " %34s: 0X%08x\n",
2387 get_fh_string(fh_tbl[i]),
2388 iwl_read_direct32(priv, fh_tbl[i]));
2389 }
2390 return 0;
2391 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree