2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include <asm/div64.h>
33 #include "drm_crtc_helper.h"
36 static int radeon_ddc_dump(struct drm_connector
*connector
);
38 static void avivo_crtc_load_lut(struct drm_crtc
*crtc
)
40 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
41 struct drm_device
*dev
= crtc
->dev
;
42 struct radeon_device
*rdev
= dev
->dev_private
;
45 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
46 WREG32(AVIVO_DC_LUTA_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
56 WREG32(AVIVO_DC_LUT_RW_SELECT
, radeon_crtc
->crtc_id
);
57 WREG32(AVIVO_DC_LUT_RW_MODE
, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK
, 0x0000003f);
60 WREG8(AVIVO_DC_LUT_RW_INDEX
, 0);
61 for (i
= 0; i
< 256; i
++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR
,
63 (radeon_crtc
->lut_r
[i
] << 20) |
64 (radeon_crtc
->lut_g
[i
] << 10) |
65 (radeon_crtc
->lut_b
[i
] << 0));
68 WREG32(AVIVO_D1GRPH_LUT_SEL
+ radeon_crtc
->crtc_offset
, radeon_crtc
->crtc_id
);
71 static void evergreen_crtc_load_lut(struct drm_crtc
*crtc
)
73 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
74 struct drm_device
*dev
= crtc
->dev
;
75 struct radeon_device
*rdev
= dev
->dev_private
;
78 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
79 WREG32(EVERGREEN_DC_LUT_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_RW_MODE
+ radeon_crtc
->crtc_offset
, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK
+ radeon_crtc
->crtc_offset
, 0x00000007);
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX
+ radeon_crtc
->crtc_offset
, 0);
93 for (i
= 0; i
< 256; i
++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR
+ radeon_crtc
->crtc_offset
,
95 (radeon_crtc
->lut_r
[i
] << 20) |
96 (radeon_crtc
->lut_g
[i
] << 10) |
97 (radeon_crtc
->lut_b
[i
] << 0));
101 static void legacy_crtc_load_lut(struct drm_crtc
*crtc
)
103 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
104 struct drm_device
*dev
= crtc
->dev
;
105 struct radeon_device
*rdev
= dev
->dev_private
;
109 dac2_cntl
= RREG32(RADEON_DAC_CNTL2
);
110 if (radeon_crtc
->crtc_id
== 0)
111 dac2_cntl
&= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL
;
113 dac2_cntl
|= RADEON_DAC2_PALETTE_ACC_CTL
;
114 WREG32(RADEON_DAC_CNTL2
, dac2_cntl
);
116 WREG8(RADEON_PALETTE_INDEX
, 0);
117 for (i
= 0; i
< 256; i
++) {
118 WREG32(RADEON_PALETTE_30_DATA
,
119 (radeon_crtc
->lut_r
[i
] << 20) |
120 (radeon_crtc
->lut_g
[i
] << 10) |
121 (radeon_crtc
->lut_b
[i
] << 0));
125 void radeon_crtc_load_lut(struct drm_crtc
*crtc
)
127 struct drm_device
*dev
= crtc
->dev
;
128 struct radeon_device
*rdev
= dev
->dev_private
;
133 if (ASIC_IS_DCE4(rdev
))
134 evergreen_crtc_load_lut(crtc
);
135 else if (ASIC_IS_AVIVO(rdev
))
136 avivo_crtc_load_lut(crtc
);
138 legacy_crtc_load_lut(crtc
);
141 /** Sets the color ramps on behalf of fbcon */
142 void radeon_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
145 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
147 radeon_crtc
->lut_r
[regno
] = red
>> 6;
148 radeon_crtc
->lut_g
[regno
] = green
>> 6;
149 radeon_crtc
->lut_b
[regno
] = blue
>> 6;
152 /** Gets the color ramps on behalf of fbcon */
153 void radeon_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
154 u16
*blue
, int regno
)
156 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
158 *red
= radeon_crtc
->lut_r
[regno
] << 6;
159 *green
= radeon_crtc
->lut_g
[regno
] << 6;
160 *blue
= radeon_crtc
->lut_b
[regno
] << 6;
163 static void radeon_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
164 u16
*blue
, uint32_t size
)
166 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
173 /* userspace palettes are always correct as is */
174 for (i
= 0; i
< 256; i
++) {
175 radeon_crtc
->lut_r
[i
] = red
[i
] >> 6;
176 radeon_crtc
->lut_g
[i
] = green
[i
] >> 6;
177 radeon_crtc
->lut_b
[i
] = blue
[i
] >> 6;
179 radeon_crtc_load_lut(crtc
);
182 static void radeon_crtc_destroy(struct drm_crtc
*crtc
)
184 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
186 drm_crtc_cleanup(crtc
);
190 static const struct drm_crtc_funcs radeon_crtc_funcs
= {
191 .cursor_set
= radeon_crtc_cursor_set
,
192 .cursor_move
= radeon_crtc_cursor_move
,
193 .gamma_set
= radeon_crtc_gamma_set
,
194 .set_config
= drm_crtc_helper_set_config
,
195 .destroy
= radeon_crtc_destroy
,
198 static void radeon_crtc_init(struct drm_device
*dev
, int index
)
200 struct radeon_device
*rdev
= dev
->dev_private
;
201 struct radeon_crtc
*radeon_crtc
;
204 radeon_crtc
= kzalloc(sizeof(struct radeon_crtc
) + (RADEONFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
205 if (radeon_crtc
== NULL
)
208 drm_crtc_init(dev
, &radeon_crtc
->base
, &radeon_crtc_funcs
);
210 drm_mode_crtc_set_gamma_size(&radeon_crtc
->base
, 256);
211 radeon_crtc
->crtc_id
= index
;
212 rdev
->mode_info
.crtcs
[index
] = radeon_crtc
;
215 radeon_crtc
->mode_set
.crtc
= &radeon_crtc
->base
;
216 radeon_crtc
->mode_set
.connectors
= (struct drm_connector
**)(radeon_crtc
+ 1);
217 radeon_crtc
->mode_set
.num_connectors
= 0;
220 for (i
= 0; i
< 256; i
++) {
221 radeon_crtc
->lut_r
[i
] = i
<< 2;
222 radeon_crtc
->lut_g
[i
] = i
<< 2;
223 radeon_crtc
->lut_b
[i
] = i
<< 2;
226 if (rdev
->is_atom_bios
&& (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
))
227 radeon_atombios_init_crtc(dev
, radeon_crtc
);
229 radeon_legacy_init_crtc(dev
, radeon_crtc
);
232 static const char *encoder_names
[34] = {
252 "INTERNAL_KLDSCP_TMDS1",
253 "INTERNAL_KLDSCP_DVO1",
254 "INTERNAL_KLDSCP_DAC1",
255 "INTERNAL_KLDSCP_DAC2",
264 "INTERNAL_KLDSCP_LVTMA",
269 static const char *connector_names
[15] = {
287 static const char *hpd_names
[6] = {
296 static void radeon_print_display_setup(struct drm_device
*dev
)
298 struct drm_connector
*connector
;
299 struct radeon_connector
*radeon_connector
;
300 struct drm_encoder
*encoder
;
301 struct radeon_encoder
*radeon_encoder
;
305 DRM_INFO("Radeon Display Connectors\n");
306 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
307 radeon_connector
= to_radeon_connector(connector
);
308 DRM_INFO("Connector %d:\n", i
);
309 DRM_INFO(" %s\n", connector_names
[connector
->connector_type
]);
310 if (radeon_connector
->hpd
.hpd
!= RADEON_HPD_NONE
)
311 DRM_INFO(" %s\n", hpd_names
[radeon_connector
->hpd
.hpd
]);
312 if (radeon_connector
->ddc_bus
) {
313 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
314 radeon_connector
->ddc_bus
->rec
.mask_clk_reg
,
315 radeon_connector
->ddc_bus
->rec
.mask_data_reg
,
316 radeon_connector
->ddc_bus
->rec
.a_clk_reg
,
317 radeon_connector
->ddc_bus
->rec
.a_data_reg
,
318 radeon_connector
->ddc_bus
->rec
.en_clk_reg
,
319 radeon_connector
->ddc_bus
->rec
.en_data_reg
,
320 radeon_connector
->ddc_bus
->rec
.y_clk_reg
,
321 radeon_connector
->ddc_bus
->rec
.y_data_reg
);
322 if (radeon_connector
->router_bus
)
323 DRM_INFO(" DDC Router 0x%x/0x%x\n",
324 radeon_connector
->router
.mux_control_pin
,
325 radeon_connector
->router
.mux_state
);
327 if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
||
328 connector
->connector_type
== DRM_MODE_CONNECTOR_DVII
||
329 connector
->connector_type
== DRM_MODE_CONNECTOR_DVID
||
330 connector
->connector_type
== DRM_MODE_CONNECTOR_DVIA
||
331 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIA
||
332 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIB
)
333 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
335 DRM_INFO(" Encoders:\n");
336 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
337 radeon_encoder
= to_radeon_encoder(encoder
);
338 devices
= radeon_encoder
->devices
& radeon_connector
->devices
;
340 if (devices
& ATOM_DEVICE_CRT1_SUPPORT
)
341 DRM_INFO(" CRT1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
342 if (devices
& ATOM_DEVICE_CRT2_SUPPORT
)
343 DRM_INFO(" CRT2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
344 if (devices
& ATOM_DEVICE_LCD1_SUPPORT
)
345 DRM_INFO(" LCD1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
346 if (devices
& ATOM_DEVICE_DFP1_SUPPORT
)
347 DRM_INFO(" DFP1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
348 if (devices
& ATOM_DEVICE_DFP2_SUPPORT
)
349 DRM_INFO(" DFP2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
350 if (devices
& ATOM_DEVICE_DFP3_SUPPORT
)
351 DRM_INFO(" DFP3: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
352 if (devices
& ATOM_DEVICE_DFP4_SUPPORT
)
353 DRM_INFO(" DFP4: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
354 if (devices
& ATOM_DEVICE_DFP5_SUPPORT
)
355 DRM_INFO(" DFP5: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
356 if (devices
& ATOM_DEVICE_TV1_SUPPORT
)
357 DRM_INFO(" TV1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
358 if (devices
& ATOM_DEVICE_CV_SUPPORT
)
359 DRM_INFO(" CV: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
366 static bool radeon_setup_enc_conn(struct drm_device
*dev
)
368 struct radeon_device
*rdev
= dev
->dev_private
;
369 struct drm_connector
*drm_connector
;
373 if (rdev
->is_atom_bios
) {
374 ret
= radeon_get_atom_connector_info_from_supported_devices_table(dev
);
376 ret
= radeon_get_atom_connector_info_from_object_table(dev
);
378 ret
= radeon_get_legacy_connector_info_from_bios(dev
);
380 ret
= radeon_get_legacy_connector_info_from_table(dev
);
383 if (!ASIC_IS_AVIVO(rdev
))
384 ret
= radeon_get_legacy_connector_info_from_table(dev
);
387 radeon_setup_encoder_clones(dev
);
388 radeon_print_display_setup(dev
);
389 list_for_each_entry(drm_connector
, &dev
->mode_config
.connector_list
, head
)
390 radeon_ddc_dump(drm_connector
);
396 int radeon_ddc_get_modes(struct radeon_connector
*radeon_connector
)
398 struct drm_device
*dev
= radeon_connector
->base
.dev
;
399 struct radeon_device
*rdev
= dev
->dev_private
;
402 /* on hw with routers, select right port */
403 if (radeon_connector
->router
.valid
)
404 radeon_router_select_port(radeon_connector
);
406 if ((radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_DisplayPort
) ||
407 (radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_eDP
)) {
408 struct radeon_connector_atom_dig
*dig
= radeon_connector
->con_priv
;
409 if ((dig
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
||
410 dig
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
) && dig
->dp_i2c_bus
)
411 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
, &dig
->dp_i2c_bus
->adapter
);
413 if (!radeon_connector
->ddc_bus
)
415 if (!radeon_connector
->edid
) {
416 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
, &radeon_connector
->ddc_bus
->adapter
);
418 /* some servers provide a hardcoded edid in rom for KVMs */
419 if (!radeon_connector
->edid
)
420 radeon_connector
->edid
= radeon_combios_get_hardcoded_edid(rdev
);
421 if (radeon_connector
->edid
) {
422 drm_mode_connector_update_edid_property(&radeon_connector
->base
, radeon_connector
->edid
);
423 ret
= drm_add_edid_modes(&radeon_connector
->base
, radeon_connector
->edid
);
426 drm_mode_connector_update_edid_property(&radeon_connector
->base
, NULL
);
430 static int radeon_ddc_dump(struct drm_connector
*connector
)
433 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
436 /* on hw with routers, select right port */
437 if (radeon_connector
->router
.valid
)
438 radeon_router_select_port(radeon_connector
);
440 if (!radeon_connector
->ddc_bus
)
442 edid
= drm_get_edid(connector
, &radeon_connector
->ddc_bus
->adapter
);
449 static inline uint32_t radeon_div(uint64_t n
, uint32_t d
)
459 static void radeon_compute_pll_legacy(struct radeon_pll
*pll
,
461 uint32_t *dot_clock_p
,
463 uint32_t *frac_fb_div_p
,
465 uint32_t *post_div_p
)
467 uint32_t min_ref_div
= pll
->min_ref_div
;
468 uint32_t max_ref_div
= pll
->max_ref_div
;
469 uint32_t min_post_div
= pll
->min_post_div
;
470 uint32_t max_post_div
= pll
->max_post_div
;
471 uint32_t min_fractional_feed_div
= 0;
472 uint32_t max_fractional_feed_div
= 0;
473 uint32_t best_vco
= pll
->best_vco
;
474 uint32_t best_post_div
= 1;
475 uint32_t best_ref_div
= 1;
476 uint32_t best_feedback_div
= 1;
477 uint32_t best_frac_feedback_div
= 0;
478 uint32_t best_freq
= -1;
479 uint32_t best_error
= 0xffffffff;
480 uint32_t best_vco_diff
= 1;
482 u32 pll_out_min
, pll_out_max
;
484 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq
, pll
->min_ref_div
, pll
->max_ref_div
);
487 if (pll
->flags
& RADEON_PLL_IS_LCD
) {
488 pll_out_min
= pll
->lcd_pll_out_min
;
489 pll_out_max
= pll
->lcd_pll_out_max
;
491 pll_out_min
= pll
->pll_out_min
;
492 pll_out_max
= pll
->pll_out_max
;
495 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
)
496 min_ref_div
= max_ref_div
= pll
->reference_div
;
498 while (min_ref_div
< max_ref_div
-1) {
499 uint32_t mid
= (min_ref_div
+ max_ref_div
) / 2;
500 uint32_t pll_in
= pll
->reference_freq
/ mid
;
501 if (pll_in
< pll
->pll_in_min
)
503 else if (pll_in
> pll
->pll_in_max
)
510 if (pll
->flags
& RADEON_PLL_USE_POST_DIV
)
511 min_post_div
= max_post_div
= pll
->post_div
;
513 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
514 min_fractional_feed_div
= pll
->min_frac_feedback_div
;
515 max_fractional_feed_div
= pll
->max_frac_feedback_div
;
518 for (post_div
= min_post_div
; post_div
<= max_post_div
; ++post_div
) {
521 if ((pll
->flags
& RADEON_PLL_NO_ODD_POST_DIV
) && (post_div
& 1))
524 /* legacy radeons only have a few post_divs */
525 if (pll
->flags
& RADEON_PLL_LEGACY
) {
526 if ((post_div
== 5) ||
537 for (ref_div
= min_ref_div
; ref_div
<= max_ref_div
; ++ref_div
) {
538 uint32_t feedback_div
, current_freq
= 0, error
, vco_diff
;
539 uint32_t pll_in
= pll
->reference_freq
/ ref_div
;
540 uint32_t min_feed_div
= pll
->min_feedback_div
;
541 uint32_t max_feed_div
= pll
->max_feedback_div
+ 1;
543 if (pll_in
< pll
->pll_in_min
|| pll_in
> pll
->pll_in_max
)
546 while (min_feed_div
< max_feed_div
) {
548 uint32_t min_frac_feed_div
= min_fractional_feed_div
;
549 uint32_t max_frac_feed_div
= max_fractional_feed_div
+ 1;
550 uint32_t frac_feedback_div
;
553 feedback_div
= (min_feed_div
+ max_feed_div
) / 2;
555 tmp
= (uint64_t)pll
->reference_freq
* feedback_div
;
556 vco
= radeon_div(tmp
, ref_div
);
558 if (vco
< pll_out_min
) {
559 min_feed_div
= feedback_div
+ 1;
561 } else if (vco
> pll_out_max
) {
562 max_feed_div
= feedback_div
;
566 while (min_frac_feed_div
< max_frac_feed_div
) {
567 frac_feedback_div
= (min_frac_feed_div
+ max_frac_feed_div
) / 2;
568 tmp
= (uint64_t)pll
->reference_freq
* 10000 * feedback_div
;
569 tmp
+= (uint64_t)pll
->reference_freq
* 1000 * frac_feedback_div
;
570 current_freq
= radeon_div(tmp
, ref_div
* post_div
);
572 if (pll
->flags
& RADEON_PLL_PREFER_CLOSEST_LOWER
) {
573 if (freq
< current_freq
)
576 error
= freq
- current_freq
;
578 error
= abs(current_freq
- freq
);
579 vco_diff
= abs(vco
- best_vco
);
581 if ((best_vco
== 0 && error
< best_error
) ||
583 ((best_error
> 100 && error
< best_error
- 100) ||
584 (abs(error
- best_error
) < 100 && vco_diff
< best_vco_diff
)))) {
585 best_post_div
= post_div
;
586 best_ref_div
= ref_div
;
587 best_feedback_div
= feedback_div
;
588 best_frac_feedback_div
= frac_feedback_div
;
589 best_freq
= current_freq
;
591 best_vco_diff
= vco_diff
;
592 } else if (current_freq
== freq
) {
593 if (best_freq
== -1) {
594 best_post_div
= post_div
;
595 best_ref_div
= ref_div
;
596 best_feedback_div
= feedback_div
;
597 best_frac_feedback_div
= frac_feedback_div
;
598 best_freq
= current_freq
;
600 best_vco_diff
= vco_diff
;
601 } else if (((pll
->flags
& RADEON_PLL_PREFER_LOW_REF_DIV
) && (ref_div
< best_ref_div
)) ||
602 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_REF_DIV
) && (ref_div
> best_ref_div
)) ||
603 ((pll
->flags
& RADEON_PLL_PREFER_LOW_FB_DIV
) && (feedback_div
< best_feedback_div
)) ||
604 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_FB_DIV
) && (feedback_div
> best_feedback_div
)) ||
605 ((pll
->flags
& RADEON_PLL_PREFER_LOW_POST_DIV
) && (post_div
< best_post_div
)) ||
606 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_POST_DIV
) && (post_div
> best_post_div
))) {
607 best_post_div
= post_div
;
608 best_ref_div
= ref_div
;
609 best_feedback_div
= feedback_div
;
610 best_frac_feedback_div
= frac_feedback_div
;
611 best_freq
= current_freq
;
613 best_vco_diff
= vco_diff
;
616 if (current_freq
< freq
)
617 min_frac_feed_div
= frac_feedback_div
+ 1;
619 max_frac_feed_div
= frac_feedback_div
;
621 if (current_freq
< freq
)
622 min_feed_div
= feedback_div
+ 1;
624 max_feed_div
= feedback_div
;
629 *dot_clock_p
= best_freq
/ 10000;
630 *fb_div_p
= best_feedback_div
;
631 *frac_fb_div_p
= best_frac_feedback_div
;
632 *ref_div_p
= best_ref_div
;
633 *post_div_p
= best_post_div
;
637 calc_fb_div(struct radeon_pll
*pll
,
642 uint32_t *fb_div_frac
)
644 fixed20_12 feedback_divider
, a
, b
;
647 vco_freq
= freq
* post_div
;
648 /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */
649 a
.full
= dfixed_const(pll
->reference_freq
);
650 feedback_divider
.full
= dfixed_const(vco_freq
);
651 feedback_divider
.full
= dfixed_div(feedback_divider
, a
);
652 a
.full
= dfixed_const(ref_div
);
653 feedback_divider
.full
= dfixed_mul(feedback_divider
, a
);
655 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
656 /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */
657 a
.full
= dfixed_const(10);
658 feedback_divider
.full
= dfixed_mul(feedback_divider
, a
);
659 feedback_divider
.full
+= dfixed_const_half(0);
660 feedback_divider
.full
= dfixed_floor(feedback_divider
);
661 feedback_divider
.full
= dfixed_div(feedback_divider
, a
);
663 /* *fb_div = floor(feedback_divider); */
664 a
.full
= dfixed_floor(feedback_divider
);
665 *fb_div
= dfixed_trunc(a
);
666 /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */
667 a
.full
= dfixed_const(10);
668 b
.full
= dfixed_mul(feedback_divider
, a
);
670 feedback_divider
.full
= dfixed_floor(feedback_divider
);
671 feedback_divider
.full
= dfixed_mul(feedback_divider
, a
);
672 feedback_divider
.full
= b
.full
- feedback_divider
.full
;
673 *fb_div_frac
= dfixed_trunc(feedback_divider
);
675 /* *fb_div = floor(feedback_divider + 0.5); */
676 feedback_divider
.full
+= dfixed_const_half(0);
677 feedback_divider
.full
= dfixed_floor(feedback_divider
);
679 *fb_div
= dfixed_trunc(feedback_divider
);
683 if (((*fb_div
) < pll
->min_feedback_div
) || ((*fb_div
) > pll
->max_feedback_div
))
690 calc_fb_ref_div(struct radeon_pll
*pll
,
694 uint32_t *fb_div_frac
,
697 fixed20_12 ffreq
, max_error
, error
, pll_out
, a
;
699 u32 pll_out_min
, pll_out_max
;
701 if (pll
->flags
& RADEON_PLL_IS_LCD
) {
702 pll_out_min
= pll
->lcd_pll_out_min
;
703 pll_out_max
= pll
->lcd_pll_out_max
;
705 pll_out_min
= pll
->pll_out_min
;
706 pll_out_max
= pll
->pll_out_max
;
709 ffreq
.full
= dfixed_const(freq
);
710 /* max_error = ffreq * 0.0025; */
711 a
.full
= dfixed_const(400);
712 max_error
.full
= dfixed_div(ffreq
, a
);
714 for ((*ref_div
) = pll
->min_ref_div
; (*ref_div
) < pll
->max_ref_div
; ++(*ref_div
)) {
715 if (calc_fb_div(pll
, freq
, post_div
, (*ref_div
), fb_div
, fb_div_frac
)) {
716 vco
= pll
->reference_freq
* (((*fb_div
) * 10) + (*fb_div_frac
));
717 vco
= vco
/ ((*ref_div
) * 10);
719 if ((vco
< pll_out_min
) || (vco
> pll_out_max
))
722 /* pll_out = vco / post_div; */
723 a
.full
= dfixed_const(post_div
);
724 pll_out
.full
= dfixed_const(vco
);
725 pll_out
.full
= dfixed_div(pll_out
, a
);
727 if (pll_out
.full
>= ffreq
.full
) {
728 error
.full
= pll_out
.full
- ffreq
.full
;
729 if (error
.full
<= max_error
.full
)
737 static void radeon_compute_pll_new(struct radeon_pll
*pll
,
739 uint32_t *dot_clock_p
,
741 uint32_t *frac_fb_div_p
,
743 uint32_t *post_div_p
)
745 u32 fb_div
= 0, fb_div_frac
= 0, post_div
= 0, ref_div
= 0;
746 u32 best_freq
= 0, vco_frequency
;
747 u32 pll_out_min
, pll_out_max
;
749 if (pll
->flags
& RADEON_PLL_IS_LCD
) {
750 pll_out_min
= pll
->lcd_pll_out_min
;
751 pll_out_max
= pll
->lcd_pll_out_max
;
753 pll_out_min
= pll
->pll_out_min
;
754 pll_out_max
= pll
->pll_out_max
;
757 /* freq = freq / 10; */
760 if (pll
->flags
& RADEON_PLL_USE_POST_DIV
) {
761 post_div
= pll
->post_div
;
762 if ((post_div
< pll
->min_post_div
) || (post_div
> pll
->max_post_div
))
765 vco_frequency
= freq
* post_div
;
766 if ((vco_frequency
< pll_out_min
) || (vco_frequency
> pll_out_max
))
769 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
) {
770 ref_div
= pll
->reference_div
;
771 if ((ref_div
< pll
->min_ref_div
) || (ref_div
> pll
->max_ref_div
))
773 if (!calc_fb_div(pll
, freq
, post_div
, ref_div
, &fb_div
, &fb_div_frac
))
777 for (post_div
= pll
->max_post_div
; post_div
>= pll
->min_post_div
; --post_div
) {
778 if (pll
->flags
& RADEON_PLL_LEGACY
) {
779 if ((post_div
== 5) ||
787 if ((pll
->flags
& RADEON_PLL_NO_ODD_POST_DIV
) && (post_div
& 1))
790 vco_frequency
= freq
* post_div
;
791 if ((vco_frequency
< pll_out_min
) || (vco_frequency
> pll_out_max
))
793 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
) {
794 ref_div
= pll
->reference_div
;
795 if ((ref_div
< pll
->min_ref_div
) || (ref_div
> pll
->max_ref_div
))
797 if (calc_fb_div(pll
, freq
, post_div
, ref_div
, &fb_div
, &fb_div_frac
))
800 if (calc_fb_ref_div(pll
, freq
, post_div
, &fb_div
, &fb_div_frac
, &ref_div
))
806 best_freq
= pll
->reference_freq
* 10 * fb_div
;
807 best_freq
+= pll
->reference_freq
* fb_div_frac
;
808 best_freq
= best_freq
/ (ref_div
* post_div
);
812 DRM_ERROR("Couldn't find valid PLL dividers\n");
814 *dot_clock_p
= best_freq
/ 10;
816 *frac_fb_div_p
= fb_div_frac
;
817 *ref_div_p
= ref_div
;
818 *post_div_p
= post_div
;
820 DRM_DEBUG_KMS("%u %d.%d, %d, %d\n", *dot_clock_p
, *fb_div_p
, *frac_fb_div_p
, *ref_div_p
, *post_div_p
);
823 void radeon_compute_pll(struct radeon_pll
*pll
,
825 uint32_t *dot_clock_p
,
827 uint32_t *frac_fb_div_p
,
829 uint32_t *post_div_p
)
833 radeon_compute_pll_new(pll
, freq
, dot_clock_p
, fb_div_p
,
834 frac_fb_div_p
, ref_div_p
, post_div_p
);
836 case PLL_ALGO_LEGACY
:
838 radeon_compute_pll_legacy(pll
, freq
, dot_clock_p
, fb_div_p
,
839 frac_fb_div_p
, ref_div_p
, post_div_p
);
844 static void radeon_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
846 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
849 drm_gem_object_unreference_unlocked(radeon_fb
->obj
);
850 drm_framebuffer_cleanup(fb
);
854 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
855 struct drm_file
*file_priv
,
856 unsigned int *handle
)
858 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
860 return drm_gem_handle_create(file_priv
, radeon_fb
->obj
, handle
);
863 static const struct drm_framebuffer_funcs radeon_fb_funcs
= {
864 .destroy
= radeon_user_framebuffer_destroy
,
865 .create_handle
= radeon_user_framebuffer_create_handle
,
869 radeon_framebuffer_init(struct drm_device
*dev
,
870 struct radeon_framebuffer
*rfb
,
871 struct drm_mode_fb_cmd
*mode_cmd
,
872 struct drm_gem_object
*obj
)
875 drm_framebuffer_init(dev
, &rfb
->base
, &radeon_fb_funcs
);
876 drm_helper_mode_fill_fb_struct(&rfb
->base
, mode_cmd
);
879 static struct drm_framebuffer
*
880 radeon_user_framebuffer_create(struct drm_device
*dev
,
881 struct drm_file
*file_priv
,
882 struct drm_mode_fb_cmd
*mode_cmd
)
884 struct drm_gem_object
*obj
;
885 struct radeon_framebuffer
*radeon_fb
;
887 obj
= drm_gem_object_lookup(dev
, file_priv
, mode_cmd
->handle
);
889 dev_err(&dev
->pdev
->dev
, "No GEM object associated to handle 0x%08X, "
890 "can't create framebuffer\n", mode_cmd
->handle
);
891 return ERR_PTR(-ENOENT
);
894 radeon_fb
= kzalloc(sizeof(*radeon_fb
), GFP_KERNEL
);
895 if (radeon_fb
== NULL
)
896 return ERR_PTR(-ENOMEM
);
898 radeon_framebuffer_init(dev
, radeon_fb
, mode_cmd
, obj
);
900 return &radeon_fb
->base
;
903 static void radeon_output_poll_changed(struct drm_device
*dev
)
905 struct radeon_device
*rdev
= dev
->dev_private
;
906 radeon_fb_output_poll_changed(rdev
);
909 static const struct drm_mode_config_funcs radeon_mode_funcs
= {
910 .fb_create
= radeon_user_framebuffer_create
,
911 .output_poll_changed
= radeon_output_poll_changed
914 struct drm_prop_enum_list
{
919 static struct drm_prop_enum_list radeon_tmds_pll_enum_list
[] =
924 static struct drm_prop_enum_list radeon_tv_std_enum_list
[] =
925 { { TV_STD_NTSC
, "ntsc" },
926 { TV_STD_PAL
, "pal" },
927 { TV_STD_PAL_M
, "pal-m" },
928 { TV_STD_PAL_60
, "pal-60" },
929 { TV_STD_NTSC_J
, "ntsc-j" },
930 { TV_STD_SCART_PAL
, "scart-pal" },
931 { TV_STD_PAL_CN
, "pal-cn" },
932 { TV_STD_SECAM
, "secam" },
935 static struct drm_prop_enum_list radeon_underscan_enum_list
[] =
936 { { UNDERSCAN_OFF
, "off" },
937 { UNDERSCAN_ON
, "on" },
938 { UNDERSCAN_AUTO
, "auto" },
941 static int radeon_modeset_create_props(struct radeon_device
*rdev
)
945 if (rdev
->is_atom_bios
) {
946 rdev
->mode_info
.coherent_mode_property
=
947 drm_property_create(rdev
->ddev
,
950 if (!rdev
->mode_info
.coherent_mode_property
)
953 rdev
->mode_info
.coherent_mode_property
->values
[0] = 0;
954 rdev
->mode_info
.coherent_mode_property
->values
[1] = 1;
957 if (!ASIC_IS_AVIVO(rdev
)) {
958 sz
= ARRAY_SIZE(radeon_tmds_pll_enum_list
);
959 rdev
->mode_info
.tmds_pll_property
=
960 drm_property_create(rdev
->ddev
,
963 for (i
= 0; i
< sz
; i
++) {
964 drm_property_add_enum(rdev
->mode_info
.tmds_pll_property
,
966 radeon_tmds_pll_enum_list
[i
].type
,
967 radeon_tmds_pll_enum_list
[i
].name
);
971 rdev
->mode_info
.load_detect_property
=
972 drm_property_create(rdev
->ddev
,
974 "load detection", 2);
975 if (!rdev
->mode_info
.load_detect_property
)
977 rdev
->mode_info
.load_detect_property
->values
[0] = 0;
978 rdev
->mode_info
.load_detect_property
->values
[1] = 1;
980 drm_mode_create_scaling_mode_property(rdev
->ddev
);
982 sz
= ARRAY_SIZE(radeon_tv_std_enum_list
);
983 rdev
->mode_info
.tv_std_property
=
984 drm_property_create(rdev
->ddev
,
987 for (i
= 0; i
< sz
; i
++) {
988 drm_property_add_enum(rdev
->mode_info
.tv_std_property
,
990 radeon_tv_std_enum_list
[i
].type
,
991 radeon_tv_std_enum_list
[i
].name
);
994 sz
= ARRAY_SIZE(radeon_underscan_enum_list
);
995 rdev
->mode_info
.underscan_property
=
996 drm_property_create(rdev
->ddev
,
999 for (i
= 0; i
< sz
; i
++) {
1000 drm_property_add_enum(rdev
->mode_info
.underscan_property
,
1002 radeon_underscan_enum_list
[i
].type
,
1003 radeon_underscan_enum_list
[i
].name
);
1009 void radeon_update_display_priority(struct radeon_device
*rdev
)
1011 /* adjustment options for the display watermarks */
1012 if ((radeon_disp_priority
== 0) || (radeon_disp_priority
> 2)) {
1013 /* set display priority to high for r3xx, rv515 chips
1014 * this avoids flickering due to underflow to the
1015 * display controllers during heavy acceleration.
1016 * Don't force high on rs4xx igp chips as it seems to
1017 * affect the sound card. See kernel bug 15982.
1019 if ((ASIC_IS_R300(rdev
) || (rdev
->family
== CHIP_RV515
)) &&
1020 !(rdev
->flags
& RADEON_IS_IGP
))
1021 rdev
->disp_priority
= 2;
1023 rdev
->disp_priority
= 0;
1025 rdev
->disp_priority
= radeon_disp_priority
;
1029 int radeon_modeset_init(struct radeon_device
*rdev
)
1034 drm_mode_config_init(rdev
->ddev
);
1035 rdev
->mode_info
.mode_config_initialized
= true;
1037 rdev
->ddev
->mode_config
.funcs
= (void *)&radeon_mode_funcs
;
1039 if (ASIC_IS_AVIVO(rdev
)) {
1040 rdev
->ddev
->mode_config
.max_width
= 8192;
1041 rdev
->ddev
->mode_config
.max_height
= 8192;
1043 rdev
->ddev
->mode_config
.max_width
= 4096;
1044 rdev
->ddev
->mode_config
.max_height
= 4096;
1047 rdev
->ddev
->mode_config
.fb_base
= rdev
->mc
.aper_base
;
1049 ret
= radeon_modeset_create_props(rdev
);
1054 /* init i2c buses */
1055 radeon_i2c_init(rdev
);
1057 /* check combios for a valid hardcoded EDID - Sun servers */
1058 if (!rdev
->is_atom_bios
) {
1059 /* check for hardcoded EDID in BIOS */
1060 radeon_combios_check_hardcoded_edid(rdev
);
1063 /* allocate crtcs */
1064 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1065 radeon_crtc_init(rdev
->ddev
, i
);
1068 /* okay we should have all the bios connectors */
1069 ret
= radeon_setup_enc_conn(rdev
->ddev
);
1073 /* initialize hpd */
1074 radeon_hpd_init(rdev
);
1076 /* Initialize power management */
1077 radeon_pm_init(rdev
);
1079 radeon_fbdev_init(rdev
);
1080 drm_kms_helper_poll_init(rdev
->ddev
);
1085 void radeon_modeset_fini(struct radeon_device
*rdev
)
1087 radeon_fbdev_fini(rdev
);
1088 kfree(rdev
->mode_info
.bios_hardcoded_edid
);
1089 radeon_pm_fini(rdev
);
1091 if (rdev
->mode_info
.mode_config_initialized
) {
1092 drm_kms_helper_poll_fini(rdev
->ddev
);
1093 radeon_hpd_fini(rdev
);
1094 drm_mode_config_cleanup(rdev
->ddev
);
1095 rdev
->mode_info
.mode_config_initialized
= false;
1097 /* free i2c buses */
1098 radeon_i2c_fini(rdev
);
1101 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc
*crtc
,
1102 struct drm_display_mode
*mode
,
1103 struct drm_display_mode
*adjusted_mode
)
1105 struct drm_device
*dev
= crtc
->dev
;
1106 struct radeon_device
*rdev
= dev
->dev_private
;
1107 struct drm_encoder
*encoder
;
1108 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1109 struct radeon_encoder
*radeon_encoder
;
1110 struct drm_connector
*connector
;
1111 struct radeon_connector
*radeon_connector
;
1113 u32 src_v
= 1, dst_v
= 1;
1114 u32 src_h
= 1, dst_h
= 1;
1116 radeon_crtc
->h_border
= 0;
1117 radeon_crtc
->v_border
= 0;
1119 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1120 if (encoder
->crtc
!= crtc
)
1122 radeon_encoder
= to_radeon_encoder(encoder
);
1123 connector
= radeon_get_connector_for_encoder(encoder
);
1124 radeon_connector
= to_radeon_connector(connector
);
1128 if (radeon_encoder
->rmx_type
== RMX_OFF
)
1129 radeon_crtc
->rmx_type
= RMX_OFF
;
1130 else if (mode
->hdisplay
< radeon_encoder
->native_mode
.hdisplay
||
1131 mode
->vdisplay
< radeon_encoder
->native_mode
.vdisplay
)
1132 radeon_crtc
->rmx_type
= radeon_encoder
->rmx_type
;
1134 radeon_crtc
->rmx_type
= RMX_OFF
;
1135 src_v
= crtc
->mode
.vdisplay
;
1136 dst_v
= radeon_crtc
->native_mode
.vdisplay
;
1137 src_h
= crtc
->mode
.hdisplay
;
1138 dst_h
= radeon_crtc
->native_mode
.vdisplay
;
1139 /* copy native mode */
1140 memcpy(&radeon_crtc
->native_mode
,
1141 &radeon_encoder
->native_mode
,
1142 sizeof(struct drm_display_mode
));
1144 /* fix up for overscan on hdmi */
1145 if (ASIC_IS_AVIVO(rdev
) &&
1146 ((radeon_encoder
->underscan_type
== UNDERSCAN_ON
) ||
1147 ((radeon_encoder
->underscan_type
== UNDERSCAN_AUTO
) &&
1148 drm_detect_hdmi_monitor(radeon_connector
->edid
)))) {
1149 radeon_crtc
->h_border
= (mode
->hdisplay
>> 5) + 16;
1150 radeon_crtc
->v_border
= (mode
->vdisplay
>> 5) + 16;
1151 radeon_crtc
->rmx_type
= RMX_FULL
;
1152 src_v
= crtc
->mode
.vdisplay
;
1153 dst_v
= crtc
->mode
.vdisplay
- (radeon_crtc
->v_border
* 2);
1154 src_h
= crtc
->mode
.hdisplay
;
1155 dst_h
= crtc
->mode
.hdisplay
- (radeon_crtc
->h_border
* 2);
1159 if (radeon_crtc
->rmx_type
!= radeon_encoder
->rmx_type
) {
1160 /* WARNING: Right now this can't happen but
1161 * in the future we need to check that scaling
1162 * are consistent across different encoder
1163 * (ie all encoder can work with the same
1166 DRM_ERROR("Scaling not consistent across encoder.\n");
1171 if (radeon_crtc
->rmx_type
!= RMX_OFF
) {
1173 a
.full
= dfixed_const(src_v
);
1174 b
.full
= dfixed_const(dst_v
);
1175 radeon_crtc
->vsc
.full
= dfixed_div(a
, b
);
1176 a
.full
= dfixed_const(src_h
);
1177 b
.full
= dfixed_const(dst_h
);
1178 radeon_crtc
->hsc
.full
= dfixed_div(a
, b
);
1180 radeon_crtc
->vsc
.full
= dfixed_const(1);
1181 radeon_crtc
->hsc
.full
= dfixed_const(1);