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OMAP: HSMMC: do not enable buffer ready interrupt if using DMA
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / mmc / host / omap_hsmmc.c
blobfee895b02f395ebf8177d42b845cf1d05b0d1b31
1 /*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_device.h>
24 #include <linux/workqueue.h>
25 #include <linux/timer.h>
26 #include <linux/clk.h>
27 #include <linux/mmc/host.h>
28 #include <linux/io.h>
29 #include <linux/semaphore.h>
30 #include <mach/dma.h>
31 #include <mach/hardware.h>
32 #include <mach/board.h>
33 #include <mach/mmc.h>
34 #include <mach/cpu.h>
35
36 /* OMAP HSMMC Host Controller Registers */
37 #define OMAP_HSMMC_SYSCONFIG 0x0010
38 #define OMAP_HSMMC_CON 0x002C
39 #define OMAP_HSMMC_BLK 0x0104
40 #define OMAP_HSMMC_ARG 0x0108
41 #define OMAP_HSMMC_CMD 0x010C
42 #define OMAP_HSMMC_RSP10 0x0110
43 #define OMAP_HSMMC_RSP32 0x0114
44 #define OMAP_HSMMC_RSP54 0x0118
45 #define OMAP_HSMMC_RSP76 0x011C
46 #define OMAP_HSMMC_DATA 0x0120
47 #define OMAP_HSMMC_HCTL 0x0128
48 #define OMAP_HSMMC_SYSCTL 0x012C
49 #define OMAP_HSMMC_STAT 0x0130
50 #define OMAP_HSMMC_IE 0x0134
51 #define OMAP_HSMMC_ISE 0x0138
52 #define OMAP_HSMMC_CAPA 0x0140
53
54 #define VS18 (1 << 26)
55 #define VS30 (1 << 25)
56 #define SDVS18 (0x5 << 9)
57 #define SDVS30 (0x6 << 9)
58 #define SDVS33 (0x7 << 9)
59 #define SDVS_MASK 0x00000E00
60 #define SDVSCLR 0xFFFFF1FF
61 #define SDVSDET 0x00000400
62 #define AUTOIDLE 0x1
63 #define SDBP (1 << 8)
64 #define DTO 0xe
65 #define ICE 0x1
66 #define ICS 0x2
67 #define CEN (1 << 2)
68 #define CLKD_MASK 0x0000FFC0
69 #define CLKD_SHIFT 6
70 #define DTO_MASK 0x000F0000
71 #define DTO_SHIFT 16
72 #define INT_EN_MASK 0x307F0033
73 #define BWR_ENABLE (1 << 4)
74 #define BRR_ENABLE (1 << 5)
75 #define INIT_STREAM (1 << 1)
76 #define DP_SELECT (1 << 21)
77 #define DDIR (1 << 4)
78 #define DMA_EN 0x1
79 #define MSBS (1 << 5)
80 #define BCE (1 << 1)
81 #define FOUR_BIT (1 << 1)
82 #define DW8 (1 << 5)
83 #define CC 0x1
84 #define TC 0x02
85 #define OD 0x1
86 #define ERR (1 << 15)
87 #define CMD_TIMEOUT (1 << 16)
88 #define DATA_TIMEOUT (1 << 20)
89 #define CMD_CRC (1 << 17)
90 #define DATA_CRC (1 << 21)
91 #define CARD_ERR (1 << 28)
92 #define STAT_CLEAR 0xFFFFFFFF
93 #define INIT_STREAM_CMD 0x00000000
94 #define DUAL_VOLT_OCR_BIT 7
95 #define SRC (1 << 25)
96 #define SRD (1 << 26)
97
98 /*
99 * FIXME: Most likely all the data using these _DEVID defines should come
100 * from the platform_data, or implemented in controller and slot specific
101 * functions.
102 */
103 #define OMAP_MMC1_DEVID 0
104 #define OMAP_MMC2_DEVID 1
105 #define OMAP_MMC3_DEVID 2
106
107 #define MMC_TIMEOUT_MS 20
108 #define OMAP_MMC_MASTER_CLOCK 96000000
109 #define DRIVER_NAME "mmci-omap-hs"
110
111 /*
112 * One controller can have multiple slots, like on some omap boards using
113 * omap.c controller driver. Luckily this is not currently done on any known
114 * omap_hsmmc.c device.
115 */
116 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
117
118 /*
119 * MMC Host controller read/write API's
120 */
121 #define OMAP_HSMMC_READ(base, reg) \
122 __raw_readl((base) + OMAP_HSMMC_##reg)
123
124 #define OMAP_HSMMC_WRITE(base, reg, val) \
125 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
126
127 struct mmc_omap_host {
128 struct device *dev;
129 struct mmc_host *mmc;
130 struct mmc_request *mrq;
131 struct mmc_command *cmd;
132 struct mmc_data *data;
133 struct clk *fclk;
134 struct clk *iclk;
135 struct clk *dbclk;
136 struct semaphore sem;
137 struct work_struct mmc_carddetect_work;
138 void __iomem *base;
139 resource_size_t mapbase;
140 unsigned int id;
141 unsigned int dma_len;
142 unsigned int dma_sg_idx;
143 unsigned char bus_mode;
144 u32 *buffer;
145 u32 bytesleft;
146 int suspended;
147 int irq;
148 int carddetect;
149 int use_dma, dma_ch;
150 int dma_line_tx, dma_line_rx;
151 int slot_id;
152 int dbclk_enabled;
153 int response_busy;
154 struct omap_mmc_platform_data *pdata;
155 };
156
157 /*
158 * Stop clock to the card
159 */
160 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
161 {
162 OMAP_HSMMC_WRITE(host->base, SYSCTL,
163 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
164 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
165 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
166 }
167
168 /*
169 * Send init stream sequence to card
170 * before sending IDLE command
171 */
172 static void send_init_stream(struct mmc_omap_host *host)
173 {
174 int reg = 0;
175 unsigned long timeout;
176
177 disable_irq(host->irq);
178 OMAP_HSMMC_WRITE(host->base, CON,
179 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
180 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
181
182 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
183 while ((reg != CC) && time_before(jiffies, timeout))
184 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
185
186 OMAP_HSMMC_WRITE(host->base, CON,
187 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
188 enable_irq(host->irq);
189 }
190
191 static inline
192 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
193 {
194 int r = 1;
195
196 if (host->pdata->slots[host->slot_id].get_cover_state)
197 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
198 host->slot_id);
199 return r;
200 }
201
202 static ssize_t
203 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
204 char *buf)
205 {
206 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
207 struct mmc_omap_host *host = mmc_priv(mmc);
208
209 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
210 "open");
211 }
212
213 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
214
215 static ssize_t
216 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
217 char *buf)
218 {
219 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
220 struct mmc_omap_host *host = mmc_priv(mmc);
221 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
222
223 return sprintf(buf, "%s\n", slot.name);
224 }
225
226 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
227
228 /*
229 * Configure the response type and send the cmd.
230 */
231 static void
232 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
233 struct mmc_data *data)
234 {
235 int cmdreg = 0, resptype = 0, cmdtype = 0;
236
237 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
238 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
239 host->cmd = cmd;
240
241 /*
242 * Clear status bits and enable interrupts
243 */
244 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
245 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
246
247 if (host->use_dma)
248 OMAP_HSMMC_WRITE(host->base, IE,
249 INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
250 else
251 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
252
253 host->response_busy = 0;
254 if (cmd->flags & MMC_RSP_PRESENT) {
255 if (cmd->flags & MMC_RSP_136)
256 resptype = 1;
257 else if (cmd->flags & MMC_RSP_BUSY) {
258 resptype = 3;
259 host->response_busy = 1;
260 } else
261 resptype = 2;
262 }
263
264 /*
265 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
266 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
267 * a val of 0x3, rest 0x0.
268 */
269 if (cmd == host->mrq->stop)
270 cmdtype = 0x3;
271
272 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
273
274 if (data) {
275 cmdreg |= DP_SELECT | MSBS | BCE;
276 if (data->flags & MMC_DATA_READ)
277 cmdreg |= DDIR;
278 else
279 cmdreg &= ~(DDIR);
280 }
281
282 if (host->use_dma)
283 cmdreg |= DMA_EN;
284
285 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
286 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
287 }
288
289 static int
290 mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
291 {
292 if (data->flags & MMC_DATA_WRITE)
293 return DMA_TO_DEVICE;
294 else
295 return DMA_FROM_DEVICE;
296 }
297
298 /*
299 * Notify the transfer complete to MMC core
300 */
301 static void
302 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
303 {
304 if (!data) {
305 struct mmc_request *mrq = host->mrq;
306
307 host->mrq = NULL;
308 mmc_request_done(host->mmc, mrq);
309 return;
310 }
311
312 host->data = NULL;
313
314 if (host->use_dma && host->dma_ch != -1)
315 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
316 mmc_omap_get_dma_dir(host, data));
317
318 if (!data->error)
319 data->bytes_xfered += data->blocks * (data->blksz);
320 else
321 data->bytes_xfered = 0;
322
323 if (!data->stop) {
324 host->mrq = NULL;
325 mmc_request_done(host->mmc, data->mrq);
326 return;
327 }
328 mmc_omap_start_command(host, data->stop, NULL);
329 }
330
331 /*
332 * Notify the core about command completion
333 */
334 static void
335 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
336 {
337 host->cmd = NULL;
338
339 if (cmd->flags & MMC_RSP_PRESENT) {
340 if (cmd->flags & MMC_RSP_136) {
341 /* response type 2 */
342 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
343 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
344 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
345 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
346 } else {
347 /* response types 1, 1b, 3, 4, 5, 6 */
348 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
349 }
350 }
351 if ((host->data == NULL && !host->response_busy) || cmd->error) {
352 host->mrq = NULL;
353 mmc_request_done(host->mmc, cmd->mrq);
354 }
355 }
356
357 /*
358 * DMA clean up for command errors
359 */
360 static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
361 {
362 host->data->error = errno;
363
364 if (host->use_dma && host->dma_ch != -1) {
365 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
366 mmc_omap_get_dma_dir(host, host->data));
367 omap_free_dma(host->dma_ch);
368 host->dma_ch = -1;
369 up(&host->sem);
370 }
371 host->data = NULL;
372 }
373
374 /*
375 * Readable error output
376 */
377 #ifdef CONFIG_MMC_DEBUG
378 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
379 {
380 /* --- means reserved bit without definition at documentation */
381 static const char *mmc_omap_status_bits[] = {
382 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
383 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
384 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
385 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
386 };
387 char res[256];
388 char *buf = res;
389 int len, i;
390
391 len = sprintf(buf, "MMC IRQ 0x%x :", status);
392 buf += len;
393
394 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
395 if (status & (1 << i)) {
396 len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
397 buf += len;
398 }
399
400 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
401 }
402 #endif /* CONFIG_MMC_DEBUG */
403
404 /*
405 * MMC controller internal state machines reset
406 *
407 * Used to reset command or data internal state machines, using respectively
408 * SRC or SRD bit of SYSCTL register
409 * Can be called from interrupt context
410 */
411 static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
412 unsigned long bit)
413 {
414 unsigned long i = 0;
415 unsigned long limit = (loops_per_jiffy *
416 msecs_to_jiffies(MMC_TIMEOUT_MS));
417
418 OMAP_HSMMC_WRITE(host->base, SYSCTL,
419 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
420
421 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
422 (i++ < limit))
423 cpu_relax();
424
425 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
426 dev_err(mmc_dev(host->mmc),
427 "Timeout waiting on controller reset in %s\n",
428 __func__);
429 }
430
431 /*
432 * MMC controller IRQ handler
433 */
434 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
435 {
436 struct mmc_omap_host *host = dev_id;
437 struct mmc_data *data;
438 int end_cmd = 0, end_trans = 0, status;
439
440 if (host->mrq == NULL) {
441 OMAP_HSMMC_WRITE(host->base, STAT,
442 OMAP_HSMMC_READ(host->base, STAT));
443 /* Flush posted write */
444 OMAP_HSMMC_READ(host->base, STAT);
445 return IRQ_HANDLED;
446 }
447
448 data = host->data;
449 status = OMAP_HSMMC_READ(host->base, STAT);
450 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
451
452 if (status & ERR) {
453 #ifdef CONFIG_MMC_DEBUG
454 mmc_omap_report_irq(host, status);
455 #endif
456 if ((status & CMD_TIMEOUT) ||
457 (status & CMD_CRC)) {
458 if (host->cmd) {
459 if (status & CMD_TIMEOUT) {
460 mmc_omap_reset_controller_fsm(host, SRC);
461 host->cmd->error = -ETIMEDOUT;
462 } else {
463 host->cmd->error = -EILSEQ;
464 }
465 end_cmd = 1;
466 }
467 if (host->data || host->response_busy) {
468 if (host->data)
469 mmc_dma_cleanup(host, -ETIMEDOUT);
470 host->response_busy = 0;
471 mmc_omap_reset_controller_fsm(host, SRD);
472 }
473 }
474 if ((status & DATA_TIMEOUT) ||
475 (status & DATA_CRC)) {
476 if (host->data || host->response_busy) {
477 int err = (status & DATA_TIMEOUT) ?
478 -ETIMEDOUT : -EILSEQ;
479
480 if (host->data)
481 mmc_dma_cleanup(host, err);
482 else
483 host->mrq->cmd->error = err;
484 host->response_busy = 0;
485 mmc_omap_reset_controller_fsm(host, SRD);
486 end_trans = 1;
487 }
488 }
489 if (status & CARD_ERR) {
490 dev_dbg(mmc_dev(host->mmc),
491 "Ignoring card err CMD%d\n", host->cmd->opcode);
492 if (host->cmd)
493 end_cmd = 1;
494 if (host->data)
495 end_trans = 1;
496 }
497 }
498
499 OMAP_HSMMC_WRITE(host->base, STAT, status);
500 /* Flush posted write */
501 OMAP_HSMMC_READ(host->base, STAT);
502
503 if (end_cmd || ((status & CC) && host->cmd))
504 mmc_omap_cmd_done(host, host->cmd);
505 if (end_trans || (status & TC))
506 mmc_omap_xfer_done(host, data);
507
508 return IRQ_HANDLED;
509 }
510
511 static void set_sd_bus_power(struct mmc_omap_host *host)
512 {
513 unsigned long i;
514
515 OMAP_HSMMC_WRITE(host->base, HCTL,
516 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
517 for (i = 0; i < loops_per_jiffy; i++) {
518 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
519 break;
520 cpu_relax();
521 }
522 }
523
524 /*
525 * Switch MMC interface voltage ... only relevant for MMC1.
526 *
527 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
528 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
529 * Some chips, like eMMC ones, use internal transceivers.
530 */
531 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
532 {
533 u32 reg_val = 0;
534 int ret;
535
536 /* Disable the clocks */
537 clk_disable(host->fclk);
538 clk_disable(host->iclk);
539 clk_disable(host->dbclk);
540
541 /* Turn the power off */
542 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
543 if (ret != 0)
544 goto err;
545
546 /* Turn the power ON with given VDD 1.8 or 3.0v */
547 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
548 if (ret != 0)
549 goto err;
550
551 clk_enable(host->fclk);
552 clk_enable(host->iclk);
553 clk_enable(host->dbclk);
554
555 OMAP_HSMMC_WRITE(host->base, HCTL,
556 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
557 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
558
559 /*
560 * If a MMC dual voltage card is detected, the set_ios fn calls
561 * this fn with VDD bit set for 1.8V. Upon card removal from the
562 * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
563 *
564 * Cope with a bit of slop in the range ... per data sheets:
565 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
566 * but recommended values are 1.71V to 1.89V
567 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
568 * but recommended values are 2.7V to 3.3V
569 *
570 * Board setup code shouldn't permit anything very out-of-range.
571 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
572 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
573 */
574 if ((1 << vdd) <= MMC_VDD_23_24)
575 reg_val |= SDVS18;
576 else
577 reg_val |= SDVS30;
578
579 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
580 set_sd_bus_power(host);
581
582 return 0;
583 err:
584 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
585 return ret;
586 }
587
588 /*
589 * Work Item to notify the core about card insertion/removal
590 */
591 static void mmc_omap_detect(struct work_struct *work)
592 {
593 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
594 mmc_carddetect_work);
595 struct omap_mmc_slot_data *slot = &mmc_slot(host);
596
597 if (mmc_slot(host).card_detect)
598 host->carddetect = slot->card_detect(slot->card_detect_irq);
599 else
600 host->carddetect = -ENOSYS;
601
602 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
603 if (host->carddetect) {
604 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
605 } else {
606 mmc_omap_reset_controller_fsm(host, SRD);
607 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
608 }
609 }
610
611 /*
612 * ISR for handling card insertion and removal
613 */
614 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
615 {
616 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
617
618 schedule_work(&host->mmc_carddetect_work);
619
620 return IRQ_HANDLED;
621 }
622
623 static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
624 struct mmc_data *data)
625 {
626 int sync_dev;
627
628 if (data->flags & MMC_DATA_WRITE)
629 sync_dev = host->dma_line_tx;
630 else
631 sync_dev = host->dma_line_rx;
632 return sync_dev;
633 }
634
635 static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
636 struct mmc_data *data,
637 struct scatterlist *sgl)
638 {
639 int blksz, nblk, dma_ch;
640
641 dma_ch = host->dma_ch;
642 if (data->flags & MMC_DATA_WRITE) {
643 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
644 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
645 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
646 sg_dma_address(sgl), 0, 0);
647 } else {
648 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
649 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
650 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
651 sg_dma_address(sgl), 0, 0);
652 }
653
654 blksz = host->data->blksz;
655 nblk = sg_dma_len(sgl) / blksz;
656
657 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
658 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
659 mmc_omap_get_dma_sync_dev(host, data),
660 !(data->flags & MMC_DATA_WRITE));
661
662 omap_start_dma(dma_ch);
663 }
664
665 /*
666 * DMA call back function
667 */
668 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
669 {
670 struct mmc_omap_host *host = data;
671
672 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
673 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
674
675 if (host->dma_ch < 0)
676 return;
677
678 host->dma_sg_idx++;
679 if (host->dma_sg_idx < host->dma_len) {
680 /* Fire up the next transfer. */
681 mmc_omap_config_dma_params(host, host->data,
682 host->data->sg + host->dma_sg_idx);
683 return;
684 }
685
686 omap_free_dma(host->dma_ch);
687 host->dma_ch = -1;
688 /*
689 * DMA Callback: run in interrupt context.
690 * mutex_unlock will throw a kernel warning if used.
691 */
692 up(&host->sem);
693 }
694
695 /*
696 * Routine to configure and start DMA for the MMC card
697 */
698 static int
699 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
700 {
701 int dma_ch = 0, ret = 0, err = 1, i;
702 struct mmc_data *data = req->data;
703
704 /* Sanity check: all the SG entries must be aligned by block size. */
705 for (i = 0; i < host->dma_len; i++) {
706 struct scatterlist *sgl;
707
708 sgl = data->sg + i;
709 if (sgl->length % data->blksz)
710 return -EINVAL;
711 }
712 if ((data->blksz % 4) != 0)
713 /* REVISIT: The MMC buffer increments only when MSB is written.
714 * Return error for blksz which is non multiple of four.
715 */
716 return -EINVAL;
717
718 /*
719 * If for some reason the DMA transfer is still active,
720 * we wait for timeout period and free the dma
721 */
722 if (host->dma_ch != -1) {
723 set_current_state(TASK_UNINTERRUPTIBLE);
724 schedule_timeout(100);
725 if (down_trylock(&host->sem)) {
726 omap_free_dma(host->dma_ch);
727 host->dma_ch = -1;
728 up(&host->sem);
729 return err;
730 }
731 } else {
732 if (down_trylock(&host->sem))
733 return err;
734 }
735
736 ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
737 mmc_omap_dma_cb,host, &dma_ch);
738 if (ret != 0) {
739 dev_err(mmc_dev(host->mmc),
740 "%s: omap_request_dma() failed with %d\n",
741 mmc_hostname(host->mmc), ret);
742 return ret;
743 }
744
745 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
746 data->sg_len, mmc_omap_get_dma_dir(host, data));
747 host->dma_ch = dma_ch;
748 host->dma_sg_idx = 0;
749
750 mmc_omap_config_dma_params(host, data, data->sg);
751
752 return 0;
753 }
754
755 static void set_data_timeout(struct mmc_omap_host *host,
756 struct mmc_request *req)
757 {
758 unsigned int timeout, cycle_ns;
759 uint32_t reg, clkd, dto = 0;
760
761 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
762 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
763 if (clkd == 0)
764 clkd = 1;
765
766 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
767 timeout = req->data->timeout_ns / cycle_ns;
768 timeout += req->data->timeout_clks;
769 if (timeout) {
770 while ((timeout & 0x80000000) == 0) {
771 dto += 1;
772 timeout <<= 1;
773 }
774 dto = 31 - dto;
775 timeout <<= 1;
776 if (timeout && dto)
777 dto += 1;
778 if (dto >= 13)
779 dto -= 13;
780 else
781 dto = 0;
782 if (dto > 14)
783 dto = 14;
784 }
785
786 reg &= ~DTO_MASK;
787 reg |= dto << DTO_SHIFT;
788 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
789 }
790
791 /*
792 * Configure block length for MMC/SD cards and initiate the transfer.
793 */
794 static int
795 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
796 {
797 int ret;
798 host->data = req->data;
799
800 if (req->data == NULL) {
801 OMAP_HSMMC_WRITE(host->base, BLK, 0);
802 return 0;
803 }
804
805 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
806 | (req->data->blocks << 16));
807 set_data_timeout(host, req);
808
809 if (host->use_dma) {
810 ret = mmc_omap_start_dma_transfer(host, req);
811 if (ret != 0) {
812 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
813 return ret;
814 }
815 }
816 return 0;
817 }
818
819 /*
820 * Request function. for read/write operation
821 */
822 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
823 {
824 struct mmc_omap_host *host = mmc_priv(mmc);
825
826 WARN_ON(host->mrq != NULL);
827 host->mrq = req;
828 mmc_omap_prepare_data(host, req);
829 mmc_omap_start_command(host, req->cmd, req->data);
830 }
831
832
833 /* Routine to configure clock values. Exposed API to core */
834 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
835 {
836 struct mmc_omap_host *host = mmc_priv(mmc);
837 u16 dsor = 0;
838 unsigned long regval;
839 unsigned long timeout;
840 u32 con;
841
842 switch (ios->power_mode) {
843 case MMC_POWER_OFF:
844 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
845 break;
846 case MMC_POWER_UP:
847 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
848 break;
849 }
850
851 con = OMAP_HSMMC_READ(host->base, CON);
852 switch (mmc->ios.bus_width) {
853 case MMC_BUS_WIDTH_8:
854 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
855 break;
856 case MMC_BUS_WIDTH_4:
857 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
858 OMAP_HSMMC_WRITE(host->base, HCTL,
859 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
860 break;
861 case MMC_BUS_WIDTH_1:
862 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
863 OMAP_HSMMC_WRITE(host->base, HCTL,
864 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
865 break;
866 }
867
868 if (host->id == OMAP_MMC1_DEVID) {
869 /* Only MMC1 can interface at 3V without some flavor
870 * of external transceiver; but they all handle 1.8V.
871 */
872 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
873 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
874 /*
875 * The mmc_select_voltage fn of the core does
876 * not seem to set the power_mode to
877 * MMC_POWER_UP upon recalculating the voltage.
878 * vdd 1.8v.
879 */
880 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
881 dev_dbg(mmc_dev(host->mmc),
882 "Switch operation failed\n");
883 }
884 }
885
886 if (ios->clock) {
887 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
888 if (dsor < 1)
889 dsor = 1;
890
891 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
892 dsor++;
893
894 if (dsor > 250)
895 dsor = 250;
896 }
897 omap_mmc_stop_clock(host);
898 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
899 regval = regval & ~(CLKD_MASK);
900 regval = regval | (dsor << 6) | (DTO << 16);
901 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
902 OMAP_HSMMC_WRITE(host->base, SYSCTL,
903 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
904
905 /* Wait till the ICS bit is set */
906 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
907 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
908 && time_before(jiffies, timeout))
909 msleep(1);
910
911 OMAP_HSMMC_WRITE(host->base, SYSCTL,
912 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
913
914 if (ios->power_mode == MMC_POWER_ON)
915 send_init_stream(host);
916
917 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
918 OMAP_HSMMC_WRITE(host->base, CON,
919 OMAP_HSMMC_READ(host->base, CON) | OD);
920 }
921
922 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
923 {
924 struct mmc_omap_host *host = mmc_priv(mmc);
925 struct omap_mmc_platform_data *pdata = host->pdata;
926
927 if (!pdata->slots[0].card_detect)
928 return -ENOSYS;
929 return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
930 }
931
932 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
933 {
934 struct mmc_omap_host *host = mmc_priv(mmc);
935 struct omap_mmc_platform_data *pdata = host->pdata;
936
937 if (!pdata->slots[0].get_ro)
938 return -ENOSYS;
939 return pdata->slots[0].get_ro(host->dev, 0);
940 }
941
942 static void omap_hsmmc_init(struct mmc_omap_host *host)
943 {
944 u32 hctl, capa, value;
945
946 /* Only MMC1 supports 3.0V */
947 if (host->id == OMAP_MMC1_DEVID) {
948 hctl = SDVS30;
949 capa = VS30 | VS18;
950 } else {
951 hctl = SDVS18;
952 capa = VS18;
953 }
954
955 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
956 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
957
958 value = OMAP_HSMMC_READ(host->base, CAPA);
959 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
960
961 /* Set the controller to AUTO IDLE mode */
962 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
963 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
964
965 /* Set SD bus power bit */
966 set_sd_bus_power(host);
967 }
968
969 static struct mmc_host_ops mmc_omap_ops = {
970 .request = omap_mmc_request,
971 .set_ios = omap_mmc_set_ios,
972 .get_cd = omap_hsmmc_get_cd,
973 .get_ro = omap_hsmmc_get_ro,
974 /* NYET -- enable_sdio_irq */
975 };
976
977 static int __init omap_mmc_probe(struct platform_device *pdev)
978 {
979 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
980 struct mmc_host *mmc;
981 struct mmc_omap_host *host = NULL;
982 struct resource *res;
983 int ret = 0, irq;
984
985 if (pdata == NULL) {
986 dev_err(&pdev->dev, "Platform Data is missing\n");
987 return -ENXIO;
988 }
989
990 if (pdata->nr_slots == 0) {
991 dev_err(&pdev->dev, "No Slots\n");
992 return -ENXIO;
993 }
994
995 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
996 irq = platform_get_irq(pdev, 0);
997 if (res == NULL || irq < 0)
998 return -ENXIO;
999
1000 res = request_mem_region(res->start, res->end - res->start + 1,
1001 pdev->name);
1002 if (res == NULL)
1003 return -EBUSY;
1004
1005 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1006 if (!mmc) {
1007 ret = -ENOMEM;
1008 goto err;
1009 }
1010
1011 host = mmc_priv(mmc);
1012 host->mmc = mmc;
1013 host->pdata = pdata;
1014 host->dev = &pdev->dev;
1015 host->use_dma = 1;
1016 host->dev->dma_mask = &pdata->dma_mask;
1017 host->dma_ch = -1;
1018 host->irq = irq;
1019 host->id = pdev->id;
1020 host->slot_id = 0;
1021 host->mapbase = res->start;
1022 host->base = ioremap(host->mapbase, SZ_4K);
1023
1024 platform_set_drvdata(pdev, host);
1025 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1026
1027 mmc->ops = &mmc_omap_ops;
1028 mmc->f_min = 400000;
1029 mmc->f_max = 52000000;
1030
1031 sema_init(&host->sem, 1);
1032
1033 host->iclk = clk_get(&pdev->dev, "ick");
1034 if (IS_ERR(host->iclk)) {
1035 ret = PTR_ERR(host->iclk);
1036 host->iclk = NULL;
1037 goto err1;
1038 }
1039 host->fclk = clk_get(&pdev->dev, "fck");
1040 if (IS_ERR(host->fclk)) {
1041 ret = PTR_ERR(host->fclk);
1042 host->fclk = NULL;
1043 clk_put(host->iclk);
1044 goto err1;
1045 }
1046
1047 if (clk_enable(host->fclk) != 0) {
1048 clk_put(host->iclk);
1049 clk_put(host->fclk);
1050 goto err1;
1051 }
1052
1053 if (clk_enable(host->iclk) != 0) {
1054 clk_disable(host->fclk);
1055 clk_put(host->iclk);
1056 clk_put(host->fclk);
1057 goto err1;
1058 }
1059
1060 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1061 /*
1062 * MMC can still work without debounce clock.
1063 */
1064 if (IS_ERR(host->dbclk))
1065 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1066 else
1067 if (clk_enable(host->dbclk) != 0)
1068 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1069 " clk failed\n");
1070 else
1071 host->dbclk_enabled = 1;
1072
1073 /* Since we do only SG emulation, we can have as many segs
1074 * as we want. */
1075 mmc->max_phys_segs = 1024;
1076 mmc->max_hw_segs = 1024;
1077
1078 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1079 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1080 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1081 mmc->max_seg_size = mmc->max_req_size;
1082
1083 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1084
1085 if (pdata->slots[host->slot_id].wires >= 8)
1086 mmc->caps |= MMC_CAP_8_BIT_DATA;
1087 else if (pdata->slots[host->slot_id].wires >= 4)
1088 mmc->caps |= MMC_CAP_4_BIT_DATA;
1089
1090 omap_hsmmc_init(host);
1091
1092 /* Select DMA lines */
1093 switch (host->id) {
1094 case OMAP_MMC1_DEVID:
1095 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1096 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1097 break;
1098 case OMAP_MMC2_DEVID:
1099 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1100 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1101 break;
1102 case OMAP_MMC3_DEVID:
1103 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1104 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1105 break;
1106 default:
1107 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1108 goto err_irq;
1109 }
1110
1111 /* Request IRQ for MMC operations */
1112 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1113 mmc_hostname(mmc), host);
1114 if (ret) {
1115 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1116 goto err_irq;
1117 }
1118
1119 /* initialize power supplies, gpios, etc */
1120 if (pdata->init != NULL) {
1121 if (pdata->init(&pdev->dev) != 0) {
1122 dev_dbg(mmc_dev(host->mmc), "late init error\n");
1123 goto err_irq_cd_init;
1124 }
1125 }
1126 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1127
1128 /* Request IRQ for card detect */
1129 if ((mmc_slot(host).card_detect_irq)) {
1130 ret = request_irq(mmc_slot(host).card_detect_irq,
1131 omap_mmc_cd_handler,
1132 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1133 | IRQF_DISABLED,
1134 mmc_hostname(mmc), host);
1135 if (ret) {
1136 dev_dbg(mmc_dev(host->mmc),
1137 "Unable to grab MMC CD IRQ\n");
1138 goto err_irq_cd;
1139 }
1140 }
1141
1142 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1143 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1144
1145 mmc_add_host(mmc);
1146
1147 if (host->pdata->slots[host->slot_id].name != NULL) {
1148 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1149 if (ret < 0)
1150 goto err_slot_name;
1151 }
1152 if (mmc_slot(host).card_detect_irq &&
1153 host->pdata->slots[host->slot_id].get_cover_state) {
1154 ret = device_create_file(&mmc->class_dev,
1155 &dev_attr_cover_switch);
1156 if (ret < 0)
1157 goto err_cover_switch;
1158 }
1159
1160 return 0;
1161
1162 err_cover_switch:
1163 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1164 err_slot_name:
1165 mmc_remove_host(mmc);
1166 err_irq_cd:
1167 free_irq(mmc_slot(host).card_detect_irq, host);
1168 err_irq_cd_init:
1169 free_irq(host->irq, host);
1170 err_irq:
1171 clk_disable(host->fclk);
1172 clk_disable(host->iclk);
1173 clk_put(host->fclk);
1174 clk_put(host->iclk);
1175 if (host->dbclk_enabled) {
1176 clk_disable(host->dbclk);
1177 clk_put(host->dbclk);
1178 }
1179
1180 err1:
1181 iounmap(host->base);
1182 err:
1183 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1184 release_mem_region(res->start, res->end - res->start + 1);
1185 if (host)
1186 mmc_free_host(mmc);
1187 return ret;
1188 }
1189
1190 static int omap_mmc_remove(struct platform_device *pdev)
1191 {
1192 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1193 struct resource *res;
1194
1195 if (host) {
1196 mmc_remove_host(host->mmc);
1197 if (host->pdata->cleanup)
1198 host->pdata->cleanup(&pdev->dev);
1199 free_irq(host->irq, host);
1200 if (mmc_slot(host).card_detect_irq)
1201 free_irq(mmc_slot(host).card_detect_irq, host);
1202 flush_scheduled_work();
1203
1204 clk_disable(host->fclk);
1205 clk_disable(host->iclk);
1206 clk_put(host->fclk);
1207 clk_put(host->iclk);
1208 if (host->dbclk_enabled) {
1209 clk_disable(host->dbclk);
1210 clk_put(host->dbclk);
1211 }
1212
1213 mmc_free_host(host->mmc);
1214 iounmap(host->base);
1215 }
1216
1217 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1218 if (res)
1219 release_mem_region(res->start, res->end - res->start + 1);
1220 platform_set_drvdata(pdev, NULL);
1221
1222 return 0;
1223 }
1224
1225 #ifdef CONFIG_PM
1226 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1227 {
1228 int ret = 0;
1229 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1230
1231 if (host && host->suspended)
1232 return 0;
1233
1234 if (host) {
1235 ret = mmc_suspend_host(host->mmc, state);
1236 if (ret == 0) {
1237 host->suspended = 1;
1238
1239 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1240 OMAP_HSMMC_WRITE(host->base, IE, 0);
1241
1242 if (host->pdata->suspend) {
1243 ret = host->pdata->suspend(&pdev->dev,
1244 host->slot_id);
1245 if (ret)
1246 dev_dbg(mmc_dev(host->mmc),
1247 "Unable to handle MMC board"
1248 " level suspend\n");
1249 }
1250
1251 OMAP_HSMMC_WRITE(host->base, HCTL,
1252 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1253 clk_disable(host->fclk);
1254 clk_disable(host->iclk);
1255 clk_disable(host->dbclk);
1256 }
1257
1258 }
1259 return ret;
1260 }
1261
1262 /* Routine to resume the MMC device */
1263 static int omap_mmc_resume(struct platform_device *pdev)
1264 {
1265 int ret = 0;
1266 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1267
1268 if (host && !host->suspended)
1269 return 0;
1270
1271 if (host) {
1272
1273 ret = clk_enable(host->fclk);
1274 if (ret)
1275 goto clk_en_err;
1276
1277 ret = clk_enable(host->iclk);
1278 if (ret) {
1279 clk_disable(host->fclk);
1280 clk_put(host->fclk);
1281 goto clk_en_err;
1282 }
1283
1284 if (clk_enable(host->dbclk) != 0)
1285 dev_dbg(mmc_dev(host->mmc),
1286 "Enabling debounce clk failed\n");
1287
1288 omap_hsmmc_init(host);
1289
1290 if (host->pdata->resume) {
1291 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1292 if (ret)
1293 dev_dbg(mmc_dev(host->mmc),
1294 "Unmask interrupt failed\n");
1295 }
1296
1297 /* Notify the core to resume the host */
1298 ret = mmc_resume_host(host->mmc);
1299 if (ret == 0)
1300 host->suspended = 0;
1301 }
1302
1303 return ret;
1304
1305 clk_en_err:
1306 dev_dbg(mmc_dev(host->mmc),
1307 "Failed to enable MMC clocks during resume\n");
1308 return ret;
1309 }
1310
1311 #else
1312 #define omap_mmc_suspend NULL
1313 #define omap_mmc_resume NULL
1314 #endif
1315
1316 static struct platform_driver omap_mmc_driver = {
1317 .probe = omap_mmc_probe,
1318 .remove = omap_mmc_remove,
1319 .suspend = omap_mmc_suspend,
1320 .resume = omap_mmc_resume,
1321 .driver = {
1322 .name = DRIVER_NAME,
1323 .owner = THIS_MODULE,
1324 },
1325 };
1326
1327 static int __init omap_mmc_init(void)
1328 {
1329 /* Register the MMC driver */
1330 return platform_driver_register(&omap_mmc_driver);
1331 }
1332
1333 static void __exit omap_mmc_cleanup(void)
1334 {
1335 /* Unregister MMC driver */
1336 platform_driver_unregister(&omap_mmc_driver);
1337 }
1338
1339 module_init(omap_mmc_init);
1340 module_exit(omap_mmc_cleanup);
1341
1342 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1343 MODULE_LICENSE("GPL");
1344 MODULE_ALIAS("platform:" DRIVER_NAME);
1345 MODULE_AUTHOR("Texas Instruments Inc");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree