drivers/edac/amd64_edac.h

   1 /*
   2  * AMD64 class Memory Controller kernel module
   3  *
   4  * Copyright (c) 2009 SoftwareBitMaker.
   5  * Copyright (c) 2009 Advanced Micro Devices, Inc.
   6  *
   7  * This file may be distributed under the terms of the
   8  * GNU General Public License.
   9  *
  10  *      Originally Written by Thayne Harbaugh
  11  *
  12  *      Changes by Douglas "norsk" Thompson  <dougthompson@xmission.com>:
  13  *              - K8 CPU Revision D and greater support
  14  *
  15  *      Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>:
  16  *              - Module largely rewritten, with new (and hopefully correct)
  17  *              code for dealing with node and chip select interleaving,
  18  *              various code cleanup, and bug fixes
  19  *              - Added support for memory hoisting using DRAM hole address
  20  *              register
  21  *
  22  *      Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
  23  *              -K8 Rev (1207) revision support added, required Revision
  24  *              specific mini-driver code to support Rev F as well as
  25  *              prior revisions
  26  *
  27  *      Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
  28  *              -Family 10h revision support added. New PCI Device IDs,
  29  *              indicating new changes. Actual registers modified
  30  *              were slight, less than the Rev E to Rev F transition
  31  *              but changing the PCI Device ID was the proper thing to
  32  *              do, as it provides for almost automactic family
  33  *              detection. The mods to Rev F required more family
  34  *              information detection.
  35  *
  36  *      Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>:
  37  *              - misc fixes and code cleanups
  38  *
  39  * This module is based on the following documents
  40  * (available from http://www.amd.com/):
  41  *
  42  *      Title:  BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
  43  *              Opteron Processors
  44  *      AMD publication #: 26094
  45  *`     Revision: 3.26
  46  *
  47  *      Title:  BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
  48  *              Processors
  49  *      AMD publication #: 32559
  50  *      Revision: 3.00
  51  *      Issue Date: May 2006
  52  *
  53  *      Title:  BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
  54  *              Processors
  55  *      AMD publication #: 31116
  56  *      Revision: 3.00
  57  *      Issue Date: September 07, 2007
  58  *
  59  * Sections in the first 2 documents are no longer in sync with each other.
  60  * The Family 10h BKDG was totally re-written from scratch with a new
  61  * presentation model.
  62  * Therefore, comments that refer to a Document section might be off.
  63  */
  64
  65 #include <linux/module.h>
  66 #include <linux/ctype.h>
  67 #include <linux/init.h>
  68 #include <linux/pci.h>
  69 #include <linux/pci_ids.h>
  70 #include <linux/slab.h>
  71 #include <linux/mmzone.h>
  72 #include <linux/edac.h>
  73 #include <asm/msr.h>
  74 #include "edac_core.h"
  75 #include "mce_amd.h"
  76
  77 #define amd64_printk(level, fmt, arg...) \
  78         edac_printk(level, "amd64", fmt, ##arg)
  79
  80 #define amd64_mc_printk(mci, level, fmt, arg...) \
  81         edac_mc_chipset_printk(mci, level, "amd64", fmt, ##arg)
  82
  83 /*
  84  * Throughout the comments in this code, the following terms are used:
  85  *
  86  *      SysAddr, DramAddr, and InputAddr
  87  *
  88  *  These terms come directly from the amd64 documentation
  89  * (AMD publication #26094).  They are defined as follows:
  90  *
  91  *     SysAddr:
  92  *         This is a physical address generated by a CPU core or a device
  93  *         doing DMA.  If generated by a CPU core, a SysAddr is the result of
  94  *         a virtual to physical address translation by the CPU core's address
  95  *         translation mechanism (MMU).
  96  *
  97  *     DramAddr:
  98  *         A DramAddr is derived from a SysAddr by subtracting an offset that
  99  *         depends on which node the SysAddr maps to and whether the SysAddr
 100  *         is within a range affected by memory hoisting.  The DRAM Base
 101  *         (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
 102  *         determine which node a SysAddr maps to.
 103  *
 104  *         If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
 105  *         is within the range of addresses specified by this register, then
 106  *         a value x from the DHAR is subtracted from the SysAddr to produce a
 107  *         DramAddr.  Here, x represents the base address for the node that
 108  *         the SysAddr maps to plus an offset due to memory hoisting.  See
 109  *         section 3.4.8 and the comments in amd64_get_dram_hole_info() and
 110  *         sys_addr_to_dram_addr() below for more information.
 111  *
 112  *         If the SysAddr is not affected by the DHAR then a value y is
 113  *         subtracted from the SysAddr to produce a DramAddr.  Here, y is the
 114  *         base address for the node that the SysAddr maps to.  See section
 115  *         3.4.4 and the comments in sys_addr_to_dram_addr() below for more
 116  *         information.
 117  *
 118  *     InputAddr:
 119  *         A DramAddr is translated to an InputAddr before being passed to the
 120  *         memory controller for the node that the DramAddr is associated
 121  *         with.  The memory controller then maps the InputAddr to a csrow.
 122  *         If node interleaving is not in use, then the InputAddr has the same
 123  *         value as the DramAddr.  Otherwise, the InputAddr is produced by
 124  *         discarding the bits used for node interleaving from the DramAddr.
 125  *         See section 3.4.4 for more information.
 126  *
 127  *         The memory controller for a given node uses its DRAM CS Base and
 128  *         DRAM CS Mask registers to map an InputAddr to a csrow.  See
 129  *         sections 3.5.4 and 3.5.5 for more information.
 130  */
 131
 132 #define EDAC_AMD64_VERSION              " Ver: 3.3.0 " __DATE__
 133 #define EDAC_MOD_STR                    "amd64_edac"
 134
 135 #define EDAC_MAX_NUMNODES               8
 136
 137 /* Extended Model from CPUID, for CPU Revision numbers */
 138 #define K8_REV_D                        1
 139 #define K8_REV_E                        2
 140 #define K8_REV_F                        4
 141
 142 /* Hardware limit on ChipSelect rows per MC and processors per system */
 143 #define MAX_CS_COUNT                    8
 144 #define DRAM_REG_COUNT                  8
 145
 146 #define ON true
 147 #define OFF false
 148
 149 /*
 150  * PCI-defined configuration space registers
 151  */
 152
 153
 154 /*
 155  * Function 1 - Address Map
 156  */
 157 #define K8_DRAM_BASE_LOW                0x40
 158 #define K8_DRAM_LIMIT_LOW               0x44
 159 #define K8_DHAR                         0xf0
 160
 161 #define DHAR_VALID                      BIT(0)
 162 #define F10_DRAM_MEM_HOIST_VALID        BIT(1)
 163
 164 #define DHAR_BASE_MASK                  0xff000000
 165 #define dhar_base(dhar)                 (dhar & DHAR_BASE_MASK)
 166
 167 #define K8_DHAR_OFFSET_MASK             0x0000ff00
 168 #define k8_dhar_offset(dhar)            ((dhar & K8_DHAR_OFFSET_MASK) << 16)
 169
 170 #define F10_DHAR_OFFSET_MASK            0x0000ff80
 171                                         /* NOTE: Extra mask bit vs K8 */
 172 #define f10_dhar_offset(dhar)           ((dhar & F10_DHAR_OFFSET_MASK) << 16)
 173
 174
 175 /* F10 High BASE/LIMIT registers */
 176 #define F10_DRAM_BASE_HIGH              0x140
 177 #define F10_DRAM_LIMIT_HIGH             0x144
 178
 179
 180 /*
 181  * Function 2 - DRAM controller
 182  */
 183 #define K8_DCSB0                        0x40
 184 #define F10_DCSB1                       0x140
 185
 186 #define K8_DCSB_CS_ENABLE               BIT(0)
 187 #define K8_DCSB_NPT_SPARE               BIT(1)
 188 #define K8_DCSB_NPT_TESTFAIL            BIT(2)
 189
 190 /*
 191  * REV E: select [31:21] and [15:9] from DCSB and the shift amount to form
 192  * the address
 193  */
 194 #define REV_E_DCSB_BASE_BITS            (0xFFE0FE00ULL)
 195 #define REV_E_DCS_SHIFT                 4
 196
 197 #define REV_F_F1Xh_DCSB_BASE_BITS       (0x1FF83FE0ULL)
 198 #define REV_F_F1Xh_DCS_SHIFT            8
 199
 200 /*
 201  * REV F and later: selects [28:19] and [13:5] from DCSB and the shift amount
 202  * to form the address
 203  */
 204 #define REV_F_DCSB_BASE_BITS            (0x1FF83FE0ULL)
 205 #define REV_F_DCS_SHIFT                 8
 206
 207 /* DRAM CS Mask Registers */
 208 #define K8_DCSM0                        0x60
 209 #define F10_DCSM1                       0x160
 210
 211 /* REV E: select [29:21] and [15:9] from DCSM */
 212 #define REV_E_DCSM_MASK_BITS            0x3FE0FE00
 213
 214 /* unused bits [24:20] and [12:0] */
 215 #define REV_E_DCS_NOTUSED_BITS          0x01F01FFF
 216
 217 /* REV F and later: select [28:19] and [13:5] from DCSM */
 218 #define REV_F_F1Xh_DCSM_MASK_BITS       0x1FF83FE0
 219
 220 /* unused bits [26:22] and [12:0] */
 221 #define REV_F_F1Xh_DCS_NOTUSED_BITS     0x07C01FFF
 222
 223 #define DBAM0                           0x80
 224 #define DBAM1                           0x180
 225
 226 /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
 227 #define DBAM_DIMM(i, reg)               ((((reg) >> (4*i))) & 0xF)
 228
 229 #define DBAM_MAX_VALUE                  11
 230
 231
 232 #define F10_DCLR_0                      0x90
 233 #define F10_DCLR_1                      0x190
 234 #define REVE_WIDTH_128                  BIT(16)
 235 #define F10_WIDTH_128                   BIT(11)
 236
 237
 238 #define F10_DCHR_0                      0x94
 239 #define F10_DCHR_1                      0x194
 240
 241 #define F10_DCHR_FOUR_RANK_DIMM         BIT(18)
 242 #define DDR3_MODE                       BIT(8)
 243 #define F10_DCHR_MblMode                BIT(6)
 244
 245
 246 #define F10_DCTL_SEL_LOW                0x110
 247 #define dct_sel_baseaddr(pvt)           ((pvt->dram_ctl_select_low) & 0xFFFFF800)
 248 #define dct_sel_interleave_addr(pvt)    (((pvt->dram_ctl_select_low) >> 6) & 0x3)
 249 #define dct_high_range_enabled(pvt)     (pvt->dram_ctl_select_low & BIT(0))
 250 #define dct_interleave_enabled(pvt)     (pvt->dram_ctl_select_low & BIT(2))
 251 #define dct_ganging_enabled(pvt)        (pvt->dram_ctl_select_low & BIT(4))
 252 #define dct_data_intlv_enabled(pvt)     (pvt->dram_ctl_select_low & BIT(5))
 253 #define dct_dram_enabled(pvt)           (pvt->dram_ctl_select_low & BIT(8))
 254 #define dct_memory_cleared(pvt)         (pvt->dram_ctl_select_low & BIT(10))
 255
 256 #define F10_DCTL_SEL_HIGH               0x114
 257
 258 /*
 259  * Function 3 - Misc Control
 260  */
 261 #define K8_NBCTL                        0x40
 262
 263 /* Correctable ECC error reporting enable */
 264 #define K8_NBCTL_CECCEn                 BIT(0)
 265
 266 /* UnCorrectable ECC error reporting enable */
 267 #define K8_NBCTL_UECCEn                 BIT(1)
 268
 269 #define K8_NBCFG                        0x44
 270 #define K8_NBCFG_CHIPKILL               BIT(23)
 271 #define K8_NBCFG_ECC_ENABLE             BIT(22)
 272
 273 #define K8_NBSL                         0x48
 274
 275
 276 /* Family F10h: Normalized Extended Error Codes */
 277 #define F10_NBSL_EXT_ERR_RES            0x0
 278 #define F10_NBSL_EXT_ERR_ECC            0x8
 279
 280 /* Next two are overloaded values */
 281 #define F10_NBSL_EXT_ERR_LINK_PROTO     0xB
 282 #define F10_NBSL_EXT_ERR_L3_PROTO       0xB
 283
 284 #define F10_NBSL_EXT_ERR_NB_ARRAY       0xC
 285 #define F10_NBSL_EXT_ERR_DRAM_PARITY    0xD
 286 #define F10_NBSL_EXT_ERR_LINK_RETRY     0xE
 287
 288 /* Next two are overloaded values */
 289 #define F10_NBSL_EXT_ERR_GART_WALK      0xF
 290 #define F10_NBSL_EXT_ERR_DEV_WALK       0xF
 291
 292 /* 0x10 to 0x1B: Reserved */
 293 #define F10_NBSL_EXT_ERR_L3_DATA        0x1C
 294 #define F10_NBSL_EXT_ERR_L3_TAG         0x1D
 295 #define F10_NBSL_EXT_ERR_L3_LRU         0x1E
 296
 297 /* K8: Normalized Extended Error Codes */
 298 #define K8_NBSL_EXT_ERR_ECC             0x0
 299 #define K8_NBSL_EXT_ERR_CRC             0x1
 300 #define K8_NBSL_EXT_ERR_SYNC            0x2
 301 #define K8_NBSL_EXT_ERR_MST             0x3
 302 #define K8_NBSL_EXT_ERR_TGT             0x4
 303 #define K8_NBSL_EXT_ERR_GART            0x5
 304 #define K8_NBSL_EXT_ERR_RMW             0x6
 305 #define K8_NBSL_EXT_ERR_WDT             0x7
 306 #define K8_NBSL_EXT_ERR_CHIPKILL_ECC    0x8
 307 #define K8_NBSL_EXT_ERR_DRAM_PARITY     0xD
 308
 309 /*
 310  * The following are for BUS type errors AFTER values have been normalized by
 311  * shifting right
 312  */
 313 #define K8_NBSL_PP_SRC                  0x0
 314 #define K8_NBSL_PP_RES                  0x1
 315 #define K8_NBSL_PP_OBS                  0x2
 316 #define K8_NBSL_PP_GENERIC              0x3
 317
 318 #define EXTRACT_ERR_CPU_MAP(x)          ((x) & 0xF)
 319
 320 #define K8_NBEAL                        0x50
 321 #define K8_NBEAH                        0x54
 322 #define K8_SCRCTRL                      0x58
 323
 324 #define F10_NB_CFG_LOW                  0x88
 325 #define F10_NB_CFG_LOW_ENABLE_EXT_CFG   BIT(14)
 326
 327 #define F10_NB_CFG_HIGH                 0x8C
 328
 329 #define F10_ONLINE_SPARE                0xB0
 330 #define F10_ONLINE_SPARE_SWAPDONE0(x)   ((x) & BIT(1))
 331 #define F10_ONLINE_SPARE_SWAPDONE1(x)   ((x) & BIT(3))
 332 #define F10_ONLINE_SPARE_BADDRAM_CS0(x) (((x) >> 4) & 0x00000007)
 333 #define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007)
 334
 335 #define F10_NB_ARRAY_ADDR               0xB8
 336
 337 #define F10_NB_ARRAY_DRAM_ECC           0x80000000
 338
 339 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline  */
 340 #define SET_NB_ARRAY_ADDRESS(section)   (((section) & 0x3) << 1)
 341
 342 #define F10_NB_ARRAY_DATA               0xBC
 343
 344 #define SET_NB_DRAM_INJECTION_WRITE(word, bits)  \
 345                                         (BIT(((word) & 0xF) + 20) | \
 346                                         BIT(17) | bits)
 347
 348 #define SET_NB_DRAM_INJECTION_READ(word, bits)  \
 349                                         (BIT(((word) & 0xF) + 20) | \
 350                                         BIT(16) |  bits)
 351
 352 #define K8_NBCAP                        0xE8
 353 #define K8_NBCAP_CORES                  (BIT(12)|BIT(13))
 354 #define K8_NBCAP_CHIPKILL               BIT(4)
 355 #define K8_NBCAP_SECDED                 BIT(3)
 356 #define K8_NBCAP_DCT_DUAL               BIT(0)
 357
 358 #define EXT_NB_MCA_CFG                  0x180
 359
 360 /* MSRs */
 361 #define K8_MSR_MCGCTL_NBE               BIT(4)
 362
 363 #define K8_MSR_MC4CTL                   0x0410
 364 #define K8_MSR_MC4STAT                  0x0411
 365 #define K8_MSR_MC4ADDR                  0x0412
 366
 367 /* AMD sets the first MC device at device ID 0x18. */
 368 static inline int get_node_id(struct pci_dev *pdev)
 369 {
 370         return PCI_SLOT(pdev->devfn) - 0x18;
 371 }
 372
 373 enum amd64_chipset_families {
 374         K8_CPUS = 0,
 375         F10_CPUS,
 376         F11_CPUS,
 377 };
 378
 379 /* Error injection control structure */
 380 struct error_injection {
 381         u32     section;
 382         u32     word;
 383         u32     bit_map;
 384 };
 385
 386 struct amd64_pvt {
 387         /* pci_device handles which we utilize */
 388         struct pci_dev *addr_f1_ctl;
 389         struct pci_dev *dram_f2_ctl;
 390         struct pci_dev *misc_f3_ctl;
 391
 392         int mc_node_id;         /* MC index of this MC node */
 393         int ext_model;          /* extended model value of this node */
 394
 395         struct low_ops *ops;    /* pointer to per PCI Device ID func table */
 396
 397         int channel_count;
 398
 399         /* Raw registers */
 400         u32 dclr0;              /* DRAM Configuration Low DCT0 reg */
 401         u32 dclr1;              /* DRAM Configuration Low DCT1 reg */
 402         u32 dchr0;              /* DRAM Configuration High DCT0 reg */
 403         u32 dchr1;              /* DRAM Configuration High DCT1 reg */
 404         u32 nbcap;              /* North Bridge Capabilities */
 405         u32 nbcfg;              /* F10 North Bridge Configuration */
 406         u32 ext_nbcfg;          /* Extended F10 North Bridge Configuration */
 407         u32 dhar;               /* DRAM Hoist reg */
 408         u32 dbam0;              /* DRAM Base Address Mapping reg for DCT0 */
 409         u32 dbam1;              /* DRAM Base Address Mapping reg for DCT1 */
 410
 411         /* DRAM CS Base Address Registers F2x[1,0][5C:40] */
 412         u32 dcsb0[MAX_CS_COUNT];
 413         u32 dcsb1[MAX_CS_COUNT];
 414
 415         /* DRAM CS Mask Registers F2x[1,0][6C:60] */
 416         u32 dcsm0[MAX_CS_COUNT];
 417         u32 dcsm1[MAX_CS_COUNT];
 418
 419         /*
 420          * Decoded parts of DRAM BASE and LIMIT Registers
 421          * F1x[78,70,68,60,58,50,48,40]
 422          */
 423         u64 dram_base[DRAM_REG_COUNT];
 424         u64 dram_limit[DRAM_REG_COUNT];
 425         u8  dram_IntlvSel[DRAM_REG_COUNT];
 426         u8  dram_IntlvEn[DRAM_REG_COUNT];
 427         u8  dram_DstNode[DRAM_REG_COUNT];
 428         u8  dram_rw_en[DRAM_REG_COUNT];
 429
 430         /*
 431          * The following fields are set at (load) run time, after CPU revision
 432          * has been determined, since the dct_base and dct_mask registers vary
 433          * based on revision
 434          */
 435         u32 dcsb_base;          /* DCSB base bits */
 436         u32 dcsm_mask;          /* DCSM mask bits */
 437         u32 cs_count;           /* num chip selects (== num DCSB registers) */
 438         u32 num_dcsm;           /* Number of DCSM registers */
 439         u32 dcs_mask_notused;   /* DCSM notused mask bits */
 440         u32 dcs_shift;          /* DCSB and DCSM shift value */
 441
 442         u64 top_mem;            /* top of memory below 4GB */
 443         u64 top_mem2;           /* top of memory above 4GB */
 444
 445         u32 dram_ctl_select_low;        /* DRAM Controller Select Low Reg */
 446         u32 dram_ctl_select_high;       /* DRAM Controller Select High Reg */
 447         u32 online_spare;               /* On-Line spare Reg */
 448
 449         /* x4 or x8 syndromes in use */
 450         u8 syn_type;
 451
 452         /* temp storage for when input is received from sysfs */
 453         struct err_regs ctl_error_info;
 454
 455         /* place to store error injection parameters prior to issue */
 456         struct error_injection injection;
 457
 458         /* Save old hw registers' values before we modified them */
 459         u32 nbctl_mcgctl_saved;         /* When true, following 2 are valid */
 460         u32 old_nbctl;
 461
 462         /* MC Type Index value: socket F vs Family 10h */
 463         u32 mc_type_index;
 464
 465         /* misc settings */
 466         struct flags {
 467                 unsigned long cf8_extcfg:1;
 468                 unsigned long nb_mce_enable:1;
 469                 unsigned long nb_ecc_prev:1;
 470         } flags;
 471 };
 472
 473 struct scrubrate {
 474        u32 scrubval;           /* bit pattern for scrub rate */
 475        u32 bandwidth;          /* bandwidth consumed (bytes/sec) */
 476 };
 477
 478 extern struct scrubrate scrubrates[23];
 479 extern const char *tt_msgs[4];
 480 extern const char *ll_msgs[4];
 481 extern const char *rrrr_msgs[16];
 482 extern const char *to_msgs[2];
 483 extern const char *pp_msgs[4];
 484 extern const char *ii_msgs[4];
 485 extern const char *htlink_msgs[8];
 486
 487 #ifdef CONFIG_EDAC_DEBUG
 488 #define NUM_DBG_ATTRS 5
 489 #else
 490 #define NUM_DBG_ATTRS 0
 491 #endif
 492
 493 #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
 494 #define NUM_INJ_ATTRS 5
 495 #else
 496 #define NUM_INJ_ATTRS 0
 497 #endif
 498
 499 extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
 500                                      amd64_inj_attrs[NUM_INJ_ATTRS];
 501
 502 /*
 503  * Each of the PCI Device IDs types have their own set of hardware accessor
 504  * functions and per device encoding/decoding logic.
 505  */
 506 struct low_ops {
 507         int (*early_channel_count)      (struct amd64_pvt *pvt);
 508
 509         u64 (*get_error_address)        (struct mem_ctl_info *mci,
 510                                          struct err_regs *info);
 511         void (*read_dram_base_limit)    (struct amd64_pvt *pvt, int dram);
 512         void (*read_dram_ctl_register)  (struct amd64_pvt *pvt);
 513         void (*map_sysaddr_to_csrow)    (struct mem_ctl_info *mci,
 514                                          struct err_regs *info, u64 SystemAddr);
 515         int (*dbam_to_cs)               (struct amd64_pvt *pvt, int cs_mode);
 516 };
 517
 518 struct amd64_family_type {
 519         const char *ctl_name;
 520         u16 addr_f1_ctl;
 521         u16 misc_f3_ctl;
 522         struct low_ops ops;
 523 };
 524
 525 static struct amd64_family_type amd64_family_types[];
 526
 527 static inline const char *get_amd_family_name(int index)
 528 {
 529         return amd64_family_types[index].ctl_name;
 530 }
 531
 532 static inline struct low_ops *family_ops(int index)
 533 {
 534         return &amd64_family_types[index].ops;
 535 }
 536
 537 static inline int amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
 538                                            u32 *val, const char *func)
 539 {
 540         int err = 0;
 541
 542         err = pci_read_config_dword(pdev, offset, val);
 543         if (err)
 544                 amd64_printk(KERN_WARNING, "%s: error reading F%dx%x.\n",
 545                              func, PCI_FUNC(pdev->devfn), offset);
 546
 547         return err;
 548 }
 549
 550 #define amd64_read_pci_cfg(pdev, offset, val)   \
 551         amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
 552
 553 /*
 554  * For future CPU versions, verify the following as new 'slow' rates appear and
 555  * modify the necessary skip values for the supported CPU.
 556  */
 557 #define K8_MIN_SCRUB_RATE_BITS  0x0
 558 #define F10_MIN_SCRUB_RATE_BITS 0x5
 559 #define F11_MIN_SCRUB_RATE_BITS 0x6
 560
 561 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
 562                              u64 *hole_offset, u64 *hole_size);