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crypto: mv_cesa - fill inner/outer IV fields only in HMAC case
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / crypto / mv_cesa.c
blobc1925c2a88b04d37c2d377fd8863c70c20d61d85
1 /*
2 * Support for Marvell's crypto engine which can be found on some Orion5X
3 * boards.
4 *
5 * Author: Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
6 * License: GPLv2
7 *
8 */
9 #include <crypto/aes.h>
10 #include <crypto/algapi.h>
11 #include <linux/crypto.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/kthread.h>
15 #include <linux/platform_device.h>
16 #include <linux/scatterlist.h>
17 #include <linux/slab.h>
18 #include <crypto/internal/hash.h>
19 #include <crypto/sha.h>
20
21 #include "mv_cesa.h"
22
23 #define MV_CESA "MV-CESA:"
24 #define MAX_HW_HASH_SIZE 0xFFFF
25
26 /*
27 * STM:
28 * /---------------------------------------\
29 * | | request complete
30 * \./ |
31 * IDLE -> new request -> BUSY -> done -> DEQUEUE
32 * /°\ |
33 * | | more scatter entries
34 * \________________/
35 */
36 enum engine_status {
37 ENGINE_IDLE,
38 ENGINE_BUSY,
39 ENGINE_W_DEQUEUE,
40 };
41
42 /**
43 * struct req_progress - used for every crypt request
44 * @src_sg_it: sg iterator for src
45 * @dst_sg_it: sg iterator for dst
46 * @sg_src_left: bytes left in src to process (scatter list)
47 * @src_start: offset to add to src start position (scatter list)
48 * @crypt_len: length of current hw crypt/hash process
49 * @hw_nbytes: total bytes to process in hw for this request
50 * @copy_back: whether to copy data back (crypt) or not (hash)
51 * @sg_dst_left: bytes left dst to process in this scatter list
52 * @dst_start: offset to add to dst start position (scatter list)
53 * @hw_processed_bytes: number of bytes processed by hw (request).
54 *
55 * sg helper are used to iterate over the scatterlist. Since the size of the
56 * SRAM may be less than the scatter size, this struct struct is used to keep
57 * track of progress within current scatterlist.
58 */
59 struct req_progress {
60 struct sg_mapping_iter src_sg_it;
61 struct sg_mapping_iter dst_sg_it;
62 void (*complete) (void);
63 void (*process) (int is_first);
64
65 /* src mostly */
66 int sg_src_left;
67 int src_start;
68 int crypt_len;
69 int hw_nbytes;
70 /* dst mostly */
71 int copy_back;
72 int sg_dst_left;
73 int dst_start;
74 int hw_processed_bytes;
75 };
76
77 struct crypto_priv {
78 void __iomem *reg;
79 void __iomem *sram;
80 int irq;
81 struct task_struct *queue_th;
82
83 /* the lock protects queue and eng_st */
84 spinlock_t lock;
85 struct crypto_queue queue;
86 enum engine_status eng_st;
87 struct crypto_async_request *cur_req;
88 struct req_progress p;
89 int max_req_size;
90 int sram_size;
91 int has_sha1;
92 int has_hmac_sha1;
93 };
94
95 static struct crypto_priv *cpg;
96
97 struct mv_ctx {
98 u8 aes_enc_key[AES_KEY_LEN];
99 u32 aes_dec_key[8];
100 int key_len;
101 u32 need_calc_aes_dkey;
102 };
103
104 enum crypto_op {
105 COP_AES_ECB,
106 COP_AES_CBC,
107 };
108
109 struct mv_req_ctx {
110 enum crypto_op op;
111 int decrypt;
112 };
113
114 enum hash_op {
115 COP_SHA1,
116 COP_HMAC_SHA1
117 };
118
119 struct mv_tfm_hash_ctx {
120 struct crypto_shash *fallback;
121 struct crypto_shash *base_hash;
122 u32 ivs[2 * SHA1_DIGEST_SIZE / 4];
123 int count_add;
124 enum hash_op op;
125 };
126
127 struct mv_req_hash_ctx {
128 u64 count;
129 u32 state[SHA1_DIGEST_SIZE / 4];
130 u8 buffer[SHA1_BLOCK_SIZE];
131 int first_hash; /* marks that we don't have previous state */
132 int last_chunk; /* marks that this is the 'final' request */
133 int extra_bytes; /* unprocessed bytes in buffer */
134 enum hash_op op;
135 int count_add;
136 struct scatterlist dummysg;
137 };
138
139 static void compute_aes_dec_key(struct mv_ctx *ctx)
140 {
141 struct crypto_aes_ctx gen_aes_key;
142 int key_pos;
143
144 if (!ctx->need_calc_aes_dkey)
145 return;
146
147 crypto_aes_expand_key(&gen_aes_key, ctx->aes_enc_key, ctx->key_len);
148
149 key_pos = ctx->key_len + 24;
150 memcpy(ctx->aes_dec_key, &gen_aes_key.key_enc[key_pos], 4 * 4);
151 switch (ctx->key_len) {
152 case AES_KEYSIZE_256:
153 key_pos -= 2;
154 /* fall */
155 case AES_KEYSIZE_192:
156 key_pos -= 2;
157 memcpy(&ctx->aes_dec_key[4], &gen_aes_key.key_enc[key_pos],
158 4 * 4);
159 break;
160 }
161 ctx->need_calc_aes_dkey = 0;
162 }
163
164 static int mv_setkey_aes(struct crypto_ablkcipher *cipher, const u8 *key,
165 unsigned int len)
166 {
167 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
168 struct mv_ctx *ctx = crypto_tfm_ctx(tfm);
169
170 switch (len) {
171 case AES_KEYSIZE_128:
172 case AES_KEYSIZE_192:
173 case AES_KEYSIZE_256:
174 break;
175 default:
176 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
177 return -EINVAL;
178 }
179 ctx->key_len = len;
180 ctx->need_calc_aes_dkey = 1;
181
182 memcpy(ctx->aes_enc_key, key, AES_KEY_LEN);
183 return 0;
184 }
185
186 static void copy_src_to_buf(struct req_progress *p, char *dbuf, int len)
187 {
188 int ret;
189 void *sbuf;
190 int copy_len;
191
192 while (len) {
193 if (!p->sg_src_left) {
194 ret = sg_miter_next(&p->src_sg_it);
195 BUG_ON(!ret);
196 p->sg_src_left = p->src_sg_it.length;
197 p->src_start = 0;
198 }
199
200 sbuf = p->src_sg_it.addr + p->src_start;
201
202 copy_len = min(p->sg_src_left, len);
203 memcpy(dbuf, sbuf, copy_len);
204
205 p->src_start += copy_len;
206 p->sg_src_left -= copy_len;
207
208 len -= copy_len;
209 dbuf += copy_len;
210 }
211 }
212
213 static void setup_data_in(void)
214 {
215 struct req_progress *p = &cpg->p;
216 int data_in_sram =
217 min(p->hw_nbytes - p->hw_processed_bytes, cpg->max_req_size);
218 copy_src_to_buf(p, cpg->sram + SRAM_DATA_IN_START + p->crypt_len,
219 data_in_sram - p->crypt_len);
220 p->crypt_len = data_in_sram;
221 }
222
223 static void mv_process_current_q(int first_block)
224 {
225 struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
226 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
227 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
228 struct sec_accel_config op;
229
230 switch (req_ctx->op) {
231 case COP_AES_ECB:
232 op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_ECB;
233 break;
234 case COP_AES_CBC:
235 default:
236 op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_CBC;
237 op.enc_iv = ENC_IV_POINT(SRAM_DATA_IV) |
238 ENC_IV_BUF_POINT(SRAM_DATA_IV_BUF);
239 if (first_block)
240 memcpy(cpg->sram + SRAM_DATA_IV, req->info, 16);
241 break;
242 }
243 if (req_ctx->decrypt) {
244 op.config |= CFG_DIR_DEC;
245 memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_dec_key,
246 AES_KEY_LEN);
247 } else {
248 op.config |= CFG_DIR_ENC;
249 memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_enc_key,
250 AES_KEY_LEN);
251 }
252
253 switch (ctx->key_len) {
254 case AES_KEYSIZE_128:
255 op.config |= CFG_AES_LEN_128;
256 break;
257 case AES_KEYSIZE_192:
258 op.config |= CFG_AES_LEN_192;
259 break;
260 case AES_KEYSIZE_256:
261 op.config |= CFG_AES_LEN_256;
262 break;
263 }
264 op.enc_p = ENC_P_SRC(SRAM_DATA_IN_START) |
265 ENC_P_DST(SRAM_DATA_OUT_START);
266 op.enc_key_p = SRAM_DATA_KEY_P;
267
268 setup_data_in();
269 op.enc_len = cpg->p.crypt_len;
270 memcpy(cpg->sram + SRAM_CONFIG, &op,
271 sizeof(struct sec_accel_config));
272
273 /* GO */
274 writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
275
276 /*
277 * XXX: add timer if the interrupt does not occur for some mystery
278 * reason
279 */
280 }
281
282 static void mv_crypto_algo_completion(void)
283 {
284 struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
285 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
286
287 sg_miter_stop(&cpg->p.src_sg_it);
288 sg_miter_stop(&cpg->p.dst_sg_it);
289
290 if (req_ctx->op != COP_AES_CBC)
291 return ;
292
293 memcpy(req->info, cpg->sram + SRAM_DATA_IV_BUF, 16);
294 }
295
296 static void mv_process_hash_current(int first_block)
297 {
298 struct ahash_request *req = ahash_request_cast(cpg->cur_req);
299 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
300 struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
301 struct req_progress *p = &cpg->p;
302 struct sec_accel_config op = { 0 };
303 int is_last;
304
305 switch (req_ctx->op) {
306 case COP_SHA1:
307 default:
308 op.config = CFG_OP_MAC_ONLY | CFG_MACM_SHA1;
309 break;
310 case COP_HMAC_SHA1:
311 op.config = CFG_OP_MAC_ONLY | CFG_MACM_HMAC_SHA1;
312 memcpy(cpg->sram + SRAM_HMAC_IV_IN,
313 tfm_ctx->ivs, sizeof(tfm_ctx->ivs));
314 break;
315 }
316
317 op.mac_src_p =
318 MAC_SRC_DATA_P(SRAM_DATA_IN_START) | MAC_SRC_TOTAL_LEN((u32)
319 req_ctx->
320 count);
321
322 setup_data_in();
323
324 op.mac_digest =
325 MAC_DIGEST_P(SRAM_DIGEST_BUF) | MAC_FRAG_LEN(p->crypt_len);
326 op.mac_iv =
327 MAC_INNER_IV_P(SRAM_HMAC_IV_IN) |
328 MAC_OUTER_IV_P(SRAM_HMAC_IV_OUT);
329
330 is_last = req_ctx->last_chunk
331 && (p->hw_processed_bytes + p->crypt_len >= p->hw_nbytes)
332 && (req_ctx->count <= MAX_HW_HASH_SIZE);
333 if (req_ctx->first_hash) {
334 if (is_last)
335 op.config |= CFG_NOT_FRAG;
336 else
337 op.config |= CFG_FIRST_FRAG;
338
339 req_ctx->first_hash = 0;
340 } else {
341 if (is_last)
342 op.config |= CFG_LAST_FRAG;
343 else
344 op.config |= CFG_MID_FRAG;
345 }
346
347 memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config));
348
349 /* GO */
350 writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
351
352 /*
353 * XXX: add timer if the interrupt does not occur for some mystery
354 * reason
355 */
356 }
357
358 static inline int mv_hash_import_sha1_ctx(const struct mv_req_hash_ctx *ctx,
359 struct shash_desc *desc)
360 {
361 int i;
362 struct sha1_state shash_state;
363
364 shash_state.count = ctx->count + ctx->count_add;
365 for (i = 0; i < 5; i++)
366 shash_state.state[i] = ctx->state[i];
367 memcpy(shash_state.buffer, ctx->buffer, sizeof(shash_state.buffer));
368 return crypto_shash_import(desc, &shash_state);
369 }
370
371 static int mv_hash_final_fallback(struct ahash_request *req)
372 {
373 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
374 struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
375 struct {
376 struct shash_desc shash;
377 char ctx[crypto_shash_descsize(tfm_ctx->fallback)];
378 } desc;
379 int rc;
380
381 desc.shash.tfm = tfm_ctx->fallback;
382 desc.shash.flags = CRYPTO_TFM_REQ_MAY_SLEEP;
383 if (unlikely(req_ctx->first_hash)) {
384 crypto_shash_init(&desc.shash);
385 crypto_shash_update(&desc.shash, req_ctx->buffer,
386 req_ctx->extra_bytes);
387 } else {
388 /* only SHA1 for now....
389 */
390 rc = mv_hash_import_sha1_ctx(req_ctx, &desc.shash);
391 if (rc)
392 goto out;
393 }
394 rc = crypto_shash_final(&desc.shash, req->result);
395 out:
396 return rc;
397 }
398
399 static void mv_hash_algo_completion(void)
400 {
401 struct ahash_request *req = ahash_request_cast(cpg->cur_req);
402 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
403
404 if (ctx->extra_bytes)
405 copy_src_to_buf(&cpg->p, ctx->buffer, ctx->extra_bytes);
406 sg_miter_stop(&cpg->p.src_sg_it);
407
408 if (likely(ctx->last_chunk)) {
409 if (likely(ctx->count <= MAX_HW_HASH_SIZE)) {
410 memcpy(req->result, cpg->sram + SRAM_DIGEST_BUF,
411 crypto_ahash_digestsize(crypto_ahash_reqtfm
412 (req)));
413 } else
414 mv_hash_final_fallback(req);
415 } else {
416 ctx->state[0] = readl(cpg->reg + DIGEST_INITIAL_VAL_A);
417 ctx->state[1] = readl(cpg->reg + DIGEST_INITIAL_VAL_B);
418 ctx->state[2] = readl(cpg->reg + DIGEST_INITIAL_VAL_C);
419 ctx->state[3] = readl(cpg->reg + DIGEST_INITIAL_VAL_D);
420 ctx->state[4] = readl(cpg->reg + DIGEST_INITIAL_VAL_E);
421 }
422 }
423
424 static void dequeue_complete_req(void)
425 {
426 struct crypto_async_request *req = cpg->cur_req;
427 void *buf;
428 int ret;
429 cpg->p.hw_processed_bytes += cpg->p.crypt_len;
430 if (cpg->p.copy_back) {
431 int need_copy_len = cpg->p.crypt_len;
432 int sram_offset = 0;
433 do {
434 int dst_copy;
435
436 if (!cpg->p.sg_dst_left) {
437 ret = sg_miter_next(&cpg->p.dst_sg_it);
438 BUG_ON(!ret);
439 cpg->p.sg_dst_left = cpg->p.dst_sg_it.length;
440 cpg->p.dst_start = 0;
441 }
442
443 buf = cpg->p.dst_sg_it.addr;
444 buf += cpg->p.dst_start;
445
446 dst_copy = min(need_copy_len, cpg->p.sg_dst_left);
447
448 memcpy(buf,
449 cpg->sram + SRAM_DATA_OUT_START + sram_offset,
450 dst_copy);
451 sram_offset += dst_copy;
452 cpg->p.sg_dst_left -= dst_copy;
453 need_copy_len -= dst_copy;
454 cpg->p.dst_start += dst_copy;
455 } while (need_copy_len > 0);
456 }
457
458 cpg->p.crypt_len = 0;
459
460 BUG_ON(cpg->eng_st != ENGINE_W_DEQUEUE);
461 if (cpg->p.hw_processed_bytes < cpg->p.hw_nbytes) {
462 /* process next scatter list entry */
463 cpg->eng_st = ENGINE_BUSY;
464 cpg->p.process(0);
465 } else {
466 cpg->p.complete();
467 cpg->eng_st = ENGINE_IDLE;
468 local_bh_disable();
469 req->complete(req, 0);
470 local_bh_enable();
471 }
472 }
473
474 static int count_sgs(struct scatterlist *sl, unsigned int total_bytes)
475 {
476 int i = 0;
477 size_t cur_len;
478
479 while (1) {
480 cur_len = sl[i].length;
481 ++i;
482 if (total_bytes > cur_len)
483 total_bytes -= cur_len;
484 else
485 break;
486 }
487
488 return i;
489 }
490
491 static void mv_start_new_crypt_req(struct ablkcipher_request *req)
492 {
493 struct req_progress *p = &cpg->p;
494 int num_sgs;
495
496 cpg->cur_req = &req->base;
497 memset(p, 0, sizeof(struct req_progress));
498 p->hw_nbytes = req->nbytes;
499 p->complete = mv_crypto_algo_completion;
500 p->process = mv_process_current_q;
501 p->copy_back = 1;
502
503 num_sgs = count_sgs(req->src, req->nbytes);
504 sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
505
506 num_sgs = count_sgs(req->dst, req->nbytes);
507 sg_miter_start(&p->dst_sg_it, req->dst, num_sgs, SG_MITER_TO_SG);
508
509 mv_process_current_q(1);
510 }
511
512 static void mv_start_new_hash_req(struct ahash_request *req)
513 {
514 struct req_progress *p = &cpg->p;
515 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
516 int num_sgs, hw_bytes, old_extra_bytes, rc;
517 cpg->cur_req = &req->base;
518 memset(p, 0, sizeof(struct req_progress));
519 hw_bytes = req->nbytes + ctx->extra_bytes;
520 old_extra_bytes = ctx->extra_bytes;
521
522 if (unlikely(ctx->extra_bytes)) {
523 memcpy(cpg->sram + SRAM_DATA_IN_START, ctx->buffer,
524 ctx->extra_bytes);
525 p->crypt_len = ctx->extra_bytes;
526 }
527
528 if (unlikely(!ctx->first_hash)) {
529 writel(ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A);
530 writel(ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B);
531 writel(ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C);
532 writel(ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D);
533 writel(ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E);
534 }
535
536 ctx->extra_bytes = hw_bytes % SHA1_BLOCK_SIZE;
537 if (ctx->extra_bytes != 0
538 && (!ctx->last_chunk || ctx->count > MAX_HW_HASH_SIZE))
539 hw_bytes -= ctx->extra_bytes;
540 else
541 ctx->extra_bytes = 0;
542
543 num_sgs = count_sgs(req->src, req->nbytes);
544 sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
545
546 if (hw_bytes) {
547 p->hw_nbytes = hw_bytes;
548 p->complete = mv_hash_algo_completion;
549 p->process = mv_process_hash_current;
550
551 mv_process_hash_current(1);
552 } else {
553 copy_src_to_buf(p, ctx->buffer + old_extra_bytes,
554 ctx->extra_bytes - old_extra_bytes);
555 sg_miter_stop(&p->src_sg_it);
556 if (ctx->last_chunk)
557 rc = mv_hash_final_fallback(req);
558 else
559 rc = 0;
560 cpg->eng_st = ENGINE_IDLE;
561 local_bh_disable();
562 req->base.complete(&req->base, rc);
563 local_bh_enable();
564 }
565 }
566
567 static int queue_manag(void *data)
568 {
569 cpg->eng_st = ENGINE_IDLE;
570 do {
571 struct crypto_async_request *async_req = NULL;
572 struct crypto_async_request *backlog;
573
574 __set_current_state(TASK_INTERRUPTIBLE);
575
576 if (cpg->eng_st == ENGINE_W_DEQUEUE)
577 dequeue_complete_req();
578
579 spin_lock_irq(&cpg->lock);
580 if (cpg->eng_st == ENGINE_IDLE) {
581 backlog = crypto_get_backlog(&cpg->queue);
582 async_req = crypto_dequeue_request(&cpg->queue);
583 if (async_req) {
584 BUG_ON(cpg->eng_st != ENGINE_IDLE);
585 cpg->eng_st = ENGINE_BUSY;
586 }
587 }
588 spin_unlock_irq(&cpg->lock);
589
590 if (backlog) {
591 backlog->complete(backlog, -EINPROGRESS);
592 backlog = NULL;
593 }
594
595 if (async_req) {
596 if (async_req->tfm->__crt_alg->cra_type !=
597 &crypto_ahash_type) {
598 struct ablkcipher_request *req =
599 ablkcipher_request_cast(async_req);
600 mv_start_new_crypt_req(req);
601 } else {
602 struct ahash_request *req =
603 ahash_request_cast(async_req);
604 mv_start_new_hash_req(req);
605 }
606 async_req = NULL;
607 }
608
609 schedule();
610
611 } while (!kthread_should_stop());
612 return 0;
613 }
614
615 static int mv_handle_req(struct crypto_async_request *req)
616 {
617 unsigned long flags;
618 int ret;
619
620 spin_lock_irqsave(&cpg->lock, flags);
621 ret = crypto_enqueue_request(&cpg->queue, req);
622 spin_unlock_irqrestore(&cpg->lock, flags);
623 wake_up_process(cpg->queue_th);
624 return ret;
625 }
626
627 static int mv_enc_aes_ecb(struct ablkcipher_request *req)
628 {
629 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
630
631 req_ctx->op = COP_AES_ECB;
632 req_ctx->decrypt = 0;
633
634 return mv_handle_req(&req->base);
635 }
636
637 static int mv_dec_aes_ecb(struct ablkcipher_request *req)
638 {
639 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
640 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
641
642 req_ctx->op = COP_AES_ECB;
643 req_ctx->decrypt = 1;
644
645 compute_aes_dec_key(ctx);
646 return mv_handle_req(&req->base);
647 }
648
649 static int mv_enc_aes_cbc(struct ablkcipher_request *req)
650 {
651 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
652
653 req_ctx->op = COP_AES_CBC;
654 req_ctx->decrypt = 0;
655
656 return mv_handle_req(&req->base);
657 }
658
659 static int mv_dec_aes_cbc(struct ablkcipher_request *req)
660 {
661 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
662 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
663
664 req_ctx->op = COP_AES_CBC;
665 req_ctx->decrypt = 1;
666
667 compute_aes_dec_key(ctx);
668 return mv_handle_req(&req->base);
669 }
670
671 static int mv_cra_init(struct crypto_tfm *tfm)
672 {
673 tfm->crt_ablkcipher.reqsize = sizeof(struct mv_req_ctx);
674 return 0;
675 }
676
677 static void mv_init_hash_req_ctx(struct mv_req_hash_ctx *ctx, int op,
678 int is_last, unsigned int req_len,
679 int count_add)
680 {
681 memset(ctx, 0, sizeof(*ctx));
682 ctx->op = op;
683 ctx->count = req_len;
684 ctx->first_hash = 1;
685 ctx->last_chunk = is_last;
686 ctx->count_add = count_add;
687 }
688
689 static void mv_update_hash_req_ctx(struct mv_req_hash_ctx *ctx, int is_last,
690 unsigned req_len)
691 {
692 ctx->last_chunk = is_last;
693 ctx->count += req_len;
694 }
695
696 static int mv_hash_init(struct ahash_request *req)
697 {
698 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
699 mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 0, 0,
700 tfm_ctx->count_add);
701 return 0;
702 }
703
704 static int mv_hash_update(struct ahash_request *req)
705 {
706 if (!req->nbytes)
707 return 0;
708
709 mv_update_hash_req_ctx(ahash_request_ctx(req), 0, req->nbytes);
710 return mv_handle_req(&req->base);
711 }
712
713 static int mv_hash_final(struct ahash_request *req)
714 {
715 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
716 /* dummy buffer of 4 bytes */
717 sg_init_one(&ctx->dummysg, ctx->buffer, 4);
718 /* I think I'm allowed to do that... */
719 ahash_request_set_crypt(req, &ctx->dummysg, req->result, 0);
720 mv_update_hash_req_ctx(ctx, 1, 0);
721 return mv_handle_req(&req->base);
722 }
723
724 static int mv_hash_finup(struct ahash_request *req)
725 {
726 mv_update_hash_req_ctx(ahash_request_ctx(req), 1, req->nbytes);
727 return mv_handle_req(&req->base);
728 }
729
730 static int mv_hash_digest(struct ahash_request *req)
731 {
732 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
733 mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 1,
734 req->nbytes, tfm_ctx->count_add);
735 return mv_handle_req(&req->base);
736 }
737
738 static void mv_hash_init_ivs(struct mv_tfm_hash_ctx *ctx, const void *istate,
739 const void *ostate)
740 {
741 const struct sha1_state *isha1_state = istate, *osha1_state = ostate;
742 int i;
743 for (i = 0; i < 5; i++) {
744 ctx->ivs[i] = cpu_to_be32(isha1_state->state[i]);
745 ctx->ivs[i + 5] = cpu_to_be32(osha1_state->state[i]);
746 }
747 }
748
749 static int mv_hash_setkey(struct crypto_ahash *tfm, const u8 * key,
750 unsigned int keylen)
751 {
752 int rc;
753 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(&tfm->base);
754 int bs, ds, ss;
755
756 if (!ctx->base_hash)
757 return 0;
758
759 rc = crypto_shash_setkey(ctx->fallback, key, keylen);
760 if (rc)
761 return rc;
762
763 /* Can't see a way to extract the ipad/opad from the fallback tfm
764 so I'm basically copying code from the hmac module */
765 bs = crypto_shash_blocksize(ctx->base_hash);
766 ds = crypto_shash_digestsize(ctx->base_hash);
767 ss = crypto_shash_statesize(ctx->base_hash);
768
769 {
770 struct {
771 struct shash_desc shash;
772 char ctx[crypto_shash_descsize(ctx->base_hash)];
773 } desc;
774 unsigned int i;
775 char ipad[ss];
776 char opad[ss];
777
778 desc.shash.tfm = ctx->base_hash;
779 desc.shash.flags = crypto_shash_get_flags(ctx->base_hash) &
780 CRYPTO_TFM_REQ_MAY_SLEEP;
781
782 if (keylen > bs) {
783 int err;
784
785 err =
786 crypto_shash_digest(&desc.shash, key, keylen, ipad);
787 if (err)
788 return err;
789
790 keylen = ds;
791 } else
792 memcpy(ipad, key, keylen);
793
794 memset(ipad + keylen, 0, bs - keylen);
795 memcpy(opad, ipad, bs);
796
797 for (i = 0; i < bs; i++) {
798 ipad[i] ^= 0x36;
799 opad[i] ^= 0x5c;
800 }
801
802 rc = crypto_shash_init(&desc.shash) ? :
803 crypto_shash_update(&desc.shash, ipad, bs) ? :
804 crypto_shash_export(&desc.shash, ipad) ? :
805 crypto_shash_init(&desc.shash) ? :
806 crypto_shash_update(&desc.shash, opad, bs) ? :
807 crypto_shash_export(&desc.shash, opad);
808
809 if (rc == 0)
810 mv_hash_init_ivs(ctx, ipad, opad);
811
812 return rc;
813 }
814 }
815
816 static int mv_cra_hash_init(struct crypto_tfm *tfm, const char *base_hash_name,
817 enum hash_op op, int count_add)
818 {
819 const char *fallback_driver_name = tfm->__crt_alg->cra_name;
820 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
821 struct crypto_shash *fallback_tfm = NULL;
822 struct crypto_shash *base_hash = NULL;
823 int err = -ENOMEM;
824
825 ctx->op = op;
826 ctx->count_add = count_add;
827
828 /* Allocate a fallback and abort if it failed. */
829 fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
830 CRYPTO_ALG_NEED_FALLBACK);
831 if (IS_ERR(fallback_tfm)) {
832 printk(KERN_WARNING MV_CESA
833 "Fallback driver '%s' could not be loaded!\n",
834 fallback_driver_name);
835 err = PTR_ERR(fallback_tfm);
836 goto out;
837 }
838 ctx->fallback = fallback_tfm;
839
840 if (base_hash_name) {
841 /* Allocate a hash to compute the ipad/opad of hmac. */
842 base_hash = crypto_alloc_shash(base_hash_name, 0,
843 CRYPTO_ALG_NEED_FALLBACK);
844 if (IS_ERR(base_hash)) {
845 printk(KERN_WARNING MV_CESA
846 "Base driver '%s' could not be loaded!\n",
847 base_hash_name);
848 err = PTR_ERR(base_hash);
849 goto err_bad_base;
850 }
851 }
852 ctx->base_hash = base_hash;
853
854 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
855 sizeof(struct mv_req_hash_ctx) +
856 crypto_shash_descsize(ctx->fallback));
857 return 0;
858 err_bad_base:
859 crypto_free_shash(fallback_tfm);
860 out:
861 return err;
862 }
863
864 static void mv_cra_hash_exit(struct crypto_tfm *tfm)
865 {
866 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
867
868 crypto_free_shash(ctx->fallback);
869 if (ctx->base_hash)
870 crypto_free_shash(ctx->base_hash);
871 }
872
873 static int mv_cra_hash_sha1_init(struct crypto_tfm *tfm)
874 {
875 return mv_cra_hash_init(tfm, NULL, COP_SHA1, 0);
876 }
877
878 static int mv_cra_hash_hmac_sha1_init(struct crypto_tfm *tfm)
879 {
880 return mv_cra_hash_init(tfm, "sha1", COP_HMAC_SHA1, SHA1_BLOCK_SIZE);
881 }
882
883 irqreturn_t crypto_int(int irq, void *priv)
884 {
885 u32 val;
886
887 val = readl(cpg->reg + SEC_ACCEL_INT_STATUS);
888 if (!(val & SEC_INT_ACCEL0_DONE))
889 return IRQ_NONE;
890
891 val &= ~SEC_INT_ACCEL0_DONE;
892 writel(val, cpg->reg + FPGA_INT_STATUS);
893 writel(val, cpg->reg + SEC_ACCEL_INT_STATUS);
894 BUG_ON(cpg->eng_st != ENGINE_BUSY);
895 cpg->eng_st = ENGINE_W_DEQUEUE;
896 wake_up_process(cpg->queue_th);
897 return IRQ_HANDLED;
898 }
899
900 struct crypto_alg mv_aes_alg_ecb = {
901 .cra_name = "ecb(aes)",
902 .cra_driver_name = "mv-ecb-aes",
903 .cra_priority = 300,
904 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
905 .cra_blocksize = 16,
906 .cra_ctxsize = sizeof(struct mv_ctx),
907 .cra_alignmask = 0,
908 .cra_type = &crypto_ablkcipher_type,
909 .cra_module = THIS_MODULE,
910 .cra_init = mv_cra_init,
911 .cra_u = {
912 .ablkcipher = {
913 .min_keysize = AES_MIN_KEY_SIZE,
914 .max_keysize = AES_MAX_KEY_SIZE,
915 .setkey = mv_setkey_aes,
916 .encrypt = mv_enc_aes_ecb,
917 .decrypt = mv_dec_aes_ecb,
918 },
919 },
920 };
921
922 struct crypto_alg mv_aes_alg_cbc = {
923 .cra_name = "cbc(aes)",
924 .cra_driver_name = "mv-cbc-aes",
925 .cra_priority = 300,
926 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
927 .cra_blocksize = AES_BLOCK_SIZE,
928 .cra_ctxsize = sizeof(struct mv_ctx),
929 .cra_alignmask = 0,
930 .cra_type = &crypto_ablkcipher_type,
931 .cra_module = THIS_MODULE,
932 .cra_init = mv_cra_init,
933 .cra_u = {
934 .ablkcipher = {
935 .ivsize = AES_BLOCK_SIZE,
936 .min_keysize = AES_MIN_KEY_SIZE,
937 .max_keysize = AES_MAX_KEY_SIZE,
938 .setkey = mv_setkey_aes,
939 .encrypt = mv_enc_aes_cbc,
940 .decrypt = mv_dec_aes_cbc,
941 },
942 },
943 };
944
945 struct ahash_alg mv_sha1_alg = {
946 .init = mv_hash_init,
947 .update = mv_hash_update,
948 .final = mv_hash_final,
949 .finup = mv_hash_finup,
950 .digest = mv_hash_digest,
951 .halg = {
952 .digestsize = SHA1_DIGEST_SIZE,
953 .base = {
954 .cra_name = "sha1",
955 .cra_driver_name = "mv-sha1",
956 .cra_priority = 300,
957 .cra_flags =
958 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
959 .cra_blocksize = SHA1_BLOCK_SIZE,
960 .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
961 .cra_init = mv_cra_hash_sha1_init,
962 .cra_exit = mv_cra_hash_exit,
963 .cra_module = THIS_MODULE,
964 }
965 }
966 };
967
968 struct ahash_alg mv_hmac_sha1_alg = {
969 .init = mv_hash_init,
970 .update = mv_hash_update,
971 .final = mv_hash_final,
972 .finup = mv_hash_finup,
973 .digest = mv_hash_digest,
974 .setkey = mv_hash_setkey,
975 .halg = {
976 .digestsize = SHA1_DIGEST_SIZE,
977 .base = {
978 .cra_name = "hmac(sha1)",
979 .cra_driver_name = "mv-hmac-sha1",
980 .cra_priority = 300,
981 .cra_flags =
982 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
983 .cra_blocksize = SHA1_BLOCK_SIZE,
984 .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
985 .cra_init = mv_cra_hash_hmac_sha1_init,
986 .cra_exit = mv_cra_hash_exit,
987 .cra_module = THIS_MODULE,
988 }
989 }
990 };
991
992 static int mv_probe(struct platform_device *pdev)
993 {
994 struct crypto_priv *cp;
995 struct resource *res;
996 int irq;
997 int ret;
998
999 if (cpg) {
1000 printk(KERN_ERR MV_CESA "Second crypto dev?\n");
1001 return -EEXIST;
1002 }
1003
1004 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1005 if (!res)
1006 return -ENXIO;
1007
1008 cp = kzalloc(sizeof(*cp), GFP_KERNEL);
1009 if (!cp)
1010 return -ENOMEM;
1011
1012 spin_lock_init(&cp->lock);
1013 crypto_init_queue(&cp->queue, 50);
1014 cp->reg = ioremap(res->start, resource_size(res));
1015 if (!cp->reg) {
1016 ret = -ENOMEM;
1017 goto err;
1018 }
1019
1020 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
1021 if (!res) {
1022 ret = -ENXIO;
1023 goto err_unmap_reg;
1024 }
1025 cp->sram_size = resource_size(res);
1026 cp->max_req_size = cp->sram_size - SRAM_CFG_SPACE;
1027 cp->sram = ioremap(res->start, cp->sram_size);
1028 if (!cp->sram) {
1029 ret = -ENOMEM;
1030 goto err_unmap_reg;
1031 }
1032
1033 irq = platform_get_irq(pdev, 0);
1034 if (irq < 0 || irq == NO_IRQ) {
1035 ret = irq;
1036 goto err_unmap_sram;
1037 }
1038 cp->irq = irq;
1039
1040 platform_set_drvdata(pdev, cp);
1041 cpg = cp;
1042
1043 cp->queue_th = kthread_run(queue_manag, cp, "mv_crypto");
1044 if (IS_ERR(cp->queue_th)) {
1045 ret = PTR_ERR(cp->queue_th);
1046 goto err_unmap_sram;
1047 }
1048
1049 ret = request_irq(irq, crypto_int, IRQF_DISABLED, dev_name(&pdev->dev),
1050 cp);
1051 if (ret)
1052 goto err_thread;
1053
1054 writel(SEC_INT_ACCEL0_DONE, cpg->reg + SEC_ACCEL_INT_MASK);
1055 writel(SEC_CFG_STOP_DIG_ERR, cpg->reg + SEC_ACCEL_CFG);
1056 writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
1057
1058 ret = crypto_register_alg(&mv_aes_alg_ecb);
1059 if (ret) {
1060 printk(KERN_WARNING MV_CESA
1061 "Could not register aes-ecb driver\n");
1062 goto err_irq;
1063 }
1064
1065 ret = crypto_register_alg(&mv_aes_alg_cbc);
1066 if (ret) {
1067 printk(KERN_WARNING MV_CESA
1068 "Could not register aes-cbc driver\n");
1069 goto err_unreg_ecb;
1070 }
1071
1072 ret = crypto_register_ahash(&mv_sha1_alg);
1073 if (ret == 0)
1074 cpg->has_sha1 = 1;
1075 else
1076 printk(KERN_WARNING MV_CESA "Could not register sha1 driver\n");
1077
1078 ret = crypto_register_ahash(&mv_hmac_sha1_alg);
1079 if (ret == 0) {
1080 cpg->has_hmac_sha1 = 1;
1081 } else {
1082 printk(KERN_WARNING MV_CESA
1083 "Could not register hmac-sha1 driver\n");
1084 }
1085
1086 return 0;
1087 err_unreg_ecb:
1088 crypto_unregister_alg(&mv_aes_alg_ecb);
1089 err_irq:
1090 free_irq(irq, cp);
1091 err_thread:
1092 kthread_stop(cp->queue_th);
1093 err_unmap_sram:
1094 iounmap(cp->sram);
1095 err_unmap_reg:
1096 iounmap(cp->reg);
1097 err:
1098 kfree(cp);
1099 cpg = NULL;
1100 platform_set_drvdata(pdev, NULL);
1101 return ret;
1102 }
1103
1104 static int mv_remove(struct platform_device *pdev)
1105 {
1106 struct crypto_priv *cp = platform_get_drvdata(pdev);
1107
1108 crypto_unregister_alg(&mv_aes_alg_ecb);
1109 crypto_unregister_alg(&mv_aes_alg_cbc);
1110 if (cp->has_sha1)
1111 crypto_unregister_ahash(&mv_sha1_alg);
1112 if (cp->has_hmac_sha1)
1113 crypto_unregister_ahash(&mv_hmac_sha1_alg);
1114 kthread_stop(cp->queue_th);
1115 free_irq(cp->irq, cp);
1116 memset(cp->sram, 0, cp->sram_size);
1117 iounmap(cp->sram);
1118 iounmap(cp->reg);
1119 kfree(cp);
1120 cpg = NULL;
1121 return 0;
1122 }
1123
1124 static struct platform_driver marvell_crypto = {
1125 .probe = mv_probe,
1126 .remove = mv_remove,
1127 .driver = {
1128 .owner = THIS_MODULE,
1129 .name = "mv_crypto",
1130 },
1131 };
1132 MODULE_ALIAS("platform:mv_crypto");
1133
1134 static int __init mv_crypto_init(void)
1135 {
1136 return platform_driver_register(&marvell_crypto);
1137 }
1138 module_init(mv_crypto_init);
1139
1140 static void __exit mv_crypto_exit(void)
1141 {
1142 platform_driver_unregister(&marvell_crypto);
1143 }
1144 module_exit(mv_crypto_exit);
1145
1146 MODULE_AUTHOR("Sebastian Andrzej Siewior <sebastian@breakpoint.cc>");
1147 MODULE_DESCRIPTION("Support for Marvell's cryptographic engine");
1148 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree