Revert "PCI: PCIE ASPM support"
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / pci / pci.c
blob04aac77824681a10582f1382a1c06771d2c3179e
1 /*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pm.h>
17 #include <linux/module.h>
18 #include <linux/spinlock.h>
19 #include <linux/string.h>
20 #include <linux/log2.h>
21 #include <asm/dma.h> /* isa_dma_bridge_buggy */
22 #include "pci.h"
24 unsigned int pci_pm_d3_delay = 10;
26 #ifdef CONFIG_PCI_DOMAINS
27 int pci_domains_supported = 1;
28 #endif
30 #define DEFAULT_CARDBUS_IO_SIZE (256)
31 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
32 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
33 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
34 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
36 /**
37 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
38 * @bus: pointer to PCI bus structure to search
40 * Given a PCI bus, returns the highest PCI bus number present in the set
41 * including the given PCI bus and its list of child PCI buses.
43 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
45 struct list_head *tmp;
46 unsigned char max, n;
48 max = bus->subordinate;
49 list_for_each(tmp, &bus->children) {
50 n = pci_bus_max_busnr(pci_bus_b(tmp));
51 if(n > max)
52 max = n;
54 return max;
56 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
58 #if 0
59 /**
60 * pci_max_busnr - returns maximum PCI bus number
62 * Returns the highest PCI bus number present in the system global list of
63 * PCI buses.
65 unsigned char __devinit
66 pci_max_busnr(void)
68 struct pci_bus *bus = NULL;
69 unsigned char max, n;
71 max = 0;
72 while ((bus = pci_find_next_bus(bus)) != NULL) {
73 n = pci_bus_max_busnr(bus);
74 if(n > max)
75 max = n;
77 return max;
80 #endif /* 0 */
82 #define PCI_FIND_CAP_TTL 48
84 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
85 u8 pos, int cap, int *ttl)
87 u8 id;
89 while ((*ttl)--) {
90 pci_bus_read_config_byte(bus, devfn, pos, &pos);
91 if (pos < 0x40)
92 break;
93 pos &= ~3;
94 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
95 &id);
96 if (id == 0xff)
97 break;
98 if (id == cap)
99 return pos;
100 pos += PCI_CAP_LIST_NEXT;
102 return 0;
105 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
106 u8 pos, int cap)
108 int ttl = PCI_FIND_CAP_TTL;
110 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
113 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
115 return __pci_find_next_cap(dev->bus, dev->devfn,
116 pos + PCI_CAP_LIST_NEXT, cap);
118 EXPORT_SYMBOL_GPL(pci_find_next_capability);
120 static int __pci_bus_find_cap_start(struct pci_bus *bus,
121 unsigned int devfn, u8 hdr_type)
123 u16 status;
125 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
126 if (!(status & PCI_STATUS_CAP_LIST))
127 return 0;
129 switch (hdr_type) {
130 case PCI_HEADER_TYPE_NORMAL:
131 case PCI_HEADER_TYPE_BRIDGE:
132 return PCI_CAPABILITY_LIST;
133 case PCI_HEADER_TYPE_CARDBUS:
134 return PCI_CB_CAPABILITY_LIST;
135 default:
136 return 0;
139 return 0;
143 * pci_find_capability - query for devices' capabilities
144 * @dev: PCI device to query
145 * @cap: capability code
147 * Tell if a device supports a given PCI capability.
148 * Returns the address of the requested capability structure within the
149 * device's PCI configuration space or 0 in case the device does not
150 * support it. Possible values for @cap:
152 * %PCI_CAP_ID_PM Power Management
153 * %PCI_CAP_ID_AGP Accelerated Graphics Port
154 * %PCI_CAP_ID_VPD Vital Product Data
155 * %PCI_CAP_ID_SLOTID Slot Identification
156 * %PCI_CAP_ID_MSI Message Signalled Interrupts
157 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
158 * %PCI_CAP_ID_PCIX PCI-X
159 * %PCI_CAP_ID_EXP PCI Express
161 int pci_find_capability(struct pci_dev *dev, int cap)
163 int pos;
165 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
166 if (pos)
167 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
169 return pos;
173 * pci_bus_find_capability - query for devices' capabilities
174 * @bus: the PCI bus to query
175 * @devfn: PCI device to query
176 * @cap: capability code
178 * Like pci_find_capability() but works for pci devices that do not have a
179 * pci_dev structure set up yet.
181 * Returns the address of the requested capability structure within the
182 * device's PCI configuration space or 0 in case the device does not
183 * support it.
185 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
187 int pos;
188 u8 hdr_type;
190 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
192 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
193 if (pos)
194 pos = __pci_find_next_cap(bus, devfn, pos, cap);
196 return pos;
200 * pci_find_ext_capability - Find an extended capability
201 * @dev: PCI device to query
202 * @cap: capability code
204 * Returns the address of the requested extended capability structure
205 * within the device's PCI configuration space or 0 if the device does
206 * not support it. Possible values for @cap:
208 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
209 * %PCI_EXT_CAP_ID_VC Virtual Channel
210 * %PCI_EXT_CAP_ID_DSN Device Serial Number
211 * %PCI_EXT_CAP_ID_PWR Power Budgeting
213 int pci_find_ext_capability(struct pci_dev *dev, int cap)
215 u32 header;
216 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
217 int pos = 0x100;
219 if (dev->cfg_size <= 256)
220 return 0;
222 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
223 return 0;
226 * If we have no capabilities, this is indicated by cap ID,
227 * cap version and next pointer all being 0.
229 if (header == 0)
230 return 0;
232 while (ttl-- > 0) {
233 if (PCI_EXT_CAP_ID(header) == cap)
234 return pos;
236 pos = PCI_EXT_CAP_NEXT(header);
237 if (pos < 0x100)
238 break;
240 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
241 break;
244 return 0;
246 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
248 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
250 int rc, ttl = PCI_FIND_CAP_TTL;
251 u8 cap, mask;
253 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
254 mask = HT_3BIT_CAP_MASK;
255 else
256 mask = HT_5BIT_CAP_MASK;
258 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
259 PCI_CAP_ID_HT, &ttl);
260 while (pos) {
261 rc = pci_read_config_byte(dev, pos + 3, &cap);
262 if (rc != PCIBIOS_SUCCESSFUL)
263 return 0;
265 if ((cap & mask) == ht_cap)
266 return pos;
268 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
269 pos + PCI_CAP_LIST_NEXT,
270 PCI_CAP_ID_HT, &ttl);
273 return 0;
276 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
277 * @dev: PCI device to query
278 * @pos: Position from which to continue searching
279 * @ht_cap: Hypertransport capability code
281 * To be used in conjunction with pci_find_ht_capability() to search for
282 * all capabilities matching @ht_cap. @pos should always be a value returned
283 * from pci_find_ht_capability().
285 * NB. To be 100% safe against broken PCI devices, the caller should take
286 * steps to avoid an infinite loop.
288 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
290 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
292 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
295 * pci_find_ht_capability - query a device's Hypertransport capabilities
296 * @dev: PCI device to query
297 * @ht_cap: Hypertransport capability code
299 * Tell if a device supports a given Hypertransport capability.
300 * Returns an address within the device's PCI configuration space
301 * or 0 in case the device does not support the request capability.
302 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
303 * which has a Hypertransport capability matching @ht_cap.
305 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
307 int pos;
309 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
310 if (pos)
311 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
313 return pos;
315 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
317 void pcie_wait_pending_transaction(struct pci_dev *dev)
319 int pos;
320 u16 reg16;
322 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
323 if (!pos)
324 return;
325 while (1) {
326 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &reg16);
327 if (!(reg16 & PCI_EXP_DEVSTA_TRPND))
328 break;
329 cpu_relax();
333 EXPORT_SYMBOL_GPL(pcie_wait_pending_transaction);
336 * pci_find_parent_resource - return resource region of parent bus of given region
337 * @dev: PCI device structure contains resources to be searched
338 * @res: child resource record for which parent is sought
340 * For given resource region of given device, return the resource
341 * region of parent bus the given region is contained in or where
342 * it should be allocated from.
344 struct resource *
345 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
347 const struct pci_bus *bus = dev->bus;
348 int i;
349 struct resource *best = NULL;
351 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
352 struct resource *r = bus->resource[i];
353 if (!r)
354 continue;
355 if (res->start && !(res->start >= r->start && res->end <= r->end))
356 continue; /* Not contained */
357 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
358 continue; /* Wrong type */
359 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
360 return r; /* Exact match */
361 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
362 best = r; /* Approximating prefetchable by non-prefetchable */
364 return best;
368 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
369 * @dev: PCI device to have its BARs restored
371 * Restore the BAR values for a given device, so as to make it
372 * accessible by its driver.
374 static void
375 pci_restore_bars(struct pci_dev *dev)
377 int i, numres;
379 switch (dev->hdr_type) {
380 case PCI_HEADER_TYPE_NORMAL:
381 numres = 6;
382 break;
383 case PCI_HEADER_TYPE_BRIDGE:
384 numres = 2;
385 break;
386 case PCI_HEADER_TYPE_CARDBUS:
387 numres = 1;
388 break;
389 default:
390 /* Should never get here, but just in case... */
391 return;
394 for (i = 0; i < numres; i ++)
395 pci_update_resource(dev, &dev->resource[i], i);
398 int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
401 * pci_set_power_state - Set the power state of a PCI device
402 * @dev: PCI device to be suspended
403 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
405 * Transition a device to a new power state, using the Power Management
406 * Capabilities in the device's config space.
408 * RETURN VALUE:
409 * -EINVAL if trying to enter a lower state than we're already in.
410 * 0 if we're already in the requested state.
411 * -EIO if device does not support PCI PM.
412 * 0 if we can successfully change the power state.
415 pci_set_power_state(struct pci_dev *dev, pci_power_t state)
417 int pm, need_restore = 0;
418 u16 pmcsr, pmc;
420 /* bound the state we're entering */
421 if (state > PCI_D3hot)
422 state = PCI_D3hot;
425 * If the device or the parent bridge can't support PCI PM, ignore
426 * the request if we're doing anything besides putting it into D0
427 * (which would only happen on boot).
429 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
430 return 0;
432 /* find PCI PM capability in list */
433 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
435 /* abort if the device doesn't support PM capabilities */
436 if (!pm)
437 return -EIO;
439 /* Validate current state:
440 * Can enter D0 from any state, but if we can only go deeper
441 * to sleep if we're already in a low power state
443 if (state != PCI_D0 && dev->current_state > state) {
444 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
445 __FUNCTION__, pci_name(dev), state, dev->current_state);
446 return -EINVAL;
447 } else if (dev->current_state == state)
448 return 0; /* we're already there */
451 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
452 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
453 printk(KERN_DEBUG
454 "PCI: %s has unsupported PM cap regs version (%u)\n",
455 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
456 return -EIO;
459 /* check if this device supports the desired state */
460 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
461 return -EIO;
462 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
463 return -EIO;
465 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
467 /* If we're (effectively) in D3, force entire word to 0.
468 * This doesn't affect PME_Status, disables PME_En, and
469 * sets PowerState to 0.
471 switch (dev->current_state) {
472 case PCI_D0:
473 case PCI_D1:
474 case PCI_D2:
475 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
476 pmcsr |= state;
477 break;
478 case PCI_UNKNOWN: /* Boot-up */
479 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
480 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
481 need_restore = 1;
482 /* Fall-through: force to D0 */
483 default:
484 pmcsr = 0;
485 break;
488 /* enter specified state */
489 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
491 /* Mandatory power management transition delays */
492 /* see PCI PM 1.1 5.6.1 table 18 */
493 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
494 msleep(pci_pm_d3_delay);
495 else if (state == PCI_D2 || dev->current_state == PCI_D2)
496 udelay(200);
499 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
500 * Firmware method after native method ?
502 if (platform_pci_set_power_state)
503 platform_pci_set_power_state(dev, state);
505 dev->current_state = state;
507 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
508 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
509 * from D3hot to D0 _may_ perform an internal reset, thereby
510 * going to "D0 Uninitialized" rather than "D0 Initialized".
511 * For example, at least some versions of the 3c905B and the
512 * 3c556B exhibit this behaviour.
514 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
515 * devices in a D3hot state at boot. Consequently, we need to
516 * restore at least the BARs so that the device will be
517 * accessible to its driver.
519 if (need_restore)
520 pci_restore_bars(dev);
522 return 0;
525 pci_power_t (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
528 * pci_choose_state - Choose the power state of a PCI device
529 * @dev: PCI device to be suspended
530 * @state: target sleep state for the whole system. This is the value
531 * that is passed to suspend() function.
533 * Returns PCI power state suitable for given device and given system
534 * message.
537 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
539 pci_power_t ret;
541 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
542 return PCI_D0;
544 if (platform_pci_choose_state) {
545 ret = platform_pci_choose_state(dev, state);
546 if (ret != PCI_POWER_ERROR)
547 return ret;
550 switch (state.event) {
551 case PM_EVENT_ON:
552 return PCI_D0;
553 case PM_EVENT_FREEZE:
554 case PM_EVENT_PRETHAW:
555 /* REVISIT both freeze and pre-thaw "should" use D0 */
556 case PM_EVENT_SUSPEND:
557 return PCI_D3hot;
558 default:
559 printk("Unrecognized suspend event %d\n", state.event);
560 BUG();
562 return PCI_D0;
565 EXPORT_SYMBOL(pci_choose_state);
567 static int pci_save_pcie_state(struct pci_dev *dev)
569 int pos, i = 0;
570 struct pci_cap_saved_state *save_state;
571 u16 *cap;
572 int found = 0;
574 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
575 if (pos <= 0)
576 return 0;
578 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
579 if (!save_state)
580 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
581 else
582 found = 1;
583 if (!save_state) {
584 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
585 return -ENOMEM;
587 cap = (u16 *)&save_state->data[0];
589 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
590 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
591 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
592 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
593 save_state->cap_nr = PCI_CAP_ID_EXP;
594 if (!found)
595 pci_add_saved_cap(dev, save_state);
596 return 0;
599 static void pci_restore_pcie_state(struct pci_dev *dev)
601 int i = 0, pos;
602 struct pci_cap_saved_state *save_state;
603 u16 *cap;
605 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
606 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
607 if (!save_state || pos <= 0)
608 return;
609 cap = (u16 *)&save_state->data[0];
611 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
612 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
613 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
614 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
618 static int pci_save_pcix_state(struct pci_dev *dev)
620 int pos, i = 0;
621 struct pci_cap_saved_state *save_state;
622 u16 *cap;
623 int found = 0;
625 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
626 if (pos <= 0)
627 return 0;
629 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
630 if (!save_state)
631 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
632 else
633 found = 1;
634 if (!save_state) {
635 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
636 return -ENOMEM;
638 cap = (u16 *)&save_state->data[0];
640 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
641 save_state->cap_nr = PCI_CAP_ID_PCIX;
642 if (!found)
643 pci_add_saved_cap(dev, save_state);
644 return 0;
647 static void pci_restore_pcix_state(struct pci_dev *dev)
649 int i = 0, pos;
650 struct pci_cap_saved_state *save_state;
651 u16 *cap;
653 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
654 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
655 if (!save_state || pos <= 0)
656 return;
657 cap = (u16 *)&save_state->data[0];
659 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
664 * pci_save_state - save the PCI configuration space of a device before suspending
665 * @dev: - PCI device that we're dealing with
668 pci_save_state(struct pci_dev *dev)
670 int i;
671 /* XXX: 100% dword access ok here? */
672 for (i = 0; i < 16; i++)
673 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
674 if ((i = pci_save_pcie_state(dev)) != 0)
675 return i;
676 if ((i = pci_save_pcix_state(dev)) != 0)
677 return i;
678 return 0;
681 /**
682 * pci_restore_state - Restore the saved state of a PCI device
683 * @dev: - PCI device that we're dealing with
685 int
686 pci_restore_state(struct pci_dev *dev)
688 int i;
689 u32 val;
691 /* PCI Express register must be restored first */
692 pci_restore_pcie_state(dev);
695 * The Base Address register should be programmed before the command
696 * register(s)
698 for (i = 15; i >= 0; i--) {
699 pci_read_config_dword(dev, i * 4, &val);
700 if (val != dev->saved_config_space[i]) {
701 printk(KERN_DEBUG "PM: Writing back config space on "
702 "device %s at offset %x (was %x, writing %x)\n",
703 pci_name(dev), i,
704 val, (int)dev->saved_config_space[i]);
705 pci_write_config_dword(dev,i * 4,
706 dev->saved_config_space[i]);
709 pci_restore_pcix_state(dev);
710 pci_restore_msi_state(dev);
712 return 0;
715 static int do_pci_enable_device(struct pci_dev *dev, int bars)
717 int err;
719 err = pci_set_power_state(dev, PCI_D0);
720 if (err < 0 && err != -EIO)
721 return err;
722 err = pcibios_enable_device(dev, bars);
723 if (err < 0)
724 return err;
725 pci_fixup_device(pci_fixup_enable, dev);
727 return 0;
731 * pci_reenable_device - Resume abandoned device
732 * @dev: PCI device to be resumed
734 * Note this function is a backend of pci_default_resume and is not supposed
735 * to be called by normal code, write proper resume handler and use it instead.
737 int pci_reenable_device(struct pci_dev *dev)
739 if (atomic_read(&dev->enable_cnt))
740 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
741 return 0;
744 static int __pci_enable_device_flags(struct pci_dev *dev,
745 resource_size_t flags)
747 int err;
748 int i, bars = 0;
750 if (atomic_add_return(1, &dev->enable_cnt) > 1)
751 return 0; /* already enabled */
753 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
754 if (dev->resource[i].flags & flags)
755 bars |= (1 << i);
757 err = do_pci_enable_device(dev, bars);
758 if (err < 0)
759 atomic_dec(&dev->enable_cnt);
760 return err;
764 * pci_enable_device_io - Initialize a device for use with IO space
765 * @dev: PCI device to be initialized
767 * Initialize device before it's used by a driver. Ask low-level code
768 * to enable I/O resources. Wake up the device if it was suspended.
769 * Beware, this function can fail.
771 int pci_enable_device_io(struct pci_dev *dev)
773 return __pci_enable_device_flags(dev, IORESOURCE_IO);
777 * pci_enable_device_mem - Initialize a device for use with Memory space
778 * @dev: PCI device to be initialized
780 * Initialize device before it's used by a driver. Ask low-level code
781 * to enable Memory resources. Wake up the device if it was suspended.
782 * Beware, this function can fail.
784 int pci_enable_device_mem(struct pci_dev *dev)
786 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
790 * pci_enable_device - Initialize device before it's used by a driver.
791 * @dev: PCI device to be initialized
793 * Initialize device before it's used by a driver. Ask low-level code
794 * to enable I/O and memory. Wake up the device if it was suspended.
795 * Beware, this function can fail.
797 * Note we don't actually enable the device many times if we call
798 * this function repeatedly (we just increment the count).
800 int pci_enable_device(struct pci_dev *dev)
802 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
806 * Managed PCI resources. This manages device on/off, intx/msi/msix
807 * on/off and BAR regions. pci_dev itself records msi/msix status, so
808 * there's no need to track it separately. pci_devres is initialized
809 * when a device is enabled using managed PCI device enable interface.
811 struct pci_devres {
812 unsigned int enabled:1;
813 unsigned int pinned:1;
814 unsigned int orig_intx:1;
815 unsigned int restore_intx:1;
816 u32 region_mask;
819 static void pcim_release(struct device *gendev, void *res)
821 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
822 struct pci_devres *this = res;
823 int i;
825 if (dev->msi_enabled)
826 pci_disable_msi(dev);
827 if (dev->msix_enabled)
828 pci_disable_msix(dev);
830 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
831 if (this->region_mask & (1 << i))
832 pci_release_region(dev, i);
834 if (this->restore_intx)
835 pci_intx(dev, this->orig_intx);
837 if (this->enabled && !this->pinned)
838 pci_disable_device(dev);
841 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
843 struct pci_devres *dr, *new_dr;
845 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
846 if (dr)
847 return dr;
849 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
850 if (!new_dr)
851 return NULL;
852 return devres_get(&pdev->dev, new_dr, NULL, NULL);
855 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
857 if (pci_is_managed(pdev))
858 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
859 return NULL;
863 * pcim_enable_device - Managed pci_enable_device()
864 * @pdev: PCI device to be initialized
866 * Managed pci_enable_device().
868 int pcim_enable_device(struct pci_dev *pdev)
870 struct pci_devres *dr;
871 int rc;
873 dr = get_pci_dr(pdev);
874 if (unlikely(!dr))
875 return -ENOMEM;
876 if (dr->enabled)
877 return 0;
879 rc = pci_enable_device(pdev);
880 if (!rc) {
881 pdev->is_managed = 1;
882 dr->enabled = 1;
884 return rc;
888 * pcim_pin_device - Pin managed PCI device
889 * @pdev: PCI device to pin
891 * Pin managed PCI device @pdev. Pinned device won't be disabled on
892 * driver detach. @pdev must have been enabled with
893 * pcim_enable_device().
895 void pcim_pin_device(struct pci_dev *pdev)
897 struct pci_devres *dr;
899 dr = find_pci_dr(pdev);
900 WARN_ON(!dr || !dr->enabled);
901 if (dr)
902 dr->pinned = 1;
906 * pcibios_disable_device - disable arch specific PCI resources for device dev
907 * @dev: the PCI device to disable
909 * Disables architecture specific PCI resources for the device. This
910 * is the default implementation. Architecture implementations can
911 * override this.
913 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
916 * pci_disable_device - Disable PCI device after use
917 * @dev: PCI device to be disabled
919 * Signal to the system that the PCI device is not in use by the system
920 * anymore. This only involves disabling PCI bus-mastering, if active.
922 * Note we don't actually disable the device until all callers of
923 * pci_device_enable() have called pci_device_disable().
925 void
926 pci_disable_device(struct pci_dev *dev)
928 struct pci_devres *dr;
929 u16 pci_command;
931 dr = find_pci_dr(dev);
932 if (dr)
933 dr->enabled = 0;
935 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
936 return;
938 /* Wait for all transactions are finished before disabling the device */
939 pcie_wait_pending_transaction(dev);
941 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
942 if (pci_command & PCI_COMMAND_MASTER) {
943 pci_command &= ~PCI_COMMAND_MASTER;
944 pci_write_config_word(dev, PCI_COMMAND, pci_command);
946 dev->is_busmaster = 0;
948 pcibios_disable_device(dev);
952 * pcibios_set_pcie_reset_state - set reset state for device dev
953 * @dev: the PCI-E device reset
954 * @state: Reset state to enter into
957 * Sets the PCI-E reset state for the device. This is the default
958 * implementation. Architecture implementations can override this.
960 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
961 enum pcie_reset_state state)
963 return -EINVAL;
967 * pci_set_pcie_reset_state - set reset state for device dev
968 * @dev: the PCI-E device reset
969 * @state: Reset state to enter into
972 * Sets the PCI reset state for the device.
974 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
976 return pcibios_set_pcie_reset_state(dev, state);
980 * pci_enable_wake - enable PCI device as wakeup event source
981 * @dev: PCI device affected
982 * @state: PCI state from which device will issue wakeup events
983 * @enable: True to enable event generation; false to disable
985 * This enables the device as a wakeup event source, or disables it.
986 * When such events involves platform-specific hooks, those hooks are
987 * called automatically by this routine.
989 * Devices with legacy power management (no standard PCI PM capabilities)
990 * always require such platform hooks. Depending on the platform, devices
991 * supporting the standard PCI PME# signal may require such platform hooks;
992 * they always update bits in config space to allow PME# generation.
994 * -EIO is returned if the device can't ever be a wakeup event source.
995 * -EINVAL is returned if the device can't generate wakeup events from
996 * the specified PCI state. Returns zero if the operation is successful.
998 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
1000 int pm;
1001 int status;
1002 u16 value;
1004 /* Note that drivers should verify device_may_wakeup(&dev->dev)
1005 * before calling this function. Platform code should report
1006 * errors when drivers try to enable wakeup on devices that
1007 * can't issue wakeups, or on which wakeups were disabled by
1008 * userspace updating the /sys/devices.../power/wakeup file.
1011 status = call_platform_enable_wakeup(&dev->dev, enable);
1013 /* find PCI PM capability in list */
1014 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1016 /* If device doesn't support PM Capabilities, but caller wants to
1017 * disable wake events, it's a NOP. Otherwise fail unless the
1018 * platform hooks handled this legacy device already.
1020 if (!pm)
1021 return enable ? status : 0;
1023 /* Check device's ability to generate PME# */
1024 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
1026 value &= PCI_PM_CAP_PME_MASK;
1027 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
1029 /* Check if it can generate PME# from requested state. */
1030 if (!value || !(value & (1 << state))) {
1031 /* if it can't, revert what the platform hook changed,
1032 * always reporting the base "EINVAL, can't PME#" error
1034 if (enable)
1035 call_platform_enable_wakeup(&dev->dev, 0);
1036 return enable ? -EINVAL : 0;
1039 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
1041 /* Clear PME_Status by writing 1 to it and enable PME# */
1042 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1044 if (!enable)
1045 value &= ~PCI_PM_CTRL_PME_ENABLE;
1047 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
1049 return 0;
1053 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1055 u8 pin;
1057 pin = dev->pin;
1058 if (!pin)
1059 return -1;
1060 pin--;
1061 while (dev->bus->self) {
1062 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1063 dev = dev->bus->self;
1065 *bridge = dev;
1066 return pin;
1070 * pci_release_region - Release a PCI bar
1071 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1072 * @bar: BAR to release
1074 * Releases the PCI I/O and memory resources previously reserved by a
1075 * successful call to pci_request_region. Call this function only
1076 * after all use of the PCI regions has ceased.
1078 void pci_release_region(struct pci_dev *pdev, int bar)
1080 struct pci_devres *dr;
1082 if (pci_resource_len(pdev, bar) == 0)
1083 return;
1084 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1085 release_region(pci_resource_start(pdev, bar),
1086 pci_resource_len(pdev, bar));
1087 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1088 release_mem_region(pci_resource_start(pdev, bar),
1089 pci_resource_len(pdev, bar));
1091 dr = find_pci_dr(pdev);
1092 if (dr)
1093 dr->region_mask &= ~(1 << bar);
1097 * pci_request_region - Reserved PCI I/O and memory resource
1098 * @pdev: PCI device whose resources are to be reserved
1099 * @bar: BAR to be reserved
1100 * @res_name: Name to be associated with resource.
1102 * Mark the PCI region associated with PCI device @pdev BR @bar as
1103 * being reserved by owner @res_name. Do not access any
1104 * address inside the PCI regions unless this call returns
1105 * successfully.
1107 * Returns 0 on success, or %EBUSY on error. A warning
1108 * message is also printed on failure.
1110 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1112 struct pci_devres *dr;
1114 if (pci_resource_len(pdev, bar) == 0)
1115 return 0;
1117 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1118 if (!request_region(pci_resource_start(pdev, bar),
1119 pci_resource_len(pdev, bar), res_name))
1120 goto err_out;
1122 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1123 if (!request_mem_region(pci_resource_start(pdev, bar),
1124 pci_resource_len(pdev, bar), res_name))
1125 goto err_out;
1128 dr = find_pci_dr(pdev);
1129 if (dr)
1130 dr->region_mask |= 1 << bar;
1132 return 0;
1134 err_out:
1135 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
1136 "for device %s\n",
1137 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1138 bar + 1, /* PCI BAR # */
1139 (unsigned long long)pci_resource_len(pdev, bar),
1140 (unsigned long long)pci_resource_start(pdev, bar),
1141 pci_name(pdev));
1142 return -EBUSY;
1146 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1147 * @pdev: PCI device whose resources were previously reserved
1148 * @bars: Bitmask of BARs to be released
1150 * Release selected PCI I/O and memory resources previously reserved.
1151 * Call this function only after all use of the PCI regions has ceased.
1153 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1155 int i;
1157 for (i = 0; i < 6; i++)
1158 if (bars & (1 << i))
1159 pci_release_region(pdev, i);
1163 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1164 * @pdev: PCI device whose resources are to be reserved
1165 * @bars: Bitmask of BARs to be requested
1166 * @res_name: Name to be associated with resource
1168 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1169 const char *res_name)
1171 int i;
1173 for (i = 0; i < 6; i++)
1174 if (bars & (1 << i))
1175 if(pci_request_region(pdev, i, res_name))
1176 goto err_out;
1177 return 0;
1179 err_out:
1180 while(--i >= 0)
1181 if (bars & (1 << i))
1182 pci_release_region(pdev, i);
1184 return -EBUSY;
1188 * pci_release_regions - Release reserved PCI I/O and memory resources
1189 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1191 * Releases all PCI I/O and memory resources previously reserved by a
1192 * successful call to pci_request_regions. Call this function only
1193 * after all use of the PCI regions has ceased.
1196 void pci_release_regions(struct pci_dev *pdev)
1198 pci_release_selected_regions(pdev, (1 << 6) - 1);
1202 * pci_request_regions - Reserved PCI I/O and memory resources
1203 * @pdev: PCI device whose resources are to be reserved
1204 * @res_name: Name to be associated with resource.
1206 * Mark all PCI regions associated with PCI device @pdev as
1207 * being reserved by owner @res_name. Do not access any
1208 * address inside the PCI regions unless this call returns
1209 * successfully.
1211 * Returns 0 on success, or %EBUSY on error. A warning
1212 * message is also printed on failure.
1214 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1216 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1220 * pci_set_master - enables bus-mastering for device dev
1221 * @dev: the PCI device to enable
1223 * Enables bus-mastering on the device and calls pcibios_set_master()
1224 * to do the needed arch specific settings.
1226 void
1227 pci_set_master(struct pci_dev *dev)
1229 u16 cmd;
1231 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1232 if (! (cmd & PCI_COMMAND_MASTER)) {
1233 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
1234 cmd |= PCI_COMMAND_MASTER;
1235 pci_write_config_word(dev, PCI_COMMAND, cmd);
1237 dev->is_busmaster = 1;
1238 pcibios_set_master(dev);
1241 #ifdef PCI_DISABLE_MWI
1242 int pci_set_mwi(struct pci_dev *dev)
1244 return 0;
1247 int pci_try_set_mwi(struct pci_dev *dev)
1249 return 0;
1252 void pci_clear_mwi(struct pci_dev *dev)
1256 #else
1258 #ifndef PCI_CACHE_LINE_BYTES
1259 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1260 #endif
1262 /* This can be overridden by arch code. */
1263 /* Don't forget this is measured in 32-bit words, not bytes */
1264 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1267 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1268 * @dev: the PCI device for which MWI is to be enabled
1270 * Helper function for pci_set_mwi.
1271 * Originally copied from drivers/net/acenic.c.
1272 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1274 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1276 static int
1277 pci_set_cacheline_size(struct pci_dev *dev)
1279 u8 cacheline_size;
1281 if (!pci_cache_line_size)
1282 return -EINVAL; /* The system doesn't support MWI. */
1284 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1285 equal to or multiple of the right value. */
1286 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1287 if (cacheline_size >= pci_cache_line_size &&
1288 (cacheline_size % pci_cache_line_size) == 0)
1289 return 0;
1291 /* Write the correct value. */
1292 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1293 /* Read it back. */
1294 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1295 if (cacheline_size == pci_cache_line_size)
1296 return 0;
1298 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
1299 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
1301 return -EINVAL;
1305 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1306 * @dev: the PCI device for which MWI is enabled
1308 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1310 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1313 pci_set_mwi(struct pci_dev *dev)
1315 int rc;
1316 u16 cmd;
1318 rc = pci_set_cacheline_size(dev);
1319 if (rc)
1320 return rc;
1322 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1323 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1324 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n",
1325 pci_name(dev));
1326 cmd |= PCI_COMMAND_INVALIDATE;
1327 pci_write_config_word(dev, PCI_COMMAND, cmd);
1330 return 0;
1334 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1335 * @dev: the PCI device for which MWI is enabled
1337 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1338 * Callers are not required to check the return value.
1340 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1342 int pci_try_set_mwi(struct pci_dev *dev)
1344 int rc = pci_set_mwi(dev);
1345 return rc;
1349 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1350 * @dev: the PCI device to disable
1352 * Disables PCI Memory-Write-Invalidate transaction on the device
1354 void
1355 pci_clear_mwi(struct pci_dev *dev)
1357 u16 cmd;
1359 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1360 if (cmd & PCI_COMMAND_INVALIDATE) {
1361 cmd &= ~PCI_COMMAND_INVALIDATE;
1362 pci_write_config_word(dev, PCI_COMMAND, cmd);
1365 #endif /* ! PCI_DISABLE_MWI */
1368 * pci_intx - enables/disables PCI INTx for device dev
1369 * @pdev: the PCI device to operate on
1370 * @enable: boolean: whether to enable or disable PCI INTx
1372 * Enables/disables PCI INTx for device dev
1374 void
1375 pci_intx(struct pci_dev *pdev, int enable)
1377 u16 pci_command, new;
1379 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1381 if (enable) {
1382 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1383 } else {
1384 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1387 if (new != pci_command) {
1388 struct pci_devres *dr;
1390 pci_write_config_word(pdev, PCI_COMMAND, new);
1392 dr = find_pci_dr(pdev);
1393 if (dr && !dr->restore_intx) {
1394 dr->restore_intx = 1;
1395 dr->orig_intx = !enable;
1401 * pci_msi_off - disables any msi or msix capabilities
1402 * @dev: the PCI device to operate on
1404 * If you want to use msi see pci_enable_msi and friends.
1405 * This is a lower level primitive that allows us to disable
1406 * msi operation at the device level.
1408 void pci_msi_off(struct pci_dev *dev)
1410 int pos;
1411 u16 control;
1413 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1414 if (pos) {
1415 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
1416 control &= ~PCI_MSI_FLAGS_ENABLE;
1417 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
1419 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1420 if (pos) {
1421 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
1422 control &= ~PCI_MSIX_FLAGS_ENABLE;
1423 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
1427 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1429 * These can be overridden by arch-specific implementations
1432 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1434 if (!pci_dma_supported(dev, mask))
1435 return -EIO;
1437 dev->dma_mask = mask;
1439 return 0;
1443 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1445 if (!pci_dma_supported(dev, mask))
1446 return -EIO;
1448 dev->dev.coherent_dma_mask = mask;
1450 return 0;
1452 #endif
1455 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1456 * @dev: PCI device to query
1458 * Returns mmrbc: maximum designed memory read count in bytes
1459 * or appropriate error value.
1461 int pcix_get_max_mmrbc(struct pci_dev *dev)
1463 int err, cap;
1464 u32 stat;
1466 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1467 if (!cap)
1468 return -EINVAL;
1470 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1471 if (err)
1472 return -EINVAL;
1474 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
1476 EXPORT_SYMBOL(pcix_get_max_mmrbc);
1479 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1480 * @dev: PCI device to query
1482 * Returns mmrbc: maximum memory read count in bytes
1483 * or appropriate error value.
1485 int pcix_get_mmrbc(struct pci_dev *dev)
1487 int ret, cap;
1488 u32 cmd;
1490 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1491 if (!cap)
1492 return -EINVAL;
1494 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1495 if (!ret)
1496 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
1498 return ret;
1500 EXPORT_SYMBOL(pcix_get_mmrbc);
1503 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1504 * @dev: PCI device to query
1505 * @mmrbc: maximum memory read count in bytes
1506 * valid values are 512, 1024, 2048, 4096
1508 * If possible sets maximum memory read byte count, some bridges have erratas
1509 * that prevent this.
1511 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
1513 int cap, err = -EINVAL;
1514 u32 stat, cmd, v, o;
1516 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
1517 goto out;
1519 v = ffs(mmrbc) - 10;
1521 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1522 if (!cap)
1523 goto out;
1525 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1526 if (err)
1527 goto out;
1529 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
1530 return -E2BIG;
1532 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1533 if (err)
1534 goto out;
1536 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
1537 if (o != v) {
1538 if (v > o && dev->bus &&
1539 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
1540 return -EIO;
1542 cmd &= ~PCI_X_CMD_MAX_READ;
1543 cmd |= v << 2;
1544 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
1546 out:
1547 return err;
1549 EXPORT_SYMBOL(pcix_set_mmrbc);
1552 * pcie_get_readrq - get PCI Express read request size
1553 * @dev: PCI device to query
1555 * Returns maximum memory read request in bytes
1556 * or appropriate error value.
1558 int pcie_get_readrq(struct pci_dev *dev)
1560 int ret, cap;
1561 u16 ctl;
1563 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1564 if (!cap)
1565 return -EINVAL;
1567 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1568 if (!ret)
1569 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
1571 return ret;
1573 EXPORT_SYMBOL(pcie_get_readrq);
1576 * pcie_set_readrq - set PCI Express maximum memory read request
1577 * @dev: PCI device to query
1578 * @rq: maximum memory read count in bytes
1579 * valid values are 128, 256, 512, 1024, 2048, 4096
1581 * If possible sets maximum read byte count
1583 int pcie_set_readrq(struct pci_dev *dev, int rq)
1585 int cap, err = -EINVAL;
1586 u16 ctl, v;
1588 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
1589 goto out;
1591 v = (ffs(rq) - 8) << 12;
1593 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1594 if (!cap)
1595 goto out;
1597 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1598 if (err)
1599 goto out;
1601 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
1602 ctl &= ~PCI_EXP_DEVCTL_READRQ;
1603 ctl |= v;
1604 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
1607 out:
1608 return err;
1610 EXPORT_SYMBOL(pcie_set_readrq);
1613 * pci_select_bars - Make BAR mask from the type of resource
1614 * @dev: the PCI device for which BAR mask is made
1615 * @flags: resource type mask to be selected
1617 * This helper routine makes bar mask from the type of resource.
1619 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
1621 int i, bars = 0;
1622 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1623 if (pci_resource_flags(dev, i) & flags)
1624 bars |= (1 << i);
1625 return bars;
1628 static void __devinit pci_no_domains(void)
1630 #ifdef CONFIG_PCI_DOMAINS
1631 pci_domains_supported = 0;
1632 #endif
1635 static int __devinit pci_init(void)
1637 struct pci_dev *dev = NULL;
1639 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1640 pci_fixup_device(pci_fixup_final, dev);
1642 return 0;
1645 static int __devinit pci_setup(char *str)
1647 while (str) {
1648 char *k = strchr(str, ',');
1649 if (k)
1650 *k++ = 0;
1651 if (*str && (str = pcibios_setup(str)) && *str) {
1652 if (!strcmp(str, "nomsi")) {
1653 pci_no_msi();
1654 } else if (!strcmp(str, "noaer")) {
1655 pci_no_aer();
1656 } else if (!strcmp(str, "nodomains")) {
1657 pci_no_domains();
1658 } else if (!strncmp(str, "cbiosize=", 9)) {
1659 pci_cardbus_io_size = memparse(str + 9, &str);
1660 } else if (!strncmp(str, "cbmemsize=", 10)) {
1661 pci_cardbus_mem_size = memparse(str + 10, &str);
1662 } else {
1663 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1664 str);
1667 str = k;
1669 return 0;
1671 early_param("pci", pci_setup);
1673 device_initcall(pci_init);
1675 EXPORT_SYMBOL(pci_reenable_device);
1676 EXPORT_SYMBOL(pci_enable_device_io);
1677 EXPORT_SYMBOL(pci_enable_device_mem);
1678 EXPORT_SYMBOL(pci_enable_device);
1679 EXPORT_SYMBOL(pcim_enable_device);
1680 EXPORT_SYMBOL(pcim_pin_device);
1681 EXPORT_SYMBOL(pci_disable_device);
1682 EXPORT_SYMBOL(pci_find_capability);
1683 EXPORT_SYMBOL(pci_bus_find_capability);
1684 EXPORT_SYMBOL(pci_release_regions);
1685 EXPORT_SYMBOL(pci_request_regions);
1686 EXPORT_SYMBOL(pci_release_region);
1687 EXPORT_SYMBOL(pci_request_region);
1688 EXPORT_SYMBOL(pci_release_selected_regions);
1689 EXPORT_SYMBOL(pci_request_selected_regions);
1690 EXPORT_SYMBOL(pci_set_master);
1691 EXPORT_SYMBOL(pci_set_mwi);
1692 EXPORT_SYMBOL(pci_try_set_mwi);
1693 EXPORT_SYMBOL(pci_clear_mwi);
1694 EXPORT_SYMBOL_GPL(pci_intx);
1695 EXPORT_SYMBOL(pci_set_dma_mask);
1696 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1697 EXPORT_SYMBOL(pci_assign_resource);
1698 EXPORT_SYMBOL(pci_find_parent_resource);
1699 EXPORT_SYMBOL(pci_select_bars);
1701 EXPORT_SYMBOL(pci_set_power_state);
1702 EXPORT_SYMBOL(pci_save_state);
1703 EXPORT_SYMBOL(pci_restore_state);
1704 EXPORT_SYMBOL(pci_enable_wake);
1705 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);