arch/arm/mach-mx3/mm.c

   1 /*
   2  *  Copyright (C) 1999,2000 Arm Limited
   3  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   4  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   5  *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   6  *    - add MX31 specific definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/mm.h>
  20 #include <linux/init.h>
  21 #include <linux/err.h>
  22
  23 #include <asm/pgtable.h>
  24 #include <asm/mach/map.h>
  25 #include <asm/hardware/cache-l2x0.h>
  26
  27 #include <mach/common.h>
  28 #include <mach/hardware.h>
  29 #include <mach/iomux-v3.h>
  30
  31 /*!
  32  * @file mm.c
  33  *
  34  * @brief This file creates static virtual to physical mappings, common to all MX3 boards.
  35  *
  36  * @ingroup Memory
  37  */
  38
  39 #ifdef CONFIG_SOC_IMX31
  40 static struct map_desc mx31_io_desc[] __initdata = {
  41         imx_map_entry(MX31, X_MEMC, MT_DEVICE),
  42         imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
  43         imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
  44         imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
  45         imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
  46 };
  47
  48 /*
  49  * This function initializes the memory map. It is called during the
  50  * system startup to create static physical to virtual memory mappings
  51  * for the IO modules.
  52  */
  53 void __init mx31_map_io(void)
  54 {
  55         mxc_set_cpu_type(MXC_CPU_MX31);
  56         mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
  57
  58         iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
  59 }
  60
  61 int imx31_register_gpios(void);
  62 void __init mx31_init_irq(void)
  63 {
  64         mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
  65         imx31_register_gpios();
  66 }
  67 #endif /* ifdef CONFIG_SOC_IMX31 */
  68
  69 #ifdef CONFIG_SOC_IMX35
  70 static struct map_desc mx35_io_desc[] __initdata = {
  71         imx_map_entry(MX35, X_MEMC, MT_DEVICE),
  72         imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
  73         imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
  74         imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
  75         imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
  76 };
  77
  78 void __init mx35_map_io(void)
  79 {
  80         mxc_set_cpu_type(MXC_CPU_MX35);
  81         mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
  82         mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
  83
  84         iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
  85 }
  86
  87 int imx35_register_gpios(void);
  88 void __init mx35_init_irq(void)
  89 {
  90         mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
  91         imx35_register_gpios();
  92 }
  93 #endif /* ifdef CONFIG_SOC_IMX35 */
  94
  95 #ifdef CONFIG_CACHE_L2X0
  96 static int mxc_init_l2x0(void)
  97 {
  98         void __iomem *l2x0_base;
  99         void __iomem *clkctl_base;
 100 /*
 101  * First of all, we must repair broken chip settings. There are some
 102  * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
 103  * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
 104  * Workaraound is to setup the correct register setting prior enabling the
 105  * L2 cache. This should not hurt already working CPUs, as they are using the
 106  * same value
 107  */
 108 #define L2_MEM_VAL 0x10
 109
 110         clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
 111         if (clkctl_base != NULL) {
 112                 writel(0x00000515, clkctl_base + L2_MEM_VAL);
 113                 iounmap(clkctl_base);
 114         } else {
 115                 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
 116         }
 117
 118         l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
 119         if (IS_ERR(l2x0_base)) {
 120                 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
 121                                 PTR_ERR(l2x0_base));
 122                 return 0;
 123         }
 124
 125         l2x0_init(l2x0_base, 0x00030024, 0x00000000);
 126
 127         return 0;
 128 }
 129
 130 arch_initcall(mxc_init_l2x0);
 131 #endif
 132