drivers/ide/pci/sc1200.c

   1 /*
   2  * linux/drivers/ide/pci/sc1200.c               Version 0.96    Aug 2 2007
   3  *
   4  * Copyright (C) 2000-2002              Mark Lord <mlord@pobox.com>
   5  * Copyright (C)      2007              Bartlomiej Zolnierkiewicz
   6  *
   7  * May be copied or modified under the terms of the GNU General Public License
   8  *
   9  * Development of this chipset driver was funded
  10  * by the nice folks at National Semiconductor.
  11  *
  12  * Documentation:
  13  *      Available from National Semiconductor
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/types.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/timer.h>
  21 #include <linux/mm.h>
  22 #include <linux/ioport.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/hdreg.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/pci.h>
  27 #include <linux/init.h>
  28 #include <linux/ide.h>
  29 #include <linux/pm.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32
  33 #define SC1200_REV_A    0x00
  34 #define SC1200_REV_B1   0x01
  35 #define SC1200_REV_B3   0x02
  36 #define SC1200_REV_C1   0x03
  37 #define SC1200_REV_D1   0x04
  38
  39 #define PCI_CLK_33      0x00
  40 #define PCI_CLK_48      0x01
  41 #define PCI_CLK_66      0x02
  42 #define PCI_CLK_33A     0x03
  43
  44 static unsigned short sc1200_get_pci_clock (void)
  45 {
  46         unsigned char chip_id, silicon_revision;
  47         unsigned int pci_clock;
  48         /*
  49          * Check the silicon revision, as not all versions of the chip
  50          * have the register with the fast PCI bus timings.
  51          */
  52         chip_id = inb (0x903c);
  53         silicon_revision = inb (0x903d);
  54
  55         // Read the fast pci clock frequency
  56         if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
  57                 pci_clock = PCI_CLK_33;
  58         } else {
  59                 // check clock generator configuration (cfcc)
  60                 // the clock is in bits 8 and 9 of this word
  61
  62                 pci_clock = inw (0x901e);
  63                 pci_clock >>= 8;
  64                 pci_clock &= 0x03;
  65                 if (pci_clock == PCI_CLK_33A)
  66                         pci_clock = PCI_CLK_33;
  67         }
  68         return pci_clock;
  69 }
  70
  71 /*
  72  * Here are the standard PIO mode 0-4 timings for each "format".
  73  * Format-0 uses fast data reg timings, with slower command reg timings.
  74  * Format-1 uses fast timings for all registers, but won't work with all drives.
  75  */
  76 static const unsigned int sc1200_pio_timings[4][5] =
  77         {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},  // format0  33Mhz
  78          {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010},  // format1, 33Mhz
  79          {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021},  // format1, 48Mhz
  80          {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
  81
  82 /*
  83  * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
  84  */
  85 //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
  86
  87 static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
  88 {
  89         ide_hwif_t *hwif = drive->hwif;
  90         struct pci_dev *pdev = hwif->pci_dev;
  91         unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
  92
  93         pci_read_config_dword(pdev, basereg + 4, &format);
  94         format = (format >> 31) & 1;
  95         if (format)
  96                 format += sc1200_get_pci_clock();
  97         pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
  98                                sc1200_pio_timings[format][pio]);
  99 }
 100
 101 /*
 102  *      The SC1200 specifies that two drives sharing a cable cannot mix
 103  *      UDMA/MDMA.  It has to be one or the other, for the pair, though
 104  *      different timings can still be chosen for each drive.  We could
 105  *      set the appropriate timing bits on the fly, but that might be
 106  *      a bit confusing.  So, for now we statically handle this requirement
 107  *      by looking at our mate drive to see what it is capable of, before
 108  *      choosing a mode for our own drive.
 109  */
 110 static u8 sc1200_udma_filter(ide_drive_t *drive)
 111 {
 112         ide_hwif_t *hwif = drive->hwif;
 113         ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
 114         struct hd_driveid *mateid = mate->id;
 115         u8 mask = hwif->ultra_mask;
 116
 117         if (mate->present == 0)
 118                 goto out;
 119
 120         if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
 121                 if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
 122                         goto out;
 123                 if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
 124                         mask = 0;
 125         }
 126 out:
 127         return mask;
 128 }
 129
 130 static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
 131 {
 132         ide_hwif_t              *hwif = HWIF(drive);
 133         int                     unit = drive->select.b.unit;
 134         unsigned int            reg, timings;
 135         unsigned short          pci_clock;
 136         unsigned int            basereg = hwif->channel ? 0x50 : 0x40;
 137
 138         pci_clock = sc1200_get_pci_clock();
 139
 140         /*
 141          * Note that each DMA mode has several timings associated with it.
 142          * The correct timing depends on the fast PCI clock freq.
 143          */
 144         timings = 0;
 145         switch (mode) {
 146                 case XFER_UDMA_0:
 147                         switch (pci_clock) {
 148                                 case PCI_CLK_33:        timings = 0x00921250;   break;
 149                                 case PCI_CLK_48:        timings = 0x00932470;   break;
 150                                 case PCI_CLK_66:        timings = 0x009436a1;   break;
 151                         }
 152                         break;
 153                 case XFER_UDMA_1:
 154                         switch (pci_clock) {
 155                                 case PCI_CLK_33:        timings = 0x00911140;   break;
 156                                 case PCI_CLK_48:        timings = 0x00922260;   break;
 157                                 case PCI_CLK_66:        timings = 0x00933481;   break;
 158                         }
 159                         break;
 160                 case XFER_UDMA_2:
 161                         switch (pci_clock) {
 162                                 case PCI_CLK_33:        timings = 0x00911030;   break;
 163                                 case PCI_CLK_48:        timings = 0x00922140;   break;
 164                                 case PCI_CLK_66:        timings = 0x00923261;   break;
 165                         }
 166                         break;
 167                 case XFER_MW_DMA_0:
 168                         switch (pci_clock) {
 169                                 case PCI_CLK_33:        timings = 0x00077771;   break;
 170                                 case PCI_CLK_48:        timings = 0x000bbbb2;   break;
 171                                 case PCI_CLK_66:        timings = 0x000ffff3;   break;
 172                         }
 173                         break;
 174                 case XFER_MW_DMA_1:
 175                         switch (pci_clock) {
 176                                 case PCI_CLK_33:        timings = 0x00012121;   break;
 177                                 case PCI_CLK_48:        timings = 0x00024241;   break;
 178                                 case PCI_CLK_66:        timings = 0x00035352;   break;
 179                         }
 180                         break;
 181                 case XFER_MW_DMA_2:
 182                         switch (pci_clock) {
 183                                 case PCI_CLK_33:        timings = 0x00002020;   break;
 184                                 case PCI_CLK_48:        timings = 0x00013131;   break;
 185                                 case PCI_CLK_66:        timings = 0x00015151;   break;
 186                         }
 187                         break;
 188                 default:
 189                         BUG();
 190                         break;
 191         }
 192
 193         if (unit == 0) {                        /* are we configuring drive0? */
 194                 pci_read_config_dword(hwif->pci_dev, basereg+4, &reg);
 195                 timings |= reg & 0x80000000;    /* preserve PIO format bit */
 196                 pci_write_config_dword(hwif->pci_dev, basereg+4, timings);
 197         } else {
 198                 pci_write_config_dword(hwif->pci_dev, basereg+12, timings);
 199         }
 200 }
 201
 202 /*
 203  * sc1200_config_dma() handles selection/setting of DMA/UDMA modes
 204  * for both the chipset and drive.
 205  */
 206 static int sc1200_config_dma (ide_drive_t *drive)
 207 {
 208         if (ide_tune_dma(drive))
 209                 return 0;
 210
 211         return 1;
 212 }
 213
 214
 215 /*  Replacement for the standard ide_dma_end action in
 216  *  dma_proc.
 217  *
 218  *  returns 1 on error, 0 otherwise
 219  */
 220 static int sc1200_ide_dma_end (ide_drive_t *drive)
 221 {
 222         ide_hwif_t *hwif = HWIF(drive);
 223         unsigned long dma_base = hwif->dma_base;
 224         byte dma_stat;
 225
 226         dma_stat = inb(dma_base+2);             /* get DMA status */
 227
 228         if (!(dma_stat & 4))
 229                 printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
 230                   dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
 231
 232         outb(dma_stat|0x1b, dma_base+2);        /* clear the INTR & ERROR bits */
 233         outb(inb(dma_base)&~1, dma_base);       /* !! DO THIS HERE !! stop DMA */
 234
 235         drive->waiting_for_dma = 0;
 236         ide_destroy_dmatable(drive);            /* purge DMA mappings */
 237
 238         return (dma_stat & 7) != 4;             /* verify good DMA status */
 239 }
 240
 241 /*
 242  * sc1200_set_pio_mode() handles setting of PIO modes
 243  * for both the chipset and drive.
 244  *
 245  * All existing BIOSs for this chipset guarantee that all drives
 246  * will have valid default PIO timings set up before we get here.
 247  */
 248
 249 static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
 250 {
 251         ide_hwif_t      *hwif = HWIF(drive);
 252         int             mode = -1;
 253
 254         /*
 255          * bad abuse of ->set_pio_mode interface
 256          */
 257         switch (pio) {
 258                 case 200: mode = XFER_UDMA_0;   break;
 259                 case 201: mode = XFER_UDMA_1;   break;
 260                 case 202: mode = XFER_UDMA_2;   break;
 261                 case 100: mode = XFER_MW_DMA_0; break;
 262                 case 101: mode = XFER_MW_DMA_1; break;
 263                 case 102: mode = XFER_MW_DMA_2; break;
 264         }
 265         if (mode != -1) {
 266                 printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
 267                 hwif->dma_off_quietly(drive);
 268                 if (ide_set_dma_mode(drive, mode) == 0)
 269                         hwif->dma_host_on(drive);
 270                 return;
 271         }
 272
 273         sc1200_tunepio(drive, pio);
 274 }
 275
 276 #ifdef CONFIG_PM
 277 static ide_hwif_t *lookup_pci_dev (ide_hwif_t *prev, struct pci_dev *dev)
 278 {
 279         int     h;
 280
 281         for (h = 0; h < MAX_HWIFS; h++) {
 282                 ide_hwif_t *hwif = &ide_hwifs[h];
 283                 if (prev) {
 284                         if (hwif == prev)
 285                                 prev = NULL;    // found previous, now look for next match
 286                 } else {
 287                         if (hwif && hwif->pci_dev == dev)
 288                                 return hwif;    // found next match
 289                 }
 290         }
 291         return NULL;    // not found
 292 }
 293
 294 typedef struct sc1200_saved_state_s {
 295         __u32           regs[4];
 296 } sc1200_saved_state_t;
 297
 298
 299 static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
 300 {
 301         ide_hwif_t              *hwif = NULL;
 302
 303         printk("SC1200: suspend(%u)\n", state.event);
 304
 305         if (state.event == PM_EVENT_ON) {
 306                 // we only save state when going from full power to less
 307
 308                 //
 309                 // Loop over all interfaces that are part of this PCI device:
 310                 //
 311                 while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
 312                         sc1200_saved_state_t    *ss;
 313                         unsigned int            basereg, r;
 314                         //
 315                         // allocate a permanent save area, if not already allocated
 316                         //
 317                         ss = (sc1200_saved_state_t *)hwif->config_data;
 318                         if (ss == NULL) {
 319                                 ss = kmalloc(sizeof(sc1200_saved_state_t), GFP_KERNEL);
 320                                 if (ss == NULL)
 321                                         return -ENOMEM;
 322                                 hwif->config_data = (unsigned long)ss;
 323                         }
 324                         ss = (sc1200_saved_state_t *)hwif->config_data;
 325                         //
 326                         // Save timing registers:  this may be unnecessary if
 327                         // BIOS also does it
 328                         //
 329                         basereg = hwif->channel ? 0x50 : 0x40;
 330                         for (r = 0; r < 4; ++r) {
 331                                 pci_read_config_dword (hwif->pci_dev, basereg + (r<<2), &ss->regs[r]);
 332                         }
 333                 }
 334         }
 335
 336         /* You don't need to iterate over disks -- sysfs should have done that for you already */
 337
 338         pci_disable_device(dev);
 339         pci_set_power_state(dev, pci_choose_state(dev, state));
 340         dev->current_state = state.event;
 341         return 0;
 342 }
 343
 344 static int sc1200_resume (struct pci_dev *dev)
 345 {
 346         ide_hwif_t      *hwif = NULL;
 347
 348         pci_set_power_state(dev, PCI_D0);       // bring chip back from sleep state
 349         dev->current_state = PM_EVENT_ON;
 350         pci_enable_device(dev);
 351         //
 352         // loop over all interfaces that are part of this pci device:
 353         //
 354         while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
 355                 unsigned int            basereg, r;
 356                 sc1200_saved_state_t    *ss = (sc1200_saved_state_t *)hwif->config_data;
 357
 358                 //
 359                 // Restore timing registers:  this may be unnecessary if BIOS also does it
 360                 //
 361                 basereg = hwif->channel ? 0x50 : 0x40;
 362                 if (ss != NULL) {
 363                         for (r = 0; r < 4; ++r) {
 364                                 pci_write_config_dword(hwif->pci_dev, basereg + (r<<2), ss->regs[r]);
 365                         }
 366                 }
 367         }
 368         return 0;
 369 }
 370 #endif
 371
 372 /*
 373  * This gets invoked by the IDE driver once for each channel,
 374  * and performs channel-specific pre-initialization before drive probing.
 375  */
 376 static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif)
 377 {
 378         if (hwif->mate)
 379                 hwif->serialized = hwif->mate->serialized = 1;
 380         hwif->autodma = 0;
 381
 382         hwif->set_pio_mode = &sc1200_set_pio_mode;
 383         hwif->set_dma_mode = &sc1200_set_dma_mode;
 384
 385         hwif->drives[0].autotune = 1;
 386         hwif->drives[1].autotune = 1;
 387
 388         if (hwif->dma_base == 0)
 389                 return;
 390
 391         hwif->udma_filter = sc1200_udma_filter;
 392         hwif->ide_dma_check = &sc1200_config_dma;
 393         hwif->ide_dma_end   = &sc1200_ide_dma_end;
 394
 395         if (!noautodma)
 396                 hwif->autodma = 1;
 397
 398         hwif->atapi_dma = 1;
 399         hwif->ultra_mask = 0x07;
 400         hwif->mwdma_mask = 0x07;
 401
 402         hwif->drives[0].autodma = hwif->autodma;
 403         hwif->drives[1].autodma = hwif->autodma;
 404 }
 405
 406 static ide_pci_device_t sc1200_chipset __devinitdata = {
 407         .name           = "SC1200",
 408         .init_hwif      = init_hwif_sc1200,
 409         .autodma        = AUTODMA,
 410         .bootable       = ON_BOARD,
 411         .host_flags     = IDE_HFLAG_ABUSE_DMA_MODES | IDE_HFLAG_POST_SET_MODE,
 412         .pio_mask       = ATA_PIO4,
 413 };
 414
 415 static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 416 {
 417         return ide_setup_pci_device(dev, &sc1200_chipset);
 418 }
 419
 420 static struct pci_device_id sc1200_pci_tbl[] = {
 421         { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
 422         { 0, },
 423 };
 424 MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
 425
 426 static struct pci_driver driver = {
 427         .name           = "SC1200_IDE",
 428         .id_table       = sc1200_pci_tbl,
 429         .probe          = sc1200_init_one,
 430 #ifdef CONFIG_PM
 431         .suspend        = sc1200_suspend,
 432         .resume         = sc1200_resume,
 433 #endif
 434 };
 435
 436 static int __init sc1200_ide_init(void)
 437 {
 438         return ide_pci_register_driver(&driver);
 439 }
 440
 441 module_init(sc1200_ide_init);
 442
 443 MODULE_AUTHOR("Mark Lord");
 444 MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
 445 MODULE_LICENSE("GPL");