2 * linux/arch/arm/mach-at91/gpio.c
4 * Copyright (C) 2005 HP Labs
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/clk.h>
13 #include <linux/errno.h>
14 #include <linux/device.h>
15 #include <linux/gpio.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/debugfs.h>
19 #include <linux/seq_file.h>
20 #include <linux/kernel.h>
21 #include <linux/list.h>
22 #include <linux/module.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_gpio.h>
29 #include <asm/mach/irq.h>
31 #include <mach/hardware.h>
32 #include <mach/at91_pio.h>
36 struct at91_gpio_chip
{
37 struct gpio_chip chip
;
38 struct at91_gpio_chip
*next
; /* Bank sharing same clock */
39 int pioc_hwirq
; /* PIO bank interrupt identifier on AIC */
40 int pioc_virq
; /* PIO bank Linux virtual interrupt */
41 int pioc_idx
; /* PIO bank index */
42 void __iomem
*regbase
; /* PIO bank virtual address */
43 struct clk
*clock
; /* associated clock */
44 struct irq_domain
*domain
; /* associated irq domain */
47 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
49 static void at91_gpiolib_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
);
50 static void at91_gpiolib_set(struct gpio_chip
*chip
, unsigned offset
, int val
);
51 static int at91_gpiolib_get(struct gpio_chip
*chip
, unsigned offset
);
52 static int at91_gpiolib_direction_output(struct gpio_chip
*chip
,
53 unsigned offset
, int val
);
54 static int at91_gpiolib_direction_input(struct gpio_chip
*chip
,
56 static int at91_gpiolib_to_irq(struct gpio_chip
*chip
, unsigned offset
);
58 #define AT91_GPIO_CHIP(name, nr_gpio) \
62 .direction_input = at91_gpiolib_direction_input, \
63 .direction_output = at91_gpiolib_direction_output, \
64 .get = at91_gpiolib_get, \
65 .set = at91_gpiolib_set, \
66 .dbg_show = at91_gpiolib_dbg_show, \
67 .to_irq = at91_gpiolib_to_irq, \
72 static struct at91_gpio_chip gpio_chip
[] = {
73 AT91_GPIO_CHIP("pioA", 32),
74 AT91_GPIO_CHIP("pioB", 32),
75 AT91_GPIO_CHIP("pioC", 32),
76 AT91_GPIO_CHIP("pioD", 32),
77 AT91_GPIO_CHIP("pioE", 32),
80 static int gpio_banks
;
81 static unsigned long at91_gpio_caps
;
83 /* All PIO controllers support PIO3 features */
84 #define AT91_GPIO_CAP_PIO3 (1 << 0)
86 #define has_pio3() (at91_gpio_caps & AT91_GPIO_CAP_PIO3)
88 /*--------------------------------------------------------------------------*/
90 static inline void __iomem
*pin_to_controller(unsigned pin
)
93 if (likely(pin
< gpio_banks
))
94 return gpio_chip
[pin
].regbase
;
99 static inline unsigned pin_to_mask(unsigned pin
)
101 return 1 << (pin
% 32);
105 static char peripheral_function(void __iomem
*pio
, unsigned mask
)
112 select
= !!(__raw_readl(pio
+ PIO_ABCDSR1
) & mask
);
113 select
|= (!!(__raw_readl(pio
+ PIO_ABCDSR2
) & mask
) << 1);
116 ret
= __raw_readl(pio
+ PIO_ABSR
) & mask
?
124 /*--------------------------------------------------------------------------*/
126 /* Not all hardware capabilities are exposed through these calls; they
127 * only encapsulate the most common features and modes. (So if you
128 * want to change signals in groups, do it directly.)
130 * Bootloaders will usually handle some of the pin multiplexing setup.
131 * The intent is certainly that by the time Linux is fully booted, all
132 * pins should have been fully initialized. These setup calls should
133 * only be used by board setup routines, or possibly in driver probe().
135 * For bootloaders doing all that setup, these calls could be inlined
136 * as NOPs so Linux won't duplicate any setup code
141 * mux the pin to the "GPIO" peripheral role.
143 int __init_or_module
at91_set_GPIO_periph(unsigned pin
, int use_pullup
)
145 void __iomem
*pio
= pin_to_controller(pin
);
146 unsigned mask
= pin_to_mask(pin
);
150 __raw_writel(mask
, pio
+ PIO_IDR
);
151 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
152 __raw_writel(mask
, pio
+ PIO_PER
);
155 EXPORT_SYMBOL(at91_set_GPIO_periph
);
159 * mux the pin to the "A" internal peripheral role.
161 int __init_or_module
at91_set_A_periph(unsigned pin
, int use_pullup
)
163 void __iomem
*pio
= pin_to_controller(pin
);
164 unsigned mask
= pin_to_mask(pin
);
169 __raw_writel(mask
, pio
+ PIO_IDR
);
170 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
172 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR1
) & ~mask
,
174 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR2
) & ~mask
,
177 __raw_writel(mask
, pio
+ PIO_ASR
);
179 __raw_writel(mask
, pio
+ PIO_PDR
);
182 EXPORT_SYMBOL(at91_set_A_periph
);
186 * mux the pin to the "B" internal peripheral role.
188 int __init_or_module
at91_set_B_periph(unsigned pin
, int use_pullup
)
190 void __iomem
*pio
= pin_to_controller(pin
);
191 unsigned mask
= pin_to_mask(pin
);
196 __raw_writel(mask
, pio
+ PIO_IDR
);
197 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
199 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR1
) | mask
,
201 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR2
) & ~mask
,
204 __raw_writel(mask
, pio
+ PIO_BSR
);
206 __raw_writel(mask
, pio
+ PIO_PDR
);
209 EXPORT_SYMBOL(at91_set_B_periph
);
213 * mux the pin to the "C" internal peripheral role.
215 int __init_or_module
at91_set_C_periph(unsigned pin
, int use_pullup
)
217 void __iomem
*pio
= pin_to_controller(pin
);
218 unsigned mask
= pin_to_mask(pin
);
220 if (!pio
|| !has_pio3())
223 __raw_writel(mask
, pio
+ PIO_IDR
);
224 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
225 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR1
) & ~mask
, pio
+ PIO_ABCDSR1
);
226 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR2
) | mask
, pio
+ PIO_ABCDSR2
);
227 __raw_writel(mask
, pio
+ PIO_PDR
);
230 EXPORT_SYMBOL(at91_set_C_periph
);
234 * mux the pin to the "D" internal peripheral role.
236 int __init_or_module
at91_set_D_periph(unsigned pin
, int use_pullup
)
238 void __iomem
*pio
= pin_to_controller(pin
);
239 unsigned mask
= pin_to_mask(pin
);
241 if (!pio
|| !has_pio3())
244 __raw_writel(mask
, pio
+ PIO_IDR
);
245 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
246 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR1
) | mask
, pio
+ PIO_ABCDSR1
);
247 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR2
) | mask
, pio
+ PIO_ABCDSR2
);
248 __raw_writel(mask
, pio
+ PIO_PDR
);
251 EXPORT_SYMBOL(at91_set_D_periph
);
255 * mux the pin to the gpio controller (instead of "A", "B", "C"
256 * or "D" peripheral), and configure it for an input.
258 int __init_or_module
at91_set_gpio_input(unsigned pin
, int use_pullup
)
260 void __iomem
*pio
= pin_to_controller(pin
);
261 unsigned mask
= pin_to_mask(pin
);
266 __raw_writel(mask
, pio
+ PIO_IDR
);
267 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
268 __raw_writel(mask
, pio
+ PIO_ODR
);
269 __raw_writel(mask
, pio
+ PIO_PER
);
272 EXPORT_SYMBOL(at91_set_gpio_input
);
276 * mux the pin to the gpio controller (instead of "A", "B", "C"
277 * or "D" peripheral), and configure it for an output.
279 int __init_or_module
at91_set_gpio_output(unsigned pin
, int value
)
281 void __iomem
*pio
= pin_to_controller(pin
);
282 unsigned mask
= pin_to_mask(pin
);
287 __raw_writel(mask
, pio
+ PIO_IDR
);
288 __raw_writel(mask
, pio
+ PIO_PUDR
);
289 __raw_writel(mask
, pio
+ (value
? PIO_SODR
: PIO_CODR
));
290 __raw_writel(mask
, pio
+ PIO_OER
);
291 __raw_writel(mask
, pio
+ PIO_PER
);
294 EXPORT_SYMBOL(at91_set_gpio_output
);
298 * enable/disable the glitch filter; mostly used with IRQ handling.
300 int __init_or_module
at91_set_deglitch(unsigned pin
, int is_on
)
302 void __iomem
*pio
= pin_to_controller(pin
);
303 unsigned mask
= pin_to_mask(pin
);
308 if (has_pio3() && is_on
)
309 __raw_writel(mask
, pio
+ PIO_IFSCDR
);
310 __raw_writel(mask
, pio
+ (is_on
? PIO_IFER
: PIO_IFDR
));
313 EXPORT_SYMBOL(at91_set_deglitch
);
316 * enable/disable the debounce filter;
318 int __init_or_module
at91_set_debounce(unsigned pin
, int is_on
, int div
)
320 void __iomem
*pio
= pin_to_controller(pin
);
321 unsigned mask
= pin_to_mask(pin
);
323 if (!pio
|| !has_pio3())
327 __raw_writel(mask
, pio
+ PIO_IFSCER
);
328 __raw_writel(div
& PIO_SCDR_DIV
, pio
+ PIO_SCDR
);
329 __raw_writel(mask
, pio
+ PIO_IFER
);
331 __raw_writel(mask
, pio
+ PIO_IFDR
);
335 EXPORT_SYMBOL(at91_set_debounce
);
338 * enable/disable the multi-driver; This is only valid for output and
339 * allows the output pin to run as an open collector output.
341 int __init_or_module
at91_set_multi_drive(unsigned pin
, int is_on
)
343 void __iomem
*pio
= pin_to_controller(pin
);
344 unsigned mask
= pin_to_mask(pin
);
349 __raw_writel(mask
, pio
+ (is_on
? PIO_MDER
: PIO_MDDR
));
352 EXPORT_SYMBOL(at91_set_multi_drive
);
355 * enable/disable the pull-down.
356 * If pull-up already enabled while calling the function, we disable it.
358 int __init_or_module
at91_set_pulldown(unsigned pin
, int is_on
)
360 void __iomem
*pio
= pin_to_controller(pin
);
361 unsigned mask
= pin_to_mask(pin
);
363 if (!pio
|| !has_pio3())
366 /* Disable pull-up anyway */
367 __raw_writel(mask
, pio
+ PIO_PUDR
);
368 __raw_writel(mask
, pio
+ (is_on
? PIO_PPDER
: PIO_PPDDR
));
371 EXPORT_SYMBOL(at91_set_pulldown
);
374 * disable Schmitt trigger
376 int __init_or_module
at91_disable_schmitt_trig(unsigned pin
)
378 void __iomem
*pio
= pin_to_controller(pin
);
379 unsigned mask
= pin_to_mask(pin
);
381 if (!pio
|| !has_pio3())
384 __raw_writel(__raw_readl(pio
+ PIO_SCHMITT
) | mask
, pio
+ PIO_SCHMITT
);
387 EXPORT_SYMBOL(at91_disable_schmitt_trig
);
390 * assuming the pin is muxed as a gpio output, set its value.
392 int at91_set_gpio_value(unsigned pin
, int value
)
394 void __iomem
*pio
= pin_to_controller(pin
);
395 unsigned mask
= pin_to_mask(pin
);
399 __raw_writel(mask
, pio
+ (value
? PIO_SODR
: PIO_CODR
));
402 EXPORT_SYMBOL(at91_set_gpio_value
);
406 * read the pin's value (works even if it's not muxed as a gpio).
408 int at91_get_gpio_value(unsigned pin
)
410 void __iomem
*pio
= pin_to_controller(pin
);
411 unsigned mask
= pin_to_mask(pin
);
416 pdsr
= __raw_readl(pio
+ PIO_PDSR
);
417 return (pdsr
& mask
) != 0;
419 EXPORT_SYMBOL(at91_get_gpio_value
);
421 /*--------------------------------------------------------------------------*/
425 static u32 wakeups
[MAX_GPIO_BANKS
];
426 static u32 backups
[MAX_GPIO_BANKS
];
428 static int gpio_irq_set_wake(struct irq_data
*d
, unsigned state
)
430 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
431 unsigned mask
= 1 << d
->hwirq
;
432 unsigned bank
= at91_gpio
->pioc_idx
;
434 if (unlikely(bank
>= MAX_GPIO_BANKS
))
438 wakeups
[bank
] |= mask
;
440 wakeups
[bank
] &= ~mask
;
442 irq_set_irq_wake(at91_gpio
->pioc_virq
, state
);
447 void at91_gpio_suspend(void)
451 for (i
= 0; i
< gpio_banks
; i
++) {
452 void __iomem
*pio
= gpio_chip
[i
].regbase
;
454 backups
[i
] = __raw_readl(pio
+ PIO_IMR
);
455 __raw_writel(backups
[i
], pio
+ PIO_IDR
);
456 __raw_writel(wakeups
[i
], pio
+ PIO_IER
);
459 clk_unprepare(gpio_chip
[i
].clock
);
460 clk_disable(gpio_chip
[i
].clock
);
462 #ifdef CONFIG_PM_DEBUG
463 printk(KERN_DEBUG
"GPIO-%c may wake for %08x\n", 'A'+i
, wakeups
[i
]);
469 void at91_gpio_resume(void)
473 for (i
= 0; i
< gpio_banks
; i
++) {
474 void __iomem
*pio
= gpio_chip
[i
].regbase
;
477 if (clk_prepare(gpio_chip
[i
].clock
) == 0)
478 clk_enable(gpio_chip
[i
].clock
);
481 __raw_writel(wakeups
[i
], pio
+ PIO_IDR
);
482 __raw_writel(backups
[i
], pio
+ PIO_IER
);
487 #define gpio_irq_set_wake NULL
491 /* Several AIC controller irqs are dispatched through this GPIO handler.
492 * To use any AT91_PIN_* as an externally triggered IRQ, first call
493 * at91_set_gpio_input() then maybe enable its glitch filter.
494 * Then just request_irq() with the pin ID; it works like any ARM IRQ
496 * First implementation always triggers on rising and falling edges
497 * whereas the newer PIO3 can be additionally configured to trigger on
498 * level, edge with any polarity.
500 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
501 * configuring them with at91_set_a_periph() or at91_set_b_periph().
502 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
505 static void gpio_irq_mask(struct irq_data
*d
)
507 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
508 void __iomem
*pio
= at91_gpio
->regbase
;
509 unsigned mask
= 1 << d
->hwirq
;
512 __raw_writel(mask
, pio
+ PIO_IDR
);
515 static void gpio_irq_unmask(struct irq_data
*d
)
517 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
518 void __iomem
*pio
= at91_gpio
->regbase
;
519 unsigned mask
= 1 << d
->hwirq
;
522 __raw_writel(mask
, pio
+ PIO_IER
);
525 static int gpio_irq_type(struct irq_data
*d
, unsigned type
)
529 case IRQ_TYPE_EDGE_BOTH
:
536 /* Alternate irq type for PIO3 support */
537 static int alt_gpio_irq_type(struct irq_data
*d
, unsigned type
)
539 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
540 void __iomem
*pio
= at91_gpio
->regbase
;
541 unsigned mask
= 1 << d
->hwirq
;
544 case IRQ_TYPE_EDGE_RISING
:
545 __raw_writel(mask
, pio
+ PIO_ESR
);
546 __raw_writel(mask
, pio
+ PIO_REHLSR
);
548 case IRQ_TYPE_EDGE_FALLING
:
549 __raw_writel(mask
, pio
+ PIO_ESR
);
550 __raw_writel(mask
, pio
+ PIO_FELLSR
);
552 case IRQ_TYPE_LEVEL_LOW
:
553 __raw_writel(mask
, pio
+ PIO_LSR
);
554 __raw_writel(mask
, pio
+ PIO_FELLSR
);
556 case IRQ_TYPE_LEVEL_HIGH
:
557 __raw_writel(mask
, pio
+ PIO_LSR
);
558 __raw_writel(mask
, pio
+ PIO_REHLSR
);
560 case IRQ_TYPE_EDGE_BOTH
:
562 * disable additional interrupt modes:
563 * fall back to default behavior
565 __raw_writel(mask
, pio
+ PIO_AIMDR
);
569 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d
->irq
));
573 /* enable additional interrupt modes */
574 __raw_writel(mask
, pio
+ PIO_AIMER
);
579 static struct irq_chip gpio_irqchip
= {
581 .irq_disable
= gpio_irq_mask
,
582 .irq_mask
= gpio_irq_mask
,
583 .irq_unmask
= gpio_irq_unmask
,
584 /* .irq_set_type is set dynamically */
585 .irq_set_wake
= gpio_irq_set_wake
,
588 static void gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
590 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
591 struct irq_data
*idata
= irq_desc_get_irq_data(desc
);
592 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(idata
);
593 void __iomem
*pio
= at91_gpio
->regbase
;
597 chained_irq_enter(chip
, desc
);
599 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
600 * When there none are pending, we're finished unless we need
601 * to process multiple banks (like ID_PIOCDE on sam9263).
603 isr
= __raw_readl(pio
+ PIO_ISR
) & __raw_readl(pio
+ PIO_IMR
);
605 if (!at91_gpio
->next
)
607 at91_gpio
= at91_gpio
->next
;
608 pio
= at91_gpio
->regbase
;
612 n
= find_first_bit(&isr
, BITS_PER_LONG
);
613 while (n
< BITS_PER_LONG
) {
614 generic_handle_irq(irq_find_mapping(at91_gpio
->domain
, n
));
615 n
= find_next_bit(&isr
, BITS_PER_LONG
, n
+ 1);
618 chained_irq_exit(chip
, desc
);
619 /* now it may re-trigger */
622 /*--------------------------------------------------------------------------*/
624 #ifdef CONFIG_DEBUG_FS
626 static void gpio_printf(struct seq_file
*s
, void __iomem
*pio
, unsigned mask
)
628 char *trigger
= NULL
;
629 char *polarity
= NULL
;
631 if (__raw_readl(pio
+ PIO_IMR
) & mask
) {
632 if (!has_pio3() || !(__raw_readl(pio
+ PIO_AIMMR
) & mask
)) {
636 if (__raw_readl(pio
+ PIO_ELSR
) & mask
) {
638 polarity
= __raw_readl(pio
+ PIO_FRLHSR
) & mask
?
642 polarity
= __raw_readl(pio
+ PIO_FRLHSR
) & mask
?
643 "rising" : "falling";
646 seq_printf(s
, "IRQ:%s-%s\t", trigger
, polarity
);
648 seq_printf(s
, "GPIO:%s\t\t",
649 __raw_readl(pio
+ PIO_PDSR
) & mask
? "1" : "0");
653 static int at91_gpio_show(struct seq_file
*s
, void *unused
)
658 seq_printf(s
, "Pin\t");
659 for (bank
= 0; bank
< gpio_banks
; bank
++) {
660 seq_printf(s
, "PIO%c\t\t", 'A' + bank
);
662 seq_printf(s
, "\n\n");
664 /* print pin status */
665 for (j
= 0; j
< 32; j
++) {
666 seq_printf(s
, "%i:\t", j
);
668 for (bank
= 0; bank
< gpio_banks
; bank
++) {
669 unsigned pin
= (32 * bank
) + j
;
670 void __iomem
*pio
= pin_to_controller(pin
);
671 unsigned mask
= pin_to_mask(pin
);
673 if (__raw_readl(pio
+ PIO_PSR
) & mask
)
674 gpio_printf(s
, pio
, mask
);
676 seq_printf(s
, "%c\t\t",
677 peripheral_function(pio
, mask
));
686 static int at91_gpio_open(struct inode
*inode
, struct file
*file
)
688 return single_open(file
, at91_gpio_show
, NULL
);
691 static const struct file_operations at91_gpio_operations
= {
692 .open
= at91_gpio_open
,
695 .release
= single_release
,
698 static int __init
at91_gpio_debugfs_init(void)
700 /* /sys/kernel/debug/at91_gpio */
701 (void) debugfs_create_file("at91_gpio", S_IFREG
| S_IRUGO
, NULL
, NULL
, &at91_gpio_operations
);
704 postcore_initcall(at91_gpio_debugfs_init
);
708 /*--------------------------------------------------------------------------*/
711 * This lock class tells lockdep that GPIO irqs are in a different
712 * category than their parents, so it won't report false recursion.
714 static struct lock_class_key gpio_lock_class
;
716 #if defined(CONFIG_OF)
717 static int at91_gpio_irq_map(struct irq_domain
*h
, unsigned int virq
,
720 struct at91_gpio_chip
*at91_gpio
= h
->host_data
;
722 irq_set_lockdep_class(virq
, &gpio_lock_class
);
725 * Can use the "simple" and not "edge" handler since it's
726 * shorter, and the AIC handles interrupts sanely.
728 irq_set_chip_and_handler(virq
, &gpio_irqchip
,
730 set_irq_flags(virq
, IRQF_VALID
);
731 irq_set_chip_data(virq
, at91_gpio
);
736 static struct irq_domain_ops at91_gpio_ops
= {
737 .map
= at91_gpio_irq_map
,
738 .xlate
= irq_domain_xlate_twocell
,
741 int __init
at91_gpio_of_irq_setup(struct device_node
*node
,
742 struct device_node
*parent
)
744 struct at91_gpio_chip
*prev
= NULL
;
745 int alias_idx
= of_alias_get_id(node
, "gpio");
746 struct at91_gpio_chip
*at91_gpio
= &gpio_chip
[alias_idx
];
748 /* Setup proper .irq_set_type function */
750 gpio_irqchip
.irq_set_type
= alt_gpio_irq_type
;
752 gpio_irqchip
.irq_set_type
= gpio_irq_type
;
754 /* Disable irqs of this PIO controller */
755 __raw_writel(~0, at91_gpio
->regbase
+ PIO_IDR
);
757 /* Setup irq domain */
758 at91_gpio
->domain
= irq_domain_add_linear(node
, at91_gpio
->chip
.ngpio
,
759 &at91_gpio_ops
, at91_gpio
);
760 if (!at91_gpio
->domain
)
761 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
762 at91_gpio
->pioc_idx
);
764 /* Setup chained handler */
765 if (at91_gpio
->pioc_idx
)
766 prev
= &gpio_chip
[at91_gpio
->pioc_idx
- 1];
768 /* The toplevel handler handles one bank of GPIOs, except
769 * on some SoC it can handles up to three...
770 * We only set up the handler for the first of the list.
772 if (prev
&& prev
->next
== at91_gpio
)
775 at91_gpio
->pioc_virq
= irq_create_mapping(irq_find_host(parent
),
776 at91_gpio
->pioc_hwirq
);
777 irq_set_chip_data(at91_gpio
->pioc_virq
, at91_gpio
);
778 irq_set_chained_handler(at91_gpio
->pioc_virq
, gpio_irq_handler
);
783 int __init
at91_gpio_of_irq_setup(struct device_node
*node
,
784 struct device_node
*parent
)
791 * irqdomain initialization: pile up irqdomains on top of AIC range
793 static void __init
at91_gpio_irqdomain(struct at91_gpio_chip
*at91_gpio
)
797 irq_base
= irq_alloc_descs(-1, 0, at91_gpio
->chip
.ngpio
, 0);
799 panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
800 at91_gpio
->pioc_idx
, irq_base
);
801 at91_gpio
->domain
= irq_domain_add_legacy(NULL
, at91_gpio
->chip
.ngpio
,
803 &irq_domain_simple_ops
, NULL
);
804 if (!at91_gpio
->domain
)
805 panic("at91_gpio.%d: couldn't allocate irq domain.\n",
806 at91_gpio
->pioc_idx
);
810 * Called from the processor-specific init to enable GPIO interrupt support.
812 void __init
at91_gpio_irq_setup(void)
816 struct at91_gpio_chip
*this, *prev
;
818 /* Setup proper .irq_set_type function */
820 gpio_irqchip
.irq_set_type
= alt_gpio_irq_type
;
822 gpio_irqchip
.irq_set_type
= gpio_irq_type
;
824 for (pioc
= 0, this = gpio_chip
, prev
= NULL
;
826 prev
= this, this++) {
829 __raw_writel(~0, this->regbase
+ PIO_IDR
);
831 /* setup irq domain for this GPIO controller */
832 at91_gpio_irqdomain(this);
834 for (offset
= 0; offset
< this->chip
.ngpio
; offset
++) {
835 unsigned int virq
= irq_find_mapping(this->domain
, offset
);
836 irq_set_lockdep_class(virq
, &gpio_lock_class
);
839 * Can use the "simple" and not "edge" handler since it's
840 * shorter, and the AIC handles interrupts sanely.
842 irq_set_chip_and_handler(virq
, &gpio_irqchip
,
844 set_irq_flags(virq
, IRQF_VALID
);
845 irq_set_chip_data(virq
, this);
850 /* The toplevel handler handles one bank of GPIOs, except
851 * on some SoC it can handles up to three...
852 * We only set up the handler for the first of the list.
854 if (prev
&& prev
->next
== this)
857 this->pioc_virq
= irq_create_mapping(NULL
, this->pioc_hwirq
);
858 irq_set_chip_data(this->pioc_virq
, this);
859 irq_set_chained_handler(this->pioc_virq
, gpio_irq_handler
);
861 pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr
, gpio_banks
);
864 /* gpiolib support */
865 static int at91_gpiolib_direction_input(struct gpio_chip
*chip
,
868 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
869 void __iomem
*pio
= at91_gpio
->regbase
;
870 unsigned mask
= 1 << offset
;
872 __raw_writel(mask
, pio
+ PIO_ODR
);
876 static int at91_gpiolib_direction_output(struct gpio_chip
*chip
,
877 unsigned offset
, int val
)
879 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
880 void __iomem
*pio
= at91_gpio
->regbase
;
881 unsigned mask
= 1 << offset
;
883 __raw_writel(mask
, pio
+ (val
? PIO_SODR
: PIO_CODR
));
884 __raw_writel(mask
, pio
+ PIO_OER
);
888 static int at91_gpiolib_get(struct gpio_chip
*chip
, unsigned offset
)
890 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
891 void __iomem
*pio
= at91_gpio
->regbase
;
892 unsigned mask
= 1 << offset
;
895 pdsr
= __raw_readl(pio
+ PIO_PDSR
);
896 return (pdsr
& mask
) != 0;
899 static void at91_gpiolib_set(struct gpio_chip
*chip
, unsigned offset
, int val
)
901 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
902 void __iomem
*pio
= at91_gpio
->regbase
;
903 unsigned mask
= 1 << offset
;
905 __raw_writel(mask
, pio
+ (val
? PIO_SODR
: PIO_CODR
));
908 static void at91_gpiolib_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
912 for (i
= 0; i
< chip
->ngpio
; i
++) {
913 unsigned pin
= chip
->base
+ i
;
914 void __iomem
*pio
= pin_to_controller(pin
);
915 unsigned mask
= pin_to_mask(pin
);
916 const char *gpio_label
;
918 gpio_label
= gpiochip_is_requested(chip
, i
);
920 seq_printf(s
, "[%s] GPIO%s%d: ",
921 gpio_label
, chip
->label
, i
);
922 if (__raw_readl(pio
+ PIO_PSR
) & mask
)
923 seq_printf(s
, "[gpio] %s\n",
924 at91_get_gpio_value(pin
) ?
927 seq_printf(s
, "[periph %c]\n",
928 peripheral_function(pio
, mask
));
933 static int at91_gpiolib_to_irq(struct gpio_chip
*chip
, unsigned offset
)
935 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
938 if (offset
< chip
->ngpio
)
939 virq
= irq_create_mapping(at91_gpio
->domain
, offset
);
943 dev_dbg(chip
->dev
, "%s: request IRQ for GPIO %d, return %d\n",
944 chip
->label
, offset
+ chip
->base
, virq
);
948 static int __init
at91_gpio_setup_clk(int idx
)
950 struct at91_gpio_chip
*at91_gpio
= &gpio_chip
[idx
];
952 /* retreive PIO controller's clock */
953 at91_gpio
->clock
= clk_get_sys(NULL
, at91_gpio
->chip
.label
);
954 if (IS_ERR(at91_gpio
->clock
)) {
955 pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx
);
959 if (clk_prepare(at91_gpio
->clock
))
962 /* enable PIO controller's clock */
963 if (clk_enable(at91_gpio
->clock
)) {
964 pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx
);
971 clk_unprepare(at91_gpio
->clock
);
973 clk_put(at91_gpio
->clock
);
978 #ifdef CONFIG_OF_GPIO
979 static void __init
of_at91_gpio_init_one(struct device_node
*np
)
982 struct at91_gpio_chip
*at91_gpio
;
987 alias_idx
= of_alias_get_id(np
, "gpio");
988 if (alias_idx
>= MAX_GPIO_BANKS
) {
989 pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
990 alias_idx
, MAX_GPIO_BANKS
);
994 at91_gpio
= &gpio_chip
[alias_idx
];
995 at91_gpio
->chip
.base
= alias_idx
* at91_gpio
->chip
.ngpio
;
997 at91_gpio
->regbase
= of_iomap(np
, 0);
998 if (!at91_gpio
->regbase
) {
999 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
1004 /* Get the interrupts property */
1005 if (of_property_read_u32(np
, "interrupts", &at91_gpio
->pioc_hwirq
)) {
1006 pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
1011 /* Get capabilities from compatibility property */
1012 if (of_device_is_compatible(np
, "atmel,at91sam9x5-gpio"))
1013 at91_gpio_caps
|= AT91_GPIO_CAP_PIO3
;
1016 if (at91_gpio_setup_clk(alias_idx
))
1019 at91_gpio
->chip
.of_node
= np
;
1020 gpio_banks
= max(gpio_banks
, alias_idx
+ 1);
1021 at91_gpio
->pioc_idx
= alias_idx
;
1025 iounmap(at91_gpio
->regbase
);
1028 static int __init
of_at91_gpio_init(void)
1030 struct device_node
*np
= NULL
;
1033 * This isn't ideal, but it gets things hooked up until this
1034 * driver is converted into a platform_device
1036 for_each_compatible_node(np
, NULL
, "atmel,at91rm9200-gpio")
1037 of_at91_gpio_init_one(np
);
1039 return gpio_banks
> 0 ? 0 : -EINVAL
;
1042 static int __init
of_at91_gpio_init(void)
1048 static void __init
at91_gpio_init_one(int idx
, u32 regbase
, int pioc_hwirq
)
1050 struct at91_gpio_chip
*at91_gpio
= &gpio_chip
[idx
];
1052 at91_gpio
->chip
.base
= idx
* at91_gpio
->chip
.ngpio
;
1053 at91_gpio
->pioc_hwirq
= pioc_hwirq
;
1054 at91_gpio
->pioc_idx
= idx
;
1056 at91_gpio
->regbase
= ioremap(regbase
, 512);
1057 if (!at91_gpio
->regbase
) {
1058 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx
);
1062 if (at91_gpio_setup_clk(idx
))
1065 gpio_banks
= max(gpio_banks
, idx
+ 1);
1069 iounmap(at91_gpio
->regbase
);
1073 * Called from the processor-specific init to enable GPIO pin support.
1075 void __init
at91_gpio_init(struct at91_gpio_bank
*data
, int nr_banks
)
1078 struct at91_gpio_chip
*at91_gpio
, *last
= NULL
;
1080 BUG_ON(nr_banks
> MAX_GPIO_BANKS
);
1082 if (of_at91_gpio_init() < 0) {
1083 /* No GPIO controller found in device tree */
1084 for (i
= 0; i
< nr_banks
; i
++)
1085 at91_gpio_init_one(i
, data
[i
].regbase
, data
[i
].id
);
1088 for (i
= 0; i
< gpio_banks
; i
++) {
1089 at91_gpio
= &gpio_chip
[i
];
1092 * GPIO controller are grouped on some SoC:
1093 * PIOC, PIOD and PIOE can share the same IRQ line
1095 if (last
&& last
->pioc_hwirq
== at91_gpio
->pioc_hwirq
)
1096 last
->next
= at91_gpio
;
1099 gpiochip_add(&at91_gpio
->chip
);