arch/i386/kernel/cpu/cpufreq/speedstep-lib.c

   1 /*
   2  * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
   3  *
   4  *  Licensed under the terms of the GNU GPL License version 2.
   5  *
   6  *  Library for common functions for Intel SpeedStep v.1 and v.2 support
   7  *
   8  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/cpufreq.h>
  16 #include <linux/pci.h>
  17 #include <linux/slab.h>
  18
  19 #include <asm/msr.h>
  20 #include "speedstep-lib.h"
  21
  22 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-lib", msg)
  23
  24 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
  25 static int relaxed_check = 0;
  26 #else
  27 #define relaxed_check 0
  28 #endif
  29
  30 /*********************************************************************
  31  *                   GET PROCESSOR CORE SPEED IN KHZ                 *
  32  *********************************************************************/
  33
  34 static unsigned int pentium3_get_frequency (unsigned int processor)
  35 {
  36         /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
  37         struct {
  38                 unsigned int ratio;     /* Frequency Multiplier (x10) */
  39                 u8 bitmap;              /* power on configuration bits
  40                                         [27, 25:22] (in MSR 0x2a) */
  41         } msr_decode_mult [] = {
  42                 { 30, 0x01 },
  43                 { 35, 0x05 },
  44                 { 40, 0x02 },
  45                 { 45, 0x06 },
  46                 { 50, 0x00 },
  47                 { 55, 0x04 },
  48                 { 60, 0x0b },
  49                 { 65, 0x0f },
  50                 { 70, 0x09 },
  51                 { 75, 0x0d },
  52                 { 80, 0x0a },
  53                 { 85, 0x26 },
  54                 { 90, 0x20 },
  55                 { 100, 0x2b },
  56                 { 0, 0xff }     /* error or unknown value */
  57         };
  58
  59         /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
  60         struct {
  61                 unsigned int value;     /* Front Side Bus speed in MHz */
  62                 u8 bitmap;              /* power on configuration bits [18: 19]
  63                                         (in MSR 0x2a) */
  64         } msr_decode_fsb [] = {
  65                 {  66, 0x0 },
  66                 { 100, 0x2 },
  67                 { 133, 0x1 },
  68                 {   0, 0xff}
  69         };
  70
  71         u32 msr_lo, msr_tmp;
  72         int i = 0, j = 0;
  73
  74         /* read MSR 0x2a - we only need the low 32 bits */
  75         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
  76         dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
  77         msr_tmp = msr_lo;
  78
  79         /* decode the FSB */
  80         msr_tmp &= 0x00c0000;
  81         msr_tmp >>= 18;
  82         while (msr_tmp != msr_decode_fsb[i].bitmap) {
  83                 if (msr_decode_fsb[i].bitmap == 0xff)
  84                         return 0;
  85                 i++;
  86         }
  87
  88         /* decode the multiplier */
  89         if (processor == SPEEDSTEP_PROCESSOR_PIII_C_EARLY) {
  90                 dprintk("workaround for early PIIIs\n");
  91                 msr_lo &= 0x03c00000;
  92         } else
  93                 msr_lo &= 0x0bc00000;
  94         msr_lo >>= 22;
  95         while (msr_lo != msr_decode_mult[j].bitmap) {
  96                 if (msr_decode_mult[j].bitmap == 0xff)
  97                         return 0;
  98                 j++;
  99         }
 100
 101         dprintk("speed is %u\n", (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
 102
 103         return (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100);
 104 }
 105
 106
 107 static unsigned int pentiumM_get_frequency(void)
 108 {
 109         u32 msr_lo, msr_tmp;
 110
 111         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
 112         dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
 113
 114         /* see table B-2 of 24547212.pdf */
 115         if (msr_lo & 0x00040000) {
 116                 printk(KERN_DEBUG "speedstep-lib: PM - invalid FSB: 0x%x 0x%x\n", msr_lo, msr_tmp);
 117                 return 0;
 118         }
 119
 120         msr_tmp = (msr_lo >> 22) & 0x1f;
 121         dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * 100 * 1000));
 122
 123         return (msr_tmp * 100 * 1000);
 124 }
 125
 126 #ifdef CONFIG_X86_32
 127 static unsigned int pentium_core_get_frequency(void)
 128 {
 129         u32 fsb = 0;
 130         u32 msr_lo, msr_tmp;
 131
 132         rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
 133         /* see table B-2 of 24547212.pdf */
 134         switch (msr_lo & 0x07) {
 135         case 5:
 136                 fsb = 400;
 137                 break;
 138         case 1:
 139                 fsb = 533;
 140                 break;
 141         case 3:
 142                 fsb = 667;
 143                 break;
 144         default:
 145                 printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value");
 146         }
 147
 148         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
 149         dprintk("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
 150
 151         msr_tmp = (msr_lo >> 22) & 0x1f;
 152         dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * fsb * 1000));
 153
 154         return (msr_tmp * fsb * 1000);
 155 }
 156 #endif
 157
 158 static unsigned int pentium4_get_frequency(void)
 159 {
 160         struct cpuinfo_x86 *c = &boot_cpu_data;
 161         u32 msr_lo, msr_hi, mult;
 162         unsigned int fsb = 0;
 163
 164         rdmsr(0x2c, msr_lo, msr_hi);
 165
 166         dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
 167
 168         /* decode the FSB: see IA-32 Intel (C) Architecture Software
 169          * Developer's Manual, Volume 3: System Prgramming Guide,
 170          * revision #12 in Table B-1: MSRs in the Pentium 4 and
 171          * Intel Xeon Processors, on page B-4 and B-5.
 172          */
 173         if (c->x86_model < 2)
 174                 fsb = 100 * 1000;
 175         else {
 176                 u8 fsb_code = (msr_lo >> 16) & 0x7;
 177                 switch (fsb_code) {
 178                 case 0:
 179                         fsb = 100 * 1000;
 180                         break;
 181                 case 1:
 182                         fsb = 13333 * 10;
 183                         break;
 184                 case 2:
 185                         fsb = 200 * 1000;
 186                         break;
 187                 }
 188         }
 189
 190         if (!fsb)
 191                 printk(KERN_DEBUG "speedstep-lib: couldn't detect FSB speed. Please send an e-mail to <linux@brodo.de>\n");
 192
 193         /* Multiplier. */
 194         if (c->x86_model < 2)
 195                 mult = msr_lo >> 27;
 196         else
 197                 mult = msr_lo >> 24;
 198
 199         dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", fsb, mult, (fsb * mult));
 200
 201         return (fsb * mult);
 202 }
 203
 204
 205 unsigned int speedstep_get_processor_frequency(unsigned int processor)
 206 {
 207         switch (processor) {
 208 #ifdef CONFIG_X86_32
 209         case SPEEDSTEP_PROCESSOR_PCORE:
 210                 return pentium_core_get_frequency();
 211 #endif
 212         case SPEEDSTEP_PROCESSOR_PM:
 213                 return pentiumM_get_frequency();
 214         case SPEEDSTEP_PROCESSOR_P4D:
 215         case SPEEDSTEP_PROCESSOR_P4M:
 216                 return pentium4_get_frequency();
 217         case SPEEDSTEP_PROCESSOR_PIII_T:
 218         case SPEEDSTEP_PROCESSOR_PIII_C:
 219         case SPEEDSTEP_PROCESSOR_PIII_C_EARLY:
 220                 return pentium3_get_frequency(processor);
 221         default:
 222                 return 0;
 223         };
 224         return 0;
 225 }
 226 EXPORT_SYMBOL_GPL(speedstep_get_processor_frequency);
 227
 228
 229 /*********************************************************************
 230  *                 DETECT SPEEDSTEP-CAPABLE PROCESSOR                *
 231  *********************************************************************/
 232
 233 unsigned int speedstep_detect_processor (void)
 234 {
 235         struct cpuinfo_x86 *c = cpu_data;
 236         u32 ebx, msr_lo, msr_hi;
 237
 238         dprintk("x86: %x, model: %x\n", c->x86, c->x86_model);
 239
 240         if ((c->x86_vendor != X86_VENDOR_INTEL) ||
 241             ((c->x86 != 6) && (c->x86 != 0xF)))
 242                 return 0;
 243
 244         if (c->x86 == 0xF) {
 245                 /* Intel Mobile Pentium 4-M
 246                  * or Intel Mobile Pentium 4 with 533 MHz FSB */
 247                 if (c->x86_model != 2)
 248                         return 0;
 249
 250                 ebx = cpuid_ebx(0x00000001);
 251                 ebx &= 0x000000FF;
 252
 253                 dprintk("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
 254
 255                 switch (c->x86_mask) {
 256                 case 4:
 257                         /*
 258                          * B-stepping [M-P4-M]
 259                          * sample has ebx = 0x0f, production has 0x0e.
 260                          */
 261                         if ((ebx == 0x0e) || (ebx == 0x0f))
 262                                 return SPEEDSTEP_PROCESSOR_P4M;
 263                         break;
 264                 case 7:
 265                         /*
 266                          * C-stepping [M-P4-M]
 267                          * needs to have ebx=0x0e, else it's a celeron:
 268                          * cf. 25130917.pdf / page 7, footnote 5 even
 269                          * though 25072120.pdf / page 7 doesn't say
 270                          * samples are only of B-stepping...
 271                          */
 272                         if (ebx == 0x0e)
 273                                 return SPEEDSTEP_PROCESSOR_P4M;
 274                         break;
 275                 case 9:
 276                         /*
 277                          * D-stepping [M-P4-M or M-P4/533]
 278                          *
 279                          * this is totally strange: CPUID 0x0F29 is
 280                          * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
 281                          * The latter need to be sorted out as they don't
 282                          * support speedstep.
 283                          * Celerons with CPUID 0x0F29 may have either
 284                          * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
 285                          * specific.
 286                          * M-P4-Ms may have either ebx=0xe or 0xf [see above]
 287                          * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
 288                          * also, M-P4M HTs have ebx=0x8, too
 289                          * For now, they are distinguished by the model_id string
 290                          */
 291                         if ((ebx == 0x0e) || (strstr(c->x86_model_id,"Mobile Intel(R) Pentium(R) 4") != NULL))
 292                                 return SPEEDSTEP_PROCESSOR_P4M;
 293                         break;
 294                 default:
 295                         break;
 296                 }
 297                 return 0;
 298         }
 299
 300         switch (c->x86_model) {
 301         case 0x0B: /* Intel PIII [Tualatin] */
 302                 /* cpuid_ebx(1) is 0x04 for desktop PIII, 0x06 for mobile PIII-M */
 303                 ebx = cpuid_ebx(0x00000001);
 304                 dprintk("ebx is %x\n", ebx);
 305
 306                 ebx &= 0x000000FF;
 307
 308                 if (ebx != 0x06)
 309                         return 0;
 310
 311                 /* So far all PIII-M processors support SpeedStep. See
 312                  * Intel's 24540640.pdf of June 2003
 313                  */
 314                 return SPEEDSTEP_PROCESSOR_PIII_T;
 315
 316         case 0x08: /* Intel PIII [Coppermine] */
 317
 318                 /* all mobile PIII Coppermines have FSB 100 MHz
 319                  * ==> sort out a few desktop PIIIs. */
 320                 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
 321                 dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", msr_lo, msr_hi);
 322                 msr_lo &= 0x00c0000;
 323                 if (msr_lo != 0x0080000)
 324                         return 0;
 325
 326                 /*
 327                  * If the processor is a mobile version,
 328                  * platform ID has bit 50 set
 329                  * it has SpeedStep technology if either
 330                  * bit 56 or 57 is set
 331                  */
 332                 rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
 333                 dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", msr_lo, msr_hi);
 334                 if ((msr_hi & (1<<18)) && (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
 335                         if (c->x86_mask == 0x01) {
 336                                 dprintk("early PIII version\n");
 337                                 return SPEEDSTEP_PROCESSOR_PIII_C_EARLY;
 338                         } else
 339                                 return SPEEDSTEP_PROCESSOR_PIII_C;
 340                 }
 341
 342         default:
 343                 return 0;
 344         }
 345 }
 346 EXPORT_SYMBOL_GPL(speedstep_detect_processor);
 347
 348
 349 /*********************************************************************
 350  *                     DETECT SPEEDSTEP SPEEDS                       *
 351  *********************************************************************/
 352
 353 unsigned int speedstep_get_freqs(unsigned int processor,
 354                                   unsigned int *low_speed,
 355                                   unsigned int *high_speed,
 356                                   unsigned int *transition_latency,
 357                                   void (*set_state) (unsigned int state))
 358 {
 359         unsigned int prev_speed;
 360         unsigned int ret = 0;
 361         unsigned long flags;
 362         struct timeval tv1, tv2;
 363
 364         if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
 365                 return -EINVAL;
 366
 367         dprintk("trying to determine both speeds\n");
 368
 369         /* get current speed */
 370         prev_speed = speedstep_get_processor_frequency(processor);
 371         if (!prev_speed)
 372                 return -EIO;
 373
 374         dprintk("previous speed is %u\n", prev_speed);
 375
 376         local_irq_save(flags);
 377
 378         /* switch to low state */
 379         set_state(SPEEDSTEP_LOW);
 380         *low_speed = speedstep_get_processor_frequency(processor);
 381         if (!*low_speed) {
 382                 ret = -EIO;
 383                 goto out;
 384         }
 385
 386         dprintk("low speed is %u\n", *low_speed);
 387
 388         /* start latency measurement */
 389         if (transition_latency)
 390                 do_gettimeofday(&tv1);
 391
 392         /* switch to high state */
 393         set_state(SPEEDSTEP_HIGH);
 394
 395         /* end latency measurement */
 396         if (transition_latency)
 397                 do_gettimeofday(&tv2);
 398
 399         *high_speed = speedstep_get_processor_frequency(processor);
 400         if (!*high_speed) {
 401                 ret = -EIO;
 402                 goto out;
 403         }
 404
 405         dprintk("high speed is %u\n", *high_speed);
 406
 407         if (*low_speed == *high_speed) {
 408                 ret = -ENODEV;
 409                 goto out;
 410         }
 411
 412         /* switch to previous state, if necessary */
 413         if (*high_speed != prev_speed)
 414                 set_state(SPEEDSTEP_LOW);
 415
 416         if (transition_latency) {
 417                 *transition_latency = (tv2.tv_sec - tv1.tv_sec) * USEC_PER_SEC +
 418                         tv2.tv_usec - tv1.tv_usec;
 419                 dprintk("transition latency is %u uSec\n", *transition_latency);
 420
 421                 /* convert uSec to nSec and add 20% for safety reasons */
 422                 *transition_latency *= 1200;
 423
 424                 /* check if the latency measurement is too high or too low
 425                  * and set it to a safe value (500uSec) in that case
 426                  */
 427                 if (*transition_latency > 10000000 || *transition_latency < 50000) {
 428                         printk (KERN_WARNING "speedstep: frequency transition measured seems out of "
 429                                         "range (%u nSec), falling back to a safe one of %u nSec.\n",
 430                                         *transition_latency, 500000);
 431                         *transition_latency = 500000;
 432                 }
 433         }
 434
 435 out:
 436         local_irq_restore(flags);
 437         return (ret);
 438 }
 439 EXPORT_SYMBOL_GPL(speedstep_get_freqs);
 440
 441 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
 442 module_param(relaxed_check, int, 0444);
 443 MODULE_PARM_DESC(relaxed_check, "Don't do all checks for speedstep capability.");
 444 #endif
 445
 446 MODULE_AUTHOR ("Dominik Brodowski <linux@brodo.de>");
 447 MODULE_DESCRIPTION ("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
 448 MODULE_LICENSE ("GPL");