arch/arm/mach-ep93xx/clock.c

   1 /*
   2  * arch/arm/mach-ep93xx/clock.c
   3  * Clock control for Cirrus EP93xx chips.
   4  *
   5  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or (at
  10  * your option) any later version.
  11  */
  12
  13 #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/clk.h>
  17 #include <linux/err.h>
  18 #include <linux/module.h>
  19 #include <linux/string.h>
  20 #include <linux/io.h>
  21 #include <linux/spinlock.h>
  22
  23 #include <mach/hardware.h>
  24
  25 #include <asm/clkdev.h>
  26 #include <asm/div64.h>
  27
  28
  29 struct clk {
  30         struct clk      *parent;
  31         unsigned long   rate;
  32         int             users;
  33         int             sw_locked;
  34         void __iomem    *enable_reg;
  35         u32             enable_mask;
  36
  37         unsigned long   (*get_rate)(struct clk *clk);
  38         int             (*set_rate)(struct clk *clk, unsigned long rate);
  39 };
  40
  41
  42 static unsigned long get_uart_rate(struct clk *clk);
  43
  44 static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
  45 static int set_div_rate(struct clk *clk, unsigned long rate);
  46 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
  47 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
  48
  49 static struct clk clk_xtali = {
  50         .rate           = EP93XX_EXT_CLK_RATE,
  51 };
  52 static struct clk clk_uart1 = {
  53         .parent         = &clk_xtali,
  54         .sw_locked      = 1,
  55         .enable_reg     = EP93XX_SYSCON_DEVCFG,
  56         .enable_mask    = EP93XX_SYSCON_DEVCFG_U1EN,
  57         .get_rate       = get_uart_rate,
  58 };
  59 static struct clk clk_uart2 = {
  60         .parent         = &clk_xtali,
  61         .sw_locked      = 1,
  62         .enable_reg     = EP93XX_SYSCON_DEVCFG,
  63         .enable_mask    = EP93XX_SYSCON_DEVCFG_U2EN,
  64         .get_rate       = get_uart_rate,
  65 };
  66 static struct clk clk_uart3 = {
  67         .parent         = &clk_xtali,
  68         .sw_locked      = 1,
  69         .enable_reg     = EP93XX_SYSCON_DEVCFG,
  70         .enable_mask    = EP93XX_SYSCON_DEVCFG_U3EN,
  71         .get_rate       = get_uart_rate,
  72 };
  73 static struct clk clk_pll1 = {
  74         .parent         = &clk_xtali,
  75 };
  76 static struct clk clk_f = {
  77         .parent         = &clk_pll1,
  78 };
  79 static struct clk clk_h = {
  80         .parent         = &clk_pll1,
  81 };
  82 static struct clk clk_p = {
  83         .parent         = &clk_pll1,
  84 };
  85 static struct clk clk_pll2 = {
  86         .parent         = &clk_xtali,
  87 };
  88 static struct clk clk_usb_host = {
  89         .parent         = &clk_pll2,
  90         .enable_reg     = EP93XX_SYSCON_PWRCNT,
  91         .enable_mask    = EP93XX_SYSCON_PWRCNT_USH_EN,
  92 };
  93 static struct clk clk_keypad = {
  94         .parent         = &clk_xtali,
  95         .sw_locked      = 1,
  96         .enable_reg     = EP93XX_SYSCON_KEYTCHCLKDIV,
  97         .enable_mask    = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
  98         .set_rate       = set_keytchclk_rate,
  99 };
 100 static struct clk clk_spi = {
 101         .parent         = &clk_xtali,
 102         .rate           = EP93XX_EXT_CLK_RATE,
 103 };
 104 static struct clk clk_pwm = {
 105         .parent         = &clk_xtali,
 106         .rate           = EP93XX_EXT_CLK_RATE,
 107 };
 108
 109 static struct clk clk_video = {
 110         .sw_locked      = 1,
 111         .enable_reg     = EP93XX_SYSCON_VIDCLKDIV,
 112         .enable_mask    = EP93XX_SYSCON_CLKDIV_ENABLE,
 113         .set_rate       = set_div_rate,
 114 };
 115
 116 static struct clk clk_i2s_mclk = {
 117         .sw_locked      = 1,
 118         .enable_reg     = EP93XX_SYSCON_I2SCLKDIV,
 119         .enable_mask    = EP93XX_SYSCON_CLKDIV_ENABLE,
 120         .set_rate       = set_div_rate,
 121 };
 122
 123 static struct clk clk_i2s_sclk = {
 124         .sw_locked      = 1,
 125         .parent         = &clk_i2s_mclk,
 126         .enable_reg     = EP93XX_SYSCON_I2SCLKDIV,
 127         .enable_mask    = EP93XX_SYSCON_I2SCLKDIV_SENA,
 128         .set_rate       = set_i2s_sclk_rate,
 129 };
 130
 131 static struct clk clk_i2s_lrclk = {
 132         .sw_locked      = 1,
 133         .parent         = &clk_i2s_sclk,
 134         .enable_reg     = EP93XX_SYSCON_I2SCLKDIV,
 135         .enable_mask    = EP93XX_SYSCON_I2SCLKDIV_SENA,
 136         .set_rate       = set_i2s_lrclk_rate,
 137 };
 138
 139 /* DMA Clocks */
 140 static struct clk clk_m2p0 = {
 141         .parent         = &clk_h,
 142         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 143         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
 144 };
 145 static struct clk clk_m2p1 = {
 146         .parent         = &clk_h,
 147         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 148         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
 149 };
 150 static struct clk clk_m2p2 = {
 151         .parent         = &clk_h,
 152         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 153         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
 154 };
 155 static struct clk clk_m2p3 = {
 156         .parent         = &clk_h,
 157         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 158         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
 159 };
 160 static struct clk clk_m2p4 = {
 161         .parent         = &clk_h,
 162         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 163         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
 164 };
 165 static struct clk clk_m2p5 = {
 166         .parent         = &clk_h,
 167         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 168         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
 169 };
 170 static struct clk clk_m2p6 = {
 171         .parent         = &clk_h,
 172         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 173         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
 174 };
 175 static struct clk clk_m2p7 = {
 176         .parent         = &clk_h,
 177         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 178         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
 179 };
 180 static struct clk clk_m2p8 = {
 181         .parent         = &clk_h,
 182         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 183         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
 184 };
 185 static struct clk clk_m2p9 = {
 186         .parent         = &clk_h,
 187         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 188         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
 189 };
 190 static struct clk clk_m2m0 = {
 191         .parent         = &clk_h,
 192         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 193         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
 194 };
 195 static struct clk clk_m2m1 = {
 196         .parent         = &clk_h,
 197         .enable_reg     = EP93XX_SYSCON_PWRCNT,
 198         .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
 199 };
 200
 201 #define INIT_CK(dev,con,ck)                                     \
 202         { .dev_id = dev, .con_id = con, .clk = ck }
 203
 204 static struct clk_lookup clocks[] = {
 205         INIT_CK(NULL,                   "xtali",        &clk_xtali),
 206         INIT_CK("apb:uart1",            NULL,           &clk_uart1),
 207         INIT_CK("apb:uart2",            NULL,           &clk_uart2),
 208         INIT_CK("apb:uart3",            NULL,           &clk_uart3),
 209         INIT_CK(NULL,                   "pll1",         &clk_pll1),
 210         INIT_CK(NULL,                   "fclk",         &clk_f),
 211         INIT_CK(NULL,                   "hclk",         &clk_h),
 212         INIT_CK(NULL,                   "apb_pclk",     &clk_p),
 213         INIT_CK(NULL,                   "pll2",         &clk_pll2),
 214         INIT_CK("ep93xx-ohci",          NULL,           &clk_usb_host),
 215         INIT_CK("ep93xx-keypad",        NULL,           &clk_keypad),
 216         INIT_CK("ep93xx-fb",            NULL,           &clk_video),
 217         INIT_CK("ep93xx-spi.0",         NULL,           &clk_spi),
 218         INIT_CK("ep93xx-i2s",           "mclk",         &clk_i2s_mclk),
 219         INIT_CK("ep93xx-i2s",           "sclk",         &clk_i2s_sclk),
 220         INIT_CK("ep93xx-i2s",           "lrclk",        &clk_i2s_lrclk),
 221         INIT_CK(NULL,                   "pwm_clk",      &clk_pwm),
 222         INIT_CK(NULL,                   "m2p0",         &clk_m2p0),
 223         INIT_CK(NULL,                   "m2p1",         &clk_m2p1),
 224         INIT_CK(NULL,                   "m2p2",         &clk_m2p2),
 225         INIT_CK(NULL,                   "m2p3",         &clk_m2p3),
 226         INIT_CK(NULL,                   "m2p4",         &clk_m2p4),
 227         INIT_CK(NULL,                   "m2p5",         &clk_m2p5),
 228         INIT_CK(NULL,                   "m2p6",         &clk_m2p6),
 229         INIT_CK(NULL,                   "m2p7",         &clk_m2p7),
 230         INIT_CK(NULL,                   "m2p8",         &clk_m2p8),
 231         INIT_CK(NULL,                   "m2p9",         &clk_m2p9),
 232         INIT_CK(NULL,                   "m2m0",         &clk_m2m0),
 233         INIT_CK(NULL,                   "m2m1",         &clk_m2m1),
 234 };
 235
 236 static DEFINE_SPINLOCK(clk_lock);
 237
 238 static void __clk_enable(struct clk *clk)
 239 {
 240         if (!clk->users++) {
 241                 if (clk->parent)
 242                         __clk_enable(clk->parent);
 243
 244                 if (clk->enable_reg) {
 245                         u32 v;
 246
 247                         v = __raw_readl(clk->enable_reg);
 248                         v |= clk->enable_mask;
 249                         if (clk->sw_locked)
 250                                 ep93xx_syscon_swlocked_write(v, clk->enable_reg);
 251                         else
 252                                 __raw_writel(v, clk->enable_reg);
 253                 }
 254         }
 255 }
 256
 257 int clk_enable(struct clk *clk)
 258 {
 259         unsigned long flags;
 260
 261         if (!clk)
 262                 return -EINVAL;
 263
 264         spin_lock_irqsave(&clk_lock, flags);
 265         __clk_enable(clk);
 266         spin_unlock_irqrestore(&clk_lock, flags);
 267
 268         return 0;
 269 }
 270 EXPORT_SYMBOL(clk_enable);
 271
 272 static void __clk_disable(struct clk *clk)
 273 {
 274         if (!--clk->users) {
 275                 if (clk->enable_reg) {
 276                         u32 v;
 277
 278                         v = __raw_readl(clk->enable_reg);
 279                         v &= ~clk->enable_mask;
 280                         if (clk->sw_locked)
 281                                 ep93xx_syscon_swlocked_write(v, clk->enable_reg);
 282                         else
 283                                 __raw_writel(v, clk->enable_reg);
 284                 }
 285
 286                 if (clk->parent)
 287                         __clk_disable(clk->parent);
 288         }
 289 }
 290
 291 void clk_disable(struct clk *clk)
 292 {
 293         unsigned long flags;
 294
 295         if (!clk)
 296                 return;
 297
 298         spin_lock_irqsave(&clk_lock, flags);
 299         __clk_disable(clk);
 300         spin_unlock_irqrestore(&clk_lock, flags);
 301 }
 302 EXPORT_SYMBOL(clk_disable);
 303
 304 static unsigned long get_uart_rate(struct clk *clk)
 305 {
 306         unsigned long rate = clk_get_rate(clk->parent);
 307         u32 value;
 308
 309         value = __raw_readl(EP93XX_SYSCON_PWRCNT);
 310         if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
 311                 return rate;
 312         else
 313                 return rate / 2;
 314 }
 315
 316 unsigned long clk_get_rate(struct clk *clk)
 317 {
 318         if (clk->get_rate)
 319                 return clk->get_rate(clk);
 320
 321         return clk->rate;
 322 }
 323 EXPORT_SYMBOL(clk_get_rate);
 324
 325 static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
 326 {
 327         u32 val;
 328         u32 div_bit;
 329
 330         val = __raw_readl(clk->enable_reg);
 331
 332         /*
 333          * The Key Matrix and ADC clocks are configured using the same
 334          * System Controller register.  The clock used will be either
 335          * 1/4 or 1/16 the external clock rate depending on the
 336          * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
 337          * bit being set or cleared.
 338          */
 339         div_bit = clk->enable_mask >> 15;
 340
 341         if (rate == EP93XX_KEYTCHCLK_DIV4)
 342                 val |= div_bit;
 343         else if (rate == EP93XX_KEYTCHCLK_DIV16)
 344                 val &= ~div_bit;
 345         else
 346                 return -EINVAL;
 347
 348         ep93xx_syscon_swlocked_write(val, clk->enable_reg);
 349         clk->rate = rate;
 350         return 0;
 351 }
 352
 353 static int calc_clk_div(struct clk *clk, unsigned long rate,
 354                         int *psel, int *esel, int *pdiv, int *div)
 355 {
 356         struct clk *mclk;
 357         unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
 358         int i, found = 0, __div = 0, __pdiv = 0;
 359
 360         /* Don't exceed the maximum rate */
 361         max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4);
 362         rate = min(rate, max_rate);
 363
 364         /*
 365          * Try the two pll's and the external clock
 366          * Because the valid predividers are 2, 2.5 and 3, we multiply
 367          * all the clocks by 2 to avoid floating point math.
 368          *
 369          * This is based on the algorithm in the ep93xx raster guide:
 370          * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
 371          *
 372          */
 373         for (i = 0; i < 3; i++) {
 374                 if (i == 0)
 375                         mclk = &clk_xtali;
 376                 else if (i == 1)
 377                         mclk = &clk_pll1;
 378                 else
 379                         mclk = &clk_pll2;
 380                 mclk_rate = mclk->rate * 2;
 381
 382                 /* Try each predivider value */
 383                 for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
 384                         __div = mclk_rate / (rate * __pdiv);
 385                         if (__div < 2 || __div > 127)
 386                                 continue;
 387
 388                         actual_rate = mclk_rate / (__pdiv * __div);
 389
 390                         if (!found || abs(actual_rate - rate) < rate_err) {
 391                                 *pdiv = __pdiv - 3;
 392                                 *div = __div;
 393                                 *psel = (i == 2);
 394                                 *esel = (i != 0);
 395                                 clk->parent = mclk;
 396                                 clk->rate = actual_rate;
 397                                 rate_err = abs(actual_rate - rate);
 398                                 found = 1;
 399                         }
 400                 }
 401         }
 402
 403         if (!found)
 404                 return -EINVAL;
 405
 406         return 0;
 407 }
 408
 409 static int set_div_rate(struct clk *clk, unsigned long rate)
 410 {
 411         int err, psel = 0, esel = 0, pdiv = 0, div = 0;
 412         u32 val;
 413
 414         err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
 415         if (err)
 416                 return err;
 417
 418         /* Clear the esel, psel, pdiv and div bits */
 419         val = __raw_readl(clk->enable_reg);
 420         val &= ~0x7fff;
 421
 422         /* Set the new esel, psel, pdiv and div bits for the new clock rate */
 423         val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) |
 424                 (psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) |
 425                 (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div;
 426         ep93xx_syscon_swlocked_write(val, clk->enable_reg);
 427         return 0;
 428 }
 429
 430 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate)
 431 {
 432         unsigned val = __raw_readl(clk->enable_reg);
 433
 434         if (rate == clk_i2s_mclk.rate / 2)
 435                 ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV,
 436                                              clk->enable_reg);
 437         else if (rate == clk_i2s_mclk.rate / 4)
 438                 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV,
 439                                              clk->enable_reg);
 440         else
 441                 return -EINVAL;
 442
 443         clk_i2s_sclk.rate = rate;
 444         return 0;
 445 }
 446
 447 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate)
 448 {
 449         unsigned val = __raw_readl(clk->enable_reg) &
 450                 ~EP93XX_I2SCLKDIV_LRDIV_MASK;
 451
 452         if (rate == clk_i2s_sclk.rate / 32)
 453                 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32,
 454                                              clk->enable_reg);
 455         else if (rate == clk_i2s_sclk.rate / 64)
 456                 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64,
 457                                              clk->enable_reg);
 458         else if (rate == clk_i2s_sclk.rate / 128)
 459                 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128,
 460                                              clk->enable_reg);
 461         else
 462                 return -EINVAL;
 463
 464         clk_i2s_lrclk.rate = rate;
 465         return 0;
 466 }
 467
 468 int clk_set_rate(struct clk *clk, unsigned long rate)
 469 {
 470         if (clk->set_rate)
 471                 return clk->set_rate(clk, rate);
 472
 473         return -EINVAL;
 474 }
 475 EXPORT_SYMBOL(clk_set_rate);
 476
 477
 478 static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
 479 static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
 480 static char pclk_divisors[] = { 1, 2, 4, 8 };
 481
 482 /*
 483  * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
 484  */
 485 static unsigned long calc_pll_rate(u32 config_word)
 486 {
 487         unsigned long long rate;
 488         int i;
 489
 490         rate = clk_xtali.rate;
 491         rate *= ((config_word >> 11) & 0x1f) + 1;               /* X1FBD */
 492         rate *= ((config_word >> 5) & 0x3f) + 1;                /* X2FBD */
 493         do_div(rate, (config_word & 0x1f) + 1);                 /* X2IPD */
 494         for (i = 0; i < ((config_word >> 16) & 3); i++)         /* PS */
 495                 rate >>= 1;
 496
 497         return (unsigned long)rate;
 498 }
 499
 500 static void __init ep93xx_dma_clock_init(void)
 501 {
 502         clk_m2p0.rate = clk_h.rate;
 503         clk_m2p1.rate = clk_h.rate;
 504         clk_m2p2.rate = clk_h.rate;
 505         clk_m2p3.rate = clk_h.rate;
 506         clk_m2p4.rate = clk_h.rate;
 507         clk_m2p5.rate = clk_h.rate;
 508         clk_m2p6.rate = clk_h.rate;
 509         clk_m2p7.rate = clk_h.rate;
 510         clk_m2p8.rate = clk_h.rate;
 511         clk_m2p9.rate = clk_h.rate;
 512         clk_m2m0.rate = clk_h.rate;
 513         clk_m2m1.rate = clk_h.rate;
 514 }
 515
 516 static int __init ep93xx_clock_init(void)
 517 {
 518         u32 value;
 519
 520         /* Determine the bootloader configured pll1 rate */
 521         value = __raw_readl(EP93XX_SYSCON_CLKSET1);
 522         if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
 523                 clk_pll1.rate = clk_xtali.rate;
 524         else
 525                 clk_pll1.rate = calc_pll_rate(value);
 526
 527         /* Initialize the pll1 derived clocks */
 528         clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
 529         clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
 530         clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
 531         ep93xx_dma_clock_init();
 532
 533         /* Determine the bootloader configured pll2 rate */
 534         value = __raw_readl(EP93XX_SYSCON_CLKSET2);
 535         if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
 536                 clk_pll2.rate = clk_xtali.rate;
 537         else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
 538                 clk_pll2.rate = calc_pll_rate(value);
 539         else
 540                 clk_pll2.rate = 0;
 541
 542         /* Initialize the pll2 derived clocks */
 543         clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
 544
 545         /*
 546          * EP93xx SSP clock rate was doubled in version E2. For more information
 547          * see:
 548          *     http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
 549          */
 550         if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)
 551                 clk_spi.rate /= 2;
 552
 553         pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
 554                 clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
 555         pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
 556                 clk_f.rate / 1000000, clk_h.rate / 1000000,
 557                 clk_p.rate / 1000000);
 558
 559         clkdev_add_table(clocks, ARRAY_SIZE(clocks));
 560         return 0;
 561 }
 562 postcore_initcall(ep93xx_clock_init);