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e1000e: e1000e_enable_tx_pkt_filtering() returns wrong value
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / e1000e / lib.c
blob97649bf53b05f4c4fa09ea228fe9d743417348f4
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include "e1000.h"
30
31 enum e1000_mng_mode {
32 e1000_mng_mode_none = 0,
33 e1000_mng_mode_asf,
34 e1000_mng_mode_pt,
35 e1000_mng_mode_ipmi,
36 e1000_mng_mode_host_if_only
37 };
38
39 #define E1000_FACTPS_MNGCG 0x20000000
40
41 /* Intel(R) Active Management Technology signature */
42 #define E1000_IAMT_SIGNATURE 0x544D4149
43
44 /**
45 * e1000e_get_bus_info_pcie - Get PCIe bus information
46 * @hw: pointer to the HW structure
47 *
48 * Determines and stores the system bus information for a particular
49 * network interface. The following bus information is determined and stored:
50 * bus speed, bus width, type (PCIe), and PCIe function.
51 **/
52 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
53 {
54 struct e1000_bus_info *bus = &hw->bus;
55 struct e1000_adapter *adapter = hw->adapter;
56 u32 status;
57 u16 pcie_link_status, pci_header_type, cap_offset;
58
59 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
60 if (!cap_offset) {
61 bus->width = e1000_bus_width_unknown;
62 } else {
63 pci_read_config_word(adapter->pdev,
64 cap_offset + PCIE_LINK_STATUS,
65 &pcie_link_status);
66 bus->width = (enum e1000_bus_width)((pcie_link_status &
67 PCIE_LINK_WIDTH_MASK) >>
68 PCIE_LINK_WIDTH_SHIFT);
69 }
70
71 pci_read_config_word(adapter->pdev, PCI_HEADER_TYPE_REGISTER,
72 &pci_header_type);
73 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
74 status = er32(STATUS);
75 bus->func = (status & E1000_STATUS_FUNC_MASK)
76 >> E1000_STATUS_FUNC_SHIFT;
77 } else {
78 bus->func = 0;
79 }
80
81 return 0;
82 }
83
84 /**
85 * e1000_clear_vfta_generic - Clear VLAN filter table
86 * @hw: pointer to the HW structure
87 *
88 * Clears the register array which contains the VLAN filter table by
89 * setting all the values to 0.
90 **/
91 void e1000_clear_vfta_generic(struct e1000_hw *hw)
92 {
93 u32 offset;
94
95 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
96 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
97 e1e_flush();
98 }
99 }
100
101 /**
102 * e1000_write_vfta_generic - Write value to VLAN filter table
103 * @hw: pointer to the HW structure
104 * @offset: register offset in VLAN filter table
105 * @value: register value written to VLAN filter table
106 *
107 * Writes value at the given offset in the register array which stores
108 * the VLAN filter table.
109 **/
110 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
111 {
112 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
113 e1e_flush();
114 }
115
116 /**
117 * e1000e_init_rx_addrs - Initialize receive address's
118 * @hw: pointer to the HW structure
119 * @rar_count: receive address registers
120 *
121 * Setups the receive address registers by setting the base receive address
122 * register to the devices MAC address and clearing all the other receive
123 * address registers to 0.
124 **/
125 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
126 {
127 u32 i;
128
129 /* Setup the receive address */
130 e_dbg("Programming MAC Address into RAR[0]\n");
131
132 e1000e_rar_set(hw, hw->mac.addr, 0);
133
134 /* Zero out the other (rar_entry_count - 1) receive addresses */
135 e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
136 for (i = 1; i < rar_count; i++) {
137 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0);
138 e1e_flush();
139 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0);
140 e1e_flush();
141 }
142 }
143
144 /**
145 * e1000e_rar_set - Set receive address register
146 * @hw: pointer to the HW structure
147 * @addr: pointer to the receive address
148 * @index: receive address array register
149 *
150 * Sets the receive address array register at index to the address passed
151 * in by addr.
152 **/
153 void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
154 {
155 u32 rar_low, rar_high;
156
157 /*
158 * HW expects these in little endian so we reverse the byte order
159 * from network order (big endian) to little endian
160 */
161 rar_low = ((u32) addr[0] |
162 ((u32) addr[1] << 8) |
163 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
164
165 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
166
167 rar_high |= E1000_RAH_AV;
168
169 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
170 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
171 }
172
173 /**
174 * e1000_hash_mc_addr - Generate a multicast hash value
175 * @hw: pointer to the HW structure
176 * @mc_addr: pointer to a multicast address
177 *
178 * Generates a multicast address hash value which is used to determine
179 * the multicast filter table array address and new table value. See
180 * e1000_mta_set_generic()
181 **/
182 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
183 {
184 u32 hash_value, hash_mask;
185 u8 bit_shift = 0;
186
187 /* Register count multiplied by bits per register */
188 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
189
190 /*
191 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
192 * where 0xFF would still fall within the hash mask.
193 */
194 while (hash_mask >> bit_shift != 0xFF)
195 bit_shift++;
196
197 /*
198 * The portion of the address that is used for the hash table
199 * is determined by the mc_filter_type setting.
200 * The algorithm is such that there is a total of 8 bits of shifting.
201 * The bit_shift for a mc_filter_type of 0 represents the number of
202 * left-shifts where the MSB of mc_addr[5] would still fall within
203 * the hash_mask. Case 0 does this exactly. Since there are a total
204 * of 8 bits of shifting, then mc_addr[4] will shift right the
205 * remaining number of bits. Thus 8 - bit_shift. The rest of the
206 * cases are a variation of this algorithm...essentially raising the
207 * number of bits to shift mc_addr[5] left, while still keeping the
208 * 8-bit shifting total.
209 *
210 * For example, given the following Destination MAC Address and an
211 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
212 * we can see that the bit_shift for case 0 is 4. These are the hash
213 * values resulting from each mc_filter_type...
214 * [0] [1] [2] [3] [4] [5]
215 * 01 AA 00 12 34 56
216 * LSB MSB
217 *
218 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
219 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
220 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
221 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
222 */
223 switch (hw->mac.mc_filter_type) {
224 default:
225 case 0:
226 break;
227 case 1:
228 bit_shift += 1;
229 break;
230 case 2:
231 bit_shift += 2;
232 break;
233 case 3:
234 bit_shift += 4;
235 break;
236 }
237
238 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
239 (((u16) mc_addr[5]) << bit_shift)));
240
241 return hash_value;
242 }
243
244 /**
245 * e1000e_update_mc_addr_list_generic - Update Multicast addresses
246 * @hw: pointer to the HW structure
247 * @mc_addr_list: array of multicast addresses to program
248 * @mc_addr_count: number of multicast addresses to program
249 * @rar_used_count: the first RAR register free to program
250 * @rar_count: total number of supported Receive Address Registers
251 *
252 * Updates the Receive Address Registers and Multicast Table Array.
253 * The caller must have a packed mc_addr_list of multicast addresses.
254 * The parameter rar_count will usually be hw->mac.rar_entry_count
255 * unless there are workarounds that change this.
256 **/
257 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
258 u8 *mc_addr_list, u32 mc_addr_count,
259 u32 rar_used_count, u32 rar_count)
260 {
261 u32 i;
262 u32 *mcarray = kzalloc(hw->mac.mta_reg_count * sizeof(u32), GFP_ATOMIC);
263
264 if (!mcarray) {
265 printk(KERN_ERR "multicast array memory allocation failed\n");
266 return;
267 }
268
269 /*
270 * Load the first set of multicast addresses into the exact
271 * filters (RAR). If there are not enough to fill the RAR
272 * array, clear the filters.
273 */
274 for (i = rar_used_count; i < rar_count; i++) {
275 if (mc_addr_count) {
276 e1000e_rar_set(hw, mc_addr_list, i);
277 mc_addr_count--;
278 mc_addr_list += ETH_ALEN;
279 } else {
280 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0);
281 e1e_flush();
282 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0);
283 e1e_flush();
284 }
285 }
286
287 /* Load any remaining multicast addresses into the hash table. */
288 for (; mc_addr_count > 0; mc_addr_count--) {
289 u32 hash_value, hash_reg, hash_bit, mta;
290 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
291 e_dbg("Hash value = 0x%03X\n", hash_value);
292 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
293 hash_bit = hash_value & 0x1F;
294 mta = (1 << hash_bit);
295 mcarray[hash_reg] |= mta;
296 mc_addr_list += ETH_ALEN;
297 }
298
299 /* write the hash table completely */
300 for (i = 0; i < hw->mac.mta_reg_count; i++)
301 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, mcarray[i]);
302
303 e1e_flush();
304 kfree(mcarray);
305 }
306
307 /**
308 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
309 * @hw: pointer to the HW structure
310 *
311 * Clears the base hardware counters by reading the counter registers.
312 **/
313 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
314 {
315 er32(CRCERRS);
316 er32(SYMERRS);
317 er32(MPC);
318 er32(SCC);
319 er32(ECOL);
320 er32(MCC);
321 er32(LATECOL);
322 er32(COLC);
323 er32(DC);
324 er32(SEC);
325 er32(RLEC);
326 er32(XONRXC);
327 er32(XONTXC);
328 er32(XOFFRXC);
329 er32(XOFFTXC);
330 er32(FCRUC);
331 er32(GPRC);
332 er32(BPRC);
333 er32(MPRC);
334 er32(GPTC);
335 er32(GORCL);
336 er32(GORCH);
337 er32(GOTCL);
338 er32(GOTCH);
339 er32(RNBC);
340 er32(RUC);
341 er32(RFC);
342 er32(ROC);
343 er32(RJC);
344 er32(TORL);
345 er32(TORH);
346 er32(TOTL);
347 er32(TOTH);
348 er32(TPR);
349 er32(TPT);
350 er32(MPTC);
351 er32(BPTC);
352 }
353
354 /**
355 * e1000e_check_for_copper_link - Check for link (Copper)
356 * @hw: pointer to the HW structure
357 *
358 * Checks to see of the link status of the hardware has changed. If a
359 * change in link status has been detected, then we read the PHY registers
360 * to get the current speed/duplex if link exists.
361 **/
362 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
363 {
364 struct e1000_mac_info *mac = &hw->mac;
365 s32 ret_val;
366 bool link;
367
368 /*
369 * We only want to go out to the PHY registers to see if Auto-Neg
370 * has completed and/or if our link status has changed. The
371 * get_link_status flag is set upon receiving a Link Status
372 * Change or Rx Sequence Error interrupt.
373 */
374 if (!mac->get_link_status)
375 return 0;
376
377 /*
378 * First we want to see if the MII Status Register reports
379 * link. If so, then we want to get the current speed/duplex
380 * of the PHY.
381 */
382 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
383 if (ret_val)
384 return ret_val;
385
386 if (!link)
387 return ret_val; /* No link detected */
388
389 mac->get_link_status = false;
390
391 /*
392 * Check if there was DownShift, must be checked
393 * immediately after link-up
394 */
395 e1000e_check_downshift(hw);
396
397 /*
398 * If we are forcing speed/duplex, then we simply return since
399 * we have already determined whether we have link or not.
400 */
401 if (!mac->autoneg) {
402 ret_val = -E1000_ERR_CONFIG;
403 return ret_val;
404 }
405
406 /*
407 * Auto-Neg is enabled. Auto Speed Detection takes care
408 * of MAC speed/duplex configuration. So we only need to
409 * configure Collision Distance in the MAC.
410 */
411 e1000e_config_collision_dist(hw);
412
413 /*
414 * Configure Flow Control now that Auto-Neg has completed.
415 * First, we need to restore the desired flow control
416 * settings because we may have had to re-autoneg with a
417 * different link partner.
418 */
419 ret_val = e1000e_config_fc_after_link_up(hw);
420 if (ret_val) {
421 e_dbg("Error configuring flow control\n");
422 }
423
424 return ret_val;
425 }
426
427 /**
428 * e1000e_check_for_fiber_link - Check for link (Fiber)
429 * @hw: pointer to the HW structure
430 *
431 * Checks for link up on the hardware. If link is not up and we have
432 * a signal, then we need to force link up.
433 **/
434 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
435 {
436 struct e1000_mac_info *mac = &hw->mac;
437 u32 rxcw;
438 u32 ctrl;
439 u32 status;
440 s32 ret_val;
441
442 ctrl = er32(CTRL);
443 status = er32(STATUS);
444 rxcw = er32(RXCW);
445
446 /*
447 * If we don't have link (auto-negotiation failed or link partner
448 * cannot auto-negotiate), the cable is plugged in (we have signal),
449 * and our link partner is not trying to auto-negotiate with us (we
450 * are receiving idles or data), we need to force link up. We also
451 * need to give auto-negotiation time to complete, in case the cable
452 * was just plugged in. The autoneg_failed flag does this.
453 */
454 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
455 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
456 (!(rxcw & E1000_RXCW_C))) {
457 if (mac->autoneg_failed == 0) {
458 mac->autoneg_failed = 1;
459 return 0;
460 }
461 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
462
463 /* Disable auto-negotiation in the TXCW register */
464 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
465
466 /* Force link-up and also force full-duplex. */
467 ctrl = er32(CTRL);
468 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
469 ew32(CTRL, ctrl);
470
471 /* Configure Flow Control after forcing link up. */
472 ret_val = e1000e_config_fc_after_link_up(hw);
473 if (ret_val) {
474 e_dbg("Error configuring flow control\n");
475 return ret_val;
476 }
477 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
478 /*
479 * If we are forcing link and we are receiving /C/ ordered
480 * sets, re-enable auto-negotiation in the TXCW register
481 * and disable forced link in the Device Control register
482 * in an attempt to auto-negotiate with our link partner.
483 */
484 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
485 ew32(TXCW, mac->txcw);
486 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
487
488 mac->serdes_has_link = true;
489 }
490
491 return 0;
492 }
493
494 /**
495 * e1000e_check_for_serdes_link - Check for link (Serdes)
496 * @hw: pointer to the HW structure
497 *
498 * Checks for link up on the hardware. If link is not up and we have
499 * a signal, then we need to force link up.
500 **/
501 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
502 {
503 struct e1000_mac_info *mac = &hw->mac;
504 u32 rxcw;
505 u32 ctrl;
506 u32 status;
507 s32 ret_val;
508
509 ctrl = er32(CTRL);
510 status = er32(STATUS);
511 rxcw = er32(RXCW);
512
513 /*
514 * If we don't have link (auto-negotiation failed or link partner
515 * cannot auto-negotiate), and our link partner is not trying to
516 * auto-negotiate with us (we are receiving idles or data),
517 * we need to force link up. We also need to give auto-negotiation
518 * time to complete.
519 */
520 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
521 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
522 if (mac->autoneg_failed == 0) {
523 mac->autoneg_failed = 1;
524 return 0;
525 }
526 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
527
528 /* Disable auto-negotiation in the TXCW register */
529 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
530
531 /* Force link-up and also force full-duplex. */
532 ctrl = er32(CTRL);
533 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
534 ew32(CTRL, ctrl);
535
536 /* Configure Flow Control after forcing link up. */
537 ret_val = e1000e_config_fc_after_link_up(hw);
538 if (ret_val) {
539 e_dbg("Error configuring flow control\n");
540 return ret_val;
541 }
542 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
543 /*
544 * If we are forcing link and we are receiving /C/ ordered
545 * sets, re-enable auto-negotiation in the TXCW register
546 * and disable forced link in the Device Control register
547 * in an attempt to auto-negotiate with our link partner.
548 */
549 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
550 ew32(TXCW, mac->txcw);
551 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
552
553 mac->serdes_has_link = true;
554 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
555 /*
556 * If we force link for non-auto-negotiation switch, check
557 * link status based on MAC synchronization for internal
558 * serdes media type.
559 */
560 /* SYNCH bit and IV bit are sticky. */
561 udelay(10);
562 rxcw = er32(RXCW);
563 if (rxcw & E1000_RXCW_SYNCH) {
564 if (!(rxcw & E1000_RXCW_IV)) {
565 mac->serdes_has_link = true;
566 e_dbg("SERDES: Link up - forced.\n");
567 }
568 } else {
569 mac->serdes_has_link = false;
570 e_dbg("SERDES: Link down - force failed.\n");
571 }
572 }
573
574 if (E1000_TXCW_ANE & er32(TXCW)) {
575 status = er32(STATUS);
576 if (status & E1000_STATUS_LU) {
577 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
578 udelay(10);
579 rxcw = er32(RXCW);
580 if (rxcw & E1000_RXCW_SYNCH) {
581 if (!(rxcw & E1000_RXCW_IV)) {
582 mac->serdes_has_link = true;
583 e_dbg("SERDES: Link up - autoneg "
584 "completed sucessfully.\n");
585 } else {
586 mac->serdes_has_link = false;
587 e_dbg("SERDES: Link down - invalid"
588 "codewords detected in autoneg.\n");
589 }
590 } else {
591 mac->serdes_has_link = false;
592 e_dbg("SERDES: Link down - no sync.\n");
593 }
594 } else {
595 mac->serdes_has_link = false;
596 e_dbg("SERDES: Link down - autoneg failed\n");
597 }
598 }
599
600 return 0;
601 }
602
603 /**
604 * e1000_set_default_fc_generic - Set flow control default values
605 * @hw: pointer to the HW structure
606 *
607 * Read the EEPROM for the default values for flow control and store the
608 * values.
609 **/
610 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
611 {
612 s32 ret_val;
613 u16 nvm_data;
614
615 /*
616 * Read and store word 0x0F of the EEPROM. This word contains bits
617 * that determine the hardware's default PAUSE (flow control) mode,
618 * a bit that determines whether the HW defaults to enabling or
619 * disabling auto-negotiation, and the direction of the
620 * SW defined pins. If there is no SW over-ride of the flow
621 * control setting, then the variable hw->fc will
622 * be initialized based on a value in the EEPROM.
623 */
624 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
625
626 if (ret_val) {
627 e_dbg("NVM Read Error\n");
628 return ret_val;
629 }
630
631 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
632 hw->fc.requested_mode = e1000_fc_none;
633 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
634 NVM_WORD0F_ASM_DIR)
635 hw->fc.requested_mode = e1000_fc_tx_pause;
636 else
637 hw->fc.requested_mode = e1000_fc_full;
638
639 return 0;
640 }
641
642 /**
643 * e1000e_setup_link - Setup flow control and link settings
644 * @hw: pointer to the HW structure
645 *
646 * Determines which flow control settings to use, then configures flow
647 * control. Calls the appropriate media-specific link configuration
648 * function. Assuming the adapter has a valid link partner, a valid link
649 * should be established. Assumes the hardware has previously been reset
650 * and the transmitter and receiver are not enabled.
651 **/
652 s32 e1000e_setup_link(struct e1000_hw *hw)
653 {
654 struct e1000_mac_info *mac = &hw->mac;
655 s32 ret_val;
656
657 /*
658 * In the case of the phy reset being blocked, we already have a link.
659 * We do not need to set it up again.
660 */
661 if (e1000_check_reset_block(hw))
662 return 0;
663
664 /*
665 * If requested flow control is set to default, set flow control
666 * based on the EEPROM flow control settings.
667 */
668 if (hw->fc.requested_mode == e1000_fc_default) {
669 ret_val = e1000_set_default_fc_generic(hw);
670 if (ret_val)
671 return ret_val;
672 }
673
674 /*
675 * Save off the requested flow control mode for use later. Depending
676 * on the link partner's capabilities, we may or may not use this mode.
677 */
678 hw->fc.current_mode = hw->fc.requested_mode;
679
680 e_dbg("After fix-ups FlowControl is now = %x\n",
681 hw->fc.current_mode);
682
683 /* Call the necessary media_type subroutine to configure the link. */
684 ret_val = mac->ops.setup_physical_interface(hw);
685 if (ret_val)
686 return ret_val;
687
688 /*
689 * Initialize the flow control address, type, and PAUSE timer
690 * registers to their default values. This is done even if flow
691 * control is disabled, because it does not hurt anything to
692 * initialize these registers.
693 */
694 e_dbg("Initializing the Flow Control address, type and timer regs\n");
695 ew32(FCT, FLOW_CONTROL_TYPE);
696 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
697 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
698
699 ew32(FCTTV, hw->fc.pause_time);
700
701 return e1000e_set_fc_watermarks(hw);
702 }
703
704 /**
705 * e1000_commit_fc_settings_generic - Configure flow control
706 * @hw: pointer to the HW structure
707 *
708 * Write the flow control settings to the Transmit Config Word Register (TXCW)
709 * base on the flow control settings in e1000_mac_info.
710 **/
711 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
712 {
713 struct e1000_mac_info *mac = &hw->mac;
714 u32 txcw;
715
716 /*
717 * Check for a software override of the flow control settings, and
718 * setup the device accordingly. If auto-negotiation is enabled, then
719 * software will have to set the "PAUSE" bits to the correct value in
720 * the Transmit Config Word Register (TXCW) and re-start auto-
721 * negotiation. However, if auto-negotiation is disabled, then
722 * software will have to manually configure the two flow control enable
723 * bits in the CTRL register.
724 *
725 * The possible values of the "fc" parameter are:
726 * 0: Flow control is completely disabled
727 * 1: Rx flow control is enabled (we can receive pause frames,
728 * but not send pause frames).
729 * 2: Tx flow control is enabled (we can send pause frames but we
730 * do not support receiving pause frames).
731 * 3: Both Rx and Tx flow control (symmetric) are enabled.
732 */
733 switch (hw->fc.current_mode) {
734 case e1000_fc_none:
735 /* Flow control completely disabled by a software over-ride. */
736 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
737 break;
738 case e1000_fc_rx_pause:
739 /*
740 * Rx Flow control is enabled and Tx Flow control is disabled
741 * by a software over-ride. Since there really isn't a way to
742 * advertise that we are capable of Rx Pause ONLY, we will
743 * advertise that we support both symmetric and asymmetric Rx
744 * PAUSE. Later, we will disable the adapter's ability to send
745 * PAUSE frames.
746 */
747 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
748 break;
749 case e1000_fc_tx_pause:
750 /*
751 * Tx Flow control is enabled, and Rx Flow control is disabled,
752 * by a software over-ride.
753 */
754 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
755 break;
756 case e1000_fc_full:
757 /*
758 * Flow control (both Rx and Tx) is enabled by a software
759 * over-ride.
760 */
761 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
762 break;
763 default:
764 e_dbg("Flow control param set incorrectly\n");
765 return -E1000_ERR_CONFIG;
766 break;
767 }
768
769 ew32(TXCW, txcw);
770 mac->txcw = txcw;
771
772 return 0;
773 }
774
775 /**
776 * e1000_poll_fiber_serdes_link_generic - Poll for link up
777 * @hw: pointer to the HW structure
778 *
779 * Polls for link up by reading the status register, if link fails to come
780 * up with auto-negotiation, then the link is forced if a signal is detected.
781 **/
782 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
783 {
784 struct e1000_mac_info *mac = &hw->mac;
785 u32 i, status;
786 s32 ret_val;
787
788 /*
789 * If we have a signal (the cable is plugged in, or assumed true for
790 * serdes media) then poll for a "Link-Up" indication in the Device
791 * Status Register. Time-out if a link isn't seen in 500 milliseconds
792 * seconds (Auto-negotiation should complete in less than 500
793 * milliseconds even if the other end is doing it in SW).
794 */
795 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
796 msleep(10);
797 status = er32(STATUS);
798 if (status & E1000_STATUS_LU)
799 break;
800 }
801 if (i == FIBER_LINK_UP_LIMIT) {
802 e_dbg("Never got a valid link from auto-neg!!!\n");
803 mac->autoneg_failed = 1;
804 /*
805 * AutoNeg failed to achieve a link, so we'll call
806 * mac->check_for_link. This routine will force the
807 * link up if we detect a signal. This will allow us to
808 * communicate with non-autonegotiating link partners.
809 */
810 ret_val = mac->ops.check_for_link(hw);
811 if (ret_val) {
812 e_dbg("Error while checking for link\n");
813 return ret_val;
814 }
815 mac->autoneg_failed = 0;
816 } else {
817 mac->autoneg_failed = 0;
818 e_dbg("Valid Link Found\n");
819 }
820
821 return 0;
822 }
823
824 /**
825 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
826 * @hw: pointer to the HW structure
827 *
828 * Configures collision distance and flow control for fiber and serdes
829 * links. Upon successful setup, poll for link.
830 **/
831 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
832 {
833 u32 ctrl;
834 s32 ret_val;
835
836 ctrl = er32(CTRL);
837
838 /* Take the link out of reset */
839 ctrl &= ~E1000_CTRL_LRST;
840
841 e1000e_config_collision_dist(hw);
842
843 ret_val = e1000_commit_fc_settings_generic(hw);
844 if (ret_val)
845 return ret_val;
846
847 /*
848 * Since auto-negotiation is enabled, take the link out of reset (the
849 * link will be in reset, because we previously reset the chip). This
850 * will restart auto-negotiation. If auto-negotiation is successful
851 * then the link-up status bit will be set and the flow control enable
852 * bits (RFCE and TFCE) will be set according to their negotiated value.
853 */
854 e_dbg("Auto-negotiation enabled\n");
855
856 ew32(CTRL, ctrl);
857 e1e_flush();
858 msleep(1);
859
860 /*
861 * For these adapters, the SW definable pin 1 is set when the optics
862 * detect a signal. If we have a signal, then poll for a "Link-Up"
863 * indication.
864 */
865 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
866 (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
867 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
868 } else {
869 e_dbg("No signal detected\n");
870 }
871
872 return 0;
873 }
874
875 /**
876 * e1000e_config_collision_dist - Configure collision distance
877 * @hw: pointer to the HW structure
878 *
879 * Configures the collision distance to the default value and is used
880 * during link setup. Currently no func pointer exists and all
881 * implementations are handled in the generic version of this function.
882 **/
883 void e1000e_config_collision_dist(struct e1000_hw *hw)
884 {
885 u32 tctl;
886
887 tctl = er32(TCTL);
888
889 tctl &= ~E1000_TCTL_COLD;
890 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
891
892 ew32(TCTL, tctl);
893 e1e_flush();
894 }
895
896 /**
897 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
898 * @hw: pointer to the HW structure
899 *
900 * Sets the flow control high/low threshold (watermark) registers. If
901 * flow control XON frame transmission is enabled, then set XON frame
902 * transmission as well.
903 **/
904 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
905 {
906 u32 fcrtl = 0, fcrth = 0;
907
908 /*
909 * Set the flow control receive threshold registers. Normally,
910 * these registers will be set to a default threshold that may be
911 * adjusted later by the driver's runtime code. However, if the
912 * ability to transmit pause frames is not enabled, then these
913 * registers will be set to 0.
914 */
915 if (hw->fc.current_mode & e1000_fc_tx_pause) {
916 /*
917 * We need to set up the Receive Threshold high and low water
918 * marks as well as (optionally) enabling the transmission of
919 * XON frames.
920 */
921 fcrtl = hw->fc.low_water;
922 fcrtl |= E1000_FCRTL_XONE;
923 fcrth = hw->fc.high_water;
924 }
925 ew32(FCRTL, fcrtl);
926 ew32(FCRTH, fcrth);
927
928 return 0;
929 }
930
931 /**
932 * e1000e_force_mac_fc - Force the MAC's flow control settings
933 * @hw: pointer to the HW structure
934 *
935 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
936 * device control register to reflect the adapter settings. TFCE and RFCE
937 * need to be explicitly set by software when a copper PHY is used because
938 * autonegotiation is managed by the PHY rather than the MAC. Software must
939 * also configure these bits when link is forced on a fiber connection.
940 **/
941 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
942 {
943 u32 ctrl;
944
945 ctrl = er32(CTRL);
946
947 /*
948 * Because we didn't get link via the internal auto-negotiation
949 * mechanism (we either forced link or we got link via PHY
950 * auto-neg), we have to manually enable/disable transmit an
951 * receive flow control.
952 *
953 * The "Case" statement below enables/disable flow control
954 * according to the "hw->fc.current_mode" parameter.
955 *
956 * The possible values of the "fc" parameter are:
957 * 0: Flow control is completely disabled
958 * 1: Rx flow control is enabled (we can receive pause
959 * frames but not send pause frames).
960 * 2: Tx flow control is enabled (we can send pause frames
961 * frames but we do not receive pause frames).
962 * 3: Both Rx and Tx flow control (symmetric) is enabled.
963 * other: No other values should be possible at this point.
964 */
965 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
966
967 switch (hw->fc.current_mode) {
968 case e1000_fc_none:
969 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
970 break;
971 case e1000_fc_rx_pause:
972 ctrl &= (~E1000_CTRL_TFCE);
973 ctrl |= E1000_CTRL_RFCE;
974 break;
975 case e1000_fc_tx_pause:
976 ctrl &= (~E1000_CTRL_RFCE);
977 ctrl |= E1000_CTRL_TFCE;
978 break;
979 case e1000_fc_full:
980 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
981 break;
982 default:
983 e_dbg("Flow control param set incorrectly\n");
984 return -E1000_ERR_CONFIG;
985 }
986
987 ew32(CTRL, ctrl);
988
989 return 0;
990 }
991
992 /**
993 * e1000e_config_fc_after_link_up - Configures flow control after link
994 * @hw: pointer to the HW structure
995 *
996 * Checks the status of auto-negotiation after link up to ensure that the
997 * speed and duplex were not forced. If the link needed to be forced, then
998 * flow control needs to be forced also. If auto-negotiation is enabled
999 * and did not fail, then we configure flow control based on our link
1000 * partner.
1001 **/
1002 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1003 {
1004 struct e1000_mac_info *mac = &hw->mac;
1005 s32 ret_val = 0;
1006 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1007 u16 speed, duplex;
1008
1009 /*
1010 * Check for the case where we have fiber media and auto-neg failed
1011 * so we had to force link. In this case, we need to force the
1012 * configuration of the MAC to match the "fc" parameter.
1013 */
1014 if (mac->autoneg_failed) {
1015 if (hw->phy.media_type == e1000_media_type_fiber ||
1016 hw->phy.media_type == e1000_media_type_internal_serdes)
1017 ret_val = e1000e_force_mac_fc(hw);
1018 } else {
1019 if (hw->phy.media_type == e1000_media_type_copper)
1020 ret_val = e1000e_force_mac_fc(hw);
1021 }
1022
1023 if (ret_val) {
1024 e_dbg("Error forcing flow control settings\n");
1025 return ret_val;
1026 }
1027
1028 /*
1029 * Check for the case where we have copper media and auto-neg is
1030 * enabled. In this case, we need to check and see if Auto-Neg
1031 * has completed, and if so, how the PHY and link partner has
1032 * flow control configured.
1033 */
1034 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1035 /*
1036 * Read the MII Status Register and check to see if AutoNeg
1037 * has completed. We read this twice because this reg has
1038 * some "sticky" (latched) bits.
1039 */
1040 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1041 if (ret_val)
1042 return ret_val;
1043 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1044 if (ret_val)
1045 return ret_val;
1046
1047 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1048 e_dbg("Copper PHY and Auto Neg "
1049 "has not completed.\n");
1050 return ret_val;
1051 }
1052
1053 /*
1054 * The AutoNeg process has completed, so we now need to
1055 * read both the Auto Negotiation Advertisement
1056 * Register (Address 4) and the Auto_Negotiation Base
1057 * Page Ability Register (Address 5) to determine how
1058 * flow control was negotiated.
1059 */
1060 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1061 if (ret_val)
1062 return ret_val;
1063 ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1064 if (ret_val)
1065 return ret_val;
1066
1067 /*
1068 * Two bits in the Auto Negotiation Advertisement Register
1069 * (Address 4) and two bits in the Auto Negotiation Base
1070 * Page Ability Register (Address 5) determine flow control
1071 * for both the PHY and the link partner. The following
1072 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1073 * 1999, describes these PAUSE resolution bits and how flow
1074 * control is determined based upon these settings.
1075 * NOTE: DC = Don't Care
1076 *
1077 * LOCAL DEVICE | LINK PARTNER
1078 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1079 *-------|---------|-------|---------|--------------------
1080 * 0 | 0 | DC | DC | e1000_fc_none
1081 * 0 | 1 | 0 | DC | e1000_fc_none
1082 * 0 | 1 | 1 | 0 | e1000_fc_none
1083 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1084 * 1 | 0 | 0 | DC | e1000_fc_none
1085 * 1 | DC | 1 | DC | e1000_fc_full
1086 * 1 | 1 | 0 | 0 | e1000_fc_none
1087 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1088 *
1089 * Are both PAUSE bits set to 1? If so, this implies
1090 * Symmetric Flow Control is enabled at both ends. The
1091 * ASM_DIR bits are irrelevant per the spec.
1092 *
1093 * For Symmetric Flow Control:
1094 *
1095 * LOCAL DEVICE | LINK PARTNER
1096 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1097 *-------|---------|-------|---------|--------------------
1098 * 1 | DC | 1 | DC | E1000_fc_full
1099 *
1100 */
1101 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1102 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1103 /*
1104 * Now we need to check if the user selected Rx ONLY
1105 * of pause frames. In this case, we had to advertise
1106 * FULL flow control because we could not advertise Rx
1107 * ONLY. Hence, we must now check to see if we need to
1108 * turn OFF the TRANSMISSION of PAUSE frames.
1109 */
1110 if (hw->fc.requested_mode == e1000_fc_full) {
1111 hw->fc.current_mode = e1000_fc_full;
1112 e_dbg("Flow Control = FULL.\r\n");
1113 } else {
1114 hw->fc.current_mode = e1000_fc_rx_pause;
1115 e_dbg("Flow Control = "
1116 "RX PAUSE frames only.\r\n");
1117 }
1118 }
1119 /*
1120 * For receiving PAUSE frames ONLY.
1121 *
1122 * LOCAL DEVICE | LINK PARTNER
1123 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1124 *-------|---------|-------|---------|--------------------
1125 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1126 */
1127 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1128 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1129 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1130 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1131 hw->fc.current_mode = e1000_fc_tx_pause;
1132 e_dbg("Flow Control = Tx PAUSE frames only.\r\n");
1133 }
1134 /*
1135 * For transmitting PAUSE frames ONLY.
1136 *
1137 * LOCAL DEVICE | LINK PARTNER
1138 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1139 *-------|---------|-------|---------|--------------------
1140 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1141 */
1142 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1143 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1144 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1145 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1146 hw->fc.current_mode = e1000_fc_rx_pause;
1147 e_dbg("Flow Control = Rx PAUSE frames only.\r\n");
1148 } else {
1149 /*
1150 * Per the IEEE spec, at this point flow control
1151 * should be disabled.
1152 */
1153 hw->fc.current_mode = e1000_fc_none;
1154 e_dbg("Flow Control = NONE.\r\n");
1155 }
1156
1157 /*
1158 * Now we need to do one last check... If we auto-
1159 * negotiated to HALF DUPLEX, flow control should not be
1160 * enabled per IEEE 802.3 spec.
1161 */
1162 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1163 if (ret_val) {
1164 e_dbg("Error getting link speed and duplex\n");
1165 return ret_val;
1166 }
1167
1168 if (duplex == HALF_DUPLEX)
1169 hw->fc.current_mode = e1000_fc_none;
1170
1171 /*
1172 * Now we call a subroutine to actually force the MAC
1173 * controller to use the correct flow control settings.
1174 */
1175 ret_val = e1000e_force_mac_fc(hw);
1176 if (ret_val) {
1177 e_dbg("Error forcing flow control settings\n");
1178 return ret_val;
1179 }
1180 }
1181
1182 return 0;
1183 }
1184
1185 /**
1186 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1187 * @hw: pointer to the HW structure
1188 * @speed: stores the current speed
1189 * @duplex: stores the current duplex
1190 *
1191 * Read the status register for the current speed/duplex and store the current
1192 * speed and duplex for copper connections.
1193 **/
1194 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1195 {
1196 u32 status;
1197
1198 status = er32(STATUS);
1199 if (status & E1000_STATUS_SPEED_1000) {
1200 *speed = SPEED_1000;
1201 e_dbg("1000 Mbs, ");
1202 } else if (status & E1000_STATUS_SPEED_100) {
1203 *speed = SPEED_100;
1204 e_dbg("100 Mbs, ");
1205 } else {
1206 *speed = SPEED_10;
1207 e_dbg("10 Mbs, ");
1208 }
1209
1210 if (status & E1000_STATUS_FD) {
1211 *duplex = FULL_DUPLEX;
1212 e_dbg("Full Duplex\n");
1213 } else {
1214 *duplex = HALF_DUPLEX;
1215 e_dbg("Half Duplex\n");
1216 }
1217
1218 return 0;
1219 }
1220
1221 /**
1222 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1223 * @hw: pointer to the HW structure
1224 * @speed: stores the current speed
1225 * @duplex: stores the current duplex
1226 *
1227 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1228 * for fiber/serdes links.
1229 **/
1230 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1231 {
1232 *speed = SPEED_1000;
1233 *duplex = FULL_DUPLEX;
1234
1235 return 0;
1236 }
1237
1238 /**
1239 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1240 * @hw: pointer to the HW structure
1241 *
1242 * Acquire the HW semaphore to access the PHY or NVM
1243 **/
1244 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1245 {
1246 u32 swsm;
1247 s32 timeout = hw->nvm.word_size + 1;
1248 s32 i = 0;
1249
1250 /* Get the SW semaphore */
1251 while (i < timeout) {
1252 swsm = er32(SWSM);
1253 if (!(swsm & E1000_SWSM_SMBI))
1254 break;
1255
1256 udelay(50);
1257 i++;
1258 }
1259
1260 if (i == timeout) {
1261 e_dbg("Driver can't access device - SMBI bit is set.\n");
1262 return -E1000_ERR_NVM;
1263 }
1264
1265 /* Get the FW semaphore. */
1266 for (i = 0; i < timeout; i++) {
1267 swsm = er32(SWSM);
1268 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1269
1270 /* Semaphore acquired if bit latched */
1271 if (er32(SWSM) & E1000_SWSM_SWESMBI)
1272 break;
1273
1274 udelay(50);
1275 }
1276
1277 if (i == timeout) {
1278 /* Release semaphores */
1279 e1000e_put_hw_semaphore(hw);
1280 e_dbg("Driver can't access the NVM\n");
1281 return -E1000_ERR_NVM;
1282 }
1283
1284 return 0;
1285 }
1286
1287 /**
1288 * e1000e_put_hw_semaphore - Release hardware semaphore
1289 * @hw: pointer to the HW structure
1290 *
1291 * Release hardware semaphore used to access the PHY or NVM
1292 **/
1293 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1294 {
1295 u32 swsm;
1296
1297 swsm = er32(SWSM);
1298 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1299 ew32(SWSM, swsm);
1300 }
1301
1302 /**
1303 * e1000e_get_auto_rd_done - Check for auto read completion
1304 * @hw: pointer to the HW structure
1305 *
1306 * Check EEPROM for Auto Read done bit.
1307 **/
1308 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1309 {
1310 s32 i = 0;
1311
1312 while (i < AUTO_READ_DONE_TIMEOUT) {
1313 if (er32(EECD) & E1000_EECD_AUTO_RD)
1314 break;
1315 msleep(1);
1316 i++;
1317 }
1318
1319 if (i == AUTO_READ_DONE_TIMEOUT) {
1320 e_dbg("Auto read by HW from NVM has not completed.\n");
1321 return -E1000_ERR_RESET;
1322 }
1323
1324 return 0;
1325 }
1326
1327 /**
1328 * e1000e_valid_led_default - Verify a valid default LED config
1329 * @hw: pointer to the HW structure
1330 * @data: pointer to the NVM (EEPROM)
1331 *
1332 * Read the EEPROM for the current default LED configuration. If the
1333 * LED configuration is not valid, set to a valid LED configuration.
1334 **/
1335 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1336 {
1337 s32 ret_val;
1338
1339 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1340 if (ret_val) {
1341 e_dbg("NVM Read Error\n");
1342 return ret_val;
1343 }
1344
1345 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1346 *data = ID_LED_DEFAULT;
1347
1348 return 0;
1349 }
1350
1351 /**
1352 * e1000e_id_led_init -
1353 * @hw: pointer to the HW structure
1354 *
1355 **/
1356 s32 e1000e_id_led_init(struct e1000_hw *hw)
1357 {
1358 struct e1000_mac_info *mac = &hw->mac;
1359 s32 ret_val;
1360 const u32 ledctl_mask = 0x000000FF;
1361 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1362 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1363 u16 data, i, temp;
1364 const u16 led_mask = 0x0F;
1365
1366 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1367 if (ret_val)
1368 return ret_val;
1369
1370 mac->ledctl_default = er32(LEDCTL);
1371 mac->ledctl_mode1 = mac->ledctl_default;
1372 mac->ledctl_mode2 = mac->ledctl_default;
1373
1374 for (i = 0; i < 4; i++) {
1375 temp = (data >> (i << 2)) & led_mask;
1376 switch (temp) {
1377 case ID_LED_ON1_DEF2:
1378 case ID_LED_ON1_ON2:
1379 case ID_LED_ON1_OFF2:
1380 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1381 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1382 break;
1383 case ID_LED_OFF1_DEF2:
1384 case ID_LED_OFF1_ON2:
1385 case ID_LED_OFF1_OFF2:
1386 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1387 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1388 break;
1389 default:
1390 /* Do nothing */
1391 break;
1392 }
1393 switch (temp) {
1394 case ID_LED_DEF1_ON2:
1395 case ID_LED_ON1_ON2:
1396 case ID_LED_OFF1_ON2:
1397 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1398 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1399 break;
1400 case ID_LED_DEF1_OFF2:
1401 case ID_LED_ON1_OFF2:
1402 case ID_LED_OFF1_OFF2:
1403 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1404 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1405 break;
1406 default:
1407 /* Do nothing */
1408 break;
1409 }
1410 }
1411
1412 return 0;
1413 }
1414
1415 /**
1416 * e1000e_setup_led_generic - Configures SW controllable LED
1417 * @hw: pointer to the HW structure
1418 *
1419 * This prepares the SW controllable LED for use and saves the current state
1420 * of the LED so it can be later restored.
1421 **/
1422 s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1423 {
1424 u32 ledctl;
1425
1426 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) {
1427 return -E1000_ERR_CONFIG;
1428 }
1429
1430 if (hw->phy.media_type == e1000_media_type_fiber) {
1431 ledctl = er32(LEDCTL);
1432 hw->mac.ledctl_default = ledctl;
1433 /* Turn off LED0 */
1434 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1435 E1000_LEDCTL_LED0_BLINK |
1436 E1000_LEDCTL_LED0_MODE_MASK);
1437 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1438 E1000_LEDCTL_LED0_MODE_SHIFT);
1439 ew32(LEDCTL, ledctl);
1440 } else if (hw->phy.media_type == e1000_media_type_copper) {
1441 ew32(LEDCTL, hw->mac.ledctl_mode1);
1442 }
1443
1444 return 0;
1445 }
1446
1447 /**
1448 * e1000e_cleanup_led_generic - Set LED config to default operation
1449 * @hw: pointer to the HW structure
1450 *
1451 * Remove the current LED configuration and set the LED configuration
1452 * to the default value, saved from the EEPROM.
1453 **/
1454 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1455 {
1456 ew32(LEDCTL, hw->mac.ledctl_default);
1457 return 0;
1458 }
1459
1460 /**
1461 * e1000e_blink_led - Blink LED
1462 * @hw: pointer to the HW structure
1463 *
1464 * Blink the LEDs which are set to be on.
1465 **/
1466 s32 e1000e_blink_led(struct e1000_hw *hw)
1467 {
1468 u32 ledctl_blink = 0;
1469 u32 i;
1470
1471 if (hw->phy.media_type == e1000_media_type_fiber) {
1472 /* always blink LED0 for PCI-E fiber */
1473 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1474 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1475 } else {
1476 /*
1477 * set the blink bit for each LED that's "on" (0x0E)
1478 * in ledctl_mode2
1479 */
1480 ledctl_blink = hw->mac.ledctl_mode2;
1481 for (i = 0; i < 4; i++)
1482 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1483 E1000_LEDCTL_MODE_LED_ON)
1484 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1485 (i * 8));
1486 }
1487
1488 ew32(LEDCTL, ledctl_blink);
1489
1490 return 0;
1491 }
1492
1493 /**
1494 * e1000e_led_on_generic - Turn LED on
1495 * @hw: pointer to the HW structure
1496 *
1497 * Turn LED on.
1498 **/
1499 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1500 {
1501 u32 ctrl;
1502
1503 switch (hw->phy.media_type) {
1504 case e1000_media_type_fiber:
1505 ctrl = er32(CTRL);
1506 ctrl &= ~E1000_CTRL_SWDPIN0;
1507 ctrl |= E1000_CTRL_SWDPIO0;
1508 ew32(CTRL, ctrl);
1509 break;
1510 case e1000_media_type_copper:
1511 ew32(LEDCTL, hw->mac.ledctl_mode2);
1512 break;
1513 default:
1514 break;
1515 }
1516
1517 return 0;
1518 }
1519
1520 /**
1521 * e1000e_led_off_generic - Turn LED off
1522 * @hw: pointer to the HW structure
1523 *
1524 * Turn LED off.
1525 **/
1526 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1527 {
1528 u32 ctrl;
1529
1530 switch (hw->phy.media_type) {
1531 case e1000_media_type_fiber:
1532 ctrl = er32(CTRL);
1533 ctrl |= E1000_CTRL_SWDPIN0;
1534 ctrl |= E1000_CTRL_SWDPIO0;
1535 ew32(CTRL, ctrl);
1536 break;
1537 case e1000_media_type_copper:
1538 ew32(LEDCTL, hw->mac.ledctl_mode1);
1539 break;
1540 default:
1541 break;
1542 }
1543
1544 return 0;
1545 }
1546
1547 /**
1548 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1549 * @hw: pointer to the HW structure
1550 * @no_snoop: bitmap of snoop events
1551 *
1552 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1553 **/
1554 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1555 {
1556 u32 gcr;
1557
1558 if (no_snoop) {
1559 gcr = er32(GCR);
1560 gcr &= ~(PCIE_NO_SNOOP_ALL);
1561 gcr |= no_snoop;
1562 ew32(GCR, gcr);
1563 }
1564 }
1565
1566 /**
1567 * e1000e_disable_pcie_master - Disables PCI-express master access
1568 * @hw: pointer to the HW structure
1569 *
1570 * Returns 0 if successful, else returns -10
1571 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1572 * the master requests to be disabled.
1573 *
1574 * Disables PCI-Express master access and verifies there are no pending
1575 * requests.
1576 **/
1577 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1578 {
1579 u32 ctrl;
1580 s32 timeout = MASTER_DISABLE_TIMEOUT;
1581
1582 ctrl = er32(CTRL);
1583 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1584 ew32(CTRL, ctrl);
1585
1586 while (timeout) {
1587 if (!(er32(STATUS) &
1588 E1000_STATUS_GIO_MASTER_ENABLE))
1589 break;
1590 udelay(100);
1591 timeout--;
1592 }
1593
1594 if (!timeout) {
1595 e_dbg("Master requests are pending.\n");
1596 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1597 }
1598
1599 return 0;
1600 }
1601
1602 /**
1603 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1604 * @hw: pointer to the HW structure
1605 *
1606 * Reset the Adaptive Interframe Spacing throttle to default values.
1607 **/
1608 void e1000e_reset_adaptive(struct e1000_hw *hw)
1609 {
1610 struct e1000_mac_info *mac = &hw->mac;
1611
1612 if (!mac->adaptive_ifs) {
1613 e_dbg("Not in Adaptive IFS mode!\n");
1614 goto out;
1615 }
1616
1617 mac->current_ifs_val = 0;
1618 mac->ifs_min_val = IFS_MIN;
1619 mac->ifs_max_val = IFS_MAX;
1620 mac->ifs_step_size = IFS_STEP;
1621 mac->ifs_ratio = IFS_RATIO;
1622
1623 mac->in_ifs_mode = false;
1624 ew32(AIT, 0);
1625 out:
1626 return;
1627 }
1628
1629 /**
1630 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1631 * @hw: pointer to the HW structure
1632 *
1633 * Update the Adaptive Interframe Spacing Throttle value based on the
1634 * time between transmitted packets and time between collisions.
1635 **/
1636 void e1000e_update_adaptive(struct e1000_hw *hw)
1637 {
1638 struct e1000_mac_info *mac = &hw->mac;
1639
1640 if (!mac->adaptive_ifs) {
1641 e_dbg("Not in Adaptive IFS mode!\n");
1642 goto out;
1643 }
1644
1645 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1646 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1647 mac->in_ifs_mode = true;
1648 if (mac->current_ifs_val < mac->ifs_max_val) {
1649 if (!mac->current_ifs_val)
1650 mac->current_ifs_val = mac->ifs_min_val;
1651 else
1652 mac->current_ifs_val +=
1653 mac->ifs_step_size;
1654 ew32(AIT, mac->current_ifs_val);
1655 }
1656 }
1657 } else {
1658 if (mac->in_ifs_mode &&
1659 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1660 mac->current_ifs_val = 0;
1661 mac->in_ifs_mode = false;
1662 ew32(AIT, 0);
1663 }
1664 }
1665 out:
1666 return;
1667 }
1668
1669 /**
1670 * e1000_raise_eec_clk - Raise EEPROM clock
1671 * @hw: pointer to the HW structure
1672 * @eecd: pointer to the EEPROM
1673 *
1674 * Enable/Raise the EEPROM clock bit.
1675 **/
1676 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
1677 {
1678 *eecd = *eecd | E1000_EECD_SK;
1679 ew32(EECD, *eecd);
1680 e1e_flush();
1681 udelay(hw->nvm.delay_usec);
1682 }
1683
1684 /**
1685 * e1000_lower_eec_clk - Lower EEPROM clock
1686 * @hw: pointer to the HW structure
1687 * @eecd: pointer to the EEPROM
1688 *
1689 * Clear/Lower the EEPROM clock bit.
1690 **/
1691 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
1692 {
1693 *eecd = *eecd & ~E1000_EECD_SK;
1694 ew32(EECD, *eecd);
1695 e1e_flush();
1696 udelay(hw->nvm.delay_usec);
1697 }
1698
1699 /**
1700 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1701 * @hw: pointer to the HW structure
1702 * @data: data to send to the EEPROM
1703 * @count: number of bits to shift out
1704 *
1705 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1706 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1707 * In order to do this, "data" must be broken down into bits.
1708 **/
1709 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
1710 {
1711 struct e1000_nvm_info *nvm = &hw->nvm;
1712 u32 eecd = er32(EECD);
1713 u32 mask;
1714
1715 mask = 0x01 << (count - 1);
1716 if (nvm->type == e1000_nvm_eeprom_spi)
1717 eecd |= E1000_EECD_DO;
1718
1719 do {
1720 eecd &= ~E1000_EECD_DI;
1721
1722 if (data & mask)
1723 eecd |= E1000_EECD_DI;
1724
1725 ew32(EECD, eecd);
1726 e1e_flush();
1727
1728 udelay(nvm->delay_usec);
1729
1730 e1000_raise_eec_clk(hw, &eecd);
1731 e1000_lower_eec_clk(hw, &eecd);
1732
1733 mask >>= 1;
1734 } while (mask);
1735
1736 eecd &= ~E1000_EECD_DI;
1737 ew32(EECD, eecd);
1738 }
1739
1740 /**
1741 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1742 * @hw: pointer to the HW structure
1743 * @count: number of bits to shift in
1744 *
1745 * In order to read a register from the EEPROM, we need to shift 'count' bits
1746 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1747 * the EEPROM (setting the SK bit), and then reading the value of the data out
1748 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1749 * always be clear.
1750 **/
1751 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
1752 {
1753 u32 eecd;
1754 u32 i;
1755 u16 data;
1756
1757 eecd = er32(EECD);
1758
1759 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
1760 data = 0;
1761
1762 for (i = 0; i < count; i++) {
1763 data <<= 1;
1764 e1000_raise_eec_clk(hw, &eecd);
1765
1766 eecd = er32(EECD);
1767
1768 eecd &= ~E1000_EECD_DI;
1769 if (eecd & E1000_EECD_DO)
1770 data |= 1;
1771
1772 e1000_lower_eec_clk(hw, &eecd);
1773 }
1774
1775 return data;
1776 }
1777
1778 /**
1779 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1780 * @hw: pointer to the HW structure
1781 * @ee_reg: EEPROM flag for polling
1782 *
1783 * Polls the EEPROM status bit for either read or write completion based
1784 * upon the value of 'ee_reg'.
1785 **/
1786 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
1787 {
1788 u32 attempts = 100000;
1789 u32 i, reg = 0;
1790
1791 for (i = 0; i < attempts; i++) {
1792 if (ee_reg == E1000_NVM_POLL_READ)
1793 reg = er32(EERD);
1794 else
1795 reg = er32(EEWR);
1796
1797 if (reg & E1000_NVM_RW_REG_DONE)
1798 return 0;
1799
1800 udelay(5);
1801 }
1802
1803 return -E1000_ERR_NVM;
1804 }
1805
1806 /**
1807 * e1000e_acquire_nvm - Generic request for access to EEPROM
1808 * @hw: pointer to the HW structure
1809 *
1810 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1811 * Return successful if access grant bit set, else clear the request for
1812 * EEPROM access and return -E1000_ERR_NVM (-1).
1813 **/
1814 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
1815 {
1816 u32 eecd = er32(EECD);
1817 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
1818
1819 ew32(EECD, eecd | E1000_EECD_REQ);
1820 eecd = er32(EECD);
1821
1822 while (timeout) {
1823 if (eecd & E1000_EECD_GNT)
1824 break;
1825 udelay(5);
1826 eecd = er32(EECD);
1827 timeout--;
1828 }
1829
1830 if (!timeout) {
1831 eecd &= ~E1000_EECD_REQ;
1832 ew32(EECD, eecd);
1833 e_dbg("Could not acquire NVM grant\n");
1834 return -E1000_ERR_NVM;
1835 }
1836
1837 return 0;
1838 }
1839
1840 /**
1841 * e1000_standby_nvm - Return EEPROM to standby state
1842 * @hw: pointer to the HW structure
1843 *
1844 * Return the EEPROM to a standby state.
1845 **/
1846 static void e1000_standby_nvm(struct e1000_hw *hw)
1847 {
1848 struct e1000_nvm_info *nvm = &hw->nvm;
1849 u32 eecd = er32(EECD);
1850
1851 if (nvm->type == e1000_nvm_eeprom_spi) {
1852 /* Toggle CS to flush commands */
1853 eecd |= E1000_EECD_CS;
1854 ew32(EECD, eecd);
1855 e1e_flush();
1856 udelay(nvm->delay_usec);
1857 eecd &= ~E1000_EECD_CS;
1858 ew32(EECD, eecd);
1859 e1e_flush();
1860 udelay(nvm->delay_usec);
1861 }
1862 }
1863
1864 /**
1865 * e1000_stop_nvm - Terminate EEPROM command
1866 * @hw: pointer to the HW structure
1867 *
1868 * Terminates the current command by inverting the EEPROM's chip select pin.
1869 **/
1870 static void e1000_stop_nvm(struct e1000_hw *hw)
1871 {
1872 u32 eecd;
1873
1874 eecd = er32(EECD);
1875 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
1876 /* Pull CS high */
1877 eecd |= E1000_EECD_CS;
1878 e1000_lower_eec_clk(hw, &eecd);
1879 }
1880 }
1881
1882 /**
1883 * e1000e_release_nvm - Release exclusive access to EEPROM
1884 * @hw: pointer to the HW structure
1885 *
1886 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1887 **/
1888 void e1000e_release_nvm(struct e1000_hw *hw)
1889 {
1890 u32 eecd;
1891
1892 e1000_stop_nvm(hw);
1893
1894 eecd = er32(EECD);
1895 eecd &= ~E1000_EECD_REQ;
1896 ew32(EECD, eecd);
1897 }
1898
1899 /**
1900 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1901 * @hw: pointer to the HW structure
1902 *
1903 * Setups the EEPROM for reading and writing.
1904 **/
1905 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
1906 {
1907 struct e1000_nvm_info *nvm = &hw->nvm;
1908 u32 eecd = er32(EECD);
1909 u16 timeout = 0;
1910 u8 spi_stat_reg;
1911
1912 if (nvm->type == e1000_nvm_eeprom_spi) {
1913 /* Clear SK and CS */
1914 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
1915 ew32(EECD, eecd);
1916 udelay(1);
1917 timeout = NVM_MAX_RETRY_SPI;
1918
1919 /*
1920 * Read "Status Register" repeatedly until the LSB is cleared.
1921 * The EEPROM will signal that the command has been completed
1922 * by clearing bit 0 of the internal status register. If it's
1923 * not cleared within 'timeout', then error out.
1924 */
1925 while (timeout) {
1926 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
1927 hw->nvm.opcode_bits);
1928 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
1929 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
1930 break;
1931
1932 udelay(5);
1933 e1000_standby_nvm(hw);
1934 timeout--;
1935 }
1936
1937 if (!timeout) {
1938 e_dbg("SPI NVM Status error\n");
1939 return -E1000_ERR_NVM;
1940 }
1941 }
1942
1943 return 0;
1944 }
1945
1946 /**
1947 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
1948 * @hw: pointer to the HW structure
1949 * @offset: offset of word in the EEPROM to read
1950 * @words: number of words to read
1951 * @data: word read from the EEPROM
1952 *
1953 * Reads a 16 bit word from the EEPROM using the EERD register.
1954 **/
1955 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1956 {
1957 struct e1000_nvm_info *nvm = &hw->nvm;
1958 u32 i, eerd = 0;
1959 s32 ret_val = 0;
1960
1961 /*
1962 * A check for invalid values: offset too large, too many words,
1963 * too many words for the offset, and not enough words.
1964 */
1965 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
1966 (words == 0)) {
1967 e_dbg("nvm parameter(s) out of bounds\n");
1968 return -E1000_ERR_NVM;
1969 }
1970
1971 for (i = 0; i < words; i++) {
1972 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
1973 E1000_NVM_RW_REG_START;
1974
1975 ew32(EERD, eerd);
1976 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
1977 if (ret_val)
1978 break;
1979
1980 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
1981 }
1982
1983 return ret_val;
1984 }
1985
1986 /**
1987 * e1000e_write_nvm_spi - Write to EEPROM using SPI
1988 * @hw: pointer to the HW structure
1989 * @offset: offset within the EEPROM to be written to
1990 * @words: number of words to write
1991 * @data: 16 bit word(s) to be written to the EEPROM
1992 *
1993 * Writes data to EEPROM at offset using SPI interface.
1994 *
1995 * If e1000e_update_nvm_checksum is not called after this function , the
1996 * EEPROM will most likely contain an invalid checksum.
1997 **/
1998 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1999 {
2000 struct e1000_nvm_info *nvm = &hw->nvm;
2001 s32 ret_val;
2002 u16 widx = 0;
2003
2004 /*
2005 * A check for invalid values: offset too large, too many words,
2006 * and not enough words.
2007 */
2008 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2009 (words == 0)) {
2010 e_dbg("nvm parameter(s) out of bounds\n");
2011 return -E1000_ERR_NVM;
2012 }
2013
2014 ret_val = nvm->ops.acquire(hw);
2015 if (ret_val)
2016 return ret_val;
2017
2018 msleep(10);
2019
2020 while (widx < words) {
2021 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
2022
2023 ret_val = e1000_ready_nvm_eeprom(hw);
2024 if (ret_val) {
2025 nvm->ops.release(hw);
2026 return ret_val;
2027 }
2028
2029 e1000_standby_nvm(hw);
2030
2031 /* Send the WRITE ENABLE command (8 bit opcode) */
2032 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
2033 nvm->opcode_bits);
2034
2035 e1000_standby_nvm(hw);
2036
2037 /*
2038 * Some SPI eeproms use the 8th address bit embedded in the
2039 * opcode
2040 */
2041 if ((nvm->address_bits == 8) && (offset >= 128))
2042 write_opcode |= NVM_A8_OPCODE_SPI;
2043
2044 /* Send the Write command (8-bit opcode + addr) */
2045 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
2046 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
2047 nvm->address_bits);
2048
2049 /* Loop to allow for up to whole page write of eeprom */
2050 while (widx < words) {
2051 u16 word_out = data[widx];
2052 word_out = (word_out >> 8) | (word_out << 8);
2053 e1000_shift_out_eec_bits(hw, word_out, 16);
2054 widx++;
2055
2056 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
2057 e1000_standby_nvm(hw);
2058 break;
2059 }
2060 }
2061 }
2062
2063 msleep(10);
2064 nvm->ops.release(hw);
2065 return 0;
2066 }
2067
2068 /**
2069 * e1000e_read_mac_addr - Read device MAC address
2070 * @hw: pointer to the HW structure
2071 *
2072 * Reads the device MAC address from the EEPROM and stores the value.
2073 * Since devices with two ports use the same EEPROM, we increment the
2074 * last bit in the MAC address for the second port.
2075 **/
2076 s32 e1000e_read_mac_addr(struct e1000_hw *hw)
2077 {
2078 s32 ret_val;
2079 u16 offset, nvm_data, i;
2080 u16 mac_addr_offset = 0;
2081
2082 if (hw->mac.type == e1000_82571) {
2083 /* Check for an alternate MAC address. An alternate MAC
2084 * address can be setup by pre-boot software and must be
2085 * treated like a permanent address and must override the
2086 * actual permanent MAC address.*/
2087 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
2088 &mac_addr_offset);
2089 if (ret_val) {
2090 e_dbg("NVM Read Error\n");
2091 return ret_val;
2092 }
2093 if (mac_addr_offset == 0xFFFF)
2094 mac_addr_offset = 0;
2095
2096 if (mac_addr_offset) {
2097 if (hw->bus.func == E1000_FUNC_1)
2098 mac_addr_offset += ETH_ALEN/sizeof(u16);
2099
2100 /* make sure we have a valid mac address here
2101 * before using it */
2102 ret_val = e1000_read_nvm(hw, mac_addr_offset, 1,
2103 &nvm_data);
2104 if (ret_val) {
2105 e_dbg("NVM Read Error\n");
2106 return ret_val;
2107 }
2108 if (nvm_data & 0x0001)
2109 mac_addr_offset = 0;
2110 }
2111
2112 if (mac_addr_offset)
2113 hw->dev_spec.e82571.alt_mac_addr_is_present = 1;
2114 }
2115
2116 for (i = 0; i < ETH_ALEN; i += 2) {
2117 offset = mac_addr_offset + (i >> 1);
2118 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
2119 if (ret_val) {
2120 e_dbg("NVM Read Error\n");
2121 return ret_val;
2122 }
2123 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
2124 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
2125 }
2126
2127 /* Flip last bit of mac address if we're on second port */
2128 if (!mac_addr_offset && hw->bus.func == E1000_FUNC_1)
2129 hw->mac.perm_addr[5] ^= 1;
2130
2131 for (i = 0; i < ETH_ALEN; i++)
2132 hw->mac.addr[i] = hw->mac.perm_addr[i];
2133
2134 return 0;
2135 }
2136
2137 /**
2138 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2139 * @hw: pointer to the HW structure
2140 *
2141 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2142 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2143 **/
2144 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
2145 {
2146 s32 ret_val;
2147 u16 checksum = 0;
2148 u16 i, nvm_data;
2149
2150 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
2151 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2152 if (ret_val) {
2153 e_dbg("NVM Read Error\n");
2154 return ret_val;
2155 }
2156 checksum += nvm_data;
2157 }
2158
2159 if (checksum != (u16) NVM_SUM) {
2160 e_dbg("NVM Checksum Invalid\n");
2161 return -E1000_ERR_NVM;
2162 }
2163
2164 return 0;
2165 }
2166
2167 /**
2168 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2169 * @hw: pointer to the HW structure
2170 *
2171 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2172 * up to the checksum. Then calculates the EEPROM checksum and writes the
2173 * value to the EEPROM.
2174 **/
2175 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
2176 {
2177 s32 ret_val;
2178 u16 checksum = 0;
2179 u16 i, nvm_data;
2180
2181 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
2182 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2183 if (ret_val) {
2184 e_dbg("NVM Read Error while updating checksum.\n");
2185 return ret_val;
2186 }
2187 checksum += nvm_data;
2188 }
2189 checksum = (u16) NVM_SUM - checksum;
2190 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
2191 if (ret_val)
2192 e_dbg("NVM Write Error while updating checksum.\n");
2193
2194 return ret_val;
2195 }
2196
2197 /**
2198 * e1000e_reload_nvm - Reloads EEPROM
2199 * @hw: pointer to the HW structure
2200 *
2201 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2202 * extended control register.
2203 **/
2204 void e1000e_reload_nvm(struct e1000_hw *hw)
2205 {
2206 u32 ctrl_ext;
2207
2208 udelay(10);
2209 ctrl_ext = er32(CTRL_EXT);
2210 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2211 ew32(CTRL_EXT, ctrl_ext);
2212 e1e_flush();
2213 }
2214
2215 /**
2216 * e1000_calculate_checksum - Calculate checksum for buffer
2217 * @buffer: pointer to EEPROM
2218 * @length: size of EEPROM to calculate a checksum for
2219 *
2220 * Calculates the checksum for some buffer on a specified length. The
2221 * checksum calculated is returned.
2222 **/
2223 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
2224 {
2225 u32 i;
2226 u8 sum = 0;
2227
2228 if (!buffer)
2229 return 0;
2230
2231 for (i = 0; i < length; i++)
2232 sum += buffer[i];
2233
2234 return (u8) (0 - sum);
2235 }
2236
2237 /**
2238 * e1000_mng_enable_host_if - Checks host interface is enabled
2239 * @hw: pointer to the HW structure
2240 *
2241 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2242 *
2243 * This function checks whether the HOST IF is enabled for command operation
2244 * and also checks whether the previous command is completed. It busy waits
2245 * in case of previous command is not completed.
2246 **/
2247 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
2248 {
2249 u32 hicr;
2250 u8 i;
2251
2252 /* Check that the host interface is enabled. */
2253 hicr = er32(HICR);
2254 if ((hicr & E1000_HICR_EN) == 0) {
2255 e_dbg("E1000_HOST_EN bit disabled.\n");
2256 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2257 }
2258 /* check the previous command is completed */
2259 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
2260 hicr = er32(HICR);
2261 if (!(hicr & E1000_HICR_C))
2262 break;
2263 mdelay(1);
2264 }
2265
2266 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2267 e_dbg("Previous command timeout failed .\n");
2268 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2269 }
2270
2271 return 0;
2272 }
2273
2274 /**
2275 * e1000e_check_mng_mode_generic - check management mode
2276 * @hw: pointer to the HW structure
2277 *
2278 * Reads the firmware semaphore register and returns true (>0) if
2279 * manageability is enabled, else false (0).
2280 **/
2281 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
2282 {
2283 u32 fwsm = er32(FWSM);
2284
2285 return (fwsm & E1000_FWSM_MODE_MASK) ==
2286 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
2287 }
2288
2289 /**
2290 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
2291 * @hw: pointer to the HW structure
2292 *
2293 * Enables packet filtering on transmit packets if manageability is enabled
2294 * and host interface is enabled.
2295 **/
2296 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
2297 {
2298 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
2299 u32 *buffer = (u32 *)&hw->mng_cookie;
2300 u32 offset;
2301 s32 ret_val, hdr_csum, csum;
2302 u8 i, len;
2303
2304 hw->mac.tx_pkt_filtering = true;
2305
2306 /* No manageability, no filtering */
2307 if (!e1000e_check_mng_mode(hw)) {
2308 hw->mac.tx_pkt_filtering = false;
2309 goto out;
2310 }
2311
2312 /*
2313 * If we can't read from the host interface for whatever
2314 * reason, disable filtering.
2315 */
2316 ret_val = e1000_mng_enable_host_if(hw);
2317 if (ret_val) {
2318 hw->mac.tx_pkt_filtering = false;
2319 goto out;
2320 }
2321
2322 /* Read in the header. Length and offset are in dwords. */
2323 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
2324 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
2325 for (i = 0; i < len; i++)
2326 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
2327 hdr_csum = hdr->checksum;
2328 hdr->checksum = 0;
2329 csum = e1000_calculate_checksum((u8 *)hdr,
2330 E1000_MNG_DHCP_COOKIE_LENGTH);
2331 /*
2332 * If either the checksums or signature don't match, then
2333 * the cookie area isn't considered valid, in which case we
2334 * take the safe route of assuming Tx filtering is enabled.
2335 */
2336 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
2337 hw->mac.tx_pkt_filtering = true;
2338 goto out;
2339 }
2340
2341 /* Cookie area is valid, make the final check for filtering. */
2342 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
2343 hw->mac.tx_pkt_filtering = false;
2344 goto out;
2345 }
2346
2347 out:
2348 return hw->mac.tx_pkt_filtering;
2349 }
2350
2351 /**
2352 * e1000_mng_write_cmd_header - Writes manageability command header
2353 * @hw: pointer to the HW structure
2354 * @hdr: pointer to the host interface command header
2355 *
2356 * Writes the command header after does the checksum calculation.
2357 **/
2358 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2359 struct e1000_host_mng_command_header *hdr)
2360 {
2361 u16 i, length = sizeof(struct e1000_host_mng_command_header);
2362
2363 /* Write the whole command header structure with new checksum. */
2364
2365 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
2366
2367 length >>= 2;
2368 /* Write the relevant command block into the ram area. */
2369 for (i = 0; i < length; i++) {
2370 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
2371 *((u32 *) hdr + i));
2372 e1e_flush();
2373 }
2374
2375 return 0;
2376 }
2377
2378 /**
2379 * e1000_mng_host_if_write - Write to the manageability host interface
2380 * @hw: pointer to the HW structure
2381 * @buffer: pointer to the host interface buffer
2382 * @length: size of the buffer
2383 * @offset: location in the buffer to write to
2384 * @sum: sum of the data (not checksum)
2385 *
2386 * This function writes the buffer content at the offset given on the host if.
2387 * It also does alignment considerations to do the writes in most efficient
2388 * way. Also fills up the sum of the buffer in *buffer parameter.
2389 **/
2390 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
2391 u16 length, u16 offset, u8 *sum)
2392 {
2393 u8 *tmp;
2394 u8 *bufptr = buffer;
2395 u32 data = 0;
2396 u16 remaining, i, j, prev_bytes;
2397
2398 /* sum = only sum of the data and it is not checksum */
2399
2400 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
2401 return -E1000_ERR_PARAM;
2402
2403 tmp = (u8 *)&data;
2404 prev_bytes = offset & 0x3;
2405 offset >>= 2;
2406
2407 if (prev_bytes) {
2408 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
2409 for (j = prev_bytes; j < sizeof(u32); j++) {
2410 *(tmp + j) = *bufptr++;
2411 *sum += *(tmp + j);
2412 }
2413 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
2414 length -= j - prev_bytes;
2415 offset++;
2416 }
2417
2418 remaining = length & 0x3;
2419 length -= remaining;
2420
2421 /* Calculate length in DWORDs */
2422 length >>= 2;
2423
2424 /*
2425 * The device driver writes the relevant command block into the
2426 * ram area.
2427 */
2428 for (i = 0; i < length; i++) {
2429 for (j = 0; j < sizeof(u32); j++) {
2430 *(tmp + j) = *bufptr++;
2431 *sum += *(tmp + j);
2432 }
2433
2434 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2435 }
2436 if (remaining) {
2437 for (j = 0; j < sizeof(u32); j++) {
2438 if (j < remaining)
2439 *(tmp + j) = *bufptr++;
2440 else
2441 *(tmp + j) = 0;
2442
2443 *sum += *(tmp + j);
2444 }
2445 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2446 }
2447
2448 return 0;
2449 }
2450
2451 /**
2452 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2453 * @hw: pointer to the HW structure
2454 * @buffer: pointer to the host interface
2455 * @length: size of the buffer
2456 *
2457 * Writes the DHCP information to the host interface.
2458 **/
2459 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
2460 {
2461 struct e1000_host_mng_command_header hdr;
2462 s32 ret_val;
2463 u32 hicr;
2464
2465 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
2466 hdr.command_length = length;
2467 hdr.reserved1 = 0;
2468 hdr.reserved2 = 0;
2469 hdr.checksum = 0;
2470
2471 /* Enable the host interface */
2472 ret_val = e1000_mng_enable_host_if(hw);
2473 if (ret_val)
2474 return ret_val;
2475
2476 /* Populate the host interface with the contents of "buffer". */
2477 ret_val = e1000_mng_host_if_write(hw, buffer, length,
2478 sizeof(hdr), &(hdr.checksum));
2479 if (ret_val)
2480 return ret_val;
2481
2482 /* Write the manageability command header */
2483 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
2484 if (ret_val)
2485 return ret_val;
2486
2487 /* Tell the ARC a new command is pending. */
2488 hicr = er32(HICR);
2489 ew32(HICR, hicr | E1000_HICR_C);
2490
2491 return 0;
2492 }
2493
2494 /**
2495 * e1000e_enable_mng_pass_thru - Enable processing of ARP's
2496 * @hw: pointer to the HW structure
2497 *
2498 * Verifies the hardware needs to allow ARPs to be processed by the host.
2499 **/
2500 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
2501 {
2502 u32 manc;
2503 u32 fwsm, factps;
2504 bool ret_val = false;
2505
2506 manc = er32(MANC);
2507
2508 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
2509 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
2510 return ret_val;
2511
2512 if (hw->mac.arc_subsystem_valid) {
2513 fwsm = er32(FWSM);
2514 factps = er32(FACTPS);
2515
2516 if (!(factps & E1000_FACTPS_MNGCG) &&
2517 ((fwsm & E1000_FWSM_MODE_MASK) ==
2518 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
2519 ret_val = true;
2520 return ret_val;
2521 }
2522 } else {
2523 if ((manc & E1000_MANC_SMBUS_EN) &&
2524 !(manc & E1000_MANC_ASF_EN)) {
2525 ret_val = true;
2526 return ret_val;
2527 }
2528 }
2529
2530 return ret_val;
2531 }
2532
2533 s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
2534 {
2535 s32 ret_val;
2536 u16 nvm_data;
2537
2538 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
2539 if (ret_val) {
2540 e_dbg("NVM Read Error\n");
2541 return ret_val;
2542 }
2543 *pba_num = (u32)(nvm_data << 16);
2544
2545 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
2546 if (ret_val) {
2547 e_dbg("NVM Read Error\n");
2548 return ret_val;
2549 }
2550 *pba_num |= nvm_data;
2551
2552 return 0;
2553 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree