2 * MUSB OTG peripheral driver ep0 handling
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/spinlock.h>
40 #include <linux/init.h>
41 #include <linux/device.h>
42 #include <linux/interrupt.h>
44 #include "musb_core.h"
46 /* ep0 is always musb->endpoints[0].ep_in */
47 #define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
50 * locking note: we use only the controller lock, for simpler correctness.
51 * It's always held with IRQs blocked.
53 * It protects the ep0 request queue as well as ep0_state, not just the
54 * controller and indexed registers. And that lock stays held unless it
55 * needs to be dropped to allow reentering this driver ... like upcalls to
56 * the gadget driver, or adjusting endpoint halt status.
59 static char *decode_ep0stage(u8 stage
)
62 case MUSB_EP0_STAGE_IDLE
: return "idle";
63 case MUSB_EP0_STAGE_SETUP
: return "setup";
64 case MUSB_EP0_STAGE_TX
: return "in";
65 case MUSB_EP0_STAGE_RX
: return "out";
66 case MUSB_EP0_STAGE_ACKWAIT
: return "wait";
67 case MUSB_EP0_STAGE_STATUSIN
: return "in/status";
68 case MUSB_EP0_STAGE_STATUSOUT
: return "out/status";
73 /* handle a standard GET_STATUS request
74 * Context: caller holds controller lock
76 static int service_tx_status_request(
78 const struct usb_ctrlrequest
*ctrlrequest
)
80 void __iomem
*mbase
= musb
->mregs
;
82 u8 result
[2], epnum
= 0;
83 const u8 recip
= ctrlrequest
->bRequestType
& USB_RECIP_MASK
;
88 case USB_RECIP_DEVICE
:
89 result
[0] = musb
->is_self_powered
<< USB_DEVICE_SELF_POWERED
;
90 result
[0] |= musb
->may_wakeup
<< USB_DEVICE_REMOTE_WAKEUP
;
91 #ifdef CONFIG_USB_MUSB_OTG
93 result
[0] |= musb
->g
.b_hnp_enable
94 << USB_DEVICE_B_HNP_ENABLE
;
95 result
[0] |= musb
->g
.a_alt_hnp_support
96 << USB_DEVICE_A_ALT_HNP_SUPPORT
;
97 result
[0] |= musb
->g
.a_hnp_support
98 << USB_DEVICE_A_HNP_SUPPORT
;
103 case USB_RECIP_INTERFACE
:
107 case USB_RECIP_ENDPOINT
: {
113 epnum
= (u8
) ctrlrequest
->wIndex
;
119 is_in
= epnum
& USB_DIR_IN
;
122 ep
= &musb
->endpoints
[epnum
].ep_in
;
124 ep
= &musb
->endpoints
[epnum
].ep_out
;
126 regs
= musb
->endpoints
[epnum
].regs
;
128 if (epnum
>= MUSB_C_NUM_EPS
|| !ep
->desc
) {
133 musb_ep_select(mbase
, epnum
);
135 tmp
= musb_readw(regs
, MUSB_TXCSR
)
136 & MUSB_TXCSR_P_SENDSTALL
;
138 tmp
= musb_readw(regs
, MUSB_RXCSR
)
139 & MUSB_RXCSR_P_SENDSTALL
;
140 musb_ep_select(mbase
, 0);
142 result
[0] = tmp
? 1 : 0;
146 /* class, vendor, etc ... delegate */
151 /* fill up the fifo; caller updates csr0 */
153 u16 len
= le16_to_cpu(ctrlrequest
->wLength
);
157 musb_write_fifo(&musb
->endpoints
[0], len
, result
);
164 * handle a control-IN request, the end0 buffer contains the current request
165 * that is supposed to be a standard control request. Assumes the fifo to
166 * be at least 2 bytes long.
168 * @return 0 if the request was NOT HANDLED,
170 * > 0 when the request is processed
172 * Context: caller holds controller lock
175 service_in_request(struct musb
*musb
, const struct usb_ctrlrequest
*ctrlrequest
)
177 int handled
= 0; /* not handled */
179 if ((ctrlrequest
->bRequestType
& USB_TYPE_MASK
)
180 == USB_TYPE_STANDARD
) {
181 switch (ctrlrequest
->bRequest
) {
182 case USB_REQ_GET_STATUS
:
183 handled
= service_tx_status_request(musb
,
187 /* case USB_REQ_SYNC_FRAME: */
197 * Context: caller holds controller lock
199 static void musb_g_ep0_giveback(struct musb
*musb
, struct usb_request
*req
)
201 musb_g_giveback(&musb
->endpoints
[0].ep_in
, req
, 0);
205 * Tries to start B-device HNP negotiation if enabled via sysfs
207 static inline void musb_try_b_hnp_enable(struct musb
*musb
)
209 void __iomem
*mbase
= musb
->mregs
;
212 DBG(1, "HNP: Setting HR\n");
213 devctl
= musb_readb(mbase
, MUSB_DEVCTL
);
214 musb_writeb(mbase
, MUSB_DEVCTL
, devctl
| MUSB_DEVCTL_HR
);
218 * Handle all control requests with no DATA stage, including standard
220 * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
221 * always delegated to the gadget driver
222 * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
223 * always handled here, except for class/vendor/... features
225 * Context: caller holds controller lock
228 service_zero_data_request(struct musb
*musb
,
229 struct usb_ctrlrequest
*ctrlrequest
)
230 __releases(musb
->lock
)
231 __acquires(musb
->lock
)
233 int handled
= -EINVAL
;
234 void __iomem
*mbase
= musb
->mregs
;
235 const u8 recip
= ctrlrequest
->bRequestType
& USB_RECIP_MASK
;
237 /* the gadget driver handles everything except what we MUST handle */
238 if ((ctrlrequest
->bRequestType
& USB_TYPE_MASK
)
239 == USB_TYPE_STANDARD
) {
240 switch (ctrlrequest
->bRequest
) {
241 case USB_REQ_SET_ADDRESS
:
242 /* change it after the status stage */
243 musb
->set_address
= true;
244 musb
->address
= (u8
) (ctrlrequest
->wValue
& 0x7f);
248 case USB_REQ_CLEAR_FEATURE
:
250 case USB_RECIP_DEVICE
:
251 if (ctrlrequest
->wValue
252 != USB_DEVICE_REMOTE_WAKEUP
)
254 musb
->may_wakeup
= 0;
257 case USB_RECIP_INTERFACE
:
259 case USB_RECIP_ENDPOINT
:{
261 ctrlrequest
->wIndex
& 0x0f;
262 struct musb_ep
*musb_ep
;
263 struct musb_hw_ep
*ep
;
268 if (epnum
== 0 || epnum
>= MUSB_C_NUM_EPS
||
269 ctrlrequest
->wValue
!= USB_ENDPOINT_HALT
)
272 ep
= musb
->endpoints
+ epnum
;
274 is_in
= ctrlrequest
->wIndex
& USB_DIR_IN
;
276 musb_ep
= &ep
->ep_in
;
278 musb_ep
= &ep
->ep_out
;
283 /* Ignore request if endpoint is wedged */
287 musb_ep_select(mbase
, epnum
);
289 csr
= musb_readw(regs
, MUSB_TXCSR
);
290 csr
|= MUSB_TXCSR_CLRDATATOG
|
291 MUSB_TXCSR_P_WZC_BITS
;
292 csr
&= ~(MUSB_TXCSR_P_SENDSTALL
|
293 MUSB_TXCSR_P_SENTSTALL
|
294 MUSB_TXCSR_TXPKTRDY
);
295 musb_writew(regs
, MUSB_TXCSR
, csr
);
297 csr
= musb_readw(regs
, MUSB_RXCSR
);
298 csr
|= MUSB_RXCSR_CLRDATATOG
|
299 MUSB_RXCSR_P_WZC_BITS
;
300 csr
&= ~(MUSB_RXCSR_P_SENDSTALL
|
301 MUSB_RXCSR_P_SENTSTALL
);
302 musb_writew(regs
, MUSB_RXCSR
, csr
);
305 /* select ep0 again */
306 musb_ep_select(mbase
, 0);
309 /* class, vendor, etc ... delegate */
315 case USB_REQ_SET_FEATURE
:
317 case USB_RECIP_DEVICE
:
319 switch (ctrlrequest
->wValue
) {
320 case USB_DEVICE_REMOTE_WAKEUP
:
321 musb
->may_wakeup
= 1;
323 case USB_DEVICE_TEST_MODE
:
324 if (musb
->g
.speed
!= USB_SPEED_HIGH
)
326 if (ctrlrequest
->wIndex
& 0xff)
329 switch (ctrlrequest
->wIndex
>> 8) {
331 pr_debug("TEST_J\n");
338 pr_debug("TEST_K\n");
344 pr_debug("TEST_SE0_NAK\n");
350 pr_debug("TEST_PACKET\n");
357 pr_debug("TEST_FORCE_HS\n");
363 pr_debug("TEST_FORCE_FS\n");
368 /* TEST_FIFO_ACCESS */
369 pr_debug("TEST_FIFO_ACCESS\n");
371 MUSB_TEST_FIFO_ACCESS
;
374 /* TEST_FORCE_HOST */
375 pr_debug("TEST_FORCE_HOST\n");
377 MUSB_TEST_FORCE_HOST
;
383 /* enter test mode after irq */
385 musb
->test_mode
= true;
387 #ifdef CONFIG_USB_MUSB_OTG
388 case USB_DEVICE_B_HNP_ENABLE
:
391 musb
->g
.b_hnp_enable
= 1;
392 musb_try_b_hnp_enable(musb
);
394 case USB_DEVICE_A_HNP_SUPPORT
:
397 musb
->g
.a_hnp_support
= 1;
399 case USB_DEVICE_A_ALT_HNP_SUPPORT
:
402 musb
->g
.a_alt_hnp_support
= 1;
412 case USB_RECIP_INTERFACE
:
415 case USB_RECIP_ENDPOINT
:{
417 ctrlrequest
->wIndex
& 0x0f;
418 struct musb_ep
*musb_ep
;
419 struct musb_hw_ep
*ep
;
424 if (epnum
== 0 || epnum
>= MUSB_C_NUM_EPS
||
425 ctrlrequest
->wValue
!= USB_ENDPOINT_HALT
)
428 ep
= musb
->endpoints
+ epnum
;
430 is_in
= ctrlrequest
->wIndex
& USB_DIR_IN
;
432 musb_ep
= &ep
->ep_in
;
434 musb_ep
= &ep
->ep_out
;
438 musb_ep_select(mbase
, epnum
);
440 csr
= musb_readw(regs
, MUSB_TXCSR
);
441 if (csr
& MUSB_TXCSR_FIFONOTEMPTY
)
442 csr
|= MUSB_TXCSR_FLUSHFIFO
;
443 csr
|= MUSB_TXCSR_P_SENDSTALL
444 | MUSB_TXCSR_CLRDATATOG
445 | MUSB_TXCSR_P_WZC_BITS
;
446 musb_writew(regs
, MUSB_TXCSR
, csr
);
448 csr
= musb_readw(regs
, MUSB_RXCSR
);
449 csr
|= MUSB_RXCSR_P_SENDSTALL
450 | MUSB_RXCSR_FLUSHFIFO
451 | MUSB_RXCSR_CLRDATATOG
452 | MUSB_RXCSR_P_WZC_BITS
;
453 musb_writew(regs
, MUSB_RXCSR
, csr
);
456 /* select ep0 again */
457 musb_ep_select(mbase
, 0);
462 /* class, vendor, etc ... delegate */
468 /* delegate SET_CONFIGURATION, etc */
476 /* we have an ep0out data packet
477 * Context: caller holds controller lock
479 static void ep0_rxstate(struct musb
*musb
)
481 void __iomem
*regs
= musb
->control_ep
->regs
;
482 struct usb_request
*req
;
485 req
= next_ep0_request(musb
);
487 /* read packet and ack; or stall because of gadget driver bug:
488 * should have provided the rx buffer before setup() returned.
491 void *buf
= req
->buf
+ req
->actual
;
492 unsigned len
= req
->length
- req
->actual
;
494 /* read the buffer */
495 count
= musb_readb(regs
, MUSB_COUNT0
);
497 req
->status
= -EOVERFLOW
;
500 musb_read_fifo(&musb
->endpoints
[0], count
, buf
);
501 req
->actual
+= count
;
502 csr
= MUSB_CSR0_P_SVDRXPKTRDY
;
503 if (count
< 64 || req
->actual
== req
->length
) {
504 musb
->ep0_state
= MUSB_EP0_STAGE_STATUSIN
;
505 csr
|= MUSB_CSR0_P_DATAEND
;
509 csr
= MUSB_CSR0_P_SVDRXPKTRDY
| MUSB_CSR0_P_SENDSTALL
;
512 /* Completion handler may choose to stall, e.g. because the
513 * message just received holds invalid data.
517 musb_g_ep0_giveback(musb
, req
);
522 musb_ep_select(musb
->mregs
, 0);
523 musb_writew(regs
, MUSB_CSR0
, csr
);
527 * transmitting to the host (IN), this code might be called from IRQ
528 * and from kernel thread.
530 * Context: caller holds controller lock
532 static void ep0_txstate(struct musb
*musb
)
534 void __iomem
*regs
= musb
->control_ep
->regs
;
535 struct usb_request
*request
= next_ep0_request(musb
);
536 u16 csr
= MUSB_CSR0_TXPKTRDY
;
542 DBG(2, "odd; csr0 %04x\n", musb_readw(regs
, MUSB_CSR0
));
547 fifo_src
= (u8
*) request
->buf
+ request
->actual
;
548 fifo_count
= min((unsigned) MUSB_EP0_FIFOSIZE
,
549 request
->length
- request
->actual
);
550 musb_write_fifo(&musb
->endpoints
[0], fifo_count
, fifo_src
);
551 request
->actual
+= fifo_count
;
553 /* update the flags */
554 if (fifo_count
< MUSB_MAX_END0_PACKET
555 || (request
->actual
== request
->length
556 && !request
->zero
)) {
557 musb
->ep0_state
= MUSB_EP0_STAGE_STATUSOUT
;
558 csr
|= MUSB_CSR0_P_DATAEND
;
562 /* report completions as soon as the fifo's loaded; there's no
563 * win in waiting till this last packet gets acked. (other than
564 * very precise fault reporting, needed by USB TMC; possible with
565 * this hardware, but not usable from portable gadget drivers.)
569 musb_g_ep0_giveback(musb
, request
);
575 /* send it out, triggering a "txpktrdy cleared" irq */
576 musb_ep_select(musb
->mregs
, 0);
577 musb_writew(regs
, MUSB_CSR0
, csr
);
581 * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
582 * Fields are left in USB byte-order.
584 * Context: caller holds controller lock.
587 musb_read_setup(struct musb
*musb
, struct usb_ctrlrequest
*req
)
589 struct usb_request
*r
;
590 void __iomem
*regs
= musb
->control_ep
->regs
;
592 musb_read_fifo(&musb
->endpoints
[0], sizeof *req
, (u8
*)req
);
594 /* NOTE: earlier 2.6 versions changed setup packets to host
595 * order, but now USB packets always stay in USB byte order.
597 DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
600 le16_to_cpu(req
->wValue
),
601 le16_to_cpu(req
->wIndex
),
602 le16_to_cpu(req
->wLength
));
604 /* clean up any leftover transfers */
605 r
= next_ep0_request(musb
);
607 musb_g_ep0_giveback(musb
, r
);
609 /* For zero-data requests we want to delay the STATUS stage to
610 * avoid SETUPEND errors. If we read data (OUT), delay accepting
611 * packets until there's a buffer to store them in.
613 * If we write data, the controller acts happier if we enable
614 * the TX FIFO right away, and give the controller a moment
617 musb
->set_address
= false;
618 musb
->ackpend
= MUSB_CSR0_P_SVDRXPKTRDY
;
619 if (req
->wLength
== 0) {
620 if (req
->bRequestType
& USB_DIR_IN
)
621 musb
->ackpend
|= MUSB_CSR0_TXPKTRDY
;
622 musb
->ep0_state
= MUSB_EP0_STAGE_ACKWAIT
;
623 } else if (req
->bRequestType
& USB_DIR_IN
) {
624 musb
->ep0_state
= MUSB_EP0_STAGE_TX
;
625 musb_writew(regs
, MUSB_CSR0
, MUSB_CSR0_P_SVDRXPKTRDY
);
626 while ((musb_readw(regs
, MUSB_CSR0
)
627 & MUSB_CSR0_RXPKTRDY
) != 0)
631 musb
->ep0_state
= MUSB_EP0_STAGE_RX
;
635 forward_to_driver(struct musb
*musb
, const struct usb_ctrlrequest
*ctrlrequest
)
636 __releases(musb
->lock
)
637 __acquires(musb
->lock
)
640 if (!musb
->gadget_driver
)
642 spin_unlock(&musb
->lock
);
643 retval
= musb
->gadget_driver
->setup(&musb
->g
, ctrlrequest
);
644 spin_lock(&musb
->lock
);
649 * Handle peripheral ep0 interrupt
651 * Context: irq handler; we won't re-enter the driver that way.
653 irqreturn_t
musb_g_ep0_irq(struct musb
*musb
)
657 void __iomem
*mbase
= musb
->mregs
;
658 void __iomem
*regs
= musb
->endpoints
[0].regs
;
659 irqreturn_t retval
= IRQ_NONE
;
661 musb_ep_select(mbase
, 0); /* select ep0 */
662 csr
= musb_readw(regs
, MUSB_CSR0
);
663 len
= musb_readb(regs
, MUSB_COUNT0
);
665 DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
667 musb_readb(mbase
, MUSB_FADDR
),
668 decode_ep0stage(musb
->ep0_state
));
670 /* I sent a stall.. need to acknowledge it now.. */
671 if (csr
& MUSB_CSR0_P_SENTSTALL
) {
672 musb_writew(regs
, MUSB_CSR0
,
673 csr
& ~MUSB_CSR0_P_SENTSTALL
);
674 retval
= IRQ_HANDLED
;
675 musb
->ep0_state
= MUSB_EP0_STAGE_IDLE
;
676 csr
= musb_readw(regs
, MUSB_CSR0
);
679 /* request ended "early" */
680 if (csr
& MUSB_CSR0_P_SETUPEND
) {
681 musb_writew(regs
, MUSB_CSR0
, MUSB_CSR0_P_SVDSETUPEND
);
682 retval
= IRQ_HANDLED
;
683 /* Transition into the early status phase */
684 switch (musb
->ep0_state
) {
685 case MUSB_EP0_STAGE_TX
:
686 musb
->ep0_state
= MUSB_EP0_STAGE_STATUSOUT
;
688 case MUSB_EP0_STAGE_RX
:
689 musb
->ep0_state
= MUSB_EP0_STAGE_STATUSIN
;
692 ERR("SetupEnd came in a wrong ep0stage %s\n",
693 decode_ep0stage(musb
->ep0_state
));
695 csr
= musb_readw(regs
, MUSB_CSR0
);
696 /* NOTE: request may need completion */
699 /* docs from Mentor only describe tx, rx, and idle/setup states.
700 * we need to handle nuances around status stages, and also the
701 * case where status and setup stages come back-to-back ...
703 switch (musb
->ep0_state
) {
705 case MUSB_EP0_STAGE_TX
:
706 /* irq on clearing txpktrdy */
707 if ((csr
& MUSB_CSR0_TXPKTRDY
) == 0) {
709 retval
= IRQ_HANDLED
;
713 case MUSB_EP0_STAGE_RX
:
714 /* irq on set rxpktrdy */
715 if (csr
& MUSB_CSR0_RXPKTRDY
) {
717 retval
= IRQ_HANDLED
;
721 case MUSB_EP0_STAGE_STATUSIN
:
722 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
724 /* update address (if needed) only @ the end of the
725 * status phase per usb spec, which also guarantees
726 * we get 10 msec to receive this irq... until this
727 * is done we won't see the next packet.
729 if (musb
->set_address
) {
730 musb
->set_address
= false;
731 musb_writeb(mbase
, MUSB_FADDR
, musb
->address
);
734 /* enter test mode if needed (exit by reset) */
735 else if (musb
->test_mode
) {
736 DBG(1, "entering TESTMODE\n");
738 if (MUSB_TEST_PACKET
== musb
->test_mode_nr
)
739 musb_load_testpacket(musb
);
741 musb_writeb(mbase
, MUSB_TESTMODE
,
746 case MUSB_EP0_STAGE_STATUSOUT
:
747 /* end of sequence #1: write to host (TX state) */
749 struct usb_request
*req
;
751 req
= next_ep0_request(musb
);
753 musb_g_ep0_giveback(musb
, req
);
757 * In case when several interrupts can get coalesced,
758 * check to see if we've already received a SETUP packet...
760 if (csr
& MUSB_CSR0_RXPKTRDY
)
763 retval
= IRQ_HANDLED
;
764 musb
->ep0_state
= MUSB_EP0_STAGE_IDLE
;
767 case MUSB_EP0_STAGE_IDLE
:
769 * This state is typically (but not always) indiscernible
770 * from the status states since the corresponding interrupts
771 * tend to happen within too little period of time (with only
772 * a zero-length packet in between) and so get coalesced...
774 retval
= IRQ_HANDLED
;
775 musb
->ep0_state
= MUSB_EP0_STAGE_SETUP
;
778 case MUSB_EP0_STAGE_SETUP
:
780 if (csr
& MUSB_CSR0_RXPKTRDY
) {
781 struct usb_ctrlrequest setup
;
785 ERR("SETUP packet len %d != 8 ?\n", len
);
788 musb_read_setup(musb
, &setup
);
789 retval
= IRQ_HANDLED
;
791 /* sometimes the RESET won't be reported */
792 if (unlikely(musb
->g
.speed
== USB_SPEED_UNKNOWN
)) {
795 printk(KERN_NOTICE
"%s: peripheral reset "
798 power
= musb_readb(mbase
, MUSB_POWER
);
799 musb
->g
.speed
= (power
& MUSB_POWER_HSMODE
)
800 ? USB_SPEED_HIGH
: USB_SPEED_FULL
;
804 switch (musb
->ep0_state
) {
806 /* sequence #3 (no data stage), includes requests
807 * we can't forward (notably SET_ADDRESS and the
808 * device/endpoint feature set/clear operations)
809 * plus SET_CONFIGURATION and others we must
811 case MUSB_EP0_STAGE_ACKWAIT
:
812 handled
= service_zero_data_request(
816 * We're expecting no data in any case, so
817 * always set the DATAEND bit -- doing this
818 * here helps avoid SetupEnd interrupt coming
819 * in the idle stage when we're stalling...
821 musb
->ackpend
|= MUSB_CSR0_P_DATAEND
;
823 /* status stage might be immediate */
826 MUSB_EP0_STAGE_STATUSIN
;
829 /* sequence #1 (IN to host), includes GET_STATUS
830 * requests that we can't forward, GET_DESCRIPTOR
831 * and others that we must
833 case MUSB_EP0_STAGE_TX
:
834 handled
= service_in_request(musb
, &setup
);
836 musb
->ackpend
= MUSB_CSR0_TXPKTRDY
837 | MUSB_CSR0_P_DATAEND
;
839 MUSB_EP0_STAGE_STATUSOUT
;
843 /* sequence #2 (OUT from host), always forward */
844 default: /* MUSB_EP0_STAGE_RX */
848 DBG(3, "handled %d, csr %04x, ep0stage %s\n",
850 decode_ep0stage(musb
->ep0_state
));
852 /* unless we need to delegate this to the gadget
853 * driver, we know how to wrap this up: csr0 has
854 * not yet been written.
858 else if (handled
> 0)
861 handled
= forward_to_driver(musb
, &setup
);
863 musb_ep_select(mbase
, 0);
865 DBG(3, "stall (%d)\n", handled
);
866 musb
->ackpend
|= MUSB_CSR0_P_SENDSTALL
;
867 musb
->ep0_state
= MUSB_EP0_STAGE_IDLE
;
869 musb_writew(regs
, MUSB_CSR0
,
876 case MUSB_EP0_STAGE_ACKWAIT
:
877 /* This should not happen. But happens with tusb6010 with
878 * g_file_storage and high speed. Do nothing.
880 retval
= IRQ_HANDLED
;
886 musb_writew(regs
, MUSB_CSR0
, MUSB_CSR0_P_SENDSTALL
);
887 musb
->ep0_state
= MUSB_EP0_STAGE_IDLE
;
896 musb_g_ep0_enable(struct usb_ep
*ep
, const struct usb_endpoint_descriptor
*desc
)
902 static int musb_g_ep0_disable(struct usb_ep
*e
)
909 musb_g_ep0_queue(struct usb_ep
*e
, struct usb_request
*r
, gfp_t gfp_flags
)
912 struct musb_request
*req
;
915 unsigned long lockflags
;
923 regs
= musb
->control_ep
->regs
;
925 req
= to_musb_request(r
);
927 req
->request
.actual
= 0;
928 req
->request
.status
= -EINPROGRESS
;
931 spin_lock_irqsave(&musb
->lock
, lockflags
);
933 if (!list_empty(&ep
->req_list
)) {
938 switch (musb
->ep0_state
) {
939 case MUSB_EP0_STAGE_RX
: /* control-OUT data */
940 case MUSB_EP0_STAGE_TX
: /* control-IN data */
941 case MUSB_EP0_STAGE_ACKWAIT
: /* zero-length data */
945 DBG(1, "ep0 request queued in state %d\n",
951 /* add request to the list */
952 list_add_tail(&(req
->request
.list
), &(ep
->req_list
));
954 DBG(3, "queue to %s (%s), length=%d\n",
955 ep
->name
, ep
->is_in
? "IN/TX" : "OUT/RX",
956 req
->request
.length
);
958 musb_ep_select(musb
->mregs
, 0);
960 /* sequence #1, IN ... start writing the data */
961 if (musb
->ep0_state
== MUSB_EP0_STAGE_TX
)
964 /* sequence #3, no-data ... issue IN status */
965 else if (musb
->ep0_state
== MUSB_EP0_STAGE_ACKWAIT
) {
966 if (req
->request
.length
)
969 musb
->ep0_state
= MUSB_EP0_STAGE_STATUSIN
;
970 musb_writew(regs
, MUSB_CSR0
,
971 musb
->ackpend
| MUSB_CSR0_P_DATAEND
);
973 musb_g_ep0_giveback(ep
->musb
, r
);
976 /* else for sequence #2 (OUT), caller provides a buffer
977 * before the next packet arrives. deferred responses
978 * (after SETUP is acked) are racey.
980 } else if (musb
->ackpend
) {
981 musb_writew(regs
, MUSB_CSR0
, musb
->ackpend
);
986 spin_unlock_irqrestore(&musb
->lock
, lockflags
);
990 static int musb_g_ep0_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
992 /* we just won't support this */
996 static int musb_g_ep0_halt(struct usb_ep
*e
, int value
)
1000 void __iomem
*base
, *regs
;
1001 unsigned long flags
;
1011 regs
= musb
->control_ep
->regs
;
1014 spin_lock_irqsave(&musb
->lock
, flags
);
1016 if (!list_empty(&ep
->req_list
)) {
1021 musb_ep_select(base
, 0);
1022 csr
= musb
->ackpend
;
1024 switch (musb
->ep0_state
) {
1026 /* Stalls are usually issued after parsing SETUP packet, either
1027 * directly in irq context from setup() or else later.
1029 case MUSB_EP0_STAGE_TX
: /* control-IN data */
1030 case MUSB_EP0_STAGE_ACKWAIT
: /* STALL for zero-length data */
1031 case MUSB_EP0_STAGE_RX
: /* control-OUT data */
1032 csr
= musb_readw(regs
, MUSB_CSR0
);
1035 /* It's also OK to issue stalls during callbacks when a non-empty
1036 * DATA stage buffer has been read (or even written).
1038 case MUSB_EP0_STAGE_STATUSIN
: /* control-OUT status */
1039 case MUSB_EP0_STAGE_STATUSOUT
: /* control-IN status */
1041 csr
|= MUSB_CSR0_P_SENDSTALL
;
1042 musb_writew(regs
, MUSB_CSR0
, csr
);
1043 musb
->ep0_state
= MUSB_EP0_STAGE_IDLE
;
1047 DBG(1, "ep0 can't halt in state %d\n", musb
->ep0_state
);
1052 spin_unlock_irqrestore(&musb
->lock
, flags
);
1056 const struct usb_ep_ops musb_g_ep0_ops
= {
1057 .enable
= musb_g_ep0_enable
,
1058 .disable
= musb_g_ep0_disable
,
1059 .alloc_request
= musb_alloc_request
,
1060 .free_request
= musb_free_request
,
1061 .queue
= musb_g_ep0_queue
,
1062 .dequeue
= musb_g_ep0_dequeue
,
1063 .set_halt
= musb_g_ep0_halt
,